include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[linux-2.6.git] / drivers / gpu / drm / radeon / rv515.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
30 #include "drmP.h"
31 #include "rv515d.h"
32 #include "radeon.h"
33 #include "atom.h"
34 #include "rv515_reg_safe.h"
35
36 /* This files gather functions specifics to: rv515 */
37 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
38 int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
39 void rv515_gpu_init(struct radeon_device *rdev);
40 int rv515_mc_wait_for_idle(struct radeon_device *rdev);
41
42 void rv515_debugfs(struct radeon_device *rdev)
43 {
44         if (r100_debugfs_rbbm_init(rdev)) {
45                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
46         }
47         if (rv515_debugfs_pipes_info_init(rdev)) {
48                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
49         }
50         if (rv515_debugfs_ga_info_init(rdev)) {
51                 DRM_ERROR("Failed to register debugfs file for pipes !\n");
52         }
53 }
54
55 void rv515_ring_start(struct radeon_device *rdev)
56 {
57         int r;
58
59         r = radeon_ring_lock(rdev, 64);
60         if (r) {
61                 return;
62         }
63         radeon_ring_write(rdev, PACKET0(ISYNC_CNTL, 0));
64         radeon_ring_write(rdev,
65                           ISYNC_ANY2D_IDLE3D |
66                           ISYNC_ANY3D_IDLE2D |
67                           ISYNC_WAIT_IDLEGUI |
68                           ISYNC_CPSCRATCH_IDLEGUI);
69         radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
70         radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
71         radeon_ring_write(rdev, PACKET0(0x170C, 0));
72         radeon_ring_write(rdev, 1 << 31);
73         radeon_ring_write(rdev, PACKET0(GB_SELECT, 0));
74         radeon_ring_write(rdev, 0);
75         radeon_ring_write(rdev, PACKET0(GB_ENABLE, 0));
76         radeon_ring_write(rdev, 0);
77         radeon_ring_write(rdev, PACKET0(0x42C8, 0));
78         radeon_ring_write(rdev, (1 << rdev->num_gb_pipes) - 1);
79         radeon_ring_write(rdev, PACKET0(VAP_INDEX_OFFSET, 0));
80         radeon_ring_write(rdev, 0);
81         radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
82         radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE);
83         radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
84         radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE);
85         radeon_ring_write(rdev, PACKET0(WAIT_UNTIL, 0));
86         radeon_ring_write(rdev, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
87         radeon_ring_write(rdev, PACKET0(GB_AA_CONFIG, 0));
88         radeon_ring_write(rdev, 0);
89         radeon_ring_write(rdev, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
90         radeon_ring_write(rdev, RB3D_DC_FLUSH | RB3D_DC_FREE);
91         radeon_ring_write(rdev, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
92         radeon_ring_write(rdev, ZC_FLUSH | ZC_FREE);
93         radeon_ring_write(rdev, PACKET0(GB_MSPOS0, 0));
94         radeon_ring_write(rdev,
95                           ((6 << MS_X0_SHIFT) |
96                            (6 << MS_Y0_SHIFT) |
97                            (6 << MS_X1_SHIFT) |
98                            (6 << MS_Y1_SHIFT) |
99                            (6 << MS_X2_SHIFT) |
100                            (6 << MS_Y2_SHIFT) |
101                            (6 << MSBD0_Y_SHIFT) |
102                            (6 << MSBD0_X_SHIFT)));
103         radeon_ring_write(rdev, PACKET0(GB_MSPOS1, 0));
104         radeon_ring_write(rdev,
105                           ((6 << MS_X3_SHIFT) |
106                            (6 << MS_Y3_SHIFT) |
107                            (6 << MS_X4_SHIFT) |
108                            (6 << MS_Y4_SHIFT) |
109                            (6 << MS_X5_SHIFT) |
110                            (6 << MS_Y5_SHIFT) |
111                            (6 << MSBD1_SHIFT)));
112         radeon_ring_write(rdev, PACKET0(GA_ENHANCE, 0));
113         radeon_ring_write(rdev, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL);
114         radeon_ring_write(rdev, PACKET0(GA_POLY_MODE, 0));
115         radeon_ring_write(rdev, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);
116         radeon_ring_write(rdev, PACKET0(GA_ROUND_MODE, 0));
117         radeon_ring_write(rdev, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
118         radeon_ring_write(rdev, PACKET0(0x20C8, 0));
119         radeon_ring_write(rdev, 0);
120         radeon_ring_unlock_commit(rdev);
121 }
122
123 int rv515_mc_wait_for_idle(struct radeon_device *rdev)
124 {
125         unsigned i;
126         uint32_t tmp;
127
128         for (i = 0; i < rdev->usec_timeout; i++) {
129                 /* read MC_STATUS */
130                 tmp = RREG32_MC(MC_STATUS);
131                 if (tmp & MC_STATUS_IDLE) {
132                         return 0;
133                 }
134                 DRM_UDELAY(1);
135         }
136         return -1;
137 }
138
139 void rv515_vga_render_disable(struct radeon_device *rdev)
140 {
141         WREG32(R_000300_VGA_RENDER_CONTROL,
142                 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
143 }
144
145 void rv515_gpu_init(struct radeon_device *rdev)
146 {
147         unsigned pipe_select_current, gb_pipe_select, tmp;
148
149         r100_hdp_reset(rdev);
150         r100_rb2d_reset(rdev);
151
152         if (r100_gui_wait_for_idle(rdev)) {
153                 printk(KERN_WARNING "Failed to wait GUI idle while "
154                        "reseting GPU. Bad things might happen.\n");
155         }
156
157         rv515_vga_render_disable(rdev);
158
159         r420_pipes_init(rdev);
160         gb_pipe_select = RREG32(0x402C);
161         tmp = RREG32(0x170C);
162         pipe_select_current = (tmp >> 2) & 3;
163         tmp = (1 << pipe_select_current) |
164               (((gb_pipe_select >> 8) & 0xF) << 4);
165         WREG32_PLL(0x000D, tmp);
166         if (r100_gui_wait_for_idle(rdev)) {
167                 printk(KERN_WARNING "Failed to wait GUI idle while "
168                        "reseting GPU. Bad things might happen.\n");
169         }
170         if (rv515_mc_wait_for_idle(rdev)) {
171                 printk(KERN_WARNING "Failed to wait MC idle while "
172                        "programming pipes. Bad things might happen.\n");
173         }
174 }
175
176 int rv515_ga_reset(struct radeon_device *rdev)
177 {
178         uint32_t tmp;
179         bool reinit_cp;
180         int i;
181
182         reinit_cp = rdev->cp.ready;
183         rdev->cp.ready = false;
184         for (i = 0; i < rdev->usec_timeout; i++) {
185                 WREG32(CP_CSQ_MODE, 0);
186                 WREG32(CP_CSQ_CNTL, 0);
187                 WREG32(RBBM_SOFT_RESET, 0x32005);
188                 (void)RREG32(RBBM_SOFT_RESET);
189                 udelay(200);
190                 WREG32(RBBM_SOFT_RESET, 0);
191                 /* Wait to prevent race in RBBM_STATUS */
192                 mdelay(1);
193                 tmp = RREG32(RBBM_STATUS);
194                 if (tmp & ((1 << 20) | (1 << 26))) {
195                         DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)\n", tmp);
196                         /* GA still busy soft reset it */
197                         WREG32(0x429C, 0x200);
198                         WREG32(VAP_PVS_STATE_FLUSH_REG, 0);
199                         WREG32(0x43E0, 0);
200                         WREG32(0x43E4, 0);
201                         WREG32(0x24AC, 0);
202                 }
203                 /* Wait to prevent race in RBBM_STATUS */
204                 mdelay(1);
205                 tmp = RREG32(RBBM_STATUS);
206                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
207                         break;
208                 }
209         }
210         for (i = 0; i < rdev->usec_timeout; i++) {
211                 tmp = RREG32(RBBM_STATUS);
212                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
213                         DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
214                                  tmp);
215                         DRM_INFO("GA_IDLE=0x%08X\n", RREG32(0x425C));
216                         DRM_INFO("RB3D_RESET_STATUS=0x%08X\n", RREG32(0x46f0));
217                         DRM_INFO("ISYNC_CNTL=0x%08X\n", RREG32(0x1724));
218                         if (reinit_cp) {
219                                 return r100_cp_init(rdev, rdev->cp.ring_size);
220                         }
221                         return 0;
222                 }
223                 DRM_UDELAY(1);
224         }
225         tmp = RREG32(RBBM_STATUS);
226         DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
227         return -1;
228 }
229
230 int rv515_gpu_reset(struct radeon_device *rdev)
231 {
232         uint32_t status;
233
234         /* reset order likely matter */
235         status = RREG32(RBBM_STATUS);
236         /* reset HDP */
237         r100_hdp_reset(rdev);
238         /* reset rb2d */
239         if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
240                 r100_rb2d_reset(rdev);
241         }
242         /* reset GA */
243         if (status & ((1 << 20) | (1 << 26))) {
244                 rv515_ga_reset(rdev);
245         }
246         /* reset CP */
247         status = RREG32(RBBM_STATUS);
248         if (status & (1 << 16)) {
249                 r100_cp_reset(rdev);
250         }
251         /* Check if GPU is idle */
252         status = RREG32(RBBM_STATUS);
253         if (status & (1 << 31)) {
254                 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
255                 return -1;
256         }
257         DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
258         return 0;
259 }
260
261 static void rv515_vram_get_type(struct radeon_device *rdev)
262 {
263         uint32_t tmp;
264
265         rdev->mc.vram_width = 128;
266         rdev->mc.vram_is_ddr = true;
267         tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
268         switch (tmp) {
269         case 0:
270                 rdev->mc.vram_width = 64;
271                 break;
272         case 1:
273                 rdev->mc.vram_width = 128;
274                 break;
275         default:
276                 rdev->mc.vram_width = 128;
277                 break;
278         }
279 }
280
281 void rv515_mc_init(struct radeon_device *rdev)
282 {
283         fixed20_12 a;
284
285         rv515_vram_get_type(rdev);
286         r100_vram_init_sizes(rdev);
287         radeon_vram_location(rdev, &rdev->mc, 0);
288         if (!(rdev->flags & RADEON_IS_AGP))
289                 radeon_gtt_location(rdev, &rdev->mc);
290         /* FIXME: we should enforce default clock in case GPU is not in
291          * default setup
292          */
293         a.full = rfixed_const(100);
294         rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
295         rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
296 }
297
298 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
299 {
300         uint32_t r;
301
302         WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
303         r = RREG32(MC_IND_DATA);
304         WREG32(MC_IND_INDEX, 0);
305         return r;
306 }
307
308 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
309 {
310         WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
311         WREG32(MC_IND_DATA, (v));
312         WREG32(MC_IND_INDEX, 0);
313 }
314
315 #if defined(CONFIG_DEBUG_FS)
316 static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
317 {
318         struct drm_info_node *node = (struct drm_info_node *) m->private;
319         struct drm_device *dev = node->minor->dev;
320         struct radeon_device *rdev = dev->dev_private;
321         uint32_t tmp;
322
323         tmp = RREG32(GB_PIPE_SELECT);
324         seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
325         tmp = RREG32(SU_REG_DEST);
326         seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
327         tmp = RREG32(GB_TILE_CONFIG);
328         seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
329         tmp = RREG32(DST_PIPE_CONFIG);
330         seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
331         return 0;
332 }
333
334 static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
335 {
336         struct drm_info_node *node = (struct drm_info_node *) m->private;
337         struct drm_device *dev = node->minor->dev;
338         struct radeon_device *rdev = dev->dev_private;
339         uint32_t tmp;
340
341         tmp = RREG32(0x2140);
342         seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
343         radeon_gpu_reset(rdev);
344         tmp = RREG32(0x425C);
345         seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
346         return 0;
347 }
348
349 static struct drm_info_list rv515_pipes_info_list[] = {
350         {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
351 };
352
353 static struct drm_info_list rv515_ga_info_list[] = {
354         {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
355 };
356 #endif
357
358 int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
359 {
360 #if defined(CONFIG_DEBUG_FS)
361         return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
362 #else
363         return 0;
364 #endif
365 }
366
367 int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
368 {
369 #if defined(CONFIG_DEBUG_FS)
370         return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
371 #else
372         return 0;
373 #endif
374 }
375
376 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
377 {
378         save->d1vga_control = RREG32(R_000330_D1VGA_CONTROL);
379         save->d2vga_control = RREG32(R_000338_D2VGA_CONTROL);
380         save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);
381         save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
382         save->d1crtc_control = RREG32(R_006080_D1CRTC_CONTROL);
383         save->d2crtc_control = RREG32(R_006880_D2CRTC_CONTROL);
384
385         /* Stop all video */
386         WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
387         WREG32(R_000300_VGA_RENDER_CONTROL, 0);
388         WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
389         WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
390         WREG32(R_006080_D1CRTC_CONTROL, 0);
391         WREG32(R_006880_D2CRTC_CONTROL, 0);
392         WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
393         WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
394         WREG32(R_000330_D1VGA_CONTROL, 0);
395         WREG32(R_000338_D2VGA_CONTROL, 0);
396 }
397
398 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
399 {
400         WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
401         WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
402         WREG32(R_006910_D2GRPH_PRIMARY_SURFACE_ADDRESS, rdev->mc.vram_start);
403         WREG32(R_006918_D2GRPH_SECONDARY_SURFACE_ADDRESS, rdev->mc.vram_start);
404         WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
405         /* Unlock host access */
406         WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
407         mdelay(1);
408         /* Restore video state */
409         WREG32(R_000330_D1VGA_CONTROL, save->d1vga_control);
410         WREG32(R_000338_D2VGA_CONTROL, save->d2vga_control);
411         WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 1);
412         WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 1);
413         WREG32(R_006080_D1CRTC_CONTROL, save->d1crtc_control);
414         WREG32(R_006880_D2CRTC_CONTROL, save->d2crtc_control);
415         WREG32(R_0060E8_D1CRTC_UPDATE_LOCK, 0);
416         WREG32(R_0068E8_D2CRTC_UPDATE_LOCK, 0);
417         WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
418 }
419
420 void rv515_mc_program(struct radeon_device *rdev)
421 {
422         struct rv515_mc_save save;
423
424         /* Stops all mc clients */
425         rv515_mc_stop(rdev, &save);
426
427         /* Wait for mc idle */
428         if (rv515_mc_wait_for_idle(rdev))
429                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
430         /* Write VRAM size in case we are limiting it */
431         WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
432         /* Program MC, should be a 32bits limited address space */
433         WREG32_MC(R_000001_MC_FB_LOCATION,
434                         S_000001_MC_FB_START(rdev->mc.vram_start >> 16) |
435                         S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16));
436         WREG32(R_000134_HDP_FB_LOCATION,
437                 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
438         if (rdev->flags & RADEON_IS_AGP) {
439                 WREG32_MC(R_000002_MC_AGP_LOCATION,
440                         S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) |
441                         S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
442                 WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
443                 WREG32_MC(R_000004_MC_AGP_BASE_2,
444                         S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
445         } else {
446                 WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF);
447                 WREG32_MC(R_000003_MC_AGP_BASE, 0);
448                 WREG32_MC(R_000004_MC_AGP_BASE_2, 0);
449         }
450
451         rv515_mc_resume(rdev, &save);
452 }
453
454 void rv515_clock_startup(struct radeon_device *rdev)
455 {
456         if (radeon_dynclks != -1 && radeon_dynclks)
457                 radeon_atom_set_clock_gating(rdev, 1);
458         /* We need to force on some of the block */
459         WREG32_PLL(R_00000F_CP_DYN_CNTL,
460                 RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1));
461         WREG32_PLL(R_000011_E2_DYN_CNTL,
462                 RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1));
463         WREG32_PLL(R_000013_IDCT_DYN_CNTL,
464                 RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1));
465 }
466
467 static int rv515_startup(struct radeon_device *rdev)
468 {
469         int r;
470
471         rv515_mc_program(rdev);
472         /* Resume clock */
473         rv515_clock_startup(rdev);
474         /* Initialize GPU configuration (# pipes, ...) */
475         rv515_gpu_init(rdev);
476         /* Initialize GART (initialize after TTM so we can allocate
477          * memory through TTM but finalize after TTM) */
478         if (rdev->flags & RADEON_IS_PCIE) {
479                 r = rv370_pcie_gart_enable(rdev);
480                 if (r)
481                         return r;
482         }
483         /* Enable IRQ */
484         rs600_irq_set(rdev);
485         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
486         /* 1M ring buffer */
487         r = r100_cp_init(rdev, 1024 * 1024);
488         if (r) {
489                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
490                 return r;
491         }
492         r = r100_wb_init(rdev);
493         if (r)
494                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
495         r = r100_ib_init(rdev);
496         if (r) {
497                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
498                 return r;
499         }
500         return 0;
501 }
502
503 int rv515_resume(struct radeon_device *rdev)
504 {
505         /* Make sur GART are not working */
506         if (rdev->flags & RADEON_IS_PCIE)
507                 rv370_pcie_gart_disable(rdev);
508         /* Resume clock before doing reset */
509         rv515_clock_startup(rdev);
510         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
511         if (radeon_gpu_reset(rdev)) {
512                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
513                         RREG32(R_000E40_RBBM_STATUS),
514                         RREG32(R_0007C0_CP_STAT));
515         }
516         /* post */
517         atom_asic_init(rdev->mode_info.atom_context);
518         /* Resume clock after posting */
519         rv515_clock_startup(rdev);
520         /* Initialize surface registers */
521         radeon_surface_init(rdev);
522         return rv515_startup(rdev);
523 }
524
525 int rv515_suspend(struct radeon_device *rdev)
526 {
527         r100_cp_disable(rdev);
528         r100_wb_disable(rdev);
529         rs600_irq_disable(rdev);
530         if (rdev->flags & RADEON_IS_PCIE)
531                 rv370_pcie_gart_disable(rdev);
532         return 0;
533 }
534
535 void rv515_set_safe_registers(struct radeon_device *rdev)
536 {
537         rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;
538         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);
539 }
540
541 void rv515_fini(struct radeon_device *rdev)
542 {
543         r100_cp_fini(rdev);
544         r100_wb_fini(rdev);
545         r100_ib_fini(rdev);
546         radeon_gem_fini(rdev);
547         rv370_pcie_gart_fini(rdev);
548         radeon_agp_fini(rdev);
549         radeon_irq_kms_fini(rdev);
550         radeon_fence_driver_fini(rdev);
551         radeon_bo_fini(rdev);
552         radeon_atombios_fini(rdev);
553         kfree(rdev->bios);
554         rdev->bios = NULL;
555 }
556
557 int rv515_init(struct radeon_device *rdev)
558 {
559         int r;
560
561         /* Initialize scratch registers */
562         radeon_scratch_init(rdev);
563         /* Initialize surface registers */
564         radeon_surface_init(rdev);
565         /* TODO: disable VGA need to use VGA request */
566         /* BIOS*/
567         if (!radeon_get_bios(rdev)) {
568                 if (ASIC_IS_AVIVO(rdev))
569                         return -EINVAL;
570         }
571         if (rdev->is_atom_bios) {
572                 r = radeon_atombios_init(rdev);
573                 if (r)
574                         return r;
575         } else {
576                 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
577                 return -EINVAL;
578         }
579         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
580         if (radeon_gpu_reset(rdev)) {
581                 dev_warn(rdev->dev,
582                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
583                         RREG32(R_000E40_RBBM_STATUS),
584                         RREG32(R_0007C0_CP_STAT));
585         }
586         /* check if cards are posted or not */
587         if (radeon_boot_test_post_card(rdev) == false)
588                 return -EINVAL;
589         /* Initialize clocks */
590         radeon_get_clock_info(rdev->ddev);
591         /* Initialize power management */
592         radeon_pm_init(rdev);
593         /* initialize AGP */
594         if (rdev->flags & RADEON_IS_AGP) {
595                 r = radeon_agp_init(rdev);
596                 if (r) {
597                         radeon_agp_disable(rdev);
598                 }
599         }
600         /* initialize memory controller */
601         rv515_mc_init(rdev);
602         rv515_debugfs(rdev);
603         /* Fence driver */
604         r = radeon_fence_driver_init(rdev);
605         if (r)
606                 return r;
607         r = radeon_irq_kms_init(rdev);
608         if (r)
609                 return r;
610         /* Memory manager */
611         r = radeon_bo_init(rdev);
612         if (r)
613                 return r;
614         r = rv370_pcie_gart_init(rdev);
615         if (r)
616                 return r;
617         rv515_set_safe_registers(rdev);
618         rdev->accel_working = true;
619         r = rv515_startup(rdev);
620         if (r) {
621                 /* Somethings want wront with the accel init stop accel */
622                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
623                 r100_cp_fini(rdev);
624                 r100_wb_fini(rdev);
625                 r100_ib_fini(rdev);
626                 radeon_irq_kms_fini(rdev);
627                 rv370_pcie_gart_fini(rdev);
628                 radeon_agp_fini(rdev);
629                 rdev->accel_working = false;
630         }
631         return 0;
632 }
633
634 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)
635 {
636         int index_reg = 0x6578 + crtc->crtc_offset;
637         int data_reg = 0x657c + crtc->crtc_offset;
638
639         WREG32(0x659C + crtc->crtc_offset, 0x0);
640         WREG32(0x6594 + crtc->crtc_offset, 0x705);
641         WREG32(0x65A4 + crtc->crtc_offset, 0x10001);
642         WREG32(0x65D8 + crtc->crtc_offset, 0x0);
643         WREG32(0x65B0 + crtc->crtc_offset, 0x0);
644         WREG32(0x65C0 + crtc->crtc_offset, 0x0);
645         WREG32(0x65D4 + crtc->crtc_offset, 0x0);
646         WREG32(index_reg, 0x0);
647         WREG32(data_reg, 0x841880A8);
648         WREG32(index_reg, 0x1);
649         WREG32(data_reg, 0x84208680);
650         WREG32(index_reg, 0x2);
651         WREG32(data_reg, 0xBFF880B0);
652         WREG32(index_reg, 0x100);
653         WREG32(data_reg, 0x83D88088);
654         WREG32(index_reg, 0x101);
655         WREG32(data_reg, 0x84608680);
656         WREG32(index_reg, 0x102);
657         WREG32(data_reg, 0xBFF080D0);
658         WREG32(index_reg, 0x200);
659         WREG32(data_reg, 0x83988068);
660         WREG32(index_reg, 0x201);
661         WREG32(data_reg, 0x84A08680);
662         WREG32(index_reg, 0x202);
663         WREG32(data_reg, 0xBFF080F8);
664         WREG32(index_reg, 0x300);
665         WREG32(data_reg, 0x83588058);
666         WREG32(index_reg, 0x301);
667         WREG32(data_reg, 0x84E08660);
668         WREG32(index_reg, 0x302);
669         WREG32(data_reg, 0xBFF88120);
670         WREG32(index_reg, 0x400);
671         WREG32(data_reg, 0x83188040);
672         WREG32(index_reg, 0x401);
673         WREG32(data_reg, 0x85008660);
674         WREG32(index_reg, 0x402);
675         WREG32(data_reg, 0xBFF88150);
676         WREG32(index_reg, 0x500);
677         WREG32(data_reg, 0x82D88030);
678         WREG32(index_reg, 0x501);
679         WREG32(data_reg, 0x85408640);
680         WREG32(index_reg, 0x502);
681         WREG32(data_reg, 0xBFF88180);
682         WREG32(index_reg, 0x600);
683         WREG32(data_reg, 0x82A08018);
684         WREG32(index_reg, 0x601);
685         WREG32(data_reg, 0x85808620);
686         WREG32(index_reg, 0x602);
687         WREG32(data_reg, 0xBFF081B8);
688         WREG32(index_reg, 0x700);
689         WREG32(data_reg, 0x82608010);
690         WREG32(index_reg, 0x701);
691         WREG32(data_reg, 0x85A08600);
692         WREG32(index_reg, 0x702);
693         WREG32(data_reg, 0x800081F0);
694         WREG32(index_reg, 0x800);
695         WREG32(data_reg, 0x8228BFF8);
696         WREG32(index_reg, 0x801);
697         WREG32(data_reg, 0x85E085E0);
698         WREG32(index_reg, 0x802);
699         WREG32(data_reg, 0xBFF88228);
700         WREG32(index_reg, 0x10000);
701         WREG32(data_reg, 0x82A8BF00);
702         WREG32(index_reg, 0x10001);
703         WREG32(data_reg, 0x82A08CC0);
704         WREG32(index_reg, 0x10002);
705         WREG32(data_reg, 0x8008BEF8);
706         WREG32(index_reg, 0x10100);
707         WREG32(data_reg, 0x81F0BF28);
708         WREG32(index_reg, 0x10101);
709         WREG32(data_reg, 0x83608CA0);
710         WREG32(index_reg, 0x10102);
711         WREG32(data_reg, 0x8018BED0);
712         WREG32(index_reg, 0x10200);
713         WREG32(data_reg, 0x8148BF38);
714         WREG32(index_reg, 0x10201);
715         WREG32(data_reg, 0x84408C80);
716         WREG32(index_reg, 0x10202);
717         WREG32(data_reg, 0x8008BEB8);
718         WREG32(index_reg, 0x10300);
719         WREG32(data_reg, 0x80B0BF78);
720         WREG32(index_reg, 0x10301);
721         WREG32(data_reg, 0x85008C20);
722         WREG32(index_reg, 0x10302);
723         WREG32(data_reg, 0x8020BEA0);
724         WREG32(index_reg, 0x10400);
725         WREG32(data_reg, 0x8028BF90);
726         WREG32(index_reg, 0x10401);
727         WREG32(data_reg, 0x85E08BC0);
728         WREG32(index_reg, 0x10402);
729         WREG32(data_reg, 0x8018BE90);
730         WREG32(index_reg, 0x10500);
731         WREG32(data_reg, 0xBFB8BFB0);
732         WREG32(index_reg, 0x10501);
733         WREG32(data_reg, 0x86C08B40);
734         WREG32(index_reg, 0x10502);
735         WREG32(data_reg, 0x8010BE90);
736         WREG32(index_reg, 0x10600);
737         WREG32(data_reg, 0xBF58BFC8);
738         WREG32(index_reg, 0x10601);
739         WREG32(data_reg, 0x87A08AA0);
740         WREG32(index_reg, 0x10602);
741         WREG32(data_reg, 0x8010BE98);
742         WREG32(index_reg, 0x10700);
743         WREG32(data_reg, 0xBF10BFF0);
744         WREG32(index_reg, 0x10701);
745         WREG32(data_reg, 0x886089E0);
746         WREG32(index_reg, 0x10702);
747         WREG32(data_reg, 0x8018BEB0);
748         WREG32(index_reg, 0x10800);
749         WREG32(data_reg, 0xBED8BFE8);
750         WREG32(index_reg, 0x10801);
751         WREG32(data_reg, 0x89408940);
752         WREG32(index_reg, 0x10802);
753         WREG32(data_reg, 0xBFE8BED8);
754         WREG32(index_reg, 0x20000);
755         WREG32(data_reg, 0x80008000);
756         WREG32(index_reg, 0x20001);
757         WREG32(data_reg, 0x90008000);
758         WREG32(index_reg, 0x20002);
759         WREG32(data_reg, 0x80008000);
760         WREG32(index_reg, 0x20003);
761         WREG32(data_reg, 0x80008000);
762         WREG32(index_reg, 0x20100);
763         WREG32(data_reg, 0x80108000);
764         WREG32(index_reg, 0x20101);
765         WREG32(data_reg, 0x8FE0BF70);
766         WREG32(index_reg, 0x20102);
767         WREG32(data_reg, 0xBFE880C0);
768         WREG32(index_reg, 0x20103);
769         WREG32(data_reg, 0x80008000);
770         WREG32(index_reg, 0x20200);
771         WREG32(data_reg, 0x8018BFF8);
772         WREG32(index_reg, 0x20201);
773         WREG32(data_reg, 0x8F80BF08);
774         WREG32(index_reg, 0x20202);
775         WREG32(data_reg, 0xBFD081A0);
776         WREG32(index_reg, 0x20203);
777         WREG32(data_reg, 0xBFF88000);
778         WREG32(index_reg, 0x20300);
779         WREG32(data_reg, 0x80188000);
780         WREG32(index_reg, 0x20301);
781         WREG32(data_reg, 0x8EE0BEC0);
782         WREG32(index_reg, 0x20302);
783         WREG32(data_reg, 0xBFB082A0);
784         WREG32(index_reg, 0x20303);
785         WREG32(data_reg, 0x80008000);
786         WREG32(index_reg, 0x20400);
787         WREG32(data_reg, 0x80188000);
788         WREG32(index_reg, 0x20401);
789         WREG32(data_reg, 0x8E00BEA0);
790         WREG32(index_reg, 0x20402);
791         WREG32(data_reg, 0xBF8883C0);
792         WREG32(index_reg, 0x20403);
793         WREG32(data_reg, 0x80008000);
794         WREG32(index_reg, 0x20500);
795         WREG32(data_reg, 0x80188000);
796         WREG32(index_reg, 0x20501);
797         WREG32(data_reg, 0x8D00BE90);
798         WREG32(index_reg, 0x20502);
799         WREG32(data_reg, 0xBF588500);
800         WREG32(index_reg, 0x20503);
801         WREG32(data_reg, 0x80008008);
802         WREG32(index_reg, 0x20600);
803         WREG32(data_reg, 0x80188000);
804         WREG32(index_reg, 0x20601);
805         WREG32(data_reg, 0x8BC0BE98);
806         WREG32(index_reg, 0x20602);
807         WREG32(data_reg, 0xBF308660);
808         WREG32(index_reg, 0x20603);
809         WREG32(data_reg, 0x80008008);
810         WREG32(index_reg, 0x20700);
811         WREG32(data_reg, 0x80108000);
812         WREG32(index_reg, 0x20701);
813         WREG32(data_reg, 0x8A80BEB0);
814         WREG32(index_reg, 0x20702);
815         WREG32(data_reg, 0xBF0087C0);
816         WREG32(index_reg, 0x20703);
817         WREG32(data_reg, 0x80008008);
818         WREG32(index_reg, 0x20800);
819         WREG32(data_reg, 0x80108000);
820         WREG32(index_reg, 0x20801);
821         WREG32(data_reg, 0x8920BED0);
822         WREG32(index_reg, 0x20802);
823         WREG32(data_reg, 0xBED08920);
824         WREG32(index_reg, 0x20803);
825         WREG32(data_reg, 0x80008010);
826         WREG32(index_reg, 0x30000);
827         WREG32(data_reg, 0x90008000);
828         WREG32(index_reg, 0x30001);
829         WREG32(data_reg, 0x80008000);
830         WREG32(index_reg, 0x30100);
831         WREG32(data_reg, 0x8FE0BF90);
832         WREG32(index_reg, 0x30101);
833         WREG32(data_reg, 0xBFF880A0);
834         WREG32(index_reg, 0x30200);
835         WREG32(data_reg, 0x8F60BF40);
836         WREG32(index_reg, 0x30201);
837         WREG32(data_reg, 0xBFE88180);
838         WREG32(index_reg, 0x30300);
839         WREG32(data_reg, 0x8EC0BF00);
840         WREG32(index_reg, 0x30301);
841         WREG32(data_reg, 0xBFC88280);
842         WREG32(index_reg, 0x30400);
843         WREG32(data_reg, 0x8DE0BEE0);
844         WREG32(index_reg, 0x30401);
845         WREG32(data_reg, 0xBFA083A0);
846         WREG32(index_reg, 0x30500);
847         WREG32(data_reg, 0x8CE0BED0);
848         WREG32(index_reg, 0x30501);
849         WREG32(data_reg, 0xBF7884E0);
850         WREG32(index_reg, 0x30600);
851         WREG32(data_reg, 0x8BA0BED8);
852         WREG32(index_reg, 0x30601);
853         WREG32(data_reg, 0xBF508640);
854         WREG32(index_reg, 0x30700);
855         WREG32(data_reg, 0x8A60BEE8);
856         WREG32(index_reg, 0x30701);
857         WREG32(data_reg, 0xBF2087A0);
858         WREG32(index_reg, 0x30800);
859         WREG32(data_reg, 0x8900BF00);
860         WREG32(index_reg, 0x30801);
861         WREG32(data_reg, 0xBF008900);
862 }
863
864 struct rv515_watermark {
865         u32        lb_request_fifo_depth;
866         fixed20_12 num_line_pair;
867         fixed20_12 estimated_width;
868         fixed20_12 worst_case_latency;
869         fixed20_12 consumption_rate;
870         fixed20_12 active_time;
871         fixed20_12 dbpp;
872         fixed20_12 priority_mark_max;
873         fixed20_12 priority_mark;
874         fixed20_12 sclk;
875 };
876
877 void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
878                                   struct radeon_crtc *crtc,
879                                   struct rv515_watermark *wm)
880 {
881         struct drm_display_mode *mode = &crtc->base.mode;
882         fixed20_12 a, b, c;
883         fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
884         fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
885
886         if (!crtc->base.enabled) {
887                 /* FIXME: wouldn't it better to set priority mark to maximum */
888                 wm->lb_request_fifo_depth = 4;
889                 return;
890         }
891
892         if (crtc->vsc.full > rfixed_const(2))
893                 wm->num_line_pair.full = rfixed_const(2);
894         else
895                 wm->num_line_pair.full = rfixed_const(1);
896
897         b.full = rfixed_const(mode->crtc_hdisplay);
898         c.full = rfixed_const(256);
899         a.full = rfixed_div(b, c);
900         request_fifo_depth.full = rfixed_mul(a, wm->num_line_pair);
901         request_fifo_depth.full = rfixed_ceil(request_fifo_depth);
902         if (a.full < rfixed_const(4)) {
903                 wm->lb_request_fifo_depth = 4;
904         } else {
905                 wm->lb_request_fifo_depth = rfixed_trunc(request_fifo_depth);
906         }
907
908         /* Determine consumption rate
909          *  pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
910          *  vtaps = number of vertical taps,
911          *  vsc = vertical scaling ratio, defined as source/destination
912          *  hsc = horizontal scaling ration, defined as source/destination
913          */
914         a.full = rfixed_const(mode->clock);
915         b.full = rfixed_const(1000);
916         a.full = rfixed_div(a, b);
917         pclk.full = rfixed_div(b, a);
918         if (crtc->rmx_type != RMX_OFF) {
919                 b.full = rfixed_const(2);
920                 if (crtc->vsc.full > b.full)
921                         b.full = crtc->vsc.full;
922                 b.full = rfixed_mul(b, crtc->hsc);
923                 c.full = rfixed_const(2);
924                 b.full = rfixed_div(b, c);
925                 consumption_time.full = rfixed_div(pclk, b);
926         } else {
927                 consumption_time.full = pclk.full;
928         }
929         a.full = rfixed_const(1);
930         wm->consumption_rate.full = rfixed_div(a, consumption_time);
931
932
933         /* Determine line time
934          *  LineTime = total time for one line of displayhtotal
935          *  LineTime = total number of horizontal pixels
936          *  pclk = pixel clock period(ns)
937          */
938         a.full = rfixed_const(crtc->base.mode.crtc_htotal);
939         line_time.full = rfixed_mul(a, pclk);
940
941         /* Determine active time
942          *  ActiveTime = time of active region of display within one line,
943          *  hactive = total number of horizontal active pixels
944          *  htotal = total number of horizontal pixels
945          */
946         a.full = rfixed_const(crtc->base.mode.crtc_htotal);
947         b.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
948         wm->active_time.full = rfixed_mul(line_time, b);
949         wm->active_time.full = rfixed_div(wm->active_time, a);
950
951         /* Determine chunk time
952          * ChunkTime = the time it takes the DCP to send one chunk of data
953          * to the LB which consists of pipeline delay and inter chunk gap
954          * sclk = system clock(Mhz)
955          */
956         a.full = rfixed_const(600 * 1000);
957         chunk_time.full = rfixed_div(a, rdev->pm.sclk);
958         read_delay_latency.full = rfixed_const(1000);
959
960         /* Determine the worst case latency
961          * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
962          * WorstCaseLatency = worst case time from urgent to when the MC starts
963          *                    to return data
964          * READ_DELAY_IDLE_MAX = constant of 1us
965          * ChunkTime = time it takes the DCP to send one chunk of data to the LB
966          *             which consists of pipeline delay and inter chunk gap
967          */
968         if (rfixed_trunc(wm->num_line_pair) > 1) {
969                 a.full = rfixed_const(3);
970                 wm->worst_case_latency.full = rfixed_mul(a, chunk_time);
971                 wm->worst_case_latency.full += read_delay_latency.full;
972         } else {
973                 wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full;
974         }
975
976         /* Determine the tolerable latency
977          * TolerableLatency = Any given request has only 1 line time
978          *                    for the data to be returned
979          * LBRequestFifoDepth = Number of chunk requests the LB can
980          *                      put into the request FIFO for a display
981          *  LineTime = total time for one line of display
982          *  ChunkTime = the time it takes the DCP to send one chunk
983          *              of data to the LB which consists of
984          *  pipeline delay and inter chunk gap
985          */
986         if ((2+wm->lb_request_fifo_depth) >= rfixed_trunc(request_fifo_depth)) {
987                 tolerable_latency.full = line_time.full;
988         } else {
989                 tolerable_latency.full = rfixed_const(wm->lb_request_fifo_depth - 2);
990                 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
991                 tolerable_latency.full = rfixed_mul(tolerable_latency, chunk_time);
992                 tolerable_latency.full = line_time.full - tolerable_latency.full;
993         }
994         /* We assume worst case 32bits (4 bytes) */
995         wm->dbpp.full = rfixed_const(2 * 16);
996
997         /* Determine the maximum priority mark
998          *  width = viewport width in pixels
999          */
1000         a.full = rfixed_const(16);
1001         wm->priority_mark_max.full = rfixed_const(crtc->base.mode.crtc_hdisplay);
1002         wm->priority_mark_max.full = rfixed_div(wm->priority_mark_max, a);
1003         wm->priority_mark_max.full = rfixed_ceil(wm->priority_mark_max);
1004
1005         /* Determine estimated width */
1006         estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
1007         estimated_width.full = rfixed_div(estimated_width, consumption_time);
1008         if (rfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
1009                 wm->priority_mark.full = wm->priority_mark_max.full;
1010         } else {
1011                 a.full = rfixed_const(16);
1012                 wm->priority_mark.full = rfixed_div(estimated_width, a);
1013                 wm->priority_mark.full = rfixed_ceil(wm->priority_mark);
1014                 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
1015         }
1016 }
1017
1018 void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
1019 {
1020         struct drm_display_mode *mode0 = NULL;
1021         struct drm_display_mode *mode1 = NULL;
1022         struct rv515_watermark wm0;
1023         struct rv515_watermark wm1;
1024         u32 tmp;
1025         fixed20_12 priority_mark02, priority_mark12, fill_rate;
1026         fixed20_12 a, b;
1027
1028         if (rdev->mode_info.crtcs[0]->base.enabled)
1029                 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1030         if (rdev->mode_info.crtcs[1]->base.enabled)
1031                 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1032         rs690_line_buffer_adjust(rdev, mode0, mode1);
1033
1034         rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
1035         rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
1036
1037         tmp = wm0.lb_request_fifo_depth;
1038         tmp |= wm1.lb_request_fifo_depth << 16;
1039         WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
1040
1041         if (mode0 && mode1) {
1042                 if (rfixed_trunc(wm0.dbpp) > 64)
1043                         a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair);
1044                 else
1045                         a.full = wm0.num_line_pair.full;
1046                 if (rfixed_trunc(wm1.dbpp) > 64)
1047                         b.full = rfixed_div(wm1.dbpp, wm1.num_line_pair);
1048                 else
1049                         b.full = wm1.num_line_pair.full;
1050                 a.full += b.full;
1051                 fill_rate.full = rfixed_div(wm0.sclk, a);
1052                 if (wm0.consumption_rate.full > fill_rate.full) {
1053                         b.full = wm0.consumption_rate.full - fill_rate.full;
1054                         b.full = rfixed_mul(b, wm0.active_time);
1055                         a.full = rfixed_const(16);
1056                         b.full = rfixed_div(b, a);
1057                         a.full = rfixed_mul(wm0.worst_case_latency,
1058                                                 wm0.consumption_rate);
1059                         priority_mark02.full = a.full + b.full;
1060                 } else {
1061                         a.full = rfixed_mul(wm0.worst_case_latency,
1062                                                 wm0.consumption_rate);
1063                         b.full = rfixed_const(16 * 1000);
1064                         priority_mark02.full = rfixed_div(a, b);
1065                 }
1066                 if (wm1.consumption_rate.full > fill_rate.full) {
1067                         b.full = wm1.consumption_rate.full - fill_rate.full;
1068                         b.full = rfixed_mul(b, wm1.active_time);
1069                         a.full = rfixed_const(16);
1070                         b.full = rfixed_div(b, a);
1071                         a.full = rfixed_mul(wm1.worst_case_latency,
1072                                                 wm1.consumption_rate);
1073                         priority_mark12.full = a.full + b.full;
1074                 } else {
1075                         a.full = rfixed_mul(wm1.worst_case_latency,
1076                                                 wm1.consumption_rate);
1077                         b.full = rfixed_const(16 * 1000);
1078                         priority_mark12.full = rfixed_div(a, b);
1079                 }
1080                 if (wm0.priority_mark.full > priority_mark02.full)
1081                         priority_mark02.full = wm0.priority_mark.full;
1082                 if (rfixed_trunc(priority_mark02) < 0)
1083                         priority_mark02.full = 0;
1084                 if (wm0.priority_mark_max.full > priority_mark02.full)
1085                         priority_mark02.full = wm0.priority_mark_max.full;
1086                 if (wm1.priority_mark.full > priority_mark12.full)
1087                         priority_mark12.full = wm1.priority_mark.full;
1088                 if (rfixed_trunc(priority_mark12) < 0)
1089                         priority_mark12.full = 0;
1090                 if (wm1.priority_mark_max.full > priority_mark12.full)
1091                         priority_mark12.full = wm1.priority_mark_max.full;
1092                 WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
1093                 WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
1094                 WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
1095                 WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
1096         } else if (mode0) {
1097                 if (rfixed_trunc(wm0.dbpp) > 64)
1098                         a.full = rfixed_div(wm0.dbpp, wm0.num_line_pair);
1099                 else
1100                         a.full = wm0.num_line_pair.full;
1101                 fill_rate.full = rfixed_div(wm0.sclk, a);
1102                 if (wm0.consumption_rate.full > fill_rate.full) {
1103                         b.full = wm0.consumption_rate.full - fill_rate.full;
1104                         b.full = rfixed_mul(b, wm0.active_time);
1105                         a.full = rfixed_const(16);
1106                         b.full = rfixed_div(b, a);
1107                         a.full = rfixed_mul(wm0.worst_case_latency,
1108                                                 wm0.consumption_rate);
1109                         priority_mark02.full = a.full + b.full;
1110                 } else {
1111                         a.full = rfixed_mul(wm0.worst_case_latency,
1112                                                 wm0.consumption_rate);
1113                         b.full = rfixed_const(16);
1114                         priority_mark02.full = rfixed_div(a, b);
1115                 }
1116                 if (wm0.priority_mark.full > priority_mark02.full)
1117                         priority_mark02.full = wm0.priority_mark.full;
1118                 if (rfixed_trunc(priority_mark02) < 0)
1119                         priority_mark02.full = 0;
1120                 if (wm0.priority_mark_max.full > priority_mark02.full)
1121                         priority_mark02.full = wm0.priority_mark_max.full;
1122                 WREG32(D1MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark02));
1123                 WREG32(D1MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark02));
1124                 WREG32(D2MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
1125                 WREG32(D2MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
1126         } else {
1127                 if (rfixed_trunc(wm1.dbpp) > 64)
1128                         a.full = rfixed_div(wm1.dbpp, wm1.num_line_pair);
1129                 else
1130                         a.full = wm1.num_line_pair.full;
1131                 fill_rate.full = rfixed_div(wm1.sclk, a);
1132                 if (wm1.consumption_rate.full > fill_rate.full) {
1133                         b.full = wm1.consumption_rate.full - fill_rate.full;
1134                         b.full = rfixed_mul(b, wm1.active_time);
1135                         a.full = rfixed_const(16);
1136                         b.full = rfixed_div(b, a);
1137                         a.full = rfixed_mul(wm1.worst_case_latency,
1138                                                 wm1.consumption_rate);
1139                         priority_mark12.full = a.full + b.full;
1140                 } else {
1141                         a.full = rfixed_mul(wm1.worst_case_latency,
1142                                                 wm1.consumption_rate);
1143                         b.full = rfixed_const(16 * 1000);
1144                         priority_mark12.full = rfixed_div(a, b);
1145                 }
1146                 if (wm1.priority_mark.full > priority_mark12.full)
1147                         priority_mark12.full = wm1.priority_mark.full;
1148                 if (rfixed_trunc(priority_mark12) < 0)
1149                         priority_mark12.full = 0;
1150                 if (wm1.priority_mark_max.full > priority_mark12.full)
1151                         priority_mark12.full = wm1.priority_mark_max.full;
1152                 WREG32(D1MODE_PRIORITY_A_CNT, MODE_PRIORITY_OFF);
1153                 WREG32(D1MODE_PRIORITY_B_CNT, MODE_PRIORITY_OFF);
1154                 WREG32(D2MODE_PRIORITY_A_CNT, rfixed_trunc(priority_mark12));
1155                 WREG32(D2MODE_PRIORITY_B_CNT, rfixed_trunc(priority_mark12));
1156         }
1157 }
1158
1159 void rv515_bandwidth_update(struct radeon_device *rdev)
1160 {
1161         uint32_t tmp;
1162         struct drm_display_mode *mode0 = NULL;
1163         struct drm_display_mode *mode1 = NULL;
1164
1165         if (rdev->mode_info.crtcs[0]->base.enabled)
1166                 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1167         if (rdev->mode_info.crtcs[1]->base.enabled)
1168                 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1169         /*
1170          * Set display0/1 priority up in the memory controller for
1171          * modes if the user specifies HIGH for displaypriority
1172          * option.
1173          */
1174         if (rdev->disp_priority == 2) {
1175                 tmp = RREG32_MC(MC_MISC_LAT_TIMER);
1176                 tmp &= ~MC_DISP1R_INIT_LAT_MASK;
1177                 tmp &= ~MC_DISP0R_INIT_LAT_MASK;
1178                 if (mode1)
1179                         tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
1180                 if (mode0)
1181                         tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
1182                 WREG32_MC(MC_MISC_LAT_TIMER, tmp);
1183         }
1184         rv515_bandwidth_avivo_update(rdev);
1185 }