drm/radeon/kms: avoid corner case issue with unmappable vram V2
[linux-2.6.git] / drivers / gpu / drm / radeon / rs690.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include "drmP.h"
29 #include "radeon.h"
30 #include "radeon_asic.h"
31 #include "atom.h"
32 #include "rs690d.h"
33
34 static int rs690_mc_wait_for_idle(struct radeon_device *rdev)
35 {
36         unsigned i;
37         uint32_t tmp;
38
39         for (i = 0; i < rdev->usec_timeout; i++) {
40                 /* read MC_STATUS */
41                 tmp = RREG32_MC(R_000090_MC_SYSTEM_STATUS);
42                 if (G_000090_MC_SYSTEM_IDLE(tmp))
43                         return 0;
44                 udelay(1);
45         }
46         return -1;
47 }
48
49 static void rs690_gpu_init(struct radeon_device *rdev)
50 {
51         /* FIXME: is this correct ? */
52         r420_pipes_init(rdev);
53         if (rs690_mc_wait_for_idle(rdev)) {
54                 printk(KERN_WARNING "Failed to wait MC idle while "
55                        "programming pipes. Bad things might happen.\n");
56         }
57 }
58
59 union igp_info {
60         struct _ATOM_INTEGRATED_SYSTEM_INFO info;
61         struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_v2;
62 };
63
64 void rs690_pm_info(struct radeon_device *rdev)
65 {
66         int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
67         union igp_info *info;
68         uint16_t data_offset;
69         uint8_t frev, crev;
70         fixed20_12 tmp;
71
72         if (atom_parse_data_header(rdev->mode_info.atom_context, index, NULL,
73                                    &frev, &crev, &data_offset)) {
74                 info = (union igp_info *)(rdev->mode_info.atom_context->bios + data_offset);
75
76                 /* Get various system informations from bios */
77                 switch (crev) {
78                 case 1:
79                         tmp.full = dfixed_const(100);
80                         rdev->pm.igp_sideport_mclk.full = dfixed_const(info->info.ulBootUpMemoryClock);
81                         rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
82                         if (info->info.usK8MemoryClock)
83                                 rdev->pm.igp_system_mclk.full = dfixed_const(le16_to_cpu(info->info.usK8MemoryClock));
84                         else if (rdev->clock.default_mclk) {
85                                 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
86                                 rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
87                         } else
88                                 rdev->pm.igp_system_mclk.full = dfixed_const(400);
89                         rdev->pm.igp_ht_link_clk.full = dfixed_const(le16_to_cpu(info->info.usFSBClock));
90                         rdev->pm.igp_ht_link_width.full = dfixed_const(info->info.ucHTLinkWidth);
91                         break;
92                 case 2:
93                         tmp.full = dfixed_const(100);
94                         rdev->pm.igp_sideport_mclk.full = dfixed_const(info->info_v2.ulBootUpSidePortClock);
95                         rdev->pm.igp_sideport_mclk.full = dfixed_div(rdev->pm.igp_sideport_mclk, tmp);
96                         if (info->info_v2.ulBootUpUMAClock)
97                                 rdev->pm.igp_system_mclk.full = dfixed_const(info->info_v2.ulBootUpUMAClock);
98                         else if (rdev->clock.default_mclk)
99                                 rdev->pm.igp_system_mclk.full = dfixed_const(rdev->clock.default_mclk);
100                         else
101                                 rdev->pm.igp_system_mclk.full = dfixed_const(66700);
102                         rdev->pm.igp_system_mclk.full = dfixed_div(rdev->pm.igp_system_mclk, tmp);
103                         rdev->pm.igp_ht_link_clk.full = dfixed_const(info->info_v2.ulHTLinkFreq);
104                         rdev->pm.igp_ht_link_clk.full = dfixed_div(rdev->pm.igp_ht_link_clk, tmp);
105                         rdev->pm.igp_ht_link_width.full = dfixed_const(le16_to_cpu(info->info_v2.usMinHTLinkWidth));
106                         break;
107                 default:
108                         /* We assume the slower possible clock ie worst case */
109                         rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
110                         rdev->pm.igp_system_mclk.full = dfixed_const(200);
111                         rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
112                         rdev->pm.igp_ht_link_width.full = dfixed_const(8);
113                         DRM_ERROR("No integrated system info for your GPU, using safe default\n");
114                         break;
115                 }
116         } else {
117                 /* We assume the slower possible clock ie worst case */
118                 rdev->pm.igp_sideport_mclk.full = dfixed_const(200);
119                 rdev->pm.igp_system_mclk.full = dfixed_const(200);
120                 rdev->pm.igp_ht_link_clk.full = dfixed_const(1000);
121                 rdev->pm.igp_ht_link_width.full = dfixed_const(8);
122                 DRM_ERROR("No integrated system info for your GPU, using safe default\n");
123         }
124         /* Compute various bandwidth */
125         /* k8_bandwidth = (memory_clk / 2) * 2 * 8 * 0.5 = memory_clk * 4  */
126         tmp.full = dfixed_const(4);
127         rdev->pm.k8_bandwidth.full = dfixed_mul(rdev->pm.igp_system_mclk, tmp);
128         /* ht_bandwidth = ht_clk * 2 * ht_width / 8 * 0.8
129          *              = ht_clk * ht_width / 5
130          */
131         tmp.full = dfixed_const(5);
132         rdev->pm.ht_bandwidth.full = dfixed_mul(rdev->pm.igp_ht_link_clk,
133                                                 rdev->pm.igp_ht_link_width);
134         rdev->pm.ht_bandwidth.full = dfixed_div(rdev->pm.ht_bandwidth, tmp);
135         if (tmp.full < rdev->pm.max_bandwidth.full) {
136                 /* HT link is a limiting factor */
137                 rdev->pm.max_bandwidth.full = tmp.full;
138         }
139         /* sideport_bandwidth = (sideport_clk / 2) * 2 * 2 * 0.7
140          *                    = (sideport_clk * 14) / 10
141          */
142         tmp.full = dfixed_const(14);
143         rdev->pm.sideport_bandwidth.full = dfixed_mul(rdev->pm.igp_sideport_mclk, tmp);
144         tmp.full = dfixed_const(10);
145         rdev->pm.sideport_bandwidth.full = dfixed_div(rdev->pm.sideport_bandwidth, tmp);
146 }
147
148 void rs690_mc_init(struct radeon_device *rdev)
149 {
150         u64 base;
151
152         rs400_gart_adjust_size(rdev);
153         rdev->mc.vram_is_ddr = true;
154         rdev->mc.vram_width = 128;
155         rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
156         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
157         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
158         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
159         rdev->mc.visible_vram_size = rdev->mc.aper_size;
160         rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
161         base = RREG32_MC(R_000100_MCCFG_FB_LOCATION);
162         base = G_000100_MC_FB_START(base) << 16;
163         rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
164         rs690_pm_info(rdev);
165         radeon_vram_location(rdev, &rdev->mc, base);
166         rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1;
167         radeon_gtt_location(rdev, &rdev->mc);
168         radeon_update_bandwidth_info(rdev);
169 }
170
171 void rs690_line_buffer_adjust(struct radeon_device *rdev,
172                               struct drm_display_mode *mode1,
173                               struct drm_display_mode *mode2)
174 {
175         u32 tmp;
176
177         /*
178          * Line Buffer Setup
179          * There is a single line buffer shared by both display controllers.
180          * R_006520_DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
181          * the display controllers.  The paritioning can either be done
182          * manually or via one of four preset allocations specified in bits 1:0:
183          *  0 - line buffer is divided in half and shared between crtc
184          *  1 - D1 gets 3/4 of the line buffer, D2 gets 1/4
185          *  2 - D1 gets the whole buffer
186          *  3 - D1 gets 1/4 of the line buffer, D2 gets 3/4
187          * Setting bit 2 of R_006520_DC_LB_MEMORY_SPLIT controls switches to manual
188          * allocation mode. In manual allocation mode, D1 always starts at 0,
189          * D1 end/2 is specified in bits 14:4; D2 allocation follows D1.
190          */
191         tmp = RREG32(R_006520_DC_LB_MEMORY_SPLIT) & C_006520_DC_LB_MEMORY_SPLIT;
192         tmp &= ~C_006520_DC_LB_MEMORY_SPLIT_MODE;
193         /* auto */
194         if (mode1 && mode2) {
195                 if (mode1->hdisplay > mode2->hdisplay) {
196                         if (mode1->hdisplay > 2560)
197                                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
198                         else
199                                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
200                 } else if (mode2->hdisplay > mode1->hdisplay) {
201                         if (mode2->hdisplay > 2560)
202                                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
203                         else
204                                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
205                 } else
206                         tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
207         } else if (mode1) {
208                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_ONLY;
209         } else if (mode2) {
210                 tmp |= V_006520_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
211         }
212         WREG32(R_006520_DC_LB_MEMORY_SPLIT, tmp);
213 }
214
215 struct rs690_watermark {
216         u32        lb_request_fifo_depth;
217         fixed20_12 num_line_pair;
218         fixed20_12 estimated_width;
219         fixed20_12 worst_case_latency;
220         fixed20_12 consumption_rate;
221         fixed20_12 active_time;
222         fixed20_12 dbpp;
223         fixed20_12 priority_mark_max;
224         fixed20_12 priority_mark;
225         fixed20_12 sclk;
226 };
227
228 void rs690_crtc_bandwidth_compute(struct radeon_device *rdev,
229                                   struct radeon_crtc *crtc,
230                                   struct rs690_watermark *wm)
231 {
232         struct drm_display_mode *mode = &crtc->base.mode;
233         fixed20_12 a, b, c;
234         fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
235         fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
236
237         if (!crtc->base.enabled) {
238                 /* FIXME: wouldn't it better to set priority mark to maximum */
239                 wm->lb_request_fifo_depth = 4;
240                 return;
241         }
242
243         if (crtc->vsc.full > dfixed_const(2))
244                 wm->num_line_pair.full = dfixed_const(2);
245         else
246                 wm->num_line_pair.full = dfixed_const(1);
247
248         b.full = dfixed_const(mode->crtc_hdisplay);
249         c.full = dfixed_const(256);
250         a.full = dfixed_div(b, c);
251         request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
252         request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
253         if (a.full < dfixed_const(4)) {
254                 wm->lb_request_fifo_depth = 4;
255         } else {
256                 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
257         }
258
259         /* Determine consumption rate
260          *  pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
261          *  vtaps = number of vertical taps,
262          *  vsc = vertical scaling ratio, defined as source/destination
263          *  hsc = horizontal scaling ration, defined as source/destination
264          */
265         a.full = dfixed_const(mode->clock);
266         b.full = dfixed_const(1000);
267         a.full = dfixed_div(a, b);
268         pclk.full = dfixed_div(b, a);
269         if (crtc->rmx_type != RMX_OFF) {
270                 b.full = dfixed_const(2);
271                 if (crtc->vsc.full > b.full)
272                         b.full = crtc->vsc.full;
273                 b.full = dfixed_mul(b, crtc->hsc);
274                 c.full = dfixed_const(2);
275                 b.full = dfixed_div(b, c);
276                 consumption_time.full = dfixed_div(pclk, b);
277         } else {
278                 consumption_time.full = pclk.full;
279         }
280         a.full = dfixed_const(1);
281         wm->consumption_rate.full = dfixed_div(a, consumption_time);
282
283
284         /* Determine line time
285          *  LineTime = total time for one line of displayhtotal
286          *  LineTime = total number of horizontal pixels
287          *  pclk = pixel clock period(ns)
288          */
289         a.full = dfixed_const(crtc->base.mode.crtc_htotal);
290         line_time.full = dfixed_mul(a, pclk);
291
292         /* Determine active time
293          *  ActiveTime = time of active region of display within one line,
294          *  hactive = total number of horizontal active pixels
295          *  htotal = total number of horizontal pixels
296          */
297         a.full = dfixed_const(crtc->base.mode.crtc_htotal);
298         b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
299         wm->active_time.full = dfixed_mul(line_time, b);
300         wm->active_time.full = dfixed_div(wm->active_time, a);
301
302         /* Maximun bandwidth is the minimun bandwidth of all component */
303         rdev->pm.max_bandwidth = rdev->pm.core_bandwidth;
304         if (rdev->mc.igp_sideport_enabled) {
305                 if (rdev->pm.max_bandwidth.full > rdev->pm.sideport_bandwidth.full &&
306                         rdev->pm.sideport_bandwidth.full)
307                         rdev->pm.max_bandwidth = rdev->pm.sideport_bandwidth;
308                 read_delay_latency.full = dfixed_const(370 * 800 * 1000);
309                 read_delay_latency.full = dfixed_div(read_delay_latency,
310                         rdev->pm.igp_sideport_mclk);
311         } else {
312                 if (rdev->pm.max_bandwidth.full > rdev->pm.k8_bandwidth.full &&
313                         rdev->pm.k8_bandwidth.full)
314                         rdev->pm.max_bandwidth = rdev->pm.k8_bandwidth;
315                 if (rdev->pm.max_bandwidth.full > rdev->pm.ht_bandwidth.full &&
316                         rdev->pm.ht_bandwidth.full)
317                         rdev->pm.max_bandwidth = rdev->pm.ht_bandwidth;
318                 read_delay_latency.full = dfixed_const(5000);
319         }
320
321         /* sclk = system clocks(ns) = 1000 / max_bandwidth / 16 */
322         a.full = dfixed_const(16);
323         rdev->pm.sclk.full = dfixed_mul(rdev->pm.max_bandwidth, a);
324         a.full = dfixed_const(1000);
325         rdev->pm.sclk.full = dfixed_div(a, rdev->pm.sclk);
326         /* Determine chunk time
327          * ChunkTime = the time it takes the DCP to send one chunk of data
328          * to the LB which consists of pipeline delay and inter chunk gap
329          * sclk = system clock(ns)
330          */
331         a.full = dfixed_const(256 * 13);
332         chunk_time.full = dfixed_mul(rdev->pm.sclk, a);
333         a.full = dfixed_const(10);
334         chunk_time.full = dfixed_div(chunk_time, a);
335
336         /* Determine the worst case latency
337          * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
338          * WorstCaseLatency = worst case time from urgent to when the MC starts
339          *                    to return data
340          * READ_DELAY_IDLE_MAX = constant of 1us
341          * ChunkTime = time it takes the DCP to send one chunk of data to the LB
342          *             which consists of pipeline delay and inter chunk gap
343          */
344         if (dfixed_trunc(wm->num_line_pair) > 1) {
345                 a.full = dfixed_const(3);
346                 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
347                 wm->worst_case_latency.full += read_delay_latency.full;
348         } else {
349                 a.full = dfixed_const(2);
350                 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
351                 wm->worst_case_latency.full += read_delay_latency.full;
352         }
353
354         /* Determine the tolerable latency
355          * TolerableLatency = Any given request has only 1 line time
356          *                    for the data to be returned
357          * LBRequestFifoDepth = Number of chunk requests the LB can
358          *                      put into the request FIFO for a display
359          *  LineTime = total time for one line of display
360          *  ChunkTime = the time it takes the DCP to send one chunk
361          *              of data to the LB which consists of
362          *  pipeline delay and inter chunk gap
363          */
364         if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
365                 tolerable_latency.full = line_time.full;
366         } else {
367                 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
368                 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
369                 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
370                 tolerable_latency.full = line_time.full - tolerable_latency.full;
371         }
372         /* We assume worst case 32bits (4 bytes) */
373         wm->dbpp.full = dfixed_const(4 * 8);
374
375         /* Determine the maximum priority mark
376          *  width = viewport width in pixels
377          */
378         a.full = dfixed_const(16);
379         wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
380         wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
381         wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
382
383         /* Determine estimated width */
384         estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
385         estimated_width.full = dfixed_div(estimated_width, consumption_time);
386         if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
387                 wm->priority_mark.full = dfixed_const(10);
388         } else {
389                 a.full = dfixed_const(16);
390                 wm->priority_mark.full = dfixed_div(estimated_width, a);
391                 wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
392                 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
393         }
394 }
395
396 void rs690_bandwidth_update(struct radeon_device *rdev)
397 {
398         struct drm_display_mode *mode0 = NULL;
399         struct drm_display_mode *mode1 = NULL;
400         struct rs690_watermark wm0;
401         struct rs690_watermark wm1;
402         u32 tmp;
403         u32 d1mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
404         u32 d2mode_priority_a_cnt = S_006548_D1MODE_PRIORITY_A_OFF(1);
405         fixed20_12 priority_mark02, priority_mark12, fill_rate;
406         fixed20_12 a, b;
407
408         radeon_update_display_priority(rdev);
409
410         if (rdev->mode_info.crtcs[0]->base.enabled)
411                 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
412         if (rdev->mode_info.crtcs[1]->base.enabled)
413                 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
414         /*
415          * Set display0/1 priority up in the memory controller for
416          * modes if the user specifies HIGH for displaypriority
417          * option.
418          */
419         if ((rdev->disp_priority == 2) &&
420             ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))) {
421                 tmp = RREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER);
422                 tmp &= C_000104_MC_DISP0R_INIT_LAT;
423                 tmp &= C_000104_MC_DISP1R_INIT_LAT;
424                 if (mode0)
425                         tmp |= S_000104_MC_DISP0R_INIT_LAT(1);
426                 if (mode1)
427                         tmp |= S_000104_MC_DISP1R_INIT_LAT(1);
428                 WREG32_MC(R_000104_MC_INIT_MISC_LAT_TIMER, tmp);
429         }
430         rs690_line_buffer_adjust(rdev, mode0, mode1);
431
432         if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740))
433                 WREG32(R_006C9C_DCP_CONTROL, 0);
434         if ((rdev->family == CHIP_RS780) || (rdev->family == CHIP_RS880))
435                 WREG32(R_006C9C_DCP_CONTROL, 2);
436
437         rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0);
438         rs690_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1);
439
440         tmp = (wm0.lb_request_fifo_depth - 1);
441         tmp |= (wm1.lb_request_fifo_depth - 1) << 16;
442         WREG32(R_006D58_LB_MAX_REQ_OUTSTANDING, tmp);
443
444         if (mode0 && mode1) {
445                 if (dfixed_trunc(wm0.dbpp) > 64)
446                         a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair);
447                 else
448                         a.full = wm0.num_line_pair.full;
449                 if (dfixed_trunc(wm1.dbpp) > 64)
450                         b.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair);
451                 else
452                         b.full = wm1.num_line_pair.full;
453                 a.full += b.full;
454                 fill_rate.full = dfixed_div(wm0.sclk, a);
455                 if (wm0.consumption_rate.full > fill_rate.full) {
456                         b.full = wm0.consumption_rate.full - fill_rate.full;
457                         b.full = dfixed_mul(b, wm0.active_time);
458                         a.full = dfixed_mul(wm0.worst_case_latency,
459                                                 wm0.consumption_rate);
460                         a.full = a.full + b.full;
461                         b.full = dfixed_const(16 * 1000);
462                         priority_mark02.full = dfixed_div(a, b);
463                 } else {
464                         a.full = dfixed_mul(wm0.worst_case_latency,
465                                                 wm0.consumption_rate);
466                         b.full = dfixed_const(16 * 1000);
467                         priority_mark02.full = dfixed_div(a, b);
468                 }
469                 if (wm1.consumption_rate.full > fill_rate.full) {
470                         b.full = wm1.consumption_rate.full - fill_rate.full;
471                         b.full = dfixed_mul(b, wm1.active_time);
472                         a.full = dfixed_mul(wm1.worst_case_latency,
473                                                 wm1.consumption_rate);
474                         a.full = a.full + b.full;
475                         b.full = dfixed_const(16 * 1000);
476                         priority_mark12.full = dfixed_div(a, b);
477                 } else {
478                         a.full = dfixed_mul(wm1.worst_case_latency,
479                                                 wm1.consumption_rate);
480                         b.full = dfixed_const(16 * 1000);
481                         priority_mark12.full = dfixed_div(a, b);
482                 }
483                 if (wm0.priority_mark.full > priority_mark02.full)
484                         priority_mark02.full = wm0.priority_mark.full;
485                 if (dfixed_trunc(priority_mark02) < 0)
486                         priority_mark02.full = 0;
487                 if (wm0.priority_mark_max.full > priority_mark02.full)
488                         priority_mark02.full = wm0.priority_mark_max.full;
489                 if (wm1.priority_mark.full > priority_mark12.full)
490                         priority_mark12.full = wm1.priority_mark.full;
491                 if (dfixed_trunc(priority_mark12) < 0)
492                         priority_mark12.full = 0;
493                 if (wm1.priority_mark_max.full > priority_mark12.full)
494                         priority_mark12.full = wm1.priority_mark_max.full;
495                 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
496                 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
497                 if (rdev->disp_priority == 2) {
498                         d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
499                         d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
500                 }
501         } else if (mode0) {
502                 if (dfixed_trunc(wm0.dbpp) > 64)
503                         a.full = dfixed_mul(wm0.dbpp, wm0.num_line_pair);
504                 else
505                         a.full = wm0.num_line_pair.full;
506                 fill_rate.full = dfixed_div(wm0.sclk, a);
507                 if (wm0.consumption_rate.full > fill_rate.full) {
508                         b.full = wm0.consumption_rate.full - fill_rate.full;
509                         b.full = dfixed_mul(b, wm0.active_time);
510                         a.full = dfixed_mul(wm0.worst_case_latency,
511                                                 wm0.consumption_rate);
512                         a.full = a.full + b.full;
513                         b.full = dfixed_const(16 * 1000);
514                         priority_mark02.full = dfixed_div(a, b);
515                 } else {
516                         a.full = dfixed_mul(wm0.worst_case_latency,
517                                                 wm0.consumption_rate);
518                         b.full = dfixed_const(16 * 1000);
519                         priority_mark02.full = dfixed_div(a, b);
520                 }
521                 if (wm0.priority_mark.full > priority_mark02.full)
522                         priority_mark02.full = wm0.priority_mark.full;
523                 if (dfixed_trunc(priority_mark02) < 0)
524                         priority_mark02.full = 0;
525                 if (wm0.priority_mark_max.full > priority_mark02.full)
526                         priority_mark02.full = wm0.priority_mark_max.full;
527                 d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
528                 if (rdev->disp_priority == 2)
529                         d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
530         } else if (mode1) {
531                 if (dfixed_trunc(wm1.dbpp) > 64)
532                         a.full = dfixed_mul(wm1.dbpp, wm1.num_line_pair);
533                 else
534                         a.full = wm1.num_line_pair.full;
535                 fill_rate.full = dfixed_div(wm1.sclk, a);
536                 if (wm1.consumption_rate.full > fill_rate.full) {
537                         b.full = wm1.consumption_rate.full - fill_rate.full;
538                         b.full = dfixed_mul(b, wm1.active_time);
539                         a.full = dfixed_mul(wm1.worst_case_latency,
540                                                 wm1.consumption_rate);
541                         a.full = a.full + b.full;
542                         b.full = dfixed_const(16 * 1000);
543                         priority_mark12.full = dfixed_div(a, b);
544                 } else {
545                         a.full = dfixed_mul(wm1.worst_case_latency,
546                                                 wm1.consumption_rate);
547                         b.full = dfixed_const(16 * 1000);
548                         priority_mark12.full = dfixed_div(a, b);
549                 }
550                 if (wm1.priority_mark.full > priority_mark12.full)
551                         priority_mark12.full = wm1.priority_mark.full;
552                 if (dfixed_trunc(priority_mark12) < 0)
553                         priority_mark12.full = 0;
554                 if (wm1.priority_mark_max.full > priority_mark12.full)
555                         priority_mark12.full = wm1.priority_mark_max.full;
556                 d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
557                 if (rdev->disp_priority == 2)
558                         d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
559         }
560
561         WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
562         WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
563         WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
564         WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
565 }
566
567 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg)
568 {
569         uint32_t r;
570
571         WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg));
572         r = RREG32(R_00007C_MC_DATA);
573         WREG32(R_000078_MC_INDEX, ~C_000078_MC_IND_ADDR);
574         return r;
575 }
576
577 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
578 {
579         WREG32(R_000078_MC_INDEX, S_000078_MC_IND_ADDR(reg) |
580                 S_000078_MC_IND_WR_EN(1));
581         WREG32(R_00007C_MC_DATA, v);
582         WREG32(R_000078_MC_INDEX, 0x7F);
583 }
584
585 void rs690_mc_program(struct radeon_device *rdev)
586 {
587         struct rv515_mc_save save;
588
589         /* Stops all mc clients */
590         rv515_mc_stop(rdev, &save);
591
592         /* Wait for mc idle */
593         if (rs690_mc_wait_for_idle(rdev))
594                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
595         /* Program MC, should be a 32bits limited address space */
596         WREG32_MC(R_000100_MCCFG_FB_LOCATION,
597                         S_000100_MC_FB_START(rdev->mc.vram_start >> 16) |
598                         S_000100_MC_FB_TOP(rdev->mc.vram_end >> 16));
599         WREG32(R_000134_HDP_FB_LOCATION,
600                 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
601
602         rv515_mc_resume(rdev, &save);
603 }
604
605 static int rs690_startup(struct radeon_device *rdev)
606 {
607         int r;
608
609         rs690_mc_program(rdev);
610         /* Resume clock */
611         rv515_clock_startup(rdev);
612         /* Initialize GPU configuration (# pipes, ...) */
613         rs690_gpu_init(rdev);
614         /* Initialize GART (initialize after TTM so we can allocate
615          * memory through TTM but finalize after TTM) */
616         r = rs400_gart_enable(rdev);
617         if (r)
618                 return r;
619         /* Enable IRQ */
620         rs600_irq_set(rdev);
621         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
622         /* 1M ring buffer */
623         r = r100_cp_init(rdev, 1024 * 1024);
624         if (r) {
625                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
626                 return r;
627         }
628         r = r100_wb_init(rdev);
629         if (r)
630                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
631         r = r100_ib_init(rdev);
632         if (r) {
633                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
634                 return r;
635         }
636
637         r = r600_audio_init(rdev);
638         if (r) {
639                 dev_err(rdev->dev, "failed initializing audio\n");
640                 return r;
641         }
642
643         return 0;
644 }
645
646 int rs690_resume(struct radeon_device *rdev)
647 {
648         /* Make sur GART are not working */
649         rs400_gart_disable(rdev);
650         /* Resume clock before doing reset */
651         rv515_clock_startup(rdev);
652         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
653         if (radeon_asic_reset(rdev)) {
654                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
655                         RREG32(R_000E40_RBBM_STATUS),
656                         RREG32(R_0007C0_CP_STAT));
657         }
658         /* post */
659         atom_asic_init(rdev->mode_info.atom_context);
660         /* Resume clock after posting */
661         rv515_clock_startup(rdev);
662         /* Initialize surface registers */
663         radeon_surface_init(rdev);
664         return rs690_startup(rdev);
665 }
666
667 int rs690_suspend(struct radeon_device *rdev)
668 {
669         r600_audio_fini(rdev);
670         r100_cp_disable(rdev);
671         r100_wb_disable(rdev);
672         rs600_irq_disable(rdev);
673         rs400_gart_disable(rdev);
674         return 0;
675 }
676
677 void rs690_fini(struct radeon_device *rdev)
678 {
679         r600_audio_fini(rdev);
680         r100_cp_fini(rdev);
681         r100_wb_fini(rdev);
682         r100_ib_fini(rdev);
683         radeon_gem_fini(rdev);
684         rs400_gart_fini(rdev);
685         radeon_irq_kms_fini(rdev);
686         radeon_fence_driver_fini(rdev);
687         radeon_bo_fini(rdev);
688         radeon_atombios_fini(rdev);
689         kfree(rdev->bios);
690         rdev->bios = NULL;
691 }
692
693 int rs690_init(struct radeon_device *rdev)
694 {
695         int r;
696
697         /* Disable VGA */
698         rv515_vga_render_disable(rdev);
699         /* Initialize scratch registers */
700         radeon_scratch_init(rdev);
701         /* Initialize surface registers */
702         radeon_surface_init(rdev);
703         /* restore some register to sane defaults */
704         r100_restore_sanity(rdev);
705         /* TODO: disable VGA need to use VGA request */
706         /* BIOS*/
707         if (!radeon_get_bios(rdev)) {
708                 if (ASIC_IS_AVIVO(rdev))
709                         return -EINVAL;
710         }
711         if (rdev->is_atom_bios) {
712                 r = radeon_atombios_init(rdev);
713                 if (r)
714                         return r;
715         } else {
716                 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
717                 return -EINVAL;
718         }
719         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
720         if (radeon_asic_reset(rdev)) {
721                 dev_warn(rdev->dev,
722                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
723                         RREG32(R_000E40_RBBM_STATUS),
724                         RREG32(R_0007C0_CP_STAT));
725         }
726         /* check if cards are posted or not */
727         if (radeon_boot_test_post_card(rdev) == false)
728                 return -EINVAL;
729
730         /* Initialize clocks */
731         radeon_get_clock_info(rdev->ddev);
732         /* initialize memory controller */
733         rs690_mc_init(rdev);
734         rv515_debugfs(rdev);
735         /* Fence driver */
736         r = radeon_fence_driver_init(rdev);
737         if (r)
738                 return r;
739         r = radeon_irq_kms_init(rdev);
740         if (r)
741                 return r;
742         /* Memory manager */
743         r = radeon_bo_init(rdev);
744         if (r)
745                 return r;
746         r = rs400_gart_init(rdev);
747         if (r)
748                 return r;
749         rs600_set_safe_registers(rdev);
750         rdev->accel_working = true;
751         r = rs690_startup(rdev);
752         if (r) {
753                 /* Somethings want wront with the accel init stop accel */
754                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
755                 r100_cp_fini(rdev);
756                 r100_wb_fini(rdev);
757                 r100_ib_fini(rdev);
758                 rs400_gart_fini(rdev);
759                 radeon_irq_kms_fini(rdev);
760                 rdev->accel_working = false;
761         }
762         return 0;
763 }