cc05b230d7effbbae88524da0d698dace6228ccf
[linux-2.6.git] / drivers / gpu / drm / radeon / rs600.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 /* RS600 / Radeon X1250/X1270 integrated GPU
29  *
30  * This file gather function specific to RS600 which is the IGP of
31  * the X1250/X1270 family supporting intel CPU (while RS690/RS740
32  * is the X1250/X1270 supporting AMD CPU). The display engine are
33  * the avivo one, bios is an atombios, 3D block are the one of the
34  * R4XX family. The GART is different from the RS400 one and is very
35  * close to the one of the R600 family (R600 likely being an evolution
36  * of the RS600 GART block).
37  */
38 #include "drmP.h"
39 #include "radeon.h"
40 #include "radeon_asic.h"
41 #include "atom.h"
42 #include "rs600d.h"
43
44 #include "rs600_reg_safe.h"
45
46 void rs600_gpu_init(struct radeon_device *rdev);
47 int rs600_mc_wait_for_idle(struct radeon_device *rdev);
48
49 void rs600_pm_misc(struct radeon_device *rdev)
50 {
51         int requested_index = rdev->pm.requested_power_state_index;
52         struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
53         struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
54         u32 tmp, dyn_pwrmgt_sclk_length, dyn_sclk_vol_cntl;
55         u32 hdp_dyn_cntl, /*mc_host_dyn_cntl,*/ dyn_backbias_cntl;
56
57         if ((voltage->type == VOLTAGE_GPIO) && (voltage->gpio.valid)) {
58                 if (ps->misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) {
59                         tmp = RREG32(voltage->gpio.reg);
60                         if (voltage->active_high)
61                                 tmp |= voltage->gpio.mask;
62                         else
63                                 tmp &= ~(voltage->gpio.mask);
64                         WREG32(voltage->gpio.reg, tmp);
65                         if (voltage->delay)
66                                 udelay(voltage->delay);
67                 } else {
68                         tmp = RREG32(voltage->gpio.reg);
69                         if (voltage->active_high)
70                                 tmp &= ~voltage->gpio.mask;
71                         else
72                                 tmp |= voltage->gpio.mask;
73                         WREG32(voltage->gpio.reg, tmp);
74                         if (voltage->delay)
75                                 udelay(voltage->delay);
76                 }
77         } else if (voltage->type == VOLTAGE_VDDC)
78                 radeon_atom_set_voltage(rdev, voltage->vddc_id);
79
80         dyn_pwrmgt_sclk_length = RREG32_PLL(DYN_PWRMGT_SCLK_LENGTH);
81         dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_HILEN(0xf);
82         dyn_pwrmgt_sclk_length &= ~REDUCED_POWER_SCLK_LOLEN(0xf);
83         if (ps->misc & ATOM_PM_MISCINFO_ASIC_REDUCED_SPEED_SCLK_EN) {
84                 if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_2) {
85                         dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(2);
86                         dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(2);
87                 } else if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_CLOCK_DIVIDER_BY_4) {
88                         dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(4);
89                         dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(4);
90                 }
91         } else {
92                 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_HILEN(1);
93                 dyn_pwrmgt_sclk_length |= REDUCED_POWER_SCLK_LOLEN(1);
94         }
95         WREG32_PLL(DYN_PWRMGT_SCLK_LENGTH, dyn_pwrmgt_sclk_length);
96
97         dyn_sclk_vol_cntl = RREG32_PLL(DYN_SCLK_VOL_CNTL);
98         if (ps->misc & ATOM_PM_MISCINFO_ASIC_DYNAMIC_VOLTAGE_EN) {
99                 dyn_sclk_vol_cntl |= IO_CG_VOLTAGE_DROP;
100                 if (voltage->delay) {
101                         dyn_sclk_vol_cntl |= VOLTAGE_DROP_SYNC;
102                         dyn_sclk_vol_cntl |= VOLTAGE_DELAY_SEL(voltage->delay);
103                 } else
104                         dyn_sclk_vol_cntl &= ~VOLTAGE_DROP_SYNC;
105         } else
106                 dyn_sclk_vol_cntl &= ~IO_CG_VOLTAGE_DROP;
107         WREG32_PLL(DYN_SCLK_VOL_CNTL, dyn_sclk_vol_cntl);
108
109         hdp_dyn_cntl = RREG32_PLL(HDP_DYN_CNTL);
110         if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_HDP_BLOCK_EN)
111                 hdp_dyn_cntl &= ~HDP_FORCEON;
112         else
113                 hdp_dyn_cntl |= HDP_FORCEON;
114         WREG32_PLL(HDP_DYN_CNTL, hdp_dyn_cntl);
115 #if 0
116         /* mc_host_dyn seems to cause hangs from time to time */
117         mc_host_dyn_cntl = RREG32_PLL(MC_HOST_DYN_CNTL);
118         if (ps->misc & ATOM_PM_MISCINFO_DYNAMIC_MC_HOST_BLOCK_EN)
119                 mc_host_dyn_cntl &= ~MC_HOST_FORCEON;
120         else
121                 mc_host_dyn_cntl |= MC_HOST_FORCEON;
122         WREG32_PLL(MC_HOST_DYN_CNTL, mc_host_dyn_cntl);
123 #endif
124         dyn_backbias_cntl = RREG32_PLL(DYN_BACKBIAS_CNTL);
125         if (ps->misc & ATOM_PM_MISCINFO2_DYNAMIC_BACK_BIAS_EN)
126                 dyn_backbias_cntl |= IO_CG_BACKBIAS_EN;
127         else
128                 dyn_backbias_cntl &= ~IO_CG_BACKBIAS_EN;
129         WREG32_PLL(DYN_BACKBIAS_CNTL, dyn_backbias_cntl);
130
131         /* set pcie lanes */
132         if ((rdev->flags & RADEON_IS_PCIE) &&
133             !(rdev->flags & RADEON_IS_IGP) &&
134             rdev->asic->set_pcie_lanes &&
135             (ps->pcie_lanes !=
136              rdev->pm.power_state[rdev->pm.current_power_state_index].pcie_lanes)) {
137                 radeon_set_pcie_lanes(rdev,
138                                       ps->pcie_lanes);
139                 DRM_DEBUG("Setting: p: %d\n", ps->pcie_lanes);
140         }
141 }
142
143 void rs600_pm_prepare(struct radeon_device *rdev)
144 {
145         struct drm_device *ddev = rdev->ddev;
146         struct drm_crtc *crtc;
147         struct radeon_crtc *radeon_crtc;
148         u32 tmp;
149
150         /* disable any active CRTCs */
151         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
152                 radeon_crtc = to_radeon_crtc(crtc);
153                 if (radeon_crtc->enabled) {
154                         tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
155                         tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
156                         WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
157                 }
158         }
159 }
160
161 void rs600_pm_finish(struct radeon_device *rdev)
162 {
163         struct drm_device *ddev = rdev->ddev;
164         struct drm_crtc *crtc;
165         struct radeon_crtc *radeon_crtc;
166         u32 tmp;
167
168         /* enable any active CRTCs */
169         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
170                 radeon_crtc = to_radeon_crtc(crtc);
171                 if (radeon_crtc->enabled) {
172                         tmp = RREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset);
173                         tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
174                         WREG32(AVIVO_D1CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
175                 }
176         }
177 }
178
179 /* hpd for digital panel detect/disconnect */
180 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
181 {
182         u32 tmp;
183         bool connected = false;
184
185         switch (hpd) {
186         case RADEON_HPD_1:
187                 tmp = RREG32(R_007D04_DC_HOT_PLUG_DETECT1_INT_STATUS);
188                 if (G_007D04_DC_HOT_PLUG_DETECT1_SENSE(tmp))
189                         connected = true;
190                 break;
191         case RADEON_HPD_2:
192                 tmp = RREG32(R_007D14_DC_HOT_PLUG_DETECT2_INT_STATUS);
193                 if (G_007D14_DC_HOT_PLUG_DETECT2_SENSE(tmp))
194                         connected = true;
195                 break;
196         default:
197                 break;
198         }
199         return connected;
200 }
201
202 void rs600_hpd_set_polarity(struct radeon_device *rdev,
203                             enum radeon_hpd_id hpd)
204 {
205         u32 tmp;
206         bool connected = rs600_hpd_sense(rdev, hpd);
207
208         switch (hpd) {
209         case RADEON_HPD_1:
210                 tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
211                 if (connected)
212                         tmp &= ~S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
213                 else
214                         tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_POLARITY(1);
215                 WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
216                 break;
217         case RADEON_HPD_2:
218                 tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
219                 if (connected)
220                         tmp &= ~S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
221                 else
222                         tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_POLARITY(1);
223                 WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
224                 break;
225         default:
226                 break;
227         }
228 }
229
230 void rs600_hpd_init(struct radeon_device *rdev)
231 {
232         struct drm_device *dev = rdev->ddev;
233         struct drm_connector *connector;
234
235         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
236                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
237                 switch (radeon_connector->hpd.hpd) {
238                 case RADEON_HPD_1:
239                         WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
240                                S_007D00_DC_HOT_PLUG_DETECT1_EN(1));
241                         rdev->irq.hpd[0] = true;
242                         break;
243                 case RADEON_HPD_2:
244                         WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
245                                S_007D10_DC_HOT_PLUG_DETECT2_EN(1));
246                         rdev->irq.hpd[1] = true;
247                         break;
248                 default:
249                         break;
250                 }
251         }
252         if (rdev->irq.installed)
253                 rs600_irq_set(rdev);
254 }
255
256 void rs600_hpd_fini(struct radeon_device *rdev)
257 {
258         struct drm_device *dev = rdev->ddev;
259         struct drm_connector *connector;
260
261         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
262                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
263                 switch (radeon_connector->hpd.hpd) {
264                 case RADEON_HPD_1:
265                         WREG32(R_007D00_DC_HOT_PLUG_DETECT1_CONTROL,
266                                S_007D00_DC_HOT_PLUG_DETECT1_EN(0));
267                         rdev->irq.hpd[0] = false;
268                         break;
269                 case RADEON_HPD_2:
270                         WREG32(R_007D10_DC_HOT_PLUG_DETECT2_CONTROL,
271                                S_007D10_DC_HOT_PLUG_DETECT2_EN(0));
272                         rdev->irq.hpd[1] = false;
273                         break;
274                 default:
275                         break;
276                 }
277         }
278 }
279
280 void rs600_bm_disable(struct radeon_device *rdev)
281 {
282         u32 tmp;
283
284         /* disable bus mastering */
285         pci_read_config_word(rdev->pdev, 0x4, (u16*)&tmp);
286         pci_write_config_word(rdev->pdev, 0x4, tmp & 0xFFFB);
287         mdelay(1);
288 }
289
290 int rs600_asic_reset(struct radeon_device *rdev)
291 {
292         u32 status, tmp;
293
294         struct rv515_mc_save save;
295
296         /* Stops all mc clients */
297         rv515_mc_stop(rdev, &save);
298         status = RREG32(R_000E40_RBBM_STATUS);
299         if (!G_000E40_GUI_ACTIVE(status)) {
300                 return 0;
301         }
302         status = RREG32(R_000E40_RBBM_STATUS);
303         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
304         /* stop CP */
305         WREG32(RADEON_CP_CSQ_CNTL, 0);
306         tmp = RREG32(RADEON_CP_RB_CNTL);
307         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
308         WREG32(RADEON_CP_RB_RPTR_WR, 0);
309         WREG32(RADEON_CP_RB_WPTR, 0);
310         WREG32(RADEON_CP_RB_CNTL, tmp);
311         pci_save_state(rdev->pdev);
312         /* disable bus mastering */
313         rs600_bm_disable(rdev);
314         /* reset GA+VAP */
315         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_VAP(1) |
316                                         S_0000F0_SOFT_RESET_GA(1));
317         RREG32(R_0000F0_RBBM_SOFT_RESET);
318         mdelay(500);
319         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
320         mdelay(1);
321         status = RREG32(R_000E40_RBBM_STATUS);
322         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
323         /* reset CP */
324         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_CP(1));
325         RREG32(R_0000F0_RBBM_SOFT_RESET);
326         mdelay(500);
327         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
328         mdelay(1);
329         status = RREG32(R_000E40_RBBM_STATUS);
330         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
331         /* reset MC */
332         WREG32(R_0000F0_RBBM_SOFT_RESET, S_0000F0_SOFT_RESET_MC(1));
333         RREG32(R_0000F0_RBBM_SOFT_RESET);
334         mdelay(500);
335         WREG32(R_0000F0_RBBM_SOFT_RESET, 0);
336         mdelay(1);
337         status = RREG32(R_000E40_RBBM_STATUS);
338         dev_info(rdev->dev, "(%s:%d) RBBM_STATUS=0x%08X\n", __func__, __LINE__, status);
339         /* restore PCI & busmastering */
340         pci_restore_state(rdev->pdev);
341         /* Check if GPU is idle */
342         if (G_000E40_GA_BUSY(status) || G_000E40_VAP_BUSY(status)) {
343                 dev_err(rdev->dev, "failed to reset GPU\n");
344                 rdev->gpu_lockup = true;
345                 return -1;
346         }
347         rv515_mc_resume(rdev, &save);
348         dev_info(rdev->dev, "GPU reset succeed\n");
349         return 0;
350 }
351
352 /*
353  * GART.
354  */
355 void rs600_gart_tlb_flush(struct radeon_device *rdev)
356 {
357         uint32_t tmp;
358
359         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
360         tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
361         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
362
363         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
364         tmp |= S_000100_INVALIDATE_ALL_L1_TLBS(1) | S_000100_INVALIDATE_L2_CACHE(1);
365         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
366
367         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
368         tmp &= C_000100_INVALIDATE_ALL_L1_TLBS & C_000100_INVALIDATE_L2_CACHE;
369         WREG32_MC(R_000100_MC_PT0_CNTL, tmp);
370         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
371 }
372
373 int rs600_gart_init(struct radeon_device *rdev)
374 {
375         int r;
376
377         if (rdev->gart.table.vram.robj) {
378                 WARN(1, "RS600 GART already initialized.\n");
379                 return 0;
380         }
381         /* Initialize common gart structure */
382         r = radeon_gart_init(rdev);
383         if (r) {
384                 return r;
385         }
386         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
387         return radeon_gart_table_vram_alloc(rdev);
388 }
389
390 int rs600_gart_enable(struct radeon_device *rdev)
391 {
392         u32 tmp;
393         int r, i;
394
395         if (rdev->gart.table.vram.robj == NULL) {
396                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
397                 return -EINVAL;
398         }
399         r = radeon_gart_table_vram_pin(rdev);
400         if (r)
401                 return r;
402         radeon_gart_restore(rdev);
403         /* Enable bus master */
404         tmp = RREG32(R_00004C_BUS_CNTL) & C_00004C_BUS_MASTER_DIS;
405         WREG32(R_00004C_BUS_CNTL, tmp);
406         /* FIXME: setup default page */
407         WREG32_MC(R_000100_MC_PT0_CNTL,
408                   (S_000100_EFFECTIVE_L2_CACHE_SIZE(6) |
409                    S_000100_EFFECTIVE_L2_QUEUE_SIZE(6)));
410
411         for (i = 0; i < 19; i++) {
412                 WREG32_MC(R_00016C_MC_PT0_CLIENT0_CNTL + i,
413                           S_00016C_ENABLE_TRANSLATION_MODE_OVERRIDE(1) |
414                           S_00016C_SYSTEM_ACCESS_MODE_MASK(
415                                   V_00016C_SYSTEM_ACCESS_MODE_NOT_IN_SYS) |
416                           S_00016C_SYSTEM_APERTURE_UNMAPPED_ACCESS(
417                                   V_00016C_SYSTEM_APERTURE_UNMAPPED_PASSTHROUGH) |
418                           S_00016C_EFFECTIVE_L1_CACHE_SIZE(3) |
419                           S_00016C_ENABLE_FRAGMENT_PROCESSING(1) |
420                           S_00016C_EFFECTIVE_L1_QUEUE_SIZE(3));
421         }
422         /* enable first context */
423         WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL,
424                   S_000102_ENABLE_PAGE_TABLE(1) |
425                   S_000102_PAGE_TABLE_DEPTH(V_000102_PAGE_TABLE_FLAT));
426
427         /* disable all other contexts */
428         for (i = 1; i < 8; i++)
429                 WREG32_MC(R_000102_MC_PT0_CONTEXT0_CNTL + i, 0);
430
431         /* setup the page table */
432         WREG32_MC(R_00012C_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
433                   rdev->gart.table_addr);
434         WREG32_MC(R_00013C_MC_PT0_CONTEXT0_FLAT_START_ADDR, rdev->mc.gtt_start);
435         WREG32_MC(R_00014C_MC_PT0_CONTEXT0_FLAT_END_ADDR, rdev->mc.gtt_end);
436         WREG32_MC(R_00011C_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
437
438         /* System context maps to VRAM space */
439         WREG32_MC(R_000112_MC_PT0_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start);
440         WREG32_MC(R_000114_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end);
441
442         /* enable page tables */
443         tmp = RREG32_MC(R_000100_MC_PT0_CNTL);
444         WREG32_MC(R_000100_MC_PT0_CNTL, (tmp | S_000100_ENABLE_PT(1)));
445         tmp = RREG32_MC(R_000009_MC_CNTL1);
446         WREG32_MC(R_000009_MC_CNTL1, (tmp | S_000009_ENABLE_PAGE_TABLES(1)));
447         rs600_gart_tlb_flush(rdev);
448         rdev->gart.ready = true;
449         return 0;
450 }
451
452 void rs600_gart_disable(struct radeon_device *rdev)
453 {
454         u32 tmp;
455         int r;
456
457         /* FIXME: disable out of gart access */
458         WREG32_MC(R_000100_MC_PT0_CNTL, 0);
459         tmp = RREG32_MC(R_000009_MC_CNTL1);
460         WREG32_MC(R_000009_MC_CNTL1, tmp & C_000009_ENABLE_PAGE_TABLES);
461         if (rdev->gart.table.vram.robj) {
462                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
463                 if (r == 0) {
464                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
465                         radeon_bo_unpin(rdev->gart.table.vram.robj);
466                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
467                 }
468         }
469 }
470
471 void rs600_gart_fini(struct radeon_device *rdev)
472 {
473         radeon_gart_fini(rdev);
474         rs600_gart_disable(rdev);
475         radeon_gart_table_vram_free(rdev);
476 }
477
478 #define R600_PTE_VALID     (1 << 0)
479 #define R600_PTE_SYSTEM    (1 << 1)
480 #define R600_PTE_SNOOPED   (1 << 2)
481 #define R600_PTE_READABLE  (1 << 5)
482 #define R600_PTE_WRITEABLE (1 << 6)
483
484 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
485 {
486         void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
487
488         if (i < 0 || i > rdev->gart.num_gpu_pages) {
489                 return -EINVAL;
490         }
491         addr = addr & 0xFFFFFFFFFFFFF000ULL;
492         addr |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
493         addr |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
494         writeq(addr, ((void __iomem *)ptr) + (i * 8));
495         return 0;
496 }
497
498 int rs600_irq_set(struct radeon_device *rdev)
499 {
500         uint32_t tmp = 0;
501         uint32_t mode_int = 0;
502         u32 hpd1 = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL) &
503                 ~S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
504         u32 hpd2 = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL) &
505                 ~S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
506
507         if (!rdev->irq.installed) {
508                 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
509                 WREG32(R_000040_GEN_INT_CNTL, 0);
510                 return -EINVAL;
511         }
512         if (rdev->irq.sw_int) {
513                 tmp |= S_000040_SW_INT_EN(1);
514         }
515         if (rdev->irq.gui_idle) {
516                 tmp |= S_000040_GUI_IDLE(1);
517         }
518         if (rdev->irq.crtc_vblank_int[0]) {
519                 mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
520         }
521         if (rdev->irq.crtc_vblank_int[1]) {
522                 mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
523         }
524         if (rdev->irq.hpd[0]) {
525                 hpd1 |= S_007D08_DC_HOT_PLUG_DETECT1_INT_EN(1);
526         }
527         if (rdev->irq.hpd[1]) {
528                 hpd2 |= S_007D18_DC_HOT_PLUG_DETECT2_INT_EN(1);
529         }
530         WREG32(R_000040_GEN_INT_CNTL, tmp);
531         WREG32(R_006540_DxMODE_INT_MASK, mode_int);
532         WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
533         WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
534         return 0;
535 }
536
537 static inline uint32_t rs600_irq_ack(struct radeon_device *rdev, u32 *r500_disp_int)
538 {
539         uint32_t irqs = RREG32(R_000044_GEN_INT_STATUS);
540         uint32_t irq_mask = S_000044_SW_INT(1);
541         u32 tmp;
542
543         /* the interrupt works, but the status bit is permanently asserted */
544         if (rdev->irq.gui_idle && radeon_gui_idle(rdev)) {
545                 if (!rdev->irq.gui_idle_acked)
546                         irq_mask |= S_000044_GUI_IDLE_STAT(1);
547         }
548
549         if (G_000044_DISPLAY_INT_STAT(irqs)) {
550                 *r500_disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS);
551                 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(*r500_disp_int)) {
552                         WREG32(R_006534_D1MODE_VBLANK_STATUS,
553                                 S_006534_D1MODE_VBLANK_ACK(1));
554                 }
555                 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(*r500_disp_int)) {
556                         WREG32(R_006D34_D2MODE_VBLANK_STATUS,
557                                 S_006D34_D2MODE_VBLANK_ACK(1));
558                 }
559                 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(*r500_disp_int)) {
560                         tmp = RREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL);
561                         tmp |= S_007D08_DC_HOT_PLUG_DETECT1_INT_ACK(1);
562                         WREG32(R_007D08_DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
563                 }
564                 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(*r500_disp_int)) {
565                         tmp = RREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL);
566                         tmp |= S_007D18_DC_HOT_PLUG_DETECT2_INT_ACK(1);
567                         WREG32(R_007D18_DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
568                 }
569         } else {
570                 *r500_disp_int = 0;
571         }
572
573         if (irqs) {
574                 WREG32(R_000044_GEN_INT_STATUS, irqs);
575         }
576         return irqs & irq_mask;
577 }
578
579 void rs600_irq_disable(struct radeon_device *rdev)
580 {
581         u32 tmp;
582
583         WREG32(R_000040_GEN_INT_CNTL, 0);
584         WREG32(R_006540_DxMODE_INT_MASK, 0);
585         /* Wait and acknowledge irq */
586         mdelay(1);
587         rs600_irq_ack(rdev, &tmp);
588 }
589
590 int rs600_irq_process(struct radeon_device *rdev)
591 {
592         uint32_t status, msi_rearm;
593         uint32_t r500_disp_int;
594         bool queue_hotplug = false;
595
596         /* reset gui idle ack.  the status bit is broken */
597         rdev->irq.gui_idle_acked = false;
598
599         status = rs600_irq_ack(rdev, &r500_disp_int);
600         if (!status && !r500_disp_int) {
601                 return IRQ_NONE;
602         }
603         while (status || r500_disp_int) {
604                 /* SW interrupt */
605                 if (G_000044_SW_INT(status))
606                         radeon_fence_process(rdev);
607                 /* GUI idle */
608                 if (G_000040_GUI_IDLE(status)) {
609                         rdev->irq.gui_idle_acked = true;
610                         rdev->pm.gui_idle = true;
611                         wake_up(&rdev->irq.idle_queue);
612                 }
613                 /* Vertical blank interrupts */
614                 if (G_007EDC_LB_D1_VBLANK_INTERRUPT(r500_disp_int)) {
615                         drm_handle_vblank(rdev->ddev, 0);
616                         rdev->pm.vblank_sync = true;
617                         wake_up(&rdev->irq.vblank_queue);
618                 }
619                 if (G_007EDC_LB_D2_VBLANK_INTERRUPT(r500_disp_int)) {
620                         drm_handle_vblank(rdev->ddev, 1);
621                         rdev->pm.vblank_sync = true;
622                         wake_up(&rdev->irq.vblank_queue);
623                 }
624                 if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(r500_disp_int)) {
625                         queue_hotplug = true;
626                         DRM_DEBUG("HPD1\n");
627                 }
628                 if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(r500_disp_int)) {
629                         queue_hotplug = true;
630                         DRM_DEBUG("HPD2\n");
631                 }
632                 status = rs600_irq_ack(rdev, &r500_disp_int);
633         }
634         /* reset gui idle ack.  the status bit is broken */
635         rdev->irq.gui_idle_acked = false;
636         if (queue_hotplug)
637                 queue_work(rdev->wq, &rdev->hotplug_work);
638         if (rdev->msi_enabled) {
639                 switch (rdev->family) {
640                 case CHIP_RS600:
641                 case CHIP_RS690:
642                 case CHIP_RS740:
643                         msi_rearm = RREG32(RADEON_BUS_CNTL) & ~RS600_MSI_REARM;
644                         WREG32(RADEON_BUS_CNTL, msi_rearm);
645                         WREG32(RADEON_BUS_CNTL, msi_rearm | RS600_MSI_REARM);
646                         break;
647                 default:
648                         msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
649                         WREG32(RADEON_MSI_REARM_EN, msi_rearm);
650                         WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
651                         break;
652                 }
653         }
654         return IRQ_HANDLED;
655 }
656
657 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc)
658 {
659         if (crtc == 0)
660                 return RREG32(R_0060A4_D1CRTC_STATUS_FRAME_COUNT);
661         else
662                 return RREG32(R_0068A4_D2CRTC_STATUS_FRAME_COUNT);
663 }
664
665 int rs600_mc_wait_for_idle(struct radeon_device *rdev)
666 {
667         unsigned i;
668
669         for (i = 0; i < rdev->usec_timeout; i++) {
670                 if (G_000000_MC_IDLE(RREG32_MC(R_000000_MC_STATUS)))
671                         return 0;
672                 udelay(1);
673         }
674         return -1;
675 }
676
677 void rs600_gpu_init(struct radeon_device *rdev)
678 {
679         r420_pipes_init(rdev);
680         /* Wait for mc idle */
681         if (rs600_mc_wait_for_idle(rdev))
682                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
683 }
684
685 void rs600_mc_init(struct radeon_device *rdev)
686 {
687         u64 base;
688
689         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
690         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
691         rdev->mc.vram_is_ddr = true;
692         rdev->mc.vram_width = 128;
693         rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
694         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
695         rdev->mc.visible_vram_size = rdev->mc.aper_size;
696         rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
697         base = RREG32_MC(R_000004_MC_FB_LOCATION);
698         base = G_000004_MC_FB_START(base) << 16;
699         radeon_vram_location(rdev, &rdev->mc, base);
700         rdev->mc.gtt_base_align = 0;
701         radeon_gtt_location(rdev, &rdev->mc);
702         radeon_update_bandwidth_info(rdev);
703 }
704
705 void rs600_bandwidth_update(struct radeon_device *rdev)
706 {
707         struct drm_display_mode *mode0 = NULL;
708         struct drm_display_mode *mode1 = NULL;
709         u32 d1mode_priority_a_cnt, d2mode_priority_a_cnt;
710         /* FIXME: implement full support */
711
712         radeon_update_display_priority(rdev);
713
714         if (rdev->mode_info.crtcs[0]->base.enabled)
715                 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
716         if (rdev->mode_info.crtcs[1]->base.enabled)
717                 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
718
719         rs690_line_buffer_adjust(rdev, mode0, mode1);
720
721         if (rdev->disp_priority == 2) {
722                 d1mode_priority_a_cnt = RREG32(R_006548_D1MODE_PRIORITY_A_CNT);
723                 d2mode_priority_a_cnt = RREG32(R_006D48_D2MODE_PRIORITY_A_CNT);
724                 d1mode_priority_a_cnt |= S_006548_D1MODE_PRIORITY_A_ALWAYS_ON(1);
725                 d2mode_priority_a_cnt |= S_006D48_D2MODE_PRIORITY_A_ALWAYS_ON(1);
726                 WREG32(R_006548_D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
727                 WREG32(R_00654C_D1MODE_PRIORITY_B_CNT, d1mode_priority_a_cnt);
728                 WREG32(R_006D48_D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
729                 WREG32(R_006D4C_D2MODE_PRIORITY_B_CNT, d2mode_priority_a_cnt);
730         }
731 }
732
733 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg)
734 {
735         WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
736                 S_000070_MC_IND_CITF_ARB0(1));
737         return RREG32(R_000074_MC_IND_DATA);
738 }
739
740 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
741 {
742         WREG32(R_000070_MC_IND_INDEX, S_000070_MC_IND_ADDR(reg) |
743                 S_000070_MC_IND_CITF_ARB0(1) | S_000070_MC_IND_WR_EN(1));
744         WREG32(R_000074_MC_IND_DATA, v);
745 }
746
747 void rs600_debugfs(struct radeon_device *rdev)
748 {
749         if (r100_debugfs_rbbm_init(rdev))
750                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
751 }
752
753 void rs600_set_safe_registers(struct radeon_device *rdev)
754 {
755         rdev->config.r300.reg_safe_bm = rs600_reg_safe_bm;
756         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rs600_reg_safe_bm);
757 }
758
759 static void rs600_mc_program(struct radeon_device *rdev)
760 {
761         struct rv515_mc_save save;
762
763         /* Stops all mc clients */
764         rv515_mc_stop(rdev, &save);
765
766         /* Wait for mc idle */
767         if (rs600_mc_wait_for_idle(rdev))
768                 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
769
770         /* FIXME: What does AGP means for such chipset ? */
771         WREG32_MC(R_000005_MC_AGP_LOCATION, 0x0FFFFFFF);
772         WREG32_MC(R_000006_AGP_BASE, 0);
773         WREG32_MC(R_000007_AGP_BASE_2, 0);
774         /* Program MC */
775         WREG32_MC(R_000004_MC_FB_LOCATION,
776                         S_000004_MC_FB_START(rdev->mc.vram_start >> 16) |
777                         S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16));
778         WREG32(R_000134_HDP_FB_LOCATION,
779                 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
780
781         rv515_mc_resume(rdev, &save);
782 }
783
784 static int rs600_startup(struct radeon_device *rdev)
785 {
786         int r;
787
788         rs600_mc_program(rdev);
789         /* Resume clock */
790         rv515_clock_startup(rdev);
791         /* Initialize GPU configuration (# pipes, ...) */
792         rs600_gpu_init(rdev);
793         /* Initialize GART (initialize after TTM so we can allocate
794          * memory through TTM but finalize after TTM) */
795         r = rs600_gart_enable(rdev);
796         if (r)
797                 return r;
798         /* Enable IRQ */
799         rs600_irq_set(rdev);
800         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
801         /* 1M ring buffer */
802         r = r100_cp_init(rdev, 1024 * 1024);
803         if (r) {
804                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
805                 return r;
806         }
807         r = r100_wb_init(rdev);
808         if (r)
809                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
810         r = r100_ib_init(rdev);
811         if (r) {
812                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
813                 return r;
814         }
815
816         r = r600_audio_init(rdev);
817         if (r) {
818                 dev_err(rdev->dev, "failed initializing audio\n");
819                 return r;
820         }
821
822         return 0;
823 }
824
825 int rs600_resume(struct radeon_device *rdev)
826 {
827         /* Make sur GART are not working */
828         rs600_gart_disable(rdev);
829         /* Resume clock before doing reset */
830         rv515_clock_startup(rdev);
831         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
832         if (radeon_asic_reset(rdev)) {
833                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
834                         RREG32(R_000E40_RBBM_STATUS),
835                         RREG32(R_0007C0_CP_STAT));
836         }
837         /* post */
838         atom_asic_init(rdev->mode_info.atom_context);
839         /* Resume clock after posting */
840         rv515_clock_startup(rdev);
841         /* Initialize surface registers */
842         radeon_surface_init(rdev);
843         return rs600_startup(rdev);
844 }
845
846 int rs600_suspend(struct radeon_device *rdev)
847 {
848         r600_audio_fini(rdev);
849         r100_cp_disable(rdev);
850         r100_wb_disable(rdev);
851         rs600_irq_disable(rdev);
852         rs600_gart_disable(rdev);
853         return 0;
854 }
855
856 void rs600_fini(struct radeon_device *rdev)
857 {
858         r600_audio_fini(rdev);
859         r100_cp_fini(rdev);
860         r100_wb_fini(rdev);
861         r100_ib_fini(rdev);
862         radeon_gem_fini(rdev);
863         rs600_gart_fini(rdev);
864         radeon_irq_kms_fini(rdev);
865         radeon_fence_driver_fini(rdev);
866         radeon_bo_fini(rdev);
867         radeon_atombios_fini(rdev);
868         kfree(rdev->bios);
869         rdev->bios = NULL;
870 }
871
872 int rs600_init(struct radeon_device *rdev)
873 {
874         int r;
875
876         /* Disable VGA */
877         rv515_vga_render_disable(rdev);
878         /* Initialize scratch registers */
879         radeon_scratch_init(rdev);
880         /* Initialize surface registers */
881         radeon_surface_init(rdev);
882         /* restore some register to sane defaults */
883         r100_restore_sanity(rdev);
884         /* BIOS */
885         if (!radeon_get_bios(rdev)) {
886                 if (ASIC_IS_AVIVO(rdev))
887                         return -EINVAL;
888         }
889         if (rdev->is_atom_bios) {
890                 r = radeon_atombios_init(rdev);
891                 if (r)
892                         return r;
893         } else {
894                 dev_err(rdev->dev, "Expecting atombios for RS600 GPU\n");
895                 return -EINVAL;
896         }
897         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
898         if (radeon_asic_reset(rdev)) {
899                 dev_warn(rdev->dev,
900                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
901                         RREG32(R_000E40_RBBM_STATUS),
902                         RREG32(R_0007C0_CP_STAT));
903         }
904         /* check if cards are posted or not */
905         if (radeon_boot_test_post_card(rdev) == false)
906                 return -EINVAL;
907
908         /* Initialize clocks */
909         radeon_get_clock_info(rdev->ddev);
910         /* initialize memory controller */
911         rs600_mc_init(rdev);
912         rs600_debugfs(rdev);
913         /* Fence driver */
914         r = radeon_fence_driver_init(rdev);
915         if (r)
916                 return r;
917         r = radeon_irq_kms_init(rdev);
918         if (r)
919                 return r;
920         /* Memory manager */
921         r = radeon_bo_init(rdev);
922         if (r)
923                 return r;
924         r = rs600_gart_init(rdev);
925         if (r)
926                 return r;
927         rs600_set_safe_registers(rdev);
928         rdev->accel_working = true;
929         r = rs600_startup(rdev);
930         if (r) {
931                 /* Somethings want wront with the accel init stop accel */
932                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
933                 r100_cp_fini(rdev);
934                 r100_wb_fini(rdev);
935                 r100_ib_fini(rdev);
936                 rs600_gart_fini(rdev);
937                 radeon_irq_kms_fini(rdev);
938                 rdev->accel_working = false;
939         }
940         return 0;
941 }