drm/radeon: add support for evergreen/ni tiling informations v11
[linux-2.6.git] / drivers / gpu / drm / radeon / radeon_object.c
1 /*
2  * Copyright 2009 Jerome Glisse.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sub license, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
20  *
21  * The above copyright notice and this permission notice (including the
22  * next paragraph) shall be included in all copies or substantial portions
23  * of the Software.
24  *
25  */
26 /*
27  * Authors:
28  *    Jerome Glisse <glisse@freedesktop.org>
29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30  *    Dave Airlie
31  */
32 #include <linux/list.h>
33 #include <linux/slab.h>
34 #include <drm/drmP.h>
35 #include "radeon_drm.h"
36 #include "radeon.h"
37 #include "radeon_trace.h"
38
39
40 int radeon_ttm_init(struct radeon_device *rdev);
41 void radeon_ttm_fini(struct radeon_device *rdev);
42 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
43
44 /*
45  * To exclude mutual BO access we rely on bo_reserve exclusion, as all
46  * function are calling it.
47  */
48
49 void radeon_bo_clear_va(struct radeon_bo *bo)
50 {
51         struct radeon_bo_va *bo_va, *tmp;
52
53         list_for_each_entry_safe(bo_va, tmp, &bo->va, bo_list) {
54                 /* remove from all vm address space */
55                 mutex_lock(&bo_va->vm->mutex);
56                 list_del(&bo_va->vm_list);
57                 mutex_unlock(&bo_va->vm->mutex);
58                 list_del(&bo_va->bo_list);
59                 kfree(bo_va);
60         }
61 }
62
63 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
64 {
65         struct radeon_bo *bo;
66
67         bo = container_of(tbo, struct radeon_bo, tbo);
68         mutex_lock(&bo->rdev->gem.mutex);
69         list_del_init(&bo->list);
70         mutex_unlock(&bo->rdev->gem.mutex);
71         radeon_bo_clear_surface_reg(bo);
72         radeon_bo_clear_va(bo);
73         drm_gem_object_release(&bo->gem_base);
74         kfree(bo);
75 }
76
77 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
78 {
79         if (bo->destroy == &radeon_ttm_bo_destroy)
80                 return true;
81         return false;
82 }
83
84 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
85 {
86         u32 c = 0;
87
88         rbo->placement.fpfn = 0;
89         rbo->placement.lpfn = 0;
90         rbo->placement.placement = rbo->placements;
91         rbo->placement.busy_placement = rbo->placements;
92         if (domain & RADEON_GEM_DOMAIN_VRAM)
93                 rbo->placements[c++] = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
94                                         TTM_PL_FLAG_VRAM;
95         if (domain & RADEON_GEM_DOMAIN_GTT)
96                 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_TT;
97         if (domain & RADEON_GEM_DOMAIN_CPU)
98                 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
99         if (!c)
100                 rbo->placements[c++] = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
101         rbo->placement.num_placement = c;
102         rbo->placement.num_busy_placement = c;
103 }
104
105 int radeon_bo_create(struct radeon_device *rdev,
106                      unsigned long size, int byte_align, bool kernel, u32 domain,
107                      struct radeon_bo **bo_ptr)
108 {
109         struct radeon_bo *bo;
110         enum ttm_bo_type type;
111         unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
112         unsigned long max_size = 0;
113         size_t acc_size;
114         int r;
115
116         size = ALIGN(size, PAGE_SIZE);
117
118         if (unlikely(rdev->mman.bdev.dev_mapping == NULL)) {
119                 rdev->mman.bdev.dev_mapping = rdev->ddev->dev_mapping;
120         }
121         if (kernel) {
122                 type = ttm_bo_type_kernel;
123         } else {
124                 type = ttm_bo_type_device;
125         }
126         *bo_ptr = NULL;
127
128         /* maximun bo size is the minimun btw visible vram and gtt size */
129         max_size = min(rdev->mc.visible_vram_size, rdev->mc.gtt_size);
130         if ((page_align << PAGE_SHIFT) >= max_size) {
131                 printk(KERN_WARNING "%s:%d alloc size %ldM bigger than %ldMb limit\n",
132                         __func__, __LINE__, page_align  >> (20 - PAGE_SHIFT), max_size >> 20);
133                 return -ENOMEM;
134         }
135
136         acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
137                                        sizeof(struct radeon_bo));
138
139 retry:
140         bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
141         if (bo == NULL)
142                 return -ENOMEM;
143         r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
144         if (unlikely(r)) {
145                 kfree(bo);
146                 return r;
147         }
148         bo->rdev = rdev;
149         bo->gem_base.driver_private = NULL;
150         bo->surface_reg = -1;
151         INIT_LIST_HEAD(&bo->list);
152         INIT_LIST_HEAD(&bo->va);
153         radeon_ttm_placement_from_domain(bo, domain);
154         /* Kernel allocation are uninterruptible */
155         mutex_lock(&rdev->vram_mutex);
156         r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
157                         &bo->placement, page_align, 0, !kernel, NULL,
158                         acc_size, &radeon_ttm_bo_destroy);
159         mutex_unlock(&rdev->vram_mutex);
160         if (unlikely(r != 0)) {
161                 if (r != -ERESTARTSYS) {
162                         if (domain == RADEON_GEM_DOMAIN_VRAM) {
163                                 domain |= RADEON_GEM_DOMAIN_GTT;
164                                 goto retry;
165                         }
166                         dev_err(rdev->dev,
167                                 "object_init failed for (%lu, 0x%08X)\n",
168                                 size, domain);
169                 }
170                 return r;
171         }
172         *bo_ptr = bo;
173
174         trace_radeon_bo_create(bo);
175
176         return 0;
177 }
178
179 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
180 {
181         bool is_iomem;
182         int r;
183
184         if (bo->kptr) {
185                 if (ptr) {
186                         *ptr = bo->kptr;
187                 }
188                 return 0;
189         }
190         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
191         if (r) {
192                 return r;
193         }
194         bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
195         if (ptr) {
196                 *ptr = bo->kptr;
197         }
198         radeon_bo_check_tiling(bo, 0, 0);
199         return 0;
200 }
201
202 void radeon_bo_kunmap(struct radeon_bo *bo)
203 {
204         if (bo->kptr == NULL)
205                 return;
206         bo->kptr = NULL;
207         radeon_bo_check_tiling(bo, 0, 0);
208         ttm_bo_kunmap(&bo->kmap);
209 }
210
211 void radeon_bo_unref(struct radeon_bo **bo)
212 {
213         struct ttm_buffer_object *tbo;
214         struct radeon_device *rdev;
215
216         if ((*bo) == NULL)
217                 return;
218         rdev = (*bo)->rdev;
219         tbo = &((*bo)->tbo);
220         mutex_lock(&rdev->vram_mutex);
221         ttm_bo_unref(&tbo);
222         mutex_unlock(&rdev->vram_mutex);
223         if (tbo == NULL)
224                 *bo = NULL;
225 }
226
227 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
228 {
229         int r, i;
230
231         if (bo->pin_count) {
232                 bo->pin_count++;
233                 if (gpu_addr)
234                         *gpu_addr = radeon_bo_gpu_offset(bo);
235                 return 0;
236         }
237         radeon_ttm_placement_from_domain(bo, domain);
238         if (domain == RADEON_GEM_DOMAIN_VRAM) {
239                 /* force to pin into visible video ram */
240                 bo->placement.lpfn = bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
241         }
242         for (i = 0; i < bo->placement.num_placement; i++)
243                 bo->placements[i] |= TTM_PL_FLAG_NO_EVICT;
244         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
245         if (likely(r == 0)) {
246                 bo->pin_count = 1;
247                 if (gpu_addr != NULL)
248                         *gpu_addr = radeon_bo_gpu_offset(bo);
249         }
250         if (unlikely(r != 0))
251                 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
252         return r;
253 }
254
255 int radeon_bo_unpin(struct radeon_bo *bo)
256 {
257         int r, i;
258
259         if (!bo->pin_count) {
260                 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
261                 return 0;
262         }
263         bo->pin_count--;
264         if (bo->pin_count)
265                 return 0;
266         for (i = 0; i < bo->placement.num_placement; i++)
267                 bo->placements[i] &= ~TTM_PL_FLAG_NO_EVICT;
268         r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false, false);
269         if (unlikely(r != 0))
270                 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
271         return r;
272 }
273
274 int radeon_bo_evict_vram(struct radeon_device *rdev)
275 {
276         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
277         if (0 && (rdev->flags & RADEON_IS_IGP)) {
278                 if (rdev->mc.igp_sideport_enabled == false)
279                         /* Useless to evict on IGP chips */
280                         return 0;
281         }
282         return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
283 }
284
285 void radeon_bo_force_delete(struct radeon_device *rdev)
286 {
287         struct radeon_bo *bo, *n;
288
289         if (list_empty(&rdev->gem.objects)) {
290                 return;
291         }
292         dev_err(rdev->dev, "Userspace still has active objects !\n");
293         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
294                 mutex_lock(&rdev->ddev->struct_mutex);
295                 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
296                         &bo->gem_base, bo, (unsigned long)bo->gem_base.size,
297                         *((unsigned long *)&bo->gem_base.refcount));
298                 mutex_lock(&bo->rdev->gem.mutex);
299                 list_del_init(&bo->list);
300                 mutex_unlock(&bo->rdev->gem.mutex);
301                 /* this should unref the ttm bo */
302                 drm_gem_object_unreference(&bo->gem_base);
303                 mutex_unlock(&rdev->ddev->struct_mutex);
304         }
305 }
306
307 int radeon_bo_init(struct radeon_device *rdev)
308 {
309         /* Add an MTRR for the VRAM */
310         rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
311                         MTRR_TYPE_WRCOMB, 1);
312         DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
313                 rdev->mc.mc_vram_size >> 20,
314                 (unsigned long long)rdev->mc.aper_size >> 20);
315         DRM_INFO("RAM width %dbits %cDR\n",
316                         rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
317         return radeon_ttm_init(rdev);
318 }
319
320 void radeon_bo_fini(struct radeon_device *rdev)
321 {
322         radeon_ttm_fini(rdev);
323 }
324
325 void radeon_bo_list_add_object(struct radeon_bo_list *lobj,
326                                 struct list_head *head)
327 {
328         if (lobj->wdomain) {
329                 list_add(&lobj->tv.head, head);
330         } else {
331                 list_add_tail(&lobj->tv.head, head);
332         }
333 }
334
335 int radeon_bo_list_validate(struct list_head *head)
336 {
337         struct radeon_bo_list *lobj;
338         struct radeon_bo *bo;
339         u32 domain;
340         int r;
341
342         r = ttm_eu_reserve_buffers(head);
343         if (unlikely(r != 0)) {
344                 return r;
345         }
346         list_for_each_entry(lobj, head, tv.head) {
347                 bo = lobj->bo;
348                 if (!bo->pin_count) {
349                         domain = lobj->wdomain ? lobj->wdomain : lobj->rdomain;
350                         
351                 retry:
352                         radeon_ttm_placement_from_domain(bo, domain);
353                         r = ttm_bo_validate(&bo->tbo, &bo->placement,
354                                                 true, false, false);
355                         if (unlikely(r)) {
356                                 if (r != -ERESTARTSYS && domain == RADEON_GEM_DOMAIN_VRAM) {
357                                         domain |= RADEON_GEM_DOMAIN_GTT;
358                                         goto retry;
359                                 }
360                                 return r;
361                         }
362                 }
363                 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
364                 lobj->tiling_flags = bo->tiling_flags;
365         }
366         return 0;
367 }
368
369 int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
370                              struct vm_area_struct *vma)
371 {
372         return ttm_fbdev_mmap(vma, &bo->tbo);
373 }
374
375 int radeon_bo_get_surface_reg(struct radeon_bo *bo)
376 {
377         struct radeon_device *rdev = bo->rdev;
378         struct radeon_surface_reg *reg;
379         struct radeon_bo *old_object;
380         int steal;
381         int i;
382
383         BUG_ON(!atomic_read(&bo->tbo.reserved));
384
385         if (!bo->tiling_flags)
386                 return 0;
387
388         if (bo->surface_reg >= 0) {
389                 reg = &rdev->surface_regs[bo->surface_reg];
390                 i = bo->surface_reg;
391                 goto out;
392         }
393
394         steal = -1;
395         for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
396
397                 reg = &rdev->surface_regs[i];
398                 if (!reg->bo)
399                         break;
400
401                 old_object = reg->bo;
402                 if (old_object->pin_count == 0)
403                         steal = i;
404         }
405
406         /* if we are all out */
407         if (i == RADEON_GEM_MAX_SURFACES) {
408                 if (steal == -1)
409                         return -ENOMEM;
410                 /* find someone with a surface reg and nuke their BO */
411                 reg = &rdev->surface_regs[steal];
412                 old_object = reg->bo;
413                 /* blow away the mapping */
414                 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
415                 ttm_bo_unmap_virtual(&old_object->tbo);
416                 old_object->surface_reg = -1;
417                 i = steal;
418         }
419
420         bo->surface_reg = i;
421         reg->bo = bo;
422
423 out:
424         radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
425                                bo->tbo.mem.start << PAGE_SHIFT,
426                                bo->tbo.num_pages << PAGE_SHIFT);
427         return 0;
428 }
429
430 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
431 {
432         struct radeon_device *rdev = bo->rdev;
433         struct radeon_surface_reg *reg;
434
435         if (bo->surface_reg == -1)
436                 return;
437
438         reg = &rdev->surface_regs[bo->surface_reg];
439         radeon_clear_surface_reg(rdev, bo->surface_reg);
440
441         reg->bo = NULL;
442         bo->surface_reg = -1;
443 }
444
445 int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
446                                 uint32_t tiling_flags, uint32_t pitch)
447 {
448         struct radeon_device *rdev = bo->rdev;
449         int r;
450
451         if (rdev->family >= CHIP_CEDAR) {
452                 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
453
454                 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
455                 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
456                 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
457                 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
458                 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
459                 switch (bankw) {
460                 case 0:
461                 case 1:
462                 case 2:
463                 case 4:
464                 case 8:
465                         break;
466                 default:
467                         return -EINVAL;
468                 }
469                 switch (bankh) {
470                 case 0:
471                 case 1:
472                 case 2:
473                 case 4:
474                 case 8:
475                         break;
476                 default:
477                         return -EINVAL;
478                 }
479                 switch (mtaspect) {
480                 case 0:
481                 case 1:
482                 case 2:
483                 case 4:
484                 case 8:
485                         break;
486                 default:
487                         return -EINVAL;
488                 }
489                 if (tilesplit > 6) {
490                         return -EINVAL;
491                 }
492                 if (stilesplit > 6) {
493                         return -EINVAL;
494                 }
495         }
496         r = radeon_bo_reserve(bo, false);
497         if (unlikely(r != 0))
498                 return r;
499         bo->tiling_flags = tiling_flags;
500         bo->pitch = pitch;
501         radeon_bo_unreserve(bo);
502         return 0;
503 }
504
505 void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
506                                 uint32_t *tiling_flags,
507                                 uint32_t *pitch)
508 {
509         BUG_ON(!atomic_read(&bo->tbo.reserved));
510         if (tiling_flags)
511                 *tiling_flags = bo->tiling_flags;
512         if (pitch)
513                 *pitch = bo->pitch;
514 }
515
516 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
517                                 bool force_drop)
518 {
519         BUG_ON(!atomic_read(&bo->tbo.reserved));
520
521         if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
522                 return 0;
523
524         if (force_drop) {
525                 radeon_bo_clear_surface_reg(bo);
526                 return 0;
527         }
528
529         if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
530                 if (!has_moved)
531                         return 0;
532
533                 if (bo->surface_reg >= 0)
534                         radeon_bo_clear_surface_reg(bo);
535                 return 0;
536         }
537
538         if ((bo->surface_reg >= 0) && !has_moved)
539                 return 0;
540
541         return radeon_bo_get_surface_reg(bo);
542 }
543
544 void radeon_bo_move_notify(struct ttm_buffer_object *bo,
545                            struct ttm_mem_reg *mem)
546 {
547         struct radeon_bo *rbo;
548         if (!radeon_ttm_bo_is_radeon_bo(bo))
549                 return;
550         rbo = container_of(bo, struct radeon_bo, tbo);
551         radeon_bo_check_tiling(rbo, 0, 1);
552         radeon_vm_bo_invalidate(rbo->rdev, rbo);
553 }
554
555 int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
556 {
557         struct radeon_device *rdev;
558         struct radeon_bo *rbo;
559         unsigned long offset, size;
560         int r;
561
562         if (!radeon_ttm_bo_is_radeon_bo(bo))
563                 return 0;
564         rbo = container_of(bo, struct radeon_bo, tbo);
565         radeon_bo_check_tiling(rbo, 0, 0);
566         rdev = rbo->rdev;
567         if (bo->mem.mem_type == TTM_PL_VRAM) {
568                 size = bo->mem.num_pages << PAGE_SHIFT;
569                 offset = bo->mem.start << PAGE_SHIFT;
570                 if ((offset + size) > rdev->mc.visible_vram_size) {
571                         /* hurrah the memory is not visible ! */
572                         radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
573                         rbo->placement.lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
574                         r = ttm_bo_validate(bo, &rbo->placement, false, true, false);
575                         if (unlikely(r != 0))
576                                 return r;
577                         offset = bo->mem.start << PAGE_SHIFT;
578                         /* this should not happen */
579                         if ((offset + size) > rdev->mc.visible_vram_size)
580                                 return -EINVAL;
581                 }
582         }
583         return 0;
584 }
585
586 int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
587 {
588         int r;
589
590         r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
591         if (unlikely(r != 0))
592                 return r;
593         spin_lock(&bo->tbo.bdev->fence_lock);
594         if (mem_type)
595                 *mem_type = bo->tbo.mem.mem_type;
596         if (bo->tbo.sync_obj)
597                 r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
598         spin_unlock(&bo->tbo.bdev->fence_lock);
599         ttm_bo_unreserve(&bo->tbo);
600         return r;
601 }
602
603
604 /**
605  * radeon_bo_reserve - reserve bo
606  * @bo:         bo structure
607  * @no_wait:            don't sleep while trying to reserve (return -EBUSY)
608  *
609  * Returns:
610  * -EBUSY: buffer is busy and @no_wait is true
611  * -ERESTARTSYS: A wait for the buffer to become unreserved was interrupted by
612  * a signal. Release all buffer reservations and return to user-space.
613  */
614 int radeon_bo_reserve(struct radeon_bo *bo, bool no_wait)
615 {
616         int r;
617
618         r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, 0);
619         if (unlikely(r != 0)) {
620                 if (r != -ERESTARTSYS)
621                         dev_err(bo->rdev->dev, "%p reserve failed\n", bo);
622                 return r;
623         }
624         return 0;
625 }
626
627 /* object have to be reserved */
628 struct radeon_bo_va *radeon_bo_va(struct radeon_bo *rbo, struct radeon_vm *vm)
629 {
630         struct radeon_bo_va *bo_va;
631
632         list_for_each_entry(bo_va, &rbo->va, bo_list) {
633                 if (bo_va->vm == vm) {
634                         return bo_va;
635                 }
636         }
637         return NULL;
638 }