762e07b08951cc76b7aa4b0b1589b99abf8bab30
[linux-2.6.git] / drivers / gpu / drm / radeon / radeon_legacy_crtc.c
1 /*
2  * Copyright 2007-8 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: Dave Airlie
24  *          Alex Deucher
25  */
26 #include <drm/drmP.h>
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
29 #include "radeon_fixed.h"
30 #include "radeon.h"
31 #include "atom.h"
32
33 static void radeon_overscan_setup(struct drm_crtc *crtc,
34                                   struct drm_display_mode *mode)
35 {
36         struct drm_device *dev = crtc->dev;
37         struct radeon_device *rdev = dev->dev_private;
38         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
39
40         WREG32(RADEON_OVR_CLR + radeon_crtc->crtc_offset, 0);
41         WREG32(RADEON_OVR_WID_LEFT_RIGHT + radeon_crtc->crtc_offset, 0);
42         WREG32(RADEON_OVR_WID_TOP_BOTTOM + radeon_crtc->crtc_offset, 0);
43 }
44
45 static void radeon_legacy_rmx_mode_set(struct drm_crtc *crtc,
46                                        struct drm_display_mode *mode)
47 {
48         struct drm_device *dev = crtc->dev;
49         struct radeon_device *rdev = dev->dev_private;
50         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
51         int xres = mode->hdisplay;
52         int yres = mode->vdisplay;
53         bool hscale = true, vscale = true;
54         int hsync_wid;
55         int vsync_wid;
56         int hsync_start;
57         int blank_width;
58         u32 scale, inc, crtc_more_cntl;
59         u32 fp_horz_stretch, fp_vert_stretch, fp_horz_vert_active;
60         u32 fp_h_sync_strt_wid, fp_crtc_h_total_disp;
61         u32 fp_v_sync_strt_wid, fp_crtc_v_total_disp;
62         struct drm_display_mode *native_mode = &radeon_crtc->native_mode;
63
64         fp_vert_stretch = RREG32(RADEON_FP_VERT_STRETCH) &
65                 (RADEON_VERT_STRETCH_RESERVED |
66                  RADEON_VERT_AUTO_RATIO_INC);
67         fp_horz_stretch = RREG32(RADEON_FP_HORZ_STRETCH) &
68                 (RADEON_HORZ_FP_LOOP_STRETCH |
69                  RADEON_HORZ_AUTO_RATIO_INC);
70
71         crtc_more_cntl = 0;
72         if ((rdev->family == CHIP_RS100) ||
73             (rdev->family == CHIP_RS200)) {
74                 /* This is to workaround the asic bug for RMX, some versions
75                    of BIOS dosen't have this register initialized correctly. */
76                 crtc_more_cntl |= RADEON_CRTC_H_CUTOFF_ACTIVE_EN;
77         }
78
79
80         fp_crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
81                                 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
82
83         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
84         if (!hsync_wid)
85                 hsync_wid = 1;
86         hsync_start = mode->crtc_hsync_start - 8;
87
88         fp_h_sync_strt_wid = ((hsync_start & 0x1fff)
89                               | ((hsync_wid & 0x3f) << 16)
90                               | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
91                                  ? RADEON_CRTC_H_SYNC_POL
92                                  : 0));
93
94         fp_crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
95                                 | ((mode->crtc_vdisplay - 1) << 16));
96
97         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
98         if (!vsync_wid)
99                 vsync_wid = 1;
100
101         fp_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
102                               | ((vsync_wid & 0x1f) << 16)
103                               | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
104                                  ? RADEON_CRTC_V_SYNC_POL
105                                  : 0));
106
107         fp_horz_vert_active = 0;
108
109         if (native_mode->hdisplay == 0 ||
110             native_mode->vdisplay == 0) {
111                 hscale = false;
112                 vscale = false;
113         } else {
114                 if (xres > native_mode->hdisplay)
115                         xres = native_mode->hdisplay;
116                 if (yres > native_mode->vdisplay)
117                         yres = native_mode->vdisplay;
118
119                 if (xres == native_mode->hdisplay)
120                         hscale = false;
121                 if (yres == native_mode->vdisplay)
122                         vscale = false;
123         }
124
125         switch (radeon_crtc->rmx_type) {
126         case RMX_FULL:
127         case RMX_ASPECT:
128                 if (!hscale)
129                         fp_horz_stretch |= ((xres/8-1) << 16);
130                 else {
131                         inc = (fp_horz_stretch & RADEON_HORZ_AUTO_RATIO_INC) ? 1 : 0;
132                         scale = ((xres + inc) * RADEON_HORZ_STRETCH_RATIO_MAX)
133                                 / native_mode->hdisplay + 1;
134                         fp_horz_stretch |= (((scale) & RADEON_HORZ_STRETCH_RATIO_MASK) |
135                                         RADEON_HORZ_STRETCH_BLEND |
136                                         RADEON_HORZ_STRETCH_ENABLE |
137                                         ((native_mode->hdisplay/8-1) << 16));
138                 }
139
140                 if (!vscale)
141                         fp_vert_stretch |= ((yres-1) << 12);
142                 else {
143                         inc = (fp_vert_stretch & RADEON_VERT_AUTO_RATIO_INC) ? 1 : 0;
144                         scale = ((yres + inc) * RADEON_VERT_STRETCH_RATIO_MAX)
145                                 / native_mode->vdisplay + 1;
146                         fp_vert_stretch |= (((scale) & RADEON_VERT_STRETCH_RATIO_MASK) |
147                                         RADEON_VERT_STRETCH_ENABLE |
148                                         RADEON_VERT_STRETCH_BLEND |
149                                         ((native_mode->vdisplay-1) << 12));
150                 }
151                 break;
152         case RMX_CENTER:
153                 fp_horz_stretch |= ((xres/8-1) << 16);
154                 fp_vert_stretch |= ((yres-1) << 12);
155
156                 crtc_more_cntl |= (RADEON_CRTC_AUTO_HORZ_CENTER_EN |
157                                 RADEON_CRTC_AUTO_VERT_CENTER_EN);
158
159                 blank_width = (mode->crtc_hblank_end - mode->crtc_hblank_start) / 8;
160                 if (blank_width > 110)
161                         blank_width = 110;
162
163                 fp_crtc_h_total_disp = (((blank_width) & 0x3ff)
164                                 | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
165
166                 hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
167                 if (!hsync_wid)
168                         hsync_wid = 1;
169
170                 fp_h_sync_strt_wid = ((((mode->crtc_hsync_start - mode->crtc_hblank_start) / 8) & 0x1fff)
171                                 | ((hsync_wid & 0x3f) << 16)
172                                 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
173                                         ? RADEON_CRTC_H_SYNC_POL
174                                         : 0));
175
176                 fp_crtc_v_total_disp = (((mode->crtc_vblank_end - mode->crtc_vblank_start) & 0xffff)
177                                 | ((mode->crtc_vdisplay - 1) << 16));
178
179                 vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
180                 if (!vsync_wid)
181                         vsync_wid = 1;
182
183                 fp_v_sync_strt_wid = ((((mode->crtc_vsync_start - mode->crtc_vblank_start) & 0xfff)
184                                         | ((vsync_wid & 0x1f) << 16)
185                                         | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
186                                                 ? RADEON_CRTC_V_SYNC_POL
187                                                 : 0)));
188
189                 fp_horz_vert_active = (((native_mode->vdisplay) & 0xfff) |
190                                 (((native_mode->hdisplay / 8) & 0x1ff) << 16));
191                 break;
192         case RMX_OFF:
193         default:
194                 fp_horz_stretch |= ((xres/8-1) << 16);
195                 fp_vert_stretch |= ((yres-1) << 12);
196                 break;
197         }
198
199         WREG32(RADEON_FP_HORZ_STRETCH,      fp_horz_stretch);
200         WREG32(RADEON_FP_VERT_STRETCH,      fp_vert_stretch);
201         WREG32(RADEON_CRTC_MORE_CNTL,       crtc_more_cntl);
202         WREG32(RADEON_FP_HORZ_VERT_ACTIVE,  fp_horz_vert_active);
203         WREG32(RADEON_FP_H_SYNC_STRT_WID,   fp_h_sync_strt_wid);
204         WREG32(RADEON_FP_V_SYNC_STRT_WID,   fp_v_sync_strt_wid);
205         WREG32(RADEON_FP_CRTC_H_TOTAL_DISP, fp_crtc_h_total_disp);
206         WREG32(RADEON_FP_CRTC_V_TOTAL_DISP, fp_crtc_v_total_disp);
207 }
208
209 void radeon_restore_common_regs(struct drm_device *dev)
210 {
211         /* don't need this yet */
212 }
213
214 static void radeon_pll_wait_for_read_update_complete(struct drm_device *dev)
215 {
216         struct radeon_device *rdev = dev->dev_private;
217         int i = 0;
218
219         /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
220            the cause yet, but this workaround will mask the problem for now.
221            Other chips usually will pass at the very first test, so the
222            workaround shouldn't have any effect on them. */
223         for (i = 0;
224              (i < 10000 &&
225               RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
226              i++);
227 }
228
229 static void radeon_pll_write_update(struct drm_device *dev)
230 {
231         struct radeon_device *rdev = dev->dev_private;
232
233         while (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_ATOMIC_UPDATE_R);
234
235         WREG32_PLL_P(RADEON_PPLL_REF_DIV,
236                            RADEON_PPLL_ATOMIC_UPDATE_W,
237                            ~(RADEON_PPLL_ATOMIC_UPDATE_W));
238 }
239
240 static void radeon_pll2_wait_for_read_update_complete(struct drm_device *dev)
241 {
242         struct radeon_device *rdev = dev->dev_private;
243         int i = 0;
244
245
246         /* FIXME: Certain revisions of R300 can't recover here.  Not sure of
247            the cause yet, but this workaround will mask the problem for now.
248            Other chips usually will pass at the very first test, so the
249            workaround shouldn't have any effect on them. */
250         for (i = 0;
251              (i < 10000 &&
252               RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
253              i++);
254 }
255
256 static void radeon_pll2_write_update(struct drm_device *dev)
257 {
258         struct radeon_device *rdev = dev->dev_private;
259
260         while (RREG32_PLL(RADEON_P2PLL_REF_DIV) & RADEON_P2PLL_ATOMIC_UPDATE_R);
261
262         WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
263                            RADEON_P2PLL_ATOMIC_UPDATE_W,
264                            ~(RADEON_P2PLL_ATOMIC_UPDATE_W));
265 }
266
267 static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div,
268                                        uint16_t fb_div)
269 {
270         unsigned int vcoFreq;
271
272         if (!ref_div)
273                 return 1;
274
275         vcoFreq = ((unsigned)ref_freq & fb_div) / ref_div;
276
277         /*
278          * This is horribly crude: the VCO frequency range is divided into
279          * 3 parts, each part having a fixed PLL gain value.
280          */
281         if (vcoFreq >= 30000)
282                 /*
283                  * [300..max] MHz : 7
284                  */
285                 return 7;
286         else if (vcoFreq >= 18000)
287                 /*
288                  * [180..300) MHz : 4
289                  */
290                 return 4;
291         else
292                 /*
293                  * [0..180) MHz : 1
294                  */
295                 return 1;
296 }
297
298 void radeon_crtc_dpms(struct drm_crtc *crtc, int mode)
299 {
300         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
301         struct drm_device *dev = crtc->dev;
302         struct radeon_device *rdev = dev->dev_private;
303         uint32_t mask;
304
305         if (radeon_crtc->crtc_id)
306                 mask = (RADEON_CRTC2_DISP_DIS |
307                         RADEON_CRTC2_VSYNC_DIS |
308                         RADEON_CRTC2_HSYNC_DIS |
309                         RADEON_CRTC2_DISP_REQ_EN_B);
310         else
311                 mask = (RADEON_CRTC_DISPLAY_DIS |
312                         RADEON_CRTC_VSYNC_DIS |
313                         RADEON_CRTC_HSYNC_DIS);
314
315         switch (mode) {
316         case DRM_MODE_DPMS_ON:
317                 if (radeon_crtc->crtc_id)
318                         WREG32_P(RADEON_CRTC2_GEN_CNTL, RADEON_CRTC2_EN, ~(RADEON_CRTC2_EN | mask));
319                 else {
320                         WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_EN, ~(RADEON_CRTC_EN |
321                                                                          RADEON_CRTC_DISP_REQ_EN_B));
322                         WREG32_P(RADEON_CRTC_EXT_CNTL, 0, ~mask);
323                 }
324                 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
325                 radeon_crtc_load_lut(crtc);
326                 break;
327         case DRM_MODE_DPMS_STANDBY:
328         case DRM_MODE_DPMS_SUSPEND:
329         case DRM_MODE_DPMS_OFF:
330                 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
331                 if (radeon_crtc->crtc_id)
332                         WREG32_P(RADEON_CRTC2_GEN_CNTL, mask, ~(RADEON_CRTC2_EN | mask));
333                 else {
334                         WREG32_P(RADEON_CRTC_GEN_CNTL, RADEON_CRTC_DISP_REQ_EN_B, ~(RADEON_CRTC_EN |
335                                                                                     RADEON_CRTC_DISP_REQ_EN_B));
336                         WREG32_P(RADEON_CRTC_EXT_CNTL, mask, ~mask);
337                 }
338                 break;
339         }
340 }
341
342 int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
343                          struct drm_framebuffer *old_fb)
344 {
345         struct drm_device *dev = crtc->dev;
346         struct radeon_device *rdev = dev->dev_private;
347         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
348         struct radeon_framebuffer *radeon_fb;
349         struct drm_gem_object *obj;
350         struct radeon_bo *rbo;
351         uint64_t base;
352         uint32_t crtc_offset, crtc_offset_cntl, crtc_tile_x0_y0 = 0;
353         uint32_t crtc_pitch, pitch_pixels;
354         uint32_t tiling_flags;
355         int format;
356         uint32_t gen_cntl_reg, gen_cntl_val;
357         int r;
358
359         DRM_DEBUG("\n");
360         /* no fb bound */
361         if (!crtc->fb) {
362                 DRM_DEBUG("No FB bound\n");
363                 return 0;
364         }
365
366         radeon_fb = to_radeon_framebuffer(crtc->fb);
367
368         switch (crtc->fb->bits_per_pixel) {
369         case 8:
370                 format = 2;
371                 break;
372         case 15:      /*  555 */
373                 format = 3;
374                 break;
375         case 16:      /*  565 */
376                 format = 4;
377                 break;
378         case 24:      /*  RGB */
379                 format = 5;
380                 break;
381         case 32:      /* xRGB */
382                 format = 6;
383                 break;
384         default:
385                 return false;
386         }
387
388         /* Pin framebuffer & get tilling informations */
389         obj = radeon_fb->obj;
390         rbo = obj->driver_private;
391         r = radeon_bo_reserve(rbo, false);
392         if (unlikely(r != 0))
393                 return r;
394         r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base);
395         if (unlikely(r != 0)) {
396                 radeon_bo_unreserve(rbo);
397                 return -EINVAL;
398         }
399         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
400         radeon_bo_unreserve(rbo);
401         if (tiling_flags & RADEON_TILING_MICRO)
402                 DRM_ERROR("trying to scanout microtiled buffer\n");
403
404         /* if scanout was in GTT this really wouldn't work */
405         /* crtc offset is from display base addr not FB location */
406         radeon_crtc->legacy_display_base_addr = rdev->mc.vram_location;
407
408         base -= radeon_crtc->legacy_display_base_addr;
409
410         crtc_offset_cntl = 0;
411
412         pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
413         crtc_pitch  = (((pitch_pixels * crtc->fb->bits_per_pixel) +
414                         ((crtc->fb->bits_per_pixel * 8) - 1)) /
415                        (crtc->fb->bits_per_pixel * 8));
416         crtc_pitch |= crtc_pitch << 16;
417
418
419         if (tiling_flags & RADEON_TILING_MACRO) {
420                 if (ASIC_IS_R300(rdev))
421                         crtc_offset_cntl |= (R300_CRTC_X_Y_MODE_EN |
422                                              R300_CRTC_MICRO_TILE_BUFFER_DIS |
423                                              R300_CRTC_MACRO_TILE_EN);
424                 else
425                         crtc_offset_cntl |= RADEON_CRTC_TILE_EN;
426         } else {
427                 if (ASIC_IS_R300(rdev))
428                         crtc_offset_cntl &= ~(R300_CRTC_X_Y_MODE_EN |
429                                               R300_CRTC_MICRO_TILE_BUFFER_DIS |
430                                               R300_CRTC_MACRO_TILE_EN);
431                 else
432                         crtc_offset_cntl &= ~RADEON_CRTC_TILE_EN;
433         }
434
435         if (tiling_flags & RADEON_TILING_MACRO) {
436                 if (ASIC_IS_R300(rdev)) {
437                         crtc_tile_x0_y0 = x | (y << 16);
438                         base &= ~0x7ff;
439                 } else {
440                         int byteshift = crtc->fb->bits_per_pixel >> 4;
441                         int tile_addr = (((y >> 3) * pitch_pixels +  x) >> (8 - byteshift)) << 11;
442                         base += tile_addr + ((x << byteshift) % 256) + ((y % 8) << 8);
443                         crtc_offset_cntl |= (y % 16);
444                 }
445         } else {
446                 int offset = y * pitch_pixels + x;
447                 switch (crtc->fb->bits_per_pixel) {
448                 case 8:
449                         offset *= 1;
450                         break;
451                 case 15:
452                 case 16:
453                         offset *= 2;
454                         break;
455                 case 24:
456                         offset *= 3;
457                         break;
458                 case 32:
459                         offset *= 4;
460                         break;
461                 default:
462                         return false;
463                 }
464                 base += offset;
465         }
466
467         base &= ~7;
468
469         if (radeon_crtc->crtc_id == 1)
470                 gen_cntl_reg = RADEON_CRTC2_GEN_CNTL;
471         else
472                 gen_cntl_reg = RADEON_CRTC_GEN_CNTL;
473
474         gen_cntl_val = RREG32(gen_cntl_reg);
475         gen_cntl_val &= ~(0xf << 8);
476         gen_cntl_val |= (format << 8);
477         WREG32(gen_cntl_reg, gen_cntl_val);
478
479         crtc_offset = (u32)base;
480
481         WREG32(RADEON_DISPLAY_BASE_ADDR + radeon_crtc->crtc_offset, radeon_crtc->legacy_display_base_addr);
482
483         if (ASIC_IS_R300(rdev)) {
484                 if (radeon_crtc->crtc_id)
485                         WREG32(R300_CRTC2_TILE_X0_Y0, crtc_tile_x0_y0);
486                 else
487                         WREG32(R300_CRTC_TILE_X0_Y0, crtc_tile_x0_y0);
488         }
489         WREG32(RADEON_CRTC_OFFSET_CNTL + radeon_crtc->crtc_offset, crtc_offset_cntl);
490         WREG32(RADEON_CRTC_OFFSET + radeon_crtc->crtc_offset, crtc_offset);
491         WREG32(RADEON_CRTC_PITCH + radeon_crtc->crtc_offset, crtc_pitch);
492
493         if (old_fb && old_fb != crtc->fb) {
494                 radeon_fb = to_radeon_framebuffer(old_fb);
495                 rbo = radeon_fb->obj->driver_private;
496                 r = radeon_bo_reserve(rbo, false);
497                 if (unlikely(r != 0))
498                         return r;
499                 radeon_bo_unpin(rbo);
500                 radeon_bo_unreserve(rbo);
501         }
502
503         /* Bytes per pixel may have changed */
504         radeon_bandwidth_update(rdev);
505
506         return 0;
507 }
508
509 static bool radeon_set_crtc_timing(struct drm_crtc *crtc, struct drm_display_mode *mode)
510 {
511         struct drm_device *dev = crtc->dev;
512         struct radeon_device *rdev = dev->dev_private;
513         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
514         struct drm_encoder *encoder;
515         int format;
516         int hsync_start;
517         int hsync_wid;
518         int vsync_wid;
519         uint32_t crtc_h_total_disp;
520         uint32_t crtc_h_sync_strt_wid;
521         uint32_t crtc_v_total_disp;
522         uint32_t crtc_v_sync_strt_wid;
523         bool is_tv = false;
524
525         DRM_DEBUG("\n");
526         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
527                 if (encoder->crtc == crtc) {
528                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
529                         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
530                                 is_tv = true;
531                                 DRM_INFO("crtc %d is connected to a TV\n", radeon_crtc->crtc_id);
532                                 break;
533                         }
534                 }
535         }
536
537         switch (crtc->fb->bits_per_pixel) {
538         case 8:
539                 format = 2;
540                 break;
541         case 15:      /*  555 */
542                 format = 3;
543                 break;
544         case 16:      /*  565 */
545                 format = 4;
546                 break;
547         case 24:      /*  RGB */
548                 format = 5;
549                 break;
550         case 32:      /* xRGB */
551                 format = 6;
552                 break;
553         default:
554                 return false;
555         }
556
557         crtc_h_total_disp = ((((mode->crtc_htotal / 8) - 1) & 0x3ff)
558                              | ((((mode->crtc_hdisplay / 8) - 1) & 0x1ff) << 16));
559
560         hsync_wid = (mode->crtc_hsync_end - mode->crtc_hsync_start) / 8;
561         if (!hsync_wid)
562                 hsync_wid = 1;
563         hsync_start = mode->crtc_hsync_start - 8;
564
565         crtc_h_sync_strt_wid = ((hsync_start & 0x1fff)
566                                 | ((hsync_wid & 0x3f) << 16)
567                                 | ((mode->flags & DRM_MODE_FLAG_NHSYNC)
568                                    ? RADEON_CRTC_H_SYNC_POL
569                                    : 0));
570
571         /* This works for double scan mode. */
572         crtc_v_total_disp = (((mode->crtc_vtotal - 1) & 0xffff)
573                              | ((mode->crtc_vdisplay - 1) << 16));
574
575         vsync_wid = mode->crtc_vsync_end - mode->crtc_vsync_start;
576         if (!vsync_wid)
577                 vsync_wid = 1;
578
579         crtc_v_sync_strt_wid = (((mode->crtc_vsync_start - 1) & 0xfff)
580                                 | ((vsync_wid & 0x1f) << 16)
581                                 | ((mode->flags & DRM_MODE_FLAG_NVSYNC)
582                                    ? RADEON_CRTC_V_SYNC_POL
583                                    : 0));
584
585         /* TODO -> Dell Server */
586         if (0) {
587                 uint32_t disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
588                 uint32_t tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
589                 uint32_t dac2_cntl = RREG32(RADEON_DAC_CNTL2);
590                 uint32_t crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
591
592                 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
593                 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
594
595                 /* For CRT on DAC2, don't turn it on if BIOS didn't
596                    enable it, even it's detected.
597                 */
598                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
599                 tv_dac_cntl &= ~((1<<2) | (3<<8) | (7<<24) | (0xff<<16));
600                 tv_dac_cntl |= (0x03 | (2<<8) | (0x58<<16));
601
602                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
603                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
604                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
605                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
606         }
607
608         if (radeon_crtc->crtc_id) {
609                 uint32_t crtc2_gen_cntl;
610                 uint32_t disp2_merge_cntl;
611
612                 /* if TV DAC is enabled for another crtc and keep it enabled */
613                 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL) & 0x00718080;
614                 crtc2_gen_cntl |= ((format << 8)
615                                    | RADEON_CRTC2_VSYNC_DIS
616                                    | RADEON_CRTC2_HSYNC_DIS
617                                    | RADEON_CRTC2_DISP_DIS
618                                    | RADEON_CRTC2_DISP_REQ_EN_B
619                                    | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
620                                       ? RADEON_CRTC2_DBL_SCAN_EN
621                                       : 0)
622                                    | ((mode->flags & DRM_MODE_FLAG_CSYNC)
623                                       ? RADEON_CRTC2_CSYNC_EN
624                                       : 0)
625                                    | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
626                                       ? RADEON_CRTC2_INTERLACE_EN
627                                       : 0));
628
629                 disp2_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
630                 disp2_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
631
632                 WREG32(RADEON_DISP2_MERGE_CNTL, disp2_merge_cntl);
633                 WREG32(RADEON_CRTC2_GEN_CNTL, crtc2_gen_cntl);
634
635                 WREG32(RADEON_FP_H2_SYNC_STRT_WID, crtc_h_sync_strt_wid);
636                 WREG32(RADEON_FP_V2_SYNC_STRT_WID, crtc_v_sync_strt_wid);
637         } else {
638                 uint32_t crtc_gen_cntl;
639                 uint32_t crtc_ext_cntl;
640                 uint32_t disp_merge_cntl;
641
642                 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL) & 0x00718000;
643                 crtc_gen_cntl |= (RADEON_CRTC_EXT_DISP_EN
644                                  | (format << 8)
645                                  | RADEON_CRTC_DISP_REQ_EN_B
646                                  | ((mode->flags & DRM_MODE_FLAG_DBLSCAN)
647                                     ? RADEON_CRTC_DBL_SCAN_EN
648                                     : 0)
649                                  | ((mode->flags & DRM_MODE_FLAG_CSYNC)
650                                     ? RADEON_CRTC_CSYNC_EN
651                                     : 0)
652                                  | ((mode->flags & DRM_MODE_FLAG_INTERLACE)
653                                     ? RADEON_CRTC_INTERLACE_EN
654                                     : 0));
655
656                 crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
657                 crtc_ext_cntl |= (RADEON_XCRT_CNT_EN |
658                                   RADEON_CRTC_VSYNC_DIS |
659                                   RADEON_CRTC_HSYNC_DIS |
660                                   RADEON_CRTC_DISPLAY_DIS);
661
662                 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
663                 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
664
665                 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
666                 WREG32(RADEON_CRTC_GEN_CNTL, crtc_gen_cntl);
667                 WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl);
668         }
669
670         if (is_tv)
671                 radeon_legacy_tv_adjust_crtc_reg(encoder, &crtc_h_total_disp,
672                                                  &crtc_h_sync_strt_wid, &crtc_v_total_disp,
673                                                  &crtc_v_sync_strt_wid);
674
675         WREG32(RADEON_CRTC_H_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_h_total_disp);
676         WREG32(RADEON_CRTC_H_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_h_sync_strt_wid);
677         WREG32(RADEON_CRTC_V_TOTAL_DISP + radeon_crtc->crtc_offset, crtc_v_total_disp);
678         WREG32(RADEON_CRTC_V_SYNC_STRT_WID + radeon_crtc->crtc_offset, crtc_v_sync_strt_wid);
679
680         return true;
681 }
682
683 static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
684 {
685         struct drm_device *dev = crtc->dev;
686         struct radeon_device *rdev = dev->dev_private;
687         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
688         struct drm_encoder *encoder;
689         uint32_t feedback_div = 0;
690         uint32_t frac_fb_div = 0;
691         uint32_t reference_div = 0;
692         uint32_t post_divider = 0;
693         uint32_t freq = 0;
694         uint8_t pll_gain;
695         int pll_flags = RADEON_PLL_LEGACY;
696         bool use_bios_divs = false;
697         /* PLL registers */
698         uint32_t pll_ref_div = 0;
699         uint32_t pll_fb_post_div = 0;
700         uint32_t htotal_cntl = 0;
701         bool is_tv = false;
702         struct radeon_pll *pll;
703
704         struct {
705                 int divider;
706                 int bitvalue;
707         } *post_div, post_divs[]   = {
708                 /* From RAGE 128 VR/RAGE 128 GL Register
709                  * Reference Manual (Technical Reference
710                  * Manual P/N RRG-G04100-C Rev. 0.04), page
711                  * 3-17 (PLL_DIV_[3:0]).
712                  */
713                 {  1, 0 },              /* VCLK_SRC                 */
714                 {  2, 1 },              /* VCLK_SRC/2               */
715                 {  4, 2 },              /* VCLK_SRC/4               */
716                 {  8, 3 },              /* VCLK_SRC/8               */
717                 {  3, 4 },              /* VCLK_SRC/3               */
718                 { 16, 5 },              /* VCLK_SRC/16              */
719                 {  6, 6 },              /* VCLK_SRC/6               */
720                 { 12, 7 },              /* VCLK_SRC/12              */
721                 {  0, 0 }
722         };
723
724         if (radeon_crtc->crtc_id)
725                 pll = &rdev->clock.p2pll;
726         else
727                 pll = &rdev->clock.p1pll;
728
729         if (mode->clock > 200000) /* range limits??? */
730                 pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
731         else
732                 pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
733
734         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
735                 if (encoder->crtc == crtc) {
736                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
737
738                         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
739                                 is_tv = true;
740                                 break;
741                         }
742
743                         if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
744                                 pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
745                         if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS) {
746                                 if (!rdev->is_atom_bios) {
747                                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
748                                         struct radeon_encoder_lvds *lvds = (struct radeon_encoder_lvds *)radeon_encoder->enc_priv;
749                                         if (lvds) {
750                                                 if (lvds->use_bios_dividers) {
751                                                         pll_ref_div = lvds->panel_ref_divider;
752                                                         pll_fb_post_div   = (lvds->panel_fb_divider |
753                                                                              (lvds->panel_post_divider << 16));
754                                                         htotal_cntl  = 0;
755                                                         use_bios_divs = true;
756                                                 }
757                                         }
758                                 }
759                                 pll_flags |= RADEON_PLL_USE_REF_DIV;
760                         }
761                 }
762         }
763
764         DRM_DEBUG("\n");
765
766         if (!use_bios_divs) {
767                 radeon_compute_pll(pll, mode->clock,
768                                    &freq, &feedback_div, &frac_fb_div,
769                                    &reference_div, &post_divider,
770                                    pll_flags);
771
772                 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
773                         if (post_div->divider == post_divider)
774                                 break;
775                 }
776
777                 if (!post_div->divider)
778                         post_div = &post_divs[0];
779
780                 DRM_DEBUG("dc=%u, fd=%d, rd=%d, pd=%d\n",
781                           (unsigned)freq,
782                           feedback_div,
783                           reference_div,
784                           post_divider);
785
786                 pll_ref_div   = reference_div;
787 #if defined(__powerpc__) && (0) /* TODO */
788                 /* apparently programming this otherwise causes a hang??? */
789                 if (info->MacModel == RADEON_MAC_IBOOK)
790                         pll_fb_post_div = 0x000600ad;
791                 else
792 #endif
793                         pll_fb_post_div     = (feedback_div | (post_div->bitvalue << 16));
794
795                 htotal_cntl    = mode->htotal & 0x7;
796
797         }
798
799         pll_gain = radeon_compute_pll_gain(pll->reference_freq,
800                                            pll_ref_div & 0x3ff,
801                                            pll_fb_post_div & 0x7ff);
802
803         if (radeon_crtc->crtc_id) {
804                 uint32_t pixclks_cntl = ((RREG32_PLL(RADEON_PIXCLKS_CNTL) &
805                                           ~(RADEON_PIX2CLK_SRC_SEL_MASK)) |
806                                          RADEON_PIX2CLK_SRC_SEL_P2PLLCLK);
807
808                 if (is_tv) {
809                         radeon_legacy_tv_adjust_pll2(encoder, &htotal_cntl,
810                                                      &pll_ref_div, &pll_fb_post_div,
811                                                      &pixclks_cntl);
812                 }
813
814                 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
815                              RADEON_PIX2CLK_SRC_SEL_CPUCLK,
816                              ~(RADEON_PIX2CLK_SRC_SEL_MASK));
817
818                 WREG32_PLL_P(RADEON_P2PLL_CNTL,
819                              RADEON_P2PLL_RESET
820                              | RADEON_P2PLL_ATOMIC_UPDATE_EN
821                              | ((uint32_t)pll_gain << RADEON_P2PLL_PVG_SHIFT),
822                              ~(RADEON_P2PLL_RESET
823                                | RADEON_P2PLL_ATOMIC_UPDATE_EN
824                                | RADEON_P2PLL_PVG_MASK));
825
826                 WREG32_PLL_P(RADEON_P2PLL_REF_DIV,
827                              pll_ref_div,
828                              ~RADEON_P2PLL_REF_DIV_MASK);
829
830                 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
831                              pll_fb_post_div,
832                              ~RADEON_P2PLL_FB0_DIV_MASK);
833
834                 WREG32_PLL_P(RADEON_P2PLL_DIV_0,
835                              pll_fb_post_div,
836                              ~RADEON_P2PLL_POST0_DIV_MASK);
837
838                 radeon_pll2_write_update(dev);
839                 radeon_pll2_wait_for_read_update_complete(dev);
840
841                 WREG32_PLL(RADEON_HTOTAL2_CNTL, htotal_cntl);
842
843                 WREG32_PLL_P(RADEON_P2PLL_CNTL,
844                              0,
845                              ~(RADEON_P2PLL_RESET
846                                | RADEON_P2PLL_SLEEP
847                                | RADEON_P2PLL_ATOMIC_UPDATE_EN));
848
849                 DRM_DEBUG("Wrote2: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
850                           (unsigned)pll_ref_div,
851                           (unsigned)pll_fb_post_div,
852                           (unsigned)htotal_cntl,
853                           RREG32_PLL(RADEON_P2PLL_CNTL));
854                 DRM_DEBUG("Wrote2: rd=%u, fd=%u, pd=%u\n",
855                           (unsigned)pll_ref_div & RADEON_P2PLL_REF_DIV_MASK,
856                           (unsigned)pll_fb_post_div & RADEON_P2PLL_FB0_DIV_MASK,
857                           (unsigned)((pll_fb_post_div &
858                                       RADEON_P2PLL_POST0_DIV_MASK) >> 16));
859
860                 mdelay(50); /* Let the clock to lock */
861
862                 WREG32_PLL_P(RADEON_PIXCLKS_CNTL,
863                              RADEON_PIX2CLK_SRC_SEL_P2PLLCLK,
864                              ~(RADEON_PIX2CLK_SRC_SEL_MASK));
865
866                 WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
867         } else {
868                 uint32_t pixclks_cntl;
869
870
871                 if (is_tv) {
872                         pixclks_cntl = RREG32_PLL(RADEON_PIXCLKS_CNTL);
873                         radeon_legacy_tv_adjust_pll1(encoder, &htotal_cntl, &pll_ref_div,
874                                                      &pll_fb_post_div, &pixclks_cntl);
875                 }
876
877                 if (rdev->flags & RADEON_IS_MOBILITY) {
878                         /* A temporal workaround for the occational blanking on certain laptop panels.
879                            This appears to related to the PLL divider registers (fail to lock?).
880                            It occurs even when all dividers are the same with their old settings.
881                            In this case we really don't need to fiddle with PLL registers.
882                            By doing this we can avoid the blanking problem with some panels.
883                         */
884                         if ((pll_ref_div == (RREG32_PLL(RADEON_PPLL_REF_DIV) & RADEON_PPLL_REF_DIV_MASK)) &&
885                             (pll_fb_post_div == (RREG32_PLL(RADEON_PPLL_DIV_3) &
886                                                  (RADEON_PPLL_POST3_DIV_MASK | RADEON_PPLL_FB3_DIV_MASK)))) {
887                                 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
888                                          RADEON_PLL_DIV_SEL,
889                                          ~(RADEON_PLL_DIV_SEL));
890                                 r100_pll_errata_after_index(rdev);
891                                 return;
892                         }
893                 }
894
895                 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
896                              RADEON_VCLK_SRC_SEL_CPUCLK,
897                              ~(RADEON_VCLK_SRC_SEL_MASK));
898                 WREG32_PLL_P(RADEON_PPLL_CNTL,
899                              RADEON_PPLL_RESET
900                              | RADEON_PPLL_ATOMIC_UPDATE_EN
901                              | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
902                              | ((uint32_t)pll_gain << RADEON_PPLL_PVG_SHIFT),
903                              ~(RADEON_PPLL_RESET
904                                | RADEON_PPLL_ATOMIC_UPDATE_EN
905                                | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN
906                                | RADEON_PPLL_PVG_MASK));
907
908                 WREG32_P(RADEON_CLOCK_CNTL_INDEX,
909                          RADEON_PLL_DIV_SEL,
910                          ~(RADEON_PLL_DIV_SEL));
911                 r100_pll_errata_after_index(rdev);
912
913                 if (ASIC_IS_R300(rdev) ||
914                     (rdev->family == CHIP_RS300) ||
915                     (rdev->family == CHIP_RS400) ||
916                     (rdev->family == CHIP_RS480)) {
917                         if (pll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) {
918                                 /* When restoring console mode, use saved PPLL_REF_DIV
919                                  * setting.
920                                  */
921                                 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
922                                              pll_ref_div,
923                                              0);
924                         } else {
925                                 /* R300 uses ref_div_acc field as real ref divider */
926                                 WREG32_PLL_P(RADEON_PPLL_REF_DIV,
927                                              (pll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT),
928                                              ~R300_PPLL_REF_DIV_ACC_MASK);
929                         }
930                 } else
931                         WREG32_PLL_P(RADEON_PPLL_REF_DIV,
932                                      pll_ref_div,
933                                      ~RADEON_PPLL_REF_DIV_MASK);
934
935                 WREG32_PLL_P(RADEON_PPLL_DIV_3,
936                              pll_fb_post_div,
937                              ~RADEON_PPLL_FB3_DIV_MASK);
938
939                 WREG32_PLL_P(RADEON_PPLL_DIV_3,
940                              pll_fb_post_div,
941                              ~RADEON_PPLL_POST3_DIV_MASK);
942
943                 radeon_pll_write_update(dev);
944                 radeon_pll_wait_for_read_update_complete(dev);
945
946                 WREG32_PLL(RADEON_HTOTAL_CNTL, htotal_cntl);
947
948                 WREG32_PLL_P(RADEON_PPLL_CNTL,
949                              0,
950                              ~(RADEON_PPLL_RESET
951                                | RADEON_PPLL_SLEEP
952                                | RADEON_PPLL_ATOMIC_UPDATE_EN
953                                | RADEON_PPLL_VGA_ATOMIC_UPDATE_EN));
954
955                 DRM_DEBUG("Wrote: 0x%08x 0x%08x 0x%08x (0x%08x)\n",
956                           pll_ref_div,
957                           pll_fb_post_div,
958                           (unsigned)htotal_cntl,
959                           RREG32_PLL(RADEON_PPLL_CNTL));
960                 DRM_DEBUG("Wrote: rd=%d, fd=%d, pd=%d\n",
961                           pll_ref_div & RADEON_PPLL_REF_DIV_MASK,
962                           pll_fb_post_div & RADEON_PPLL_FB3_DIV_MASK,
963                           (pll_fb_post_div & RADEON_PPLL_POST3_DIV_MASK) >> 16);
964
965                 mdelay(50); /* Let the clock to lock */
966
967                 WREG32_PLL_P(RADEON_VCLK_ECP_CNTL,
968                              RADEON_VCLK_SRC_SEL_PPLLCLK,
969                              ~(RADEON_VCLK_SRC_SEL_MASK));
970
971                 if (is_tv)
972                         WREG32_PLL(RADEON_PIXCLKS_CNTL, pixclks_cntl);
973         }
974 }
975
976 static bool radeon_crtc_mode_fixup(struct drm_crtc *crtc,
977                                    struct drm_display_mode *mode,
978                                    struct drm_display_mode *adjusted_mode)
979 {
980         if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
981                 return false;
982         return true;
983 }
984
985 static int radeon_crtc_mode_set(struct drm_crtc *crtc,
986                                  struct drm_display_mode *mode,
987                                  struct drm_display_mode *adjusted_mode,
988                                  int x, int y, struct drm_framebuffer *old_fb)
989 {
990         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
991
992         /* TODO TV */
993         radeon_crtc_set_base(crtc, x, y, old_fb);
994         radeon_set_crtc_timing(crtc, adjusted_mode);
995         radeon_set_pll(crtc, adjusted_mode);
996         radeon_overscan_setup(crtc, adjusted_mode);
997         if (radeon_crtc->crtc_id == 0) {
998                 radeon_legacy_rmx_mode_set(crtc, adjusted_mode);
999         } else {
1000                 if (radeon_crtc->rmx_type != RMX_OFF) {
1001                         /* FIXME: only first crtc has rmx what should we
1002                          * do ?
1003                          */
1004                         DRM_ERROR("Mode need scaling but only first crtc can do that.\n");
1005                 }
1006         }
1007         return 0;
1008 }
1009
1010 static void radeon_crtc_prepare(struct drm_crtc *crtc)
1011 {
1012         struct drm_device *dev = crtc->dev;
1013         struct drm_crtc *crtci;
1014
1015         /*
1016         * The hardware wedges sometimes if you reconfigure one CRTC
1017         * whilst another is running (see fdo bug #24611).
1018         */
1019         list_for_each_entry(crtci, &dev->mode_config.crtc_list, head)
1020                 radeon_crtc_dpms(crtci, DRM_MODE_DPMS_OFF);
1021 }
1022
1023 static void radeon_crtc_commit(struct drm_crtc *crtc)
1024 {
1025         struct drm_device *dev = crtc->dev;
1026         struct drm_crtc *crtci;
1027
1028         /*
1029         * Reenable the CRTCs that should be running.
1030         */
1031         list_for_each_entry(crtci, &dev->mode_config.crtc_list, head) {
1032                 if (crtci->enabled)
1033                         radeon_crtc_dpms(crtci, DRM_MODE_DPMS_ON);
1034         }
1035 }
1036
1037 static const struct drm_crtc_helper_funcs legacy_helper_funcs = {
1038         .dpms = radeon_crtc_dpms,
1039         .mode_fixup = radeon_crtc_mode_fixup,
1040         .mode_set = radeon_crtc_mode_set,
1041         .mode_set_base = radeon_crtc_set_base,
1042         .prepare = radeon_crtc_prepare,
1043         .commit = radeon_crtc_commit,
1044         .load_lut = radeon_crtc_load_lut,
1045 };
1046
1047
1048 void radeon_legacy_init_crtc(struct drm_device *dev,
1049                                struct radeon_crtc *radeon_crtc)
1050 {
1051         if (radeon_crtc->crtc_id == 1)
1052                 radeon_crtc->crtc_offset = RADEON_CRTC2_H_TOTAL_DISP - RADEON_CRTC_H_TOTAL_DISP;
1053         drm_crtc_helper_add(&radeon_crtc->base, &legacy_helper_funcs);
1054 }