drm/radeon/kms: add info query for tile pipes
[linux-2.6.git] / drivers / gpu / drm / radeon / radeon_kms.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include "drmP.h"
29 #include "drm_sarea.h"
30 #include "radeon.h"
31 #include "radeon_drm.h"
32
33 #include <linux/vga_switcheroo.h>
34 #include <linux/slab.h>
35
36 int radeon_driver_unload_kms(struct drm_device *dev)
37 {
38         struct radeon_device *rdev = dev->dev_private;
39
40         if (rdev == NULL)
41                 return 0;
42         radeon_modeset_fini(rdev);
43         radeon_device_fini(rdev);
44         kfree(rdev);
45         dev->dev_private = NULL;
46         return 0;
47 }
48
49 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
50 {
51         struct radeon_device *rdev;
52         int r, acpi_status;
53
54         rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
55         if (rdev == NULL) {
56                 return -ENOMEM;
57         }
58         dev->dev_private = (void *)rdev;
59
60         /* update BUS flag */
61         if (drm_pci_device_is_agp(dev)) {
62                 flags |= RADEON_IS_AGP;
63         } else if (drm_pci_device_is_pcie(dev)) {
64                 flags |= RADEON_IS_PCIE;
65         } else {
66                 flags |= RADEON_IS_PCI;
67         }
68
69         /* radeon_device_init should report only fatal error
70          * like memory allocation failure or iomapping failure,
71          * or memory manager initialization failure, it must
72          * properly initialize the GPU MC controller and permit
73          * VRAM allocation
74          */
75         r = radeon_device_init(rdev, dev, dev->pdev, flags);
76         if (r) {
77                 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
78                 goto out;
79         }
80
81         /* Call ACPI methods */
82         acpi_status = radeon_acpi_init(rdev);
83         if (acpi_status)
84                 dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n");
85
86         /* Again modeset_init should fail only on fatal error
87          * otherwise it should provide enough functionalities
88          * for shadowfb to run
89          */
90         r = radeon_modeset_init(rdev);
91         if (r)
92                 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
93 out:
94         if (r)
95                 radeon_driver_unload_kms(dev);
96         return r;
97 }
98
99 static void radeon_set_filp_rights(struct drm_device *dev,
100                                    struct drm_file **owner,
101                                    struct drm_file *applier,
102                                    uint32_t *value)
103 {
104         mutex_lock(&dev->struct_mutex);
105         if (*value == 1) {
106                 /* wants rights */
107                 if (!*owner)
108                         *owner = applier;
109         } else if (*value == 0) {
110                 /* revokes rights */
111                 if (*owner == applier)
112                         *owner = NULL;
113         }
114         *value = *owner == applier ? 1 : 0;
115         mutex_unlock(&dev->struct_mutex);
116 }
117
118 /*
119  * Userspace get information ioctl
120  */
121 int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
122 {
123         struct radeon_device *rdev = dev->dev_private;
124         struct drm_radeon_info *info;
125         struct radeon_mode_info *minfo = &rdev->mode_info;
126         uint32_t *value_ptr;
127         uint32_t value;
128         struct drm_crtc *crtc;
129         int i, found;
130
131         info = data;
132         value_ptr = (uint32_t *)((unsigned long)info->value);
133         if (DRM_COPY_FROM_USER(&value, value_ptr, sizeof(value)))
134                 return -EFAULT;
135
136         switch (info->request) {
137         case RADEON_INFO_DEVICE_ID:
138                 value = dev->pci_device;
139                 break;
140         case RADEON_INFO_NUM_GB_PIPES:
141                 value = rdev->num_gb_pipes;
142                 break;
143         case RADEON_INFO_NUM_Z_PIPES:
144                 value = rdev->num_z_pipes;
145                 break;
146         case RADEON_INFO_ACCEL_WORKING:
147                 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
148                 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
149                         value = false;
150                 else
151                         value = rdev->accel_working;
152                 break;
153         case RADEON_INFO_CRTC_FROM_ID:
154                 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
155                         crtc = (struct drm_crtc *)minfo->crtcs[i];
156                         if (crtc && crtc->base.id == value) {
157                                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
158                                 value = radeon_crtc->crtc_id;
159                                 found = 1;
160                                 break;
161                         }
162                 }
163                 if (!found) {
164                         DRM_DEBUG_KMS("unknown crtc id %d\n", value);
165                         return -EINVAL;
166                 }
167                 break;
168         case RADEON_INFO_ACCEL_WORKING2:
169                 value = rdev->accel_working;
170                 break;
171         case RADEON_INFO_TILING_CONFIG:
172                 if (rdev->family >= CHIP_CAYMAN)
173                         value = rdev->config.cayman.tile_config;
174                 else if (rdev->family >= CHIP_CEDAR)
175                         value = rdev->config.evergreen.tile_config;
176                 else if (rdev->family >= CHIP_RV770)
177                         value = rdev->config.rv770.tile_config;
178                 else if (rdev->family >= CHIP_R600)
179                         value = rdev->config.r600.tile_config;
180                 else {
181                         DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
182                         return -EINVAL;
183                 }
184                 break;
185         case RADEON_INFO_WANT_HYPERZ:
186                 /* The "value" here is both an input and output parameter.
187                  * If the input value is 1, filp requests hyper-z access.
188                  * If the input value is 0, filp revokes its hyper-z access.
189                  *
190                  * When returning, the value is 1 if filp owns hyper-z access,
191                  * 0 otherwise. */
192                 if (value >= 2) {
193                         DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", value);
194                         return -EINVAL;
195                 }
196                 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, &value);
197                 break;
198         case RADEON_INFO_WANT_CMASK:
199                 /* The same logic as Hyper-Z. */
200                 if (value >= 2) {
201                         DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", value);
202                         return -EINVAL;
203                 }
204                 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, &value);
205                 break;
206         case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
207                 /* return clock value in KHz */
208                 value = rdev->clock.spll.reference_freq * 10;
209                 break;
210         case RADEON_INFO_NUM_BACKENDS:
211                 if (rdev->family >= CHIP_CAYMAN)
212                         value = rdev->config.cayman.max_backends_per_se *
213                                 rdev->config.cayman.max_shader_engines;
214                 else if (rdev->family >= CHIP_CEDAR)
215                         value = rdev->config.evergreen.max_backends;
216                 else if (rdev->family >= CHIP_RV770)
217                         value = rdev->config.rv770.max_backends;
218                 else if (rdev->family >= CHIP_R600)
219                         value = rdev->config.r600.max_backends;
220                 else {
221                         return -EINVAL;
222                 }
223                 break;
224         case RADEON_INFO_NUM_TILE_PIPES:
225                 if (rdev->family >= CHIP_CAYMAN)
226                         value = rdev->config.cayman.max_tile_pipes;
227                 else if (rdev->family >= CHIP_CEDAR)
228                         value = rdev->config.evergreen.max_tile_pipes;
229                 else if (rdev->family >= CHIP_RV770)
230                         value = rdev->config.rv770.max_tile_pipes;
231                 else if (rdev->family >= CHIP_R600)
232                         value = rdev->config.r600.max_tile_pipes;
233                 else {
234                         return -EINVAL;
235                 }
236                 break;
237         default:
238                 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
239                 return -EINVAL;
240         }
241         if (DRM_COPY_TO_USER(value_ptr, &value, sizeof(uint32_t))) {
242                 DRM_ERROR("copy_to_user\n");
243                 return -EFAULT;
244         }
245         return 0;
246 }
247
248
249 /*
250  * Outdated mess for old drm with Xorg being in charge (void function now).
251  */
252 int radeon_driver_firstopen_kms(struct drm_device *dev)
253 {
254         return 0;
255 }
256
257
258 void radeon_driver_lastclose_kms(struct drm_device *dev)
259 {
260         vga_switcheroo_process_delayed_switch();
261 }
262
263 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
264 {
265         return 0;
266 }
267
268 void radeon_driver_postclose_kms(struct drm_device *dev,
269                                  struct drm_file *file_priv)
270 {
271 }
272
273 void radeon_driver_preclose_kms(struct drm_device *dev,
274                                 struct drm_file *file_priv)
275 {
276         struct radeon_device *rdev = dev->dev_private;
277         if (rdev->hyperz_filp == file_priv)
278                 rdev->hyperz_filp = NULL;
279         if (rdev->cmask_filp == file_priv)
280                 rdev->cmask_filp = NULL;
281 }
282
283 /*
284  * VBlank related functions.
285  */
286 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
287 {
288         struct radeon_device *rdev = dev->dev_private;
289
290         if (crtc < 0 || crtc >= rdev->num_crtc) {
291                 DRM_ERROR("Invalid crtc %d\n", crtc);
292                 return -EINVAL;
293         }
294
295         return radeon_get_vblank_counter(rdev, crtc);
296 }
297
298 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
299 {
300         struct radeon_device *rdev = dev->dev_private;
301
302         if (crtc < 0 || crtc >= rdev->num_crtc) {
303                 DRM_ERROR("Invalid crtc %d\n", crtc);
304                 return -EINVAL;
305         }
306
307         rdev->irq.crtc_vblank_int[crtc] = true;
308
309         return radeon_irq_set(rdev);
310 }
311
312 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
313 {
314         struct radeon_device *rdev = dev->dev_private;
315
316         if (crtc < 0 || crtc >= rdev->num_crtc) {
317                 DRM_ERROR("Invalid crtc %d\n", crtc);
318                 return;
319         }
320
321         rdev->irq.crtc_vblank_int[crtc] = false;
322
323         radeon_irq_set(rdev);
324 }
325
326 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
327                                     int *max_error,
328                                     struct timeval *vblank_time,
329                                     unsigned flags)
330 {
331         struct drm_crtc *drmcrtc;
332         struct radeon_device *rdev = dev->dev_private;
333
334         if (crtc < 0 || crtc >= dev->num_crtcs) {
335                 DRM_ERROR("Invalid crtc %d\n", crtc);
336                 return -EINVAL;
337         }
338
339         /* Get associated drm_crtc: */
340         drmcrtc = &rdev->mode_info.crtcs[crtc]->base;
341
342         /* Helper routine in DRM core does all the work: */
343         return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
344                                                      vblank_time, flags,
345                                                      drmcrtc);
346 }
347
348 /*
349  * IOCTL.
350  */
351 int radeon_dma_ioctl_kms(struct drm_device *dev, void *data,
352                          struct drm_file *file_priv)
353 {
354         /* Not valid in KMS. */
355         return -EINVAL;
356 }
357
358 #define KMS_INVALID_IOCTL(name)                                         \
359 int name(struct drm_device *dev, void *data, struct drm_file *file_priv)\
360 {                                                                       \
361         DRM_ERROR("invalid ioctl with kms %s\n", __func__);             \
362         return -EINVAL;                                                 \
363 }
364
365 /*
366  * All these ioctls are invalid in kms world.
367  */
368 KMS_INVALID_IOCTL(radeon_cp_init_kms)
369 KMS_INVALID_IOCTL(radeon_cp_start_kms)
370 KMS_INVALID_IOCTL(radeon_cp_stop_kms)
371 KMS_INVALID_IOCTL(radeon_cp_reset_kms)
372 KMS_INVALID_IOCTL(radeon_cp_idle_kms)
373 KMS_INVALID_IOCTL(radeon_cp_resume_kms)
374 KMS_INVALID_IOCTL(radeon_engine_reset_kms)
375 KMS_INVALID_IOCTL(radeon_fullscreen_kms)
376 KMS_INVALID_IOCTL(radeon_cp_swap_kms)
377 KMS_INVALID_IOCTL(radeon_cp_clear_kms)
378 KMS_INVALID_IOCTL(radeon_cp_vertex_kms)
379 KMS_INVALID_IOCTL(radeon_cp_indices_kms)
380 KMS_INVALID_IOCTL(radeon_cp_texture_kms)
381 KMS_INVALID_IOCTL(radeon_cp_stipple_kms)
382 KMS_INVALID_IOCTL(radeon_cp_indirect_kms)
383 KMS_INVALID_IOCTL(radeon_cp_vertex2_kms)
384 KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms)
385 KMS_INVALID_IOCTL(radeon_cp_getparam_kms)
386 KMS_INVALID_IOCTL(radeon_cp_flip_kms)
387 KMS_INVALID_IOCTL(radeon_mem_alloc_kms)
388 KMS_INVALID_IOCTL(radeon_mem_free_kms)
389 KMS_INVALID_IOCTL(radeon_mem_init_heap_kms)
390 KMS_INVALID_IOCTL(radeon_irq_emit_kms)
391 KMS_INVALID_IOCTL(radeon_irq_wait_kms)
392 KMS_INVALID_IOCTL(radeon_cp_setparam_kms)
393 KMS_INVALID_IOCTL(radeon_surface_alloc_kms)
394 KMS_INVALID_IOCTL(radeon_surface_free_kms)
395
396
397 struct drm_ioctl_desc radeon_ioctls_kms[] = {
398         DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
399         DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
400         DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
401         DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
402         DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
403         DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
404         DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
405         DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
406         DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
407         DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
408         DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
409         DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
410         DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
411         DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
412         DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
413         DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
414         DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
415         DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
416         DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
417         DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
418         DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
419         DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
420         DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
421         DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
422         DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
423         DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
424         DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
425         /* KMS */
426         DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
427         DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED),
428         DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED),
429         DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED),
430         DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED),
431         DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED),
432         DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED),
433         DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED),
434         DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
435         DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
436         DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
437         DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
438 };
439 int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms);