drm: move pci bus master enable into driver.
[linux-2.6.git] / drivers / gpu / drm / radeon / radeon_kms.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include "drmP.h"
29 #include "drm_sarea.h"
30 #include "radeon.h"
31 #include "radeon_drm.h"
32
33 #include <linux/vga_switcheroo.h>
34 #include <linux/slab.h>
35
36 int radeon_driver_unload_kms(struct drm_device *dev)
37 {
38         struct radeon_device *rdev = dev->dev_private;
39
40         if (rdev == NULL)
41                 return 0;
42         radeon_modeset_fini(rdev);
43         radeon_device_fini(rdev);
44         kfree(rdev);
45         dev->dev_private = NULL;
46         return 0;
47 }
48
49 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
50 {
51         struct radeon_device *rdev;
52         int r, acpi_status;
53
54         rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
55         if (rdev == NULL) {
56                 return -ENOMEM;
57         }
58         dev->dev_private = (void *)rdev;
59
60         pci_set_master(dev->pdev);
61
62         /* update BUS flag */
63         if (drm_pci_device_is_agp(dev)) {
64                 flags |= RADEON_IS_AGP;
65         } else if (pci_is_pcie(dev->pdev)) {
66                 flags |= RADEON_IS_PCIE;
67         } else {
68                 flags |= RADEON_IS_PCI;
69         }
70
71         /* radeon_device_init should report only fatal error
72          * like memory allocation failure or iomapping failure,
73          * or memory manager initialization failure, it must
74          * properly initialize the GPU MC controller and permit
75          * VRAM allocation
76          */
77         r = radeon_device_init(rdev, dev, dev->pdev, flags);
78         if (r) {
79                 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
80                 goto out;
81         }
82
83         /* Call ACPI methods */
84         acpi_status = radeon_acpi_init(rdev);
85         if (acpi_status)
86                 dev_dbg(&dev->pdev->dev, "Error during ACPI methods call\n");
87
88         /* Again modeset_init should fail only on fatal error
89          * otherwise it should provide enough functionalities
90          * for shadowfb to run
91          */
92         r = radeon_modeset_init(rdev);
93         if (r)
94                 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
95 out:
96         if (r)
97                 radeon_driver_unload_kms(dev);
98         return r;
99 }
100
101 static void radeon_set_filp_rights(struct drm_device *dev,
102                                    struct drm_file **owner,
103                                    struct drm_file *applier,
104                                    uint32_t *value)
105 {
106         mutex_lock(&dev->struct_mutex);
107         if (*value == 1) {
108                 /* wants rights */
109                 if (!*owner)
110                         *owner = applier;
111         } else if (*value == 0) {
112                 /* revokes rights */
113                 if (*owner == applier)
114                         *owner = NULL;
115         }
116         *value = *owner == applier ? 1 : 0;
117         mutex_unlock(&dev->struct_mutex);
118 }
119
120 /*
121  * Userspace get information ioctl
122  */
123 int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
124 {
125         struct radeon_device *rdev = dev->dev_private;
126         struct drm_radeon_info *info;
127         struct radeon_mode_info *minfo = &rdev->mode_info;
128         uint32_t *value_ptr;
129         uint32_t value;
130         struct drm_crtc *crtc;
131         int i, found;
132
133         info = data;
134         value_ptr = (uint32_t *)((unsigned long)info->value);
135         if (DRM_COPY_FROM_USER(&value, value_ptr, sizeof(value)))
136                 return -EFAULT;
137
138         switch (info->request) {
139         case RADEON_INFO_DEVICE_ID:
140                 value = dev->pci_device;
141                 break;
142         case RADEON_INFO_NUM_GB_PIPES:
143                 value = rdev->num_gb_pipes;
144                 break;
145         case RADEON_INFO_NUM_Z_PIPES:
146                 value = rdev->num_z_pipes;
147                 break;
148         case RADEON_INFO_ACCEL_WORKING:
149                 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
150                 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
151                         value = false;
152                 else
153                         value = rdev->accel_working;
154                 break;
155         case RADEON_INFO_CRTC_FROM_ID:
156                 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
157                         crtc = (struct drm_crtc *)minfo->crtcs[i];
158                         if (crtc && crtc->base.id == value) {
159                                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
160                                 value = radeon_crtc->crtc_id;
161                                 found = 1;
162                                 break;
163                         }
164                 }
165                 if (!found) {
166                         DRM_DEBUG_KMS("unknown crtc id %d\n", value);
167                         return -EINVAL;
168                 }
169                 break;
170         case RADEON_INFO_ACCEL_WORKING2:
171                 value = rdev->accel_working;
172                 break;
173         case RADEON_INFO_TILING_CONFIG:
174                 if (rdev->family >= CHIP_CAYMAN)
175                         value = rdev->config.cayman.tile_config;
176                 else if (rdev->family >= CHIP_CEDAR)
177                         value = rdev->config.evergreen.tile_config;
178                 else if (rdev->family >= CHIP_RV770)
179                         value = rdev->config.rv770.tile_config;
180                 else if (rdev->family >= CHIP_R600)
181                         value = rdev->config.r600.tile_config;
182                 else {
183                         DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
184                         return -EINVAL;
185                 }
186                 break;
187         case RADEON_INFO_WANT_HYPERZ:
188                 /* The "value" here is both an input and output parameter.
189                  * If the input value is 1, filp requests hyper-z access.
190                  * If the input value is 0, filp revokes its hyper-z access.
191                  *
192                  * When returning, the value is 1 if filp owns hyper-z access,
193                  * 0 otherwise. */
194                 if (value >= 2) {
195                         DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", value);
196                         return -EINVAL;
197                 }
198                 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, &value);
199                 break;
200         case RADEON_INFO_WANT_CMASK:
201                 /* The same logic as Hyper-Z. */
202                 if (value >= 2) {
203                         DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", value);
204                         return -EINVAL;
205                 }
206                 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, &value);
207                 break;
208         case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
209                 /* return clock value in KHz */
210                 value = rdev->clock.spll.reference_freq * 10;
211                 break;
212         case RADEON_INFO_NUM_BACKENDS:
213                 if (rdev->family >= CHIP_CAYMAN)
214                         value = rdev->config.cayman.max_backends_per_se *
215                                 rdev->config.cayman.max_shader_engines;
216                 else if (rdev->family >= CHIP_CEDAR)
217                         value = rdev->config.evergreen.max_backends;
218                 else if (rdev->family >= CHIP_RV770)
219                         value = rdev->config.rv770.max_backends;
220                 else if (rdev->family >= CHIP_R600)
221                         value = rdev->config.r600.max_backends;
222                 else {
223                         return -EINVAL;
224                 }
225                 break;
226         case RADEON_INFO_NUM_TILE_PIPES:
227                 if (rdev->family >= CHIP_CAYMAN)
228                         value = rdev->config.cayman.max_tile_pipes;
229                 else if (rdev->family >= CHIP_CEDAR)
230                         value = rdev->config.evergreen.max_tile_pipes;
231                 else if (rdev->family >= CHIP_RV770)
232                         value = rdev->config.rv770.max_tile_pipes;
233                 else if (rdev->family >= CHIP_R600)
234                         value = rdev->config.r600.max_tile_pipes;
235                 else {
236                         return -EINVAL;
237                 }
238                 break;
239         case RADEON_INFO_FUSION_GART_WORKING:
240                 value = 1;
241                 break;
242         case RADEON_INFO_BACKEND_MAP:
243                 if (rdev->family >= CHIP_CAYMAN)
244                         value = rdev->config.cayman.backend_map;
245                 else if (rdev->family >= CHIP_CEDAR)
246                         value = rdev->config.evergreen.backend_map;
247                 else if (rdev->family >= CHIP_RV770)
248                         value = rdev->config.rv770.backend_map;
249                 else if (rdev->family >= CHIP_R600)
250                         value = rdev->config.r600.backend_map;
251                 else {
252                         return -EINVAL;
253                 }
254                 break;
255         case RADEON_INFO_VA_START:
256                 /* this is where we report if vm is supported or not */
257                 if (rdev->family < CHIP_CAYMAN)
258                         return -EINVAL;
259                 value = RADEON_VA_RESERVED_SIZE;
260                 break;
261         case RADEON_INFO_IB_VM_MAX_SIZE:
262                 /* this is where we report if vm is supported or not */
263                 if (rdev->family < CHIP_CAYMAN)
264                         return -EINVAL;
265                 value = RADEON_IB_VM_MAX_SIZE;
266                 break;
267         default:
268                 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
269                 return -EINVAL;
270         }
271         if (DRM_COPY_TO_USER(value_ptr, &value, sizeof(uint32_t))) {
272                 DRM_ERROR("copy_to_user\n");
273                 return -EFAULT;
274         }
275         return 0;
276 }
277
278
279 /*
280  * Outdated mess for old drm with Xorg being in charge (void function now).
281  */
282 int radeon_driver_firstopen_kms(struct drm_device *dev)
283 {
284         return 0;
285 }
286
287 void radeon_driver_lastclose_kms(struct drm_device *dev)
288 {
289         vga_switcheroo_process_delayed_switch();
290 }
291
292 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
293 {
294         struct radeon_device *rdev = dev->dev_private;
295
296         file_priv->driver_priv = NULL;
297
298         /* new gpu have virtual address space support */
299         if (rdev->family >= CHIP_CAYMAN) {
300                 struct radeon_fpriv *fpriv;
301                 int r;
302
303                 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
304                 if (unlikely(!fpriv)) {
305                         return -ENOMEM;
306                 }
307
308                 r = radeon_vm_init(rdev, &fpriv->vm);
309                 if (r) {
310                         radeon_vm_fini(rdev, &fpriv->vm);
311                         kfree(fpriv);
312                         return r;
313                 }
314
315                 file_priv->driver_priv = fpriv;
316         }
317         return 0;
318 }
319
320 void radeon_driver_postclose_kms(struct drm_device *dev,
321                                  struct drm_file *file_priv)
322 {
323         struct radeon_device *rdev = dev->dev_private;
324
325         /* new gpu have virtual address space support */
326         if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
327                 struct radeon_fpriv *fpriv = file_priv->driver_priv;
328
329                 radeon_vm_fini(rdev, &fpriv->vm);
330                 kfree(fpriv);
331                 file_priv->driver_priv = NULL;
332         }
333 }
334
335 void radeon_driver_preclose_kms(struct drm_device *dev,
336                                 struct drm_file *file_priv)
337 {
338         struct radeon_device *rdev = dev->dev_private;
339         if (rdev->hyperz_filp == file_priv)
340                 rdev->hyperz_filp = NULL;
341         if (rdev->cmask_filp == file_priv)
342                 rdev->cmask_filp = NULL;
343 }
344
345 /*
346  * VBlank related functions.
347  */
348 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
349 {
350         struct radeon_device *rdev = dev->dev_private;
351
352         if (crtc < 0 || crtc >= rdev->num_crtc) {
353                 DRM_ERROR("Invalid crtc %d\n", crtc);
354                 return -EINVAL;
355         }
356
357         return radeon_get_vblank_counter(rdev, crtc);
358 }
359
360 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
361 {
362         struct radeon_device *rdev = dev->dev_private;
363
364         if (crtc < 0 || crtc >= rdev->num_crtc) {
365                 DRM_ERROR("Invalid crtc %d\n", crtc);
366                 return -EINVAL;
367         }
368
369         rdev->irq.crtc_vblank_int[crtc] = true;
370
371         return radeon_irq_set(rdev);
372 }
373
374 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
375 {
376         struct radeon_device *rdev = dev->dev_private;
377
378         if (crtc < 0 || crtc >= rdev->num_crtc) {
379                 DRM_ERROR("Invalid crtc %d\n", crtc);
380                 return;
381         }
382
383         rdev->irq.crtc_vblank_int[crtc] = false;
384
385         radeon_irq_set(rdev);
386 }
387
388 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
389                                     int *max_error,
390                                     struct timeval *vblank_time,
391                                     unsigned flags)
392 {
393         struct drm_crtc *drmcrtc;
394         struct radeon_device *rdev = dev->dev_private;
395
396         if (crtc < 0 || crtc >= dev->num_crtcs) {
397                 DRM_ERROR("Invalid crtc %d\n", crtc);
398                 return -EINVAL;
399         }
400
401         /* Get associated drm_crtc: */
402         drmcrtc = &rdev->mode_info.crtcs[crtc]->base;
403
404         /* Helper routine in DRM core does all the work: */
405         return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
406                                                      vblank_time, flags,
407                                                      drmcrtc);
408 }
409
410 /*
411  * IOCTL.
412  */
413 int radeon_dma_ioctl_kms(struct drm_device *dev, void *data,
414                          struct drm_file *file_priv)
415 {
416         /* Not valid in KMS. */
417         return -EINVAL;
418 }
419
420 #define KMS_INVALID_IOCTL(name)                                         \
421 int name(struct drm_device *dev, void *data, struct drm_file *file_priv)\
422 {                                                                       \
423         DRM_ERROR("invalid ioctl with kms %s\n", __func__);             \
424         return -EINVAL;                                                 \
425 }
426
427 /*
428  * All these ioctls are invalid in kms world.
429  */
430 KMS_INVALID_IOCTL(radeon_cp_init_kms)
431 KMS_INVALID_IOCTL(radeon_cp_start_kms)
432 KMS_INVALID_IOCTL(radeon_cp_stop_kms)
433 KMS_INVALID_IOCTL(radeon_cp_reset_kms)
434 KMS_INVALID_IOCTL(radeon_cp_idle_kms)
435 KMS_INVALID_IOCTL(radeon_cp_resume_kms)
436 KMS_INVALID_IOCTL(radeon_engine_reset_kms)
437 KMS_INVALID_IOCTL(radeon_fullscreen_kms)
438 KMS_INVALID_IOCTL(radeon_cp_swap_kms)
439 KMS_INVALID_IOCTL(radeon_cp_clear_kms)
440 KMS_INVALID_IOCTL(radeon_cp_vertex_kms)
441 KMS_INVALID_IOCTL(radeon_cp_indices_kms)
442 KMS_INVALID_IOCTL(radeon_cp_texture_kms)
443 KMS_INVALID_IOCTL(radeon_cp_stipple_kms)
444 KMS_INVALID_IOCTL(radeon_cp_indirect_kms)
445 KMS_INVALID_IOCTL(radeon_cp_vertex2_kms)
446 KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms)
447 KMS_INVALID_IOCTL(radeon_cp_getparam_kms)
448 KMS_INVALID_IOCTL(radeon_cp_flip_kms)
449 KMS_INVALID_IOCTL(radeon_mem_alloc_kms)
450 KMS_INVALID_IOCTL(radeon_mem_free_kms)
451 KMS_INVALID_IOCTL(radeon_mem_init_heap_kms)
452 KMS_INVALID_IOCTL(radeon_irq_emit_kms)
453 KMS_INVALID_IOCTL(radeon_irq_wait_kms)
454 KMS_INVALID_IOCTL(radeon_cp_setparam_kms)
455 KMS_INVALID_IOCTL(radeon_surface_alloc_kms)
456 KMS_INVALID_IOCTL(radeon_surface_free_kms)
457
458
459 struct drm_ioctl_desc radeon_ioctls_kms[] = {
460         DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
461         DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
462         DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
463         DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
464         DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
465         DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
466         DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
467         DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
468         DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
469         DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
470         DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
471         DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
472         DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
473         DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
474         DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
475         DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
476         DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
477         DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
478         DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
479         DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
480         DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
481         DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
482         DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
483         DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
484         DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
485         DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
486         DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
487         /* KMS */
488         DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
489         DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED),
490         DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED),
491         DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED),
492         DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED),
493         DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED),
494         DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED),
495         DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED),
496         DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
497         DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
498         DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
499         DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
500         DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED),
501 };
502 int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms);