Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-2.6
[linux-2.6.git] / drivers / gpu / drm / radeon / radeon_encoders.c
1 /*
2  * Copyright 2007-8 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: Dave Airlie
24  *          Alex Deucher
25  */
26 #include "drmP.h"
27 #include "drm_crtc_helper.h"
28 #include "radeon_drm.h"
29 #include "radeon.h"
30 #include "atom.h"
31
32 extern int atom_debug;
33
34 /* evil but including atombios.h is much worse */
35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36                                 struct drm_display_mode *mode);
37
38 static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
39 {
40         struct drm_device *dev = encoder->dev;
41         struct radeon_device *rdev = dev->dev_private;
42         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
43         struct drm_encoder *clone_encoder;
44         uint32_t index_mask = 0;
45         int count;
46
47         /* DIG routing gets problematic */
48         if (rdev->family >= CHIP_R600)
49                 return index_mask;
50         /* LVDS/TV are too wacky */
51         if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
52                 return index_mask;
53         /* DVO requires 2x ppll clocks depending on tmds chip */
54         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
55                 return index_mask;
56
57         count = -1;
58         list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
59                 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
60                 count++;
61
62                 if (clone_encoder == encoder)
63                         continue;
64                 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
65                         continue;
66                 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
67                         continue;
68                 else
69                         index_mask |= (1 << count);
70         }
71         return index_mask;
72 }
73
74 void radeon_setup_encoder_clones(struct drm_device *dev)
75 {
76         struct drm_encoder *encoder;
77
78         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
79                 encoder->possible_clones = radeon_encoder_clones(encoder);
80         }
81 }
82
83 uint32_t
84 radeon_get_encoder_id(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
85 {
86         struct radeon_device *rdev = dev->dev_private;
87         uint32_t ret = 0;
88
89         switch (supported_device) {
90         case ATOM_DEVICE_CRT1_SUPPORT:
91         case ATOM_DEVICE_TV1_SUPPORT:
92         case ATOM_DEVICE_TV2_SUPPORT:
93         case ATOM_DEVICE_CRT2_SUPPORT:
94         case ATOM_DEVICE_CV_SUPPORT:
95                 switch (dac) {
96                 case 1: /* dac a */
97                         if ((rdev->family == CHIP_RS300) ||
98                             (rdev->family == CHIP_RS400) ||
99                             (rdev->family == CHIP_RS480))
100                                 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
101                         else if (ASIC_IS_AVIVO(rdev))
102                                 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1;
103                         else
104                                 ret = ENCODER_OBJECT_ID_INTERNAL_DAC1;
105                         break;
106                 case 2: /* dac b */
107                         if (ASIC_IS_AVIVO(rdev))
108                                 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2;
109                         else {
110                                 /*if (rdev->family == CHIP_R200)
111                                   ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
112                                   else*/
113                                 ret = ENCODER_OBJECT_ID_INTERNAL_DAC2;
114                         }
115                         break;
116                 case 3: /* external dac */
117                         if (ASIC_IS_AVIVO(rdev))
118                                 ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
119                         else
120                                 ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
121                         break;
122                 }
123                 break;
124         case ATOM_DEVICE_LCD1_SUPPORT:
125                 if (ASIC_IS_AVIVO(rdev))
126                         ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
127                 else
128                         ret = ENCODER_OBJECT_ID_INTERNAL_LVDS;
129                 break;
130         case ATOM_DEVICE_DFP1_SUPPORT:
131                 if ((rdev->family == CHIP_RS300) ||
132                     (rdev->family == CHIP_RS400) ||
133                     (rdev->family == CHIP_RS480))
134                         ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
135                 else if (ASIC_IS_AVIVO(rdev))
136                         ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1;
137                 else
138                         ret = ENCODER_OBJECT_ID_INTERNAL_TMDS1;
139                 break;
140         case ATOM_DEVICE_LCD2_SUPPORT:
141         case ATOM_DEVICE_DFP2_SUPPORT:
142                 if ((rdev->family == CHIP_RS600) ||
143                     (rdev->family == CHIP_RS690) ||
144                     (rdev->family == CHIP_RS740))
145                         ret = ENCODER_OBJECT_ID_INTERNAL_DDI;
146                 else if (ASIC_IS_AVIVO(rdev))
147                         ret = ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1;
148                 else
149                         ret = ENCODER_OBJECT_ID_INTERNAL_DVO1;
150                 break;
151         case ATOM_DEVICE_DFP3_SUPPORT:
152                 ret = ENCODER_OBJECT_ID_INTERNAL_LVTM1;
153                 break;
154         }
155
156         return ret;
157 }
158
159 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
160 {
161         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
162         switch (radeon_encoder->encoder_id) {
163         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
164         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
165         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
166         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
167         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
168         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
169         case ENCODER_OBJECT_ID_INTERNAL_DDI:
170         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
171         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
172         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
173         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
174                 return true;
175         default:
176                 return false;
177         }
178 }
179 void
180 radeon_link_encoder_connector(struct drm_device *dev)
181 {
182         struct drm_connector *connector;
183         struct radeon_connector *radeon_connector;
184         struct drm_encoder *encoder;
185         struct radeon_encoder *radeon_encoder;
186
187         /* walk the list and link encoders to connectors */
188         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
189                 radeon_connector = to_radeon_connector(connector);
190                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
191                         radeon_encoder = to_radeon_encoder(encoder);
192                         if (radeon_encoder->devices & radeon_connector->devices)
193                                 drm_mode_connector_attach_encoder(connector, encoder);
194                 }
195         }
196 }
197
198 void radeon_encoder_set_active_device(struct drm_encoder *encoder)
199 {
200         struct drm_device *dev = encoder->dev;
201         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
202         struct drm_connector *connector;
203
204         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
205                 if (connector->encoder == encoder) {
206                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
207                         radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
208                         DRM_DEBUG("setting active device to %08x from %08x %08x for encoder %d\n",
209                                   radeon_encoder->active_device, radeon_encoder->devices,
210                                   radeon_connector->devices, encoder->encoder_type);
211                 }
212         }
213 }
214
215 static struct drm_connector *
216 radeon_get_connector_for_encoder(struct drm_encoder *encoder)
217 {
218         struct drm_device *dev = encoder->dev;
219         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
220         struct drm_connector *connector;
221         struct radeon_connector *radeon_connector;
222
223         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
224                 radeon_connector = to_radeon_connector(connector);
225                 if (radeon_encoder->active_device & radeon_connector->devices)
226                         return connector;
227         }
228         return NULL;
229 }
230
231 static struct radeon_connector_atom_dig *
232 radeon_get_atom_connector_priv_from_encoder(struct drm_encoder *encoder)
233 {
234         struct drm_device *dev = encoder->dev;
235         struct radeon_device *rdev = dev->dev_private;
236         struct drm_connector *connector;
237         struct radeon_connector *radeon_connector;
238         struct radeon_connector_atom_dig *dig_connector;
239
240         if (!rdev->is_atom_bios)
241                 return NULL;
242
243         connector = radeon_get_connector_for_encoder(encoder);
244         if (!connector)
245                 return NULL;
246
247         radeon_connector = to_radeon_connector(connector);
248
249         if (!radeon_connector->con_priv)
250                 return NULL;
251
252         dig_connector = radeon_connector->con_priv;
253
254         return dig_connector;
255 }
256
257 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
258                                    struct drm_display_mode *mode,
259                                    struct drm_display_mode *adjusted_mode)
260 {
261         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
262         struct drm_device *dev = encoder->dev;
263         struct radeon_device *rdev = dev->dev_private;
264
265         /* adjust pm to upcoming mode change */
266         radeon_pm_compute_clocks(rdev);
267
268         /* set the active encoder to connector routing */
269         radeon_encoder_set_active_device(encoder);
270         drm_mode_set_crtcinfo(adjusted_mode, 0);
271
272         /* hw bug */
273         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
274             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
275                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
276
277         /* get the native mode for LVDS */
278         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
279                 struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
280                 int mode_id = adjusted_mode->base.id;
281                 *adjusted_mode = *native_mode;
282                 if (!ASIC_IS_AVIVO(rdev)) {
283                         adjusted_mode->hdisplay = mode->hdisplay;
284                         adjusted_mode->vdisplay = mode->vdisplay;
285                         adjusted_mode->crtc_hdisplay = mode->hdisplay;
286                         adjusted_mode->crtc_vdisplay = mode->vdisplay;
287                 }
288                 adjusted_mode->base.id = mode_id;
289         }
290
291         /* get the native mode for TV */
292         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
293                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
294                 if (tv_dac) {
295                         if (tv_dac->tv_std == TV_STD_NTSC ||
296                             tv_dac->tv_std == TV_STD_NTSC_J ||
297                             tv_dac->tv_std == TV_STD_PAL_M)
298                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
299                         else
300                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
301                 }
302         }
303
304         if (ASIC_IS_DCE3(rdev) &&
305             (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))) {
306                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
307                 radeon_dp_set_link_config(connector, mode);
308         }
309
310         return true;
311 }
312
313 static void
314 atombios_dac_setup(struct drm_encoder *encoder, int action)
315 {
316         struct drm_device *dev = encoder->dev;
317         struct radeon_device *rdev = dev->dev_private;
318         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
319         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
320         int index = 0, num = 0;
321         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
322         enum radeon_tv_std tv_std = TV_STD_NTSC;
323
324         if (dac_info->tv_std)
325                 tv_std = dac_info->tv_std;
326
327         memset(&args, 0, sizeof(args));
328
329         switch (radeon_encoder->encoder_id) {
330         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
331         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
332                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
333                 num = 1;
334                 break;
335         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
336         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
337                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
338                 num = 2;
339                 break;
340         }
341
342         args.ucAction = action;
343
344         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
345                 args.ucDacStandard = ATOM_DAC1_PS2;
346         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
347                 args.ucDacStandard = ATOM_DAC1_CV;
348         else {
349                 switch (tv_std) {
350                 case TV_STD_PAL:
351                 case TV_STD_PAL_M:
352                 case TV_STD_SCART_PAL:
353                 case TV_STD_SECAM:
354                 case TV_STD_PAL_CN:
355                         args.ucDacStandard = ATOM_DAC1_PAL;
356                         break;
357                 case TV_STD_NTSC:
358                 case TV_STD_NTSC_J:
359                 case TV_STD_PAL_60:
360                 default:
361                         args.ucDacStandard = ATOM_DAC1_NTSC;
362                         break;
363                 }
364         }
365         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
366
367         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
368
369 }
370
371 static void
372 atombios_tv_setup(struct drm_encoder *encoder, int action)
373 {
374         struct drm_device *dev = encoder->dev;
375         struct radeon_device *rdev = dev->dev_private;
376         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
377         TV_ENCODER_CONTROL_PS_ALLOCATION args;
378         int index = 0;
379         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
380         enum radeon_tv_std tv_std = TV_STD_NTSC;
381
382         if (dac_info->tv_std)
383                 tv_std = dac_info->tv_std;
384
385         memset(&args, 0, sizeof(args));
386
387         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
388
389         args.sTVEncoder.ucAction = action;
390
391         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
392                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
393         else {
394                 switch (tv_std) {
395                 case TV_STD_NTSC:
396                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
397                         break;
398                 case TV_STD_PAL:
399                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
400                         break;
401                 case TV_STD_PAL_M:
402                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
403                         break;
404                 case TV_STD_PAL_60:
405                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
406                         break;
407                 case TV_STD_NTSC_J:
408                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
409                         break;
410                 case TV_STD_SCART_PAL:
411                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
412                         break;
413                 case TV_STD_SECAM:
414                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
415                         break;
416                 case TV_STD_PAL_CN:
417                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
418                         break;
419                 default:
420                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
421                         break;
422                 }
423         }
424
425         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
426
427         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
428
429 }
430
431 void
432 atombios_external_tmds_setup(struct drm_encoder *encoder, int action)
433 {
434         struct drm_device *dev = encoder->dev;
435         struct radeon_device *rdev = dev->dev_private;
436         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
437         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION args;
438         int index = 0;
439
440         memset(&args, 0, sizeof(args));
441
442         index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
443
444         args.sXTmdsEncoder.ucEnable = action;
445
446         if (radeon_encoder->pixel_clock > 165000)
447                 args.sXTmdsEncoder.ucMisc = PANEL_ENCODER_MISC_DUAL;
448
449         /*if (pScrn->rgbBits == 8)*/
450         args.sXTmdsEncoder.ucMisc |= (1 << 1);
451
452         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
453
454 }
455
456 static void
457 atombios_ddia_setup(struct drm_encoder *encoder, int action)
458 {
459         struct drm_device *dev = encoder->dev;
460         struct radeon_device *rdev = dev->dev_private;
461         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
462         DVO_ENCODER_CONTROL_PS_ALLOCATION args;
463         int index = 0;
464
465         memset(&args, 0, sizeof(args));
466
467         index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
468
469         args.sDVOEncoder.ucAction = action;
470         args.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
471
472         if (radeon_encoder->pixel_clock > 165000)
473                 args.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute = PANEL_ENCODER_MISC_DUAL;
474
475         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
476
477 }
478
479 union lvds_encoder_control {
480         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
481         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
482 };
483
484 void
485 atombios_digital_setup(struct drm_encoder *encoder, int action)
486 {
487         struct drm_device *dev = encoder->dev;
488         struct radeon_device *rdev = dev->dev_private;
489         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
490         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
491         struct radeon_connector_atom_dig *dig_connector =
492                 radeon_get_atom_connector_priv_from_encoder(encoder);
493         union lvds_encoder_control args;
494         int index = 0;
495         int hdmi_detected = 0;
496         uint8_t frev, crev;
497
498         if (!dig || !dig_connector)
499                 return;
500
501         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
502                 hdmi_detected = 1;
503
504         memset(&args, 0, sizeof(args));
505
506         switch (radeon_encoder->encoder_id) {
507         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
508                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
509                 break;
510         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
511         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
512                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
513                 break;
514         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
515                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
516                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
517                 else
518                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
519                 break;
520         }
521
522         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
523                 return;
524
525         switch (frev) {
526         case 1:
527         case 2:
528                 switch (crev) {
529                 case 1:
530                         args.v1.ucMisc = 0;
531                         args.v1.ucAction = action;
532                         if (hdmi_detected)
533                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
534                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
535                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
536                                 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
537                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
538                                 if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
539                                         args.v1.ucMisc |= (1 << 1);
540                         } else {
541                                 if (dig_connector->linkb)
542                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
543                                 if (radeon_encoder->pixel_clock > 165000)
544                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
545                                 /*if (pScrn->rgbBits == 8) */
546                                 args.v1.ucMisc |= (1 << 1);
547                         }
548                         break;
549                 case 2:
550                 case 3:
551                         args.v2.ucMisc = 0;
552                         args.v2.ucAction = action;
553                         if (crev == 3) {
554                                 if (dig->coherent_mode)
555                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
556                         }
557                         if (hdmi_detected)
558                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
559                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
560                         args.v2.ucTruncate = 0;
561                         args.v2.ucSpatial = 0;
562                         args.v2.ucTemporal = 0;
563                         args.v2.ucFRC = 0;
564                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
565                                 if (dig->lvds_misc & ATOM_PANEL_MISC_DUAL)
566                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
567                                 if (dig->lvds_misc & ATOM_PANEL_MISC_SPATIAL) {
568                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
569                                         if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
570                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
571                                 }
572                                 if (dig->lvds_misc & ATOM_PANEL_MISC_TEMPORAL) {
573                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
574                                         if (dig->lvds_misc & ATOM_PANEL_MISC_888RGB)
575                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
576                                         if (((dig->lvds_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
577                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
578                                 }
579                         } else {
580                                 if (dig_connector->linkb)
581                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
582                                 if (radeon_encoder->pixel_clock > 165000)
583                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
584                         }
585                         break;
586                 default:
587                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
588                         break;
589                 }
590                 break;
591         default:
592                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
593                 break;
594         }
595
596         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
597 }
598
599 int
600 atombios_get_encoder_mode(struct drm_encoder *encoder)
601 {
602         struct drm_connector *connector;
603         struct radeon_connector *radeon_connector;
604         struct radeon_connector_atom_dig *dig_connector;
605
606         connector = radeon_get_connector_for_encoder(encoder);
607         if (!connector)
608                 return 0;
609
610         radeon_connector = to_radeon_connector(connector);
611
612         switch (connector->connector_type) {
613         case DRM_MODE_CONNECTOR_DVII:
614         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
615                 if (drm_detect_hdmi_monitor(radeon_connector->edid))
616                         return ATOM_ENCODER_MODE_HDMI;
617                 else if (radeon_connector->use_digital)
618                         return ATOM_ENCODER_MODE_DVI;
619                 else
620                         return ATOM_ENCODER_MODE_CRT;
621                 break;
622         case DRM_MODE_CONNECTOR_DVID:
623         case DRM_MODE_CONNECTOR_HDMIA:
624         default:
625                 if (drm_detect_hdmi_monitor(radeon_connector->edid))
626                         return ATOM_ENCODER_MODE_HDMI;
627                 else
628                         return ATOM_ENCODER_MODE_DVI;
629                 break;
630         case DRM_MODE_CONNECTOR_LVDS:
631                 return ATOM_ENCODER_MODE_LVDS;
632                 break;
633         case DRM_MODE_CONNECTOR_DisplayPort:
634         case DRM_MODE_CONNECTOR_eDP:
635                 dig_connector = radeon_connector->con_priv;
636                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
637                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
638                         return ATOM_ENCODER_MODE_DP;
639                 else if (drm_detect_hdmi_monitor(radeon_connector->edid))
640                         return ATOM_ENCODER_MODE_HDMI;
641                 else
642                         return ATOM_ENCODER_MODE_DVI;
643                 break;
644         case DRM_MODE_CONNECTOR_DVIA:
645         case DRM_MODE_CONNECTOR_VGA:
646                 return ATOM_ENCODER_MODE_CRT;
647                 break;
648         case DRM_MODE_CONNECTOR_Composite:
649         case DRM_MODE_CONNECTOR_SVIDEO:
650         case DRM_MODE_CONNECTOR_9PinDIN:
651                 /* fix me */
652                 return ATOM_ENCODER_MODE_TV;
653                 /*return ATOM_ENCODER_MODE_CV;*/
654                 break;
655         }
656 }
657
658 /*
659  * DIG Encoder/Transmitter Setup
660  *
661  * DCE 3.0/3.1
662  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
663  * Supports up to 3 digital outputs
664  * - 2 DIG encoder blocks.
665  * DIG1 can drive UNIPHY link A or link B
666  * DIG2 can drive UNIPHY link B or LVTMA
667  *
668  * DCE 3.2
669  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
670  * Supports up to 5 digital outputs
671  * - 2 DIG encoder blocks.
672  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
673  *
674  * DCE 4.0
675  * - 3 DIG transmitter blocks UNPHY0/1/2 (links A and B).
676  * Supports up to 6 digital outputs
677  * - 6 DIG encoder blocks.
678  * - DIG to PHY mapping is hardcoded
679  * DIG1 drives UNIPHY0 link A, A+B
680  * DIG2 drives UNIPHY0 link B
681  * DIG3 drives UNIPHY1 link A, A+B
682  * DIG4 drives UNIPHY1 link B
683  * DIG5 drives UNIPHY2 link A, A+B
684  * DIG6 drives UNIPHY2 link B
685  *
686  * Routing
687  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
688  * Examples:
689  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
690  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
691  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
692  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
693  */
694
695 union dig_encoder_control {
696         DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
697         DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
698         DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
699 };
700
701 void
702 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
703 {
704         struct drm_device *dev = encoder->dev;
705         struct radeon_device *rdev = dev->dev_private;
706         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
707         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
708         struct radeon_connector_atom_dig *dig_connector =
709                 radeon_get_atom_connector_priv_from_encoder(encoder);
710         union dig_encoder_control args;
711         int index = 0;
712         uint8_t frev, crev;
713
714         if (!dig || !dig_connector)
715                 return;
716
717         memset(&args, 0, sizeof(args));
718
719         if (ASIC_IS_DCE4(rdev))
720                 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
721         else {
722                 if (dig->dig_encoder)
723                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
724                 else
725                         index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
726         }
727
728         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
729                 return;
730
731         args.v1.ucAction = action;
732         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
733         args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
734
735         if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
736                 if (dig_connector->dp_clock == 270000)
737                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
738                 args.v1.ucLaneNum = dig_connector->dp_lane_count;
739         } else if (radeon_encoder->pixel_clock > 165000)
740                 args.v1.ucLaneNum = 8;
741         else
742                 args.v1.ucLaneNum = 4;
743
744         if (ASIC_IS_DCE4(rdev)) {
745                 args.v3.acConfig.ucDigSel = dig->dig_encoder;
746                 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
747         } else {
748                 switch (radeon_encoder->encoder_id) {
749                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
750                         args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
751                         break;
752                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
753                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
754                         args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
755                         break;
756                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
757                         args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
758                         break;
759                 }
760                 if (dig_connector->linkb)
761                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
762                 else
763                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
764         }
765
766         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
767
768 }
769
770 union dig_transmitter_control {
771         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
772         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
773         DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
774 };
775
776 void
777 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
778 {
779         struct drm_device *dev = encoder->dev;
780         struct radeon_device *rdev = dev->dev_private;
781         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
782         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
783         struct radeon_connector_atom_dig *dig_connector =
784                 radeon_get_atom_connector_priv_from_encoder(encoder);
785         struct drm_connector *connector;
786         struct radeon_connector *radeon_connector;
787         union dig_transmitter_control args;
788         int index = 0;
789         uint8_t frev, crev;
790         bool is_dp = false;
791         int pll_id = 0;
792
793         if (!dig || !dig_connector)
794                 return;
795
796         connector = radeon_get_connector_for_encoder(encoder);
797         radeon_connector = to_radeon_connector(connector);
798
799         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
800                 is_dp = true;
801
802         memset(&args, 0, sizeof(args));
803
804         if (ASIC_IS_DCE32(rdev) || ASIC_IS_DCE4(rdev))
805                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
806         else {
807                 switch (radeon_encoder->encoder_id) {
808                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
809                         index = GetIndexIntoMasterTable(COMMAND, DIG1TransmitterControl);
810                         break;
811                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
812                         index = GetIndexIntoMasterTable(COMMAND, DIG2TransmitterControl);
813                         break;
814                 }
815         }
816
817         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
818                 return;
819
820         args.v1.ucAction = action;
821         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
822                 args.v1.usInitInfo = radeon_connector->connector_object_id;
823         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
824                 args.v1.asMode.ucLaneSel = lane_num;
825                 args.v1.asMode.ucLaneSet = lane_set;
826         } else {
827                 if (is_dp)
828                         args.v1.usPixelClock =
829                                 cpu_to_le16(dig_connector->dp_clock / 10);
830                 else if (radeon_encoder->pixel_clock > 165000)
831                         args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
832                 else
833                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
834         }
835         if (ASIC_IS_DCE4(rdev)) {
836                 if (is_dp)
837                         args.v3.ucLaneNum = dig_connector->dp_lane_count;
838                 else if (radeon_encoder->pixel_clock > 165000)
839                         args.v3.ucLaneNum = 8;
840                 else
841                         args.v3.ucLaneNum = 4;
842
843                 if (dig_connector->linkb) {
844                         args.v3.acConfig.ucLinkSel = 1;
845                         args.v3.acConfig.ucEncoderSel = 1;
846                 }
847
848                 /* Select the PLL for the PHY
849                  * DP PHY should be clocked from external src if there is
850                  * one.
851                  */
852                 if (encoder->crtc) {
853                         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
854                         pll_id = radeon_crtc->pll_id;
855                 }
856                 if (is_dp && rdev->clock.dp_extclk)
857                         args.v3.acConfig.ucRefClkSource = 2; /* external src */
858                 else
859                         args.v3.acConfig.ucRefClkSource = pll_id;
860
861                 switch (radeon_encoder->encoder_id) {
862                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
863                         args.v3.acConfig.ucTransmitterSel = 0;
864                         break;
865                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
866                         args.v3.acConfig.ucTransmitterSel = 1;
867                         break;
868                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
869                         args.v3.acConfig.ucTransmitterSel = 2;
870                         break;
871                 }
872
873                 if (is_dp)
874                         args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
875                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
876                         if (dig->coherent_mode)
877                                 args.v3.acConfig.fCoherentMode = 1;
878                 }
879         } else if (ASIC_IS_DCE32(rdev)) {
880                 args.v2.acConfig.ucEncoderSel = dig->dig_encoder;
881                 if (dig_connector->linkb)
882                         args.v2.acConfig.ucLinkSel = 1;
883
884                 switch (radeon_encoder->encoder_id) {
885                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
886                         args.v2.acConfig.ucTransmitterSel = 0;
887                         break;
888                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
889                         args.v2.acConfig.ucTransmitterSel = 1;
890                         break;
891                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
892                         args.v2.acConfig.ucTransmitterSel = 2;
893                         break;
894                 }
895
896                 if (is_dp)
897                         args.v2.acConfig.fCoherentMode = 1;
898                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
899                         if (dig->coherent_mode)
900                                 args.v2.acConfig.fCoherentMode = 1;
901                 }
902         } else {
903                 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
904
905                 if (dig->dig_encoder)
906                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
907                 else
908                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
909
910                 if ((rdev->flags & RADEON_IS_IGP) &&
911                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
912                         if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
913                                 if (dig_connector->igp_lane_info & 0x1)
914                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
915                                 else if (dig_connector->igp_lane_info & 0x2)
916                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
917                                 else if (dig_connector->igp_lane_info & 0x4)
918                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
919                                 else if (dig_connector->igp_lane_info & 0x8)
920                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
921                         } else {
922                                 if (dig_connector->igp_lane_info & 0x3)
923                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
924                                 else if (dig_connector->igp_lane_info & 0xc)
925                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
926                         }
927                 }
928
929                 if (dig_connector->linkb)
930                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
931                 else
932                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
933
934                 if (is_dp)
935                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
936                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
937                         if (dig->coherent_mode)
938                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
939                         if (radeon_encoder->pixel_clock > 165000)
940                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
941                 }
942         }
943
944         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
945 }
946
947 static void
948 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
949 {
950         struct drm_device *dev = encoder->dev;
951         struct radeon_device *rdev = dev->dev_private;
952         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
953         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
954         ENABLE_YUV_PS_ALLOCATION args;
955         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
956         uint32_t temp, reg;
957
958         memset(&args, 0, sizeof(args));
959
960         if (rdev->family >= CHIP_R600)
961                 reg = R600_BIOS_3_SCRATCH;
962         else
963                 reg = RADEON_BIOS_3_SCRATCH;
964
965         /* XXX: fix up scratch reg handling */
966         temp = RREG32(reg);
967         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
968                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
969                              (radeon_crtc->crtc_id << 18)));
970         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
971                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
972         else
973                 WREG32(reg, 0);
974
975         if (enable)
976                 args.ucEnable = ATOM_ENABLE;
977         args.ucCRTC = radeon_crtc->crtc_id;
978
979         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
980
981         WREG32(reg, temp);
982 }
983
984 static void
985 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
986 {
987         struct drm_device *dev = encoder->dev;
988         struct radeon_device *rdev = dev->dev_private;
989         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
990         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
991         int index = 0;
992         bool is_dig = false;
993
994         memset(&args, 0, sizeof(args));
995
996         DRM_DEBUG("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
997                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
998                   radeon_encoder->active_device);
999         switch (radeon_encoder->encoder_id) {
1000         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1001         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1002                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1003                 break;
1004         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1005         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1006         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1007         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1008                 is_dig = true;
1009                 break;
1010         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1011         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1012         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1013                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1014                 break;
1015         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1016                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1017                 break;
1018         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1019                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1020                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1021                 else
1022                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1023                 break;
1024         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1025         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1026                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1027                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1028                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1029                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1030                 else
1031                         index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1032                 break;
1033         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1034         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1035                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1036                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1037                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1038                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1039                 else
1040                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1041                 break;
1042         }
1043
1044         if (is_dig) {
1045                 switch (mode) {
1046                 case DRM_MODE_DPMS_ON:
1047                         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1048                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1049
1050                                 dp_link_train(encoder, connector);
1051                                 if (ASIC_IS_DCE4(rdev))
1052                                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON);
1053                         }
1054                         if (!ASIC_IS_DCE4(rdev))
1055                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1056                         break;
1057                 case DRM_MODE_DPMS_STANDBY:
1058                 case DRM_MODE_DPMS_SUSPEND:
1059                 case DRM_MODE_DPMS_OFF:
1060                         if (!ASIC_IS_DCE4(rdev))
1061                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1062                         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1063                                 if (ASIC_IS_DCE4(rdev))
1064                                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF);
1065                         }
1066                         break;
1067                 }
1068         } else {
1069                 switch (mode) {
1070                 case DRM_MODE_DPMS_ON:
1071                         args.ucAction = ATOM_ENABLE;
1072                         break;
1073                 case DRM_MODE_DPMS_STANDBY:
1074                 case DRM_MODE_DPMS_SUSPEND:
1075                 case DRM_MODE_DPMS_OFF:
1076                         args.ucAction = ATOM_DISABLE;
1077                         break;
1078                 }
1079                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1080         }
1081         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1082
1083         /* adjust pm to dpms change */
1084         radeon_pm_compute_clocks(rdev);
1085 }
1086
1087 union crtc_source_param {
1088         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1089         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1090 };
1091
1092 static void
1093 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1094 {
1095         struct drm_device *dev = encoder->dev;
1096         struct radeon_device *rdev = dev->dev_private;
1097         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1098         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1099         union crtc_source_param args;
1100         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1101         uint8_t frev, crev;
1102         struct radeon_encoder_atom_dig *dig;
1103
1104         memset(&args, 0, sizeof(args));
1105
1106         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1107                 return;
1108
1109         switch (frev) {
1110         case 1:
1111                 switch (crev) {
1112                 case 1:
1113                 default:
1114                         if (ASIC_IS_AVIVO(rdev))
1115                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
1116                         else {
1117                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1118                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
1119                                 } else {
1120                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1121                                 }
1122                         }
1123                         switch (radeon_encoder->encoder_id) {
1124                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1125                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1126                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1127                                 break;
1128                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1129                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1130                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1131                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1132                                 else
1133                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1134                                 break;
1135                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1136                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1137                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1138                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1139                                 break;
1140                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1141                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1142                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1143                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1144                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1145                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1146                                 else
1147                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1148                                 break;
1149                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1150                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1151                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1152                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1153                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1154                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1155                                 else
1156                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1157                                 break;
1158                         }
1159                         break;
1160                 case 2:
1161                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1162                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1163                         switch (radeon_encoder->encoder_id) {
1164                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1165                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1166                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1167                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1168                                 dig = radeon_encoder->enc_priv;
1169                                 switch (dig->dig_encoder) {
1170                                 case 0:
1171                                         args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1172                                         break;
1173                                 case 1:
1174                                         args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1175                                         break;
1176                                 case 2:
1177                                         args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1178                                         break;
1179                                 case 3:
1180                                         args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1181                                         break;
1182                                 case 4:
1183                                         args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1184                                         break;
1185                                 case 5:
1186                                         args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1187                                         break;
1188                                 }
1189                                 break;
1190                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1191                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1192                                 break;
1193                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1194                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1195                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1196                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1197                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1198                                 else
1199                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1200                                 break;
1201                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1202                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1203                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1204                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1205                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1206                                 else
1207                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1208                                 break;
1209                         }
1210                         break;
1211                 }
1212                 break;
1213         default:
1214                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1215                 break;
1216         }
1217
1218         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1219
1220         /* update scratch regs with new routing */
1221         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1222 }
1223
1224 static void
1225 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1226                               struct drm_display_mode *mode)
1227 {
1228         struct drm_device *dev = encoder->dev;
1229         struct radeon_device *rdev = dev->dev_private;
1230         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1231         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1232
1233         /* Funky macbooks */
1234         if ((dev->pdev->device == 0x71C5) &&
1235             (dev->pdev->subsystem_vendor == 0x106b) &&
1236             (dev->pdev->subsystem_device == 0x0080)) {
1237                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1238                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1239
1240                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1241                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1242
1243                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1244                 }
1245         }
1246
1247         /* set scaler clears this on some chips */
1248         /* XXX check DCE4 */
1249         if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) {
1250                 if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
1251                         WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1252                                AVIVO_D1MODE_INTERLEAVE_EN);
1253         }
1254 }
1255
1256 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1257 {
1258         struct drm_device *dev = encoder->dev;
1259         struct radeon_device *rdev = dev->dev_private;
1260         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1261         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1262         struct drm_encoder *test_encoder;
1263         struct radeon_encoder_atom_dig *dig;
1264         uint32_t dig_enc_in_use = 0;
1265
1266         if (ASIC_IS_DCE4(rdev)) {
1267                 struct radeon_connector_atom_dig *dig_connector =
1268                         radeon_get_atom_connector_priv_from_encoder(encoder);
1269
1270                 switch (radeon_encoder->encoder_id) {
1271                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1272                         if (dig_connector->linkb)
1273                                 return 1;
1274                         else
1275                                 return 0;
1276                         break;
1277                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1278                         if (dig_connector->linkb)
1279                                 return 3;
1280                         else
1281                                 return 2;
1282                         break;
1283                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1284                         if (dig_connector->linkb)
1285                                 return 5;
1286                         else
1287                                 return 4;
1288                         break;
1289                 }
1290         }
1291
1292         /* on DCE32 and encoder can driver any block so just crtc id */
1293         if (ASIC_IS_DCE32(rdev)) {
1294                 return radeon_crtc->crtc_id;
1295         }
1296
1297         /* on DCE3 - LVTMA can only be driven by DIGB */
1298         list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1299                 struct radeon_encoder *radeon_test_encoder;
1300
1301                 if (encoder == test_encoder)
1302                         continue;
1303
1304                 if (!radeon_encoder_is_digital(test_encoder))
1305                         continue;
1306
1307                 radeon_test_encoder = to_radeon_encoder(test_encoder);
1308                 dig = radeon_test_encoder->enc_priv;
1309
1310                 if (dig->dig_encoder >= 0)
1311                         dig_enc_in_use |= (1 << dig->dig_encoder);
1312         }
1313
1314         if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1315                 if (dig_enc_in_use & 0x2)
1316                         DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1317                 return 1;
1318         }
1319         if (!(dig_enc_in_use & 1))
1320                 return 0;
1321         return 1;
1322 }
1323
1324 static void
1325 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1326                              struct drm_display_mode *mode,
1327                              struct drm_display_mode *adjusted_mode)
1328 {
1329         struct drm_device *dev = encoder->dev;
1330         struct radeon_device *rdev = dev->dev_private;
1331         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1332
1333         radeon_encoder->pixel_clock = adjusted_mode->clock;
1334
1335         if (ASIC_IS_AVIVO(rdev)) {
1336                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1337                         atombios_yuv_setup(encoder, true);
1338                 else
1339                         atombios_yuv_setup(encoder, false);
1340         }
1341
1342         switch (radeon_encoder->encoder_id) {
1343         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1344         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1345         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1346         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1347                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1348                 break;
1349         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1350         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1351         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1352         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1353                 if (ASIC_IS_DCE4(rdev)) {
1354                         /* disable the transmitter */
1355                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1356                         /* setup and enable the encoder */
1357                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP);
1358
1359                         /* init and enable the transmitter */
1360                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1361                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1362                 } else {
1363                         /* disable the encoder and transmitter */
1364                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1365                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1366
1367                         /* setup and enable the encoder and transmitter */
1368                         atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1369                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1370                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1371                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1372                 }
1373                 break;
1374         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1375                 atombios_ddia_setup(encoder, ATOM_ENABLE);
1376                 break;
1377         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1378         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1379                 atombios_external_tmds_setup(encoder, ATOM_ENABLE);
1380                 break;
1381         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1382         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1383         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1384         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1385                 atombios_dac_setup(encoder, ATOM_ENABLE);
1386                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1387                         atombios_tv_setup(encoder, ATOM_ENABLE);
1388                 break;
1389         }
1390         atombios_apply_encoder_quirks(encoder, adjusted_mode);
1391
1392         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1393                 r600_hdmi_enable(encoder);
1394                 r600_hdmi_setmode(encoder, adjusted_mode);
1395         }
1396 }
1397
1398 static bool
1399 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1400 {
1401         struct drm_device *dev = encoder->dev;
1402         struct radeon_device *rdev = dev->dev_private;
1403         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1404         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1405
1406         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1407                                        ATOM_DEVICE_CV_SUPPORT |
1408                                        ATOM_DEVICE_CRT_SUPPORT)) {
1409                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1410                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1411                 uint8_t frev, crev;
1412
1413                 memset(&args, 0, sizeof(args));
1414
1415                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1416                         return false;
1417
1418                 args.sDacload.ucMisc = 0;
1419
1420                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1421                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1422                         args.sDacload.ucDacType = ATOM_DAC_A;
1423                 else
1424                         args.sDacload.ucDacType = ATOM_DAC_B;
1425
1426                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1427                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1428                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1429                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1430                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1431                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1432                         if (crev >= 3)
1433                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1434                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1435                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1436                         if (crev >= 3)
1437                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1438                 }
1439
1440                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1441
1442                 return true;
1443         } else
1444                 return false;
1445 }
1446
1447 static enum drm_connector_status
1448 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1449 {
1450         struct drm_device *dev = encoder->dev;
1451         struct radeon_device *rdev = dev->dev_private;
1452         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1453         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1454         uint32_t bios_0_scratch;
1455
1456         if (!atombios_dac_load_detect(encoder, connector)) {
1457                 DRM_DEBUG("detect returned false \n");
1458                 return connector_status_unknown;
1459         }
1460
1461         if (rdev->family >= CHIP_R600)
1462                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1463         else
1464                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1465
1466         DRM_DEBUG("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1467         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1468                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1469                         return connector_status_connected;
1470         }
1471         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1472                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1473                         return connector_status_connected;
1474         }
1475         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1476                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1477                         return connector_status_connected;
1478         }
1479         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1480                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1481                         return connector_status_connected; /* CTV */
1482                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1483                         return connector_status_connected; /* STV */
1484         }
1485         return connector_status_disconnected;
1486 }
1487
1488 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1489 {
1490         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1491
1492         if (radeon_encoder->active_device &
1493             (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) {
1494                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1495                 if (dig)
1496                         dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
1497         }
1498
1499         radeon_atom_output_lock(encoder, true);
1500         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1501
1502         /* this is needed for the pll/ss setup to work correctly in some cases */
1503         atombios_set_encoder_crtc_source(encoder);
1504 }
1505
1506 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1507 {
1508         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1509         radeon_atom_output_lock(encoder, false);
1510 }
1511
1512 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1513 {
1514         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1515         struct radeon_encoder_atom_dig *dig;
1516         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1517
1518         if (radeon_encoder_is_digital(encoder)) {
1519                 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
1520                         r600_hdmi_disable(encoder);
1521                 dig = radeon_encoder->enc_priv;
1522                 dig->dig_encoder = -1;
1523         }
1524         radeon_encoder->active_device = 0;
1525 }
1526
1527 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
1528         .dpms = radeon_atom_encoder_dpms,
1529         .mode_fixup = radeon_atom_mode_fixup,
1530         .prepare = radeon_atom_encoder_prepare,
1531         .mode_set = radeon_atom_encoder_mode_set,
1532         .commit = radeon_atom_encoder_commit,
1533         .disable = radeon_atom_encoder_disable,
1534         /* no detect for TMDS/LVDS yet */
1535 };
1536
1537 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
1538         .dpms = radeon_atom_encoder_dpms,
1539         .mode_fixup = radeon_atom_mode_fixup,
1540         .prepare = radeon_atom_encoder_prepare,
1541         .mode_set = radeon_atom_encoder_mode_set,
1542         .commit = radeon_atom_encoder_commit,
1543         .detect = radeon_atom_dac_detect,
1544 };
1545
1546 void radeon_enc_destroy(struct drm_encoder *encoder)
1547 {
1548         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1549         kfree(radeon_encoder->enc_priv);
1550         drm_encoder_cleanup(encoder);
1551         kfree(radeon_encoder);
1552 }
1553
1554 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
1555         .destroy = radeon_enc_destroy,
1556 };
1557
1558 struct radeon_encoder_atom_dac *
1559 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
1560 {
1561         struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
1562
1563         if (!dac)
1564                 return NULL;
1565
1566         dac->tv_std = TV_STD_NTSC;
1567         return dac;
1568 }
1569
1570 struct radeon_encoder_atom_dig *
1571 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1572 {
1573         struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1574
1575         if (!dig)
1576                 return NULL;
1577
1578         /* coherent mode by default */
1579         dig->coherent_mode = true;
1580         dig->dig_encoder = -1;
1581
1582         return dig;
1583 }
1584
1585 void
1586 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_id, uint32_t supported_device)
1587 {
1588         struct radeon_device *rdev = dev->dev_private;
1589         struct drm_encoder *encoder;
1590         struct radeon_encoder *radeon_encoder;
1591
1592         /* see if we already added it */
1593         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1594                 radeon_encoder = to_radeon_encoder(encoder);
1595                 if (radeon_encoder->encoder_id == encoder_id) {
1596                         radeon_encoder->devices |= supported_device;
1597                         return;
1598                 }
1599
1600         }
1601
1602         /* add a new one */
1603         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1604         if (!radeon_encoder)
1605                 return;
1606
1607         encoder = &radeon_encoder->base;
1608         switch (rdev->num_crtc) {
1609         case 1:
1610                 encoder->possible_crtcs = 0x1;
1611                 break;
1612         case 2:
1613         default:
1614                 encoder->possible_crtcs = 0x3;
1615                 break;
1616         case 6:
1617                 encoder->possible_crtcs = 0x3f;
1618                 break;
1619         }
1620
1621         radeon_encoder->enc_priv = NULL;
1622
1623         radeon_encoder->encoder_id = encoder_id;
1624         radeon_encoder->devices = supported_device;
1625         radeon_encoder->rmx_type = RMX_OFF;
1626
1627         switch (radeon_encoder->encoder_id) {
1628         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1629         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1630         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1631         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1632                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1633                         radeon_encoder->rmx_type = RMX_FULL;
1634                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1635                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1636                 } else {
1637                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1638                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1639                 }
1640                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1641                 break;
1642         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1643                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
1644                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1645                 break;
1646         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1647         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1648         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1649                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
1650                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1651                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1652                 break;
1653         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1654         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1655         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1656         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1657         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1658         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1659         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1660                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1661                         radeon_encoder->rmx_type = RMX_FULL;
1662                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1663                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1664                 } else {
1665                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1666                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1667                 }
1668                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1669                 break;
1670         }
1671 }