041943df966be15803ebedc2e5291fa00953745e
[linux-2.6.git] / drivers / gpu / drm / radeon / radeon_encoders.c
1 /*
2  * Copyright 2007-8 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: Dave Airlie
24  *          Alex Deucher
25  */
26 #include "drmP.h"
27 #include "drm_crtc_helper.h"
28 #include "radeon_drm.h"
29 #include "radeon.h"
30 #include "atom.h"
31
32 extern int atom_debug;
33
34 /* evil but including atombios.h is much worse */
35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36                                 struct drm_display_mode *mode);
37
38 static uint32_t radeon_encoder_clones(struct drm_encoder *encoder)
39 {
40         struct drm_device *dev = encoder->dev;
41         struct radeon_device *rdev = dev->dev_private;
42         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
43         struct drm_encoder *clone_encoder;
44         uint32_t index_mask = 0;
45         int count;
46
47         /* DIG routing gets problematic */
48         if (rdev->family >= CHIP_R600)
49                 return index_mask;
50         /* LVDS/TV are too wacky */
51         if (radeon_encoder->devices & ATOM_DEVICE_LCD_SUPPORT)
52                 return index_mask;
53         /* DVO requires 2x ppll clocks depending on tmds chip */
54         if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT)
55                 return index_mask;
56
57         count = -1;
58         list_for_each_entry(clone_encoder, &dev->mode_config.encoder_list, head) {
59                 struct radeon_encoder *radeon_clone = to_radeon_encoder(clone_encoder);
60                 count++;
61
62                 if (clone_encoder == encoder)
63                         continue;
64                 if (radeon_clone->devices & (ATOM_DEVICE_LCD_SUPPORT))
65                         continue;
66                 if (radeon_clone->devices & ATOM_DEVICE_DFP2_SUPPORT)
67                         continue;
68                 else
69                         index_mask |= (1 << count);
70         }
71         return index_mask;
72 }
73
74 void radeon_setup_encoder_clones(struct drm_device *dev)
75 {
76         struct drm_encoder *encoder;
77
78         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
79                 encoder->possible_clones = radeon_encoder_clones(encoder);
80         }
81 }
82
83 uint32_t
84 radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device, uint8_t dac)
85 {
86         struct radeon_device *rdev = dev->dev_private;
87         uint32_t ret = 0;
88
89         switch (supported_device) {
90         case ATOM_DEVICE_CRT1_SUPPORT:
91         case ATOM_DEVICE_TV1_SUPPORT:
92         case ATOM_DEVICE_TV2_SUPPORT:
93         case ATOM_DEVICE_CRT2_SUPPORT:
94         case ATOM_DEVICE_CV_SUPPORT:
95                 switch (dac) {
96                 case 1: /* dac a */
97                         if ((rdev->family == CHIP_RS300) ||
98                             (rdev->family == CHIP_RS400) ||
99                             (rdev->family == CHIP_RS480))
100                                 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
101                         else if (ASIC_IS_AVIVO(rdev))
102                                 ret = ENCODER_INTERNAL_KLDSCP_DAC1_ENUM_ID1;
103                         else
104                                 ret = ENCODER_INTERNAL_DAC1_ENUM_ID1;
105                         break;
106                 case 2: /* dac b */
107                         if (ASIC_IS_AVIVO(rdev))
108                                 ret = ENCODER_INTERNAL_KLDSCP_DAC2_ENUM_ID1;
109                         else {
110                                 /*if (rdev->family == CHIP_R200)
111                                   ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
112                                   else*/
113                                 ret = ENCODER_INTERNAL_DAC2_ENUM_ID1;
114                         }
115                         break;
116                 case 3: /* external dac */
117                         if (ASIC_IS_AVIVO(rdev))
118                                 ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
119                         else
120                                 ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
121                         break;
122                 }
123                 break;
124         case ATOM_DEVICE_LCD1_SUPPORT:
125                 if (ASIC_IS_AVIVO(rdev))
126                         ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
127                 else
128                         ret = ENCODER_INTERNAL_LVDS_ENUM_ID1;
129                 break;
130         case ATOM_DEVICE_DFP1_SUPPORT:
131                 if ((rdev->family == CHIP_RS300) ||
132                     (rdev->family == CHIP_RS400) ||
133                     (rdev->family == CHIP_RS480))
134                         ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
135                 else if (ASIC_IS_AVIVO(rdev))
136                         ret = ENCODER_INTERNAL_KLDSCP_TMDS1_ENUM_ID1;
137                 else
138                         ret = ENCODER_INTERNAL_TMDS1_ENUM_ID1;
139                 break;
140         case ATOM_DEVICE_LCD2_SUPPORT:
141         case ATOM_DEVICE_DFP2_SUPPORT:
142                 if ((rdev->family == CHIP_RS600) ||
143                     (rdev->family == CHIP_RS690) ||
144                     (rdev->family == CHIP_RS740))
145                         ret = ENCODER_INTERNAL_DDI_ENUM_ID1;
146                 else if (ASIC_IS_AVIVO(rdev))
147                         ret = ENCODER_INTERNAL_KLDSCP_DVO1_ENUM_ID1;
148                 else
149                         ret = ENCODER_INTERNAL_DVO1_ENUM_ID1;
150                 break;
151         case ATOM_DEVICE_DFP3_SUPPORT:
152                 ret = ENCODER_INTERNAL_LVTM1_ENUM_ID1;
153                 break;
154         }
155
156         return ret;
157 }
158
159 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
160 {
161         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
162         switch (radeon_encoder->encoder_id) {
163         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
164         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
165         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
166         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
167         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
168         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
169         case ENCODER_OBJECT_ID_INTERNAL_DDI:
170         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
171         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
172         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
173         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
174                 return true;
175         default:
176                 return false;
177         }
178 }
179
180 void
181 radeon_link_encoder_connector(struct drm_device *dev)
182 {
183         struct drm_connector *connector;
184         struct radeon_connector *radeon_connector;
185         struct drm_encoder *encoder;
186         struct radeon_encoder *radeon_encoder;
187
188         /* walk the list and link encoders to connectors */
189         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
190                 radeon_connector = to_radeon_connector(connector);
191                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
192                         radeon_encoder = to_radeon_encoder(encoder);
193                         if (radeon_encoder->devices & radeon_connector->devices)
194                                 drm_mode_connector_attach_encoder(connector, encoder);
195                 }
196         }
197 }
198
199 void radeon_encoder_set_active_device(struct drm_encoder *encoder)
200 {
201         struct drm_device *dev = encoder->dev;
202         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
203         struct drm_connector *connector;
204
205         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
206                 if (connector->encoder == encoder) {
207                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
208                         radeon_encoder->active_device = radeon_encoder->devices & radeon_connector->devices;
209                         DRM_DEBUG_KMS("setting active device to %08x from %08x %08x for encoder %d\n",
210                                   radeon_encoder->active_device, radeon_encoder->devices,
211                                   radeon_connector->devices, encoder->encoder_type);
212                 }
213         }
214 }
215
216 struct drm_connector *
217 radeon_get_connector_for_encoder(struct drm_encoder *encoder)
218 {
219         struct drm_device *dev = encoder->dev;
220         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
221         struct drm_connector *connector;
222         struct radeon_connector *radeon_connector;
223
224         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
225                 radeon_connector = to_radeon_connector(connector);
226                 if (radeon_encoder->active_device & radeon_connector->devices)
227                         return connector;
228         }
229         return NULL;
230 }
231
232 struct drm_encoder *radeon_atom_get_external_encoder(struct drm_encoder *encoder)
233 {
234         struct drm_device *dev = encoder->dev;
235         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
236         struct drm_encoder *other_encoder;
237         struct radeon_encoder *other_radeon_encoder;
238
239         if (radeon_encoder->is_ext_encoder)
240                 return NULL;
241
242         list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
243                 if (other_encoder == encoder)
244                         continue;
245                 other_radeon_encoder = to_radeon_encoder(other_encoder);
246                 if (other_radeon_encoder->is_ext_encoder &&
247                     (radeon_encoder->devices & other_radeon_encoder->devices))
248                         return other_encoder;
249         }
250         return NULL;
251 }
252
253 void radeon_panel_mode_fixup(struct drm_encoder *encoder,
254                              struct drm_display_mode *adjusted_mode)
255 {
256         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
257         struct drm_device *dev = encoder->dev;
258         struct radeon_device *rdev = dev->dev_private;
259         struct drm_display_mode *native_mode = &radeon_encoder->native_mode;
260         unsigned hblank = native_mode->htotal - native_mode->hdisplay;
261         unsigned vblank = native_mode->vtotal - native_mode->vdisplay;
262         unsigned hover = native_mode->hsync_start - native_mode->hdisplay;
263         unsigned vover = native_mode->vsync_start - native_mode->vdisplay;
264         unsigned hsync_width = native_mode->hsync_end - native_mode->hsync_start;
265         unsigned vsync_width = native_mode->vsync_end - native_mode->vsync_start;
266
267         adjusted_mode->clock = native_mode->clock;
268         adjusted_mode->flags = native_mode->flags;
269
270         if (ASIC_IS_AVIVO(rdev)) {
271                 adjusted_mode->hdisplay = native_mode->hdisplay;
272                 adjusted_mode->vdisplay = native_mode->vdisplay;
273         }
274
275         adjusted_mode->htotal = native_mode->hdisplay + hblank;
276         adjusted_mode->hsync_start = native_mode->hdisplay + hover;
277         adjusted_mode->hsync_end = adjusted_mode->hsync_start + hsync_width;
278
279         adjusted_mode->vtotal = native_mode->vdisplay + vblank;
280         adjusted_mode->vsync_start = native_mode->vdisplay + vover;
281         adjusted_mode->vsync_end = adjusted_mode->vsync_start + vsync_width;
282
283         drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
284
285         if (ASIC_IS_AVIVO(rdev)) {
286                 adjusted_mode->crtc_hdisplay = native_mode->hdisplay;
287                 adjusted_mode->crtc_vdisplay = native_mode->vdisplay;
288         }
289
290         adjusted_mode->crtc_htotal = adjusted_mode->crtc_hdisplay + hblank;
291         adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hdisplay + hover;
292         adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + hsync_width;
293
294         adjusted_mode->crtc_vtotal = adjusted_mode->crtc_vdisplay + vblank;
295         adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + vover;
296         adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + vsync_width;
297
298 }
299
300 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
301                                    struct drm_display_mode *mode,
302                                    struct drm_display_mode *adjusted_mode)
303 {
304         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
305         struct drm_device *dev = encoder->dev;
306         struct radeon_device *rdev = dev->dev_private;
307
308         /* set the active encoder to connector routing */
309         radeon_encoder_set_active_device(encoder);
310         drm_mode_set_crtcinfo(adjusted_mode, 0);
311
312         /* hw bug */
313         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
314             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
315                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
316
317         /* get the native mode for LVDS */
318         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
319                 radeon_panel_mode_fixup(encoder, adjusted_mode);
320
321         /* get the native mode for TV */
322         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
323                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
324                 if (tv_dac) {
325                         if (tv_dac->tv_std == TV_STD_NTSC ||
326                             tv_dac->tv_std == TV_STD_NTSC_J ||
327                             tv_dac->tv_std == TV_STD_PAL_M)
328                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
329                         else
330                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
331                 }
332         }
333
334         if (ASIC_IS_DCE3(rdev) &&
335             (radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT))) {
336                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
337                 radeon_dp_set_link_config(connector, mode);
338         }
339
340         return true;
341 }
342
343 static void
344 atombios_dac_setup(struct drm_encoder *encoder, int action)
345 {
346         struct drm_device *dev = encoder->dev;
347         struct radeon_device *rdev = dev->dev_private;
348         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
349         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
350         int index = 0;
351         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
352
353         memset(&args, 0, sizeof(args));
354
355         switch (radeon_encoder->encoder_id) {
356         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
357         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
358                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
359                 break;
360         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
361         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
362                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
363                 break;
364         }
365
366         args.ucAction = action;
367
368         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
369                 args.ucDacStandard = ATOM_DAC1_PS2;
370         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
371                 args.ucDacStandard = ATOM_DAC1_CV;
372         else {
373                 switch (dac_info->tv_std) {
374                 case TV_STD_PAL:
375                 case TV_STD_PAL_M:
376                 case TV_STD_SCART_PAL:
377                 case TV_STD_SECAM:
378                 case TV_STD_PAL_CN:
379                         args.ucDacStandard = ATOM_DAC1_PAL;
380                         break;
381                 case TV_STD_NTSC:
382                 case TV_STD_NTSC_J:
383                 case TV_STD_PAL_60:
384                 default:
385                         args.ucDacStandard = ATOM_DAC1_NTSC;
386                         break;
387                 }
388         }
389         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
390
391         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
392
393 }
394
395 static void
396 atombios_tv_setup(struct drm_encoder *encoder, int action)
397 {
398         struct drm_device *dev = encoder->dev;
399         struct radeon_device *rdev = dev->dev_private;
400         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
401         TV_ENCODER_CONTROL_PS_ALLOCATION args;
402         int index = 0;
403         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
404
405         memset(&args, 0, sizeof(args));
406
407         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
408
409         args.sTVEncoder.ucAction = action;
410
411         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
412                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
413         else {
414                 switch (dac_info->tv_std) {
415                 case TV_STD_NTSC:
416                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
417                         break;
418                 case TV_STD_PAL:
419                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
420                         break;
421                 case TV_STD_PAL_M:
422                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
423                         break;
424                 case TV_STD_PAL_60:
425                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
426                         break;
427                 case TV_STD_NTSC_J:
428                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
429                         break;
430                 case TV_STD_SCART_PAL:
431                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
432                         break;
433                 case TV_STD_SECAM:
434                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
435                         break;
436                 case TV_STD_PAL_CN:
437                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
438                         break;
439                 default:
440                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
441                         break;
442                 }
443         }
444
445         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
446
447         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
448
449 }
450
451 union dvo_encoder_control {
452         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
453         DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
454         DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
455 };
456
457 void
458 atombios_dvo_setup(struct drm_encoder *encoder, int action)
459 {
460         struct drm_device *dev = encoder->dev;
461         struct radeon_device *rdev = dev->dev_private;
462         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
463         union dvo_encoder_control args;
464         int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
465
466         memset(&args, 0, sizeof(args));
467
468         if (ASIC_IS_DCE3(rdev)) {
469                 /* DCE3+ */
470                 args.dvo_v3.ucAction = action;
471                 args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
472                 args.dvo_v3.ucDVOConfig = 0; /* XXX */
473         } else if (ASIC_IS_DCE2(rdev)) {
474                 /* DCE2 (pre-DCE3 R6xx, RS600/690/740 */
475                 args.dvo.sDVOEncoder.ucAction = action;
476                 args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
477                 /* DFP1, CRT1, TV1 depending on the type of port */
478                 args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
479
480                 if (radeon_encoder->pixel_clock > 165000)
481                         args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
482         } else {
483                 /* R4xx, R5xx */
484                 args.ext_tmds.sXTmdsEncoder.ucEnable = action;
485
486                 if (radeon_encoder->pixel_clock > 165000)
487                         args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
488
489                 /*if (pScrn->rgbBits == 8)*/
490                 args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
491         }
492
493         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
494 }
495
496 union lvds_encoder_control {
497         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
498         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
499 };
500
501 void
502 atombios_digital_setup(struct drm_encoder *encoder, int action)
503 {
504         struct drm_device *dev = encoder->dev;
505         struct radeon_device *rdev = dev->dev_private;
506         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
507         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
508         union lvds_encoder_control args;
509         int index = 0;
510         int hdmi_detected = 0;
511         uint8_t frev, crev;
512
513         if (!dig)
514                 return;
515
516         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
517                 hdmi_detected = 1;
518
519         memset(&args, 0, sizeof(args));
520
521         switch (radeon_encoder->encoder_id) {
522         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
523                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
524                 break;
525         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
526         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
527                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
528                 break;
529         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
530                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
531                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
532                 else
533                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
534                 break;
535         }
536
537         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
538                 return;
539
540         switch (frev) {
541         case 1:
542         case 2:
543                 switch (crev) {
544                 case 1:
545                         args.v1.ucMisc = 0;
546                         args.v1.ucAction = action;
547                         if (hdmi_detected)
548                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
549                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
550                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
551                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
552                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
553                                 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
554                                         args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
555                         } else {
556                                 if (dig->linkb)
557                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
558                                 if (radeon_encoder->pixel_clock > 165000)
559                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
560                                 /*if (pScrn->rgbBits == 8) */
561                                 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
562                         }
563                         break;
564                 case 2:
565                 case 3:
566                         args.v2.ucMisc = 0;
567                         args.v2.ucAction = action;
568                         if (crev == 3) {
569                                 if (dig->coherent_mode)
570                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
571                         }
572                         if (hdmi_detected)
573                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
574                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
575                         args.v2.ucTruncate = 0;
576                         args.v2.ucSpatial = 0;
577                         args.v2.ucTemporal = 0;
578                         args.v2.ucFRC = 0;
579                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
580                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
581                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
582                                 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
583                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
584                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
585                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
586                                 }
587                                 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
588                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
589                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
590                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
591                                         if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
592                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
593                                 }
594                         } else {
595                                 if (dig->linkb)
596                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
597                                 if (radeon_encoder->pixel_clock > 165000)
598                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
599                         }
600                         break;
601                 default:
602                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
603                         break;
604                 }
605                 break;
606         default:
607                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
608                 break;
609         }
610
611         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
612 }
613
614 int
615 atombios_get_encoder_mode(struct drm_encoder *encoder)
616 {
617         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
618         struct drm_device *dev = encoder->dev;
619         struct radeon_device *rdev = dev->dev_private;
620         struct drm_connector *connector;
621         struct radeon_connector *radeon_connector;
622         struct radeon_connector_atom_dig *dig_connector;
623
624         connector = radeon_get_connector_for_encoder(encoder);
625         if (!connector) {
626                 switch (radeon_encoder->encoder_id) {
627                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
628                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
629                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
630                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
631                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
632                         return ATOM_ENCODER_MODE_DVI;
633                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
634                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
635                 default:
636                         return ATOM_ENCODER_MODE_CRT;
637                 }
638         }
639         radeon_connector = to_radeon_connector(connector);
640
641         switch (connector->connector_type) {
642         case DRM_MODE_CONNECTOR_DVII:
643         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
644                 if (drm_detect_hdmi_monitor(radeon_connector->edid)) {
645                         /* fix me */
646                         if (ASIC_IS_DCE4(rdev))
647                                 return ATOM_ENCODER_MODE_DVI;
648                         else
649                                 return ATOM_ENCODER_MODE_HDMI;
650                 } else if (radeon_connector->use_digital)
651                         return ATOM_ENCODER_MODE_DVI;
652                 else
653                         return ATOM_ENCODER_MODE_CRT;
654                 break;
655         case DRM_MODE_CONNECTOR_DVID:
656         case DRM_MODE_CONNECTOR_HDMIA:
657         default:
658                 if (drm_detect_hdmi_monitor(radeon_connector->edid)) {
659                         /* fix me */
660                         if (ASIC_IS_DCE4(rdev))
661                                 return ATOM_ENCODER_MODE_DVI;
662                         else
663                                 return ATOM_ENCODER_MODE_HDMI;
664                 } else
665                         return ATOM_ENCODER_MODE_DVI;
666                 break;
667         case DRM_MODE_CONNECTOR_LVDS:
668                 return ATOM_ENCODER_MODE_LVDS;
669                 break;
670         case DRM_MODE_CONNECTOR_DisplayPort:
671         case DRM_MODE_CONNECTOR_eDP:
672                 dig_connector = radeon_connector->con_priv;
673                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
674                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
675                         return ATOM_ENCODER_MODE_DP;
676                 else if (drm_detect_hdmi_monitor(radeon_connector->edid)) {
677                         /* fix me */
678                         if (ASIC_IS_DCE4(rdev))
679                                 return ATOM_ENCODER_MODE_DVI;
680                         else
681                                 return ATOM_ENCODER_MODE_HDMI;
682                 } else
683                         return ATOM_ENCODER_MODE_DVI;
684                 break;
685         case DRM_MODE_CONNECTOR_DVIA:
686         case DRM_MODE_CONNECTOR_VGA:
687                 return ATOM_ENCODER_MODE_CRT;
688                 break;
689         case DRM_MODE_CONNECTOR_Composite:
690         case DRM_MODE_CONNECTOR_SVIDEO:
691         case DRM_MODE_CONNECTOR_9PinDIN:
692                 /* fix me */
693                 return ATOM_ENCODER_MODE_TV;
694                 /*return ATOM_ENCODER_MODE_CV;*/
695                 break;
696         }
697 }
698
699 /*
700  * DIG Encoder/Transmitter Setup
701  *
702  * DCE 3.0/3.1
703  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
704  * Supports up to 3 digital outputs
705  * - 2 DIG encoder blocks.
706  * DIG1 can drive UNIPHY link A or link B
707  * DIG2 can drive UNIPHY link B or LVTMA
708  *
709  * DCE 3.2
710  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
711  * Supports up to 5 digital outputs
712  * - 2 DIG encoder blocks.
713  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
714  *
715  * DCE 4.0
716  * - 3 DIG transmitter blocks UNPHY0/1/2 (links A and B).
717  * Supports up to 6 digital outputs
718  * - 6 DIG encoder blocks.
719  * - DIG to PHY mapping is hardcoded
720  * DIG1 drives UNIPHY0 link A, A+B
721  * DIG2 drives UNIPHY0 link B
722  * DIG3 drives UNIPHY1 link A, A+B
723  * DIG4 drives UNIPHY1 link B
724  * DIG5 drives UNIPHY2 link A, A+B
725  * DIG6 drives UNIPHY2 link B
726  *
727  * Routing
728  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
729  * Examples:
730  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
731  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
732  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
733  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
734  */
735
736 union dig_encoder_control {
737         DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
738         DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
739         DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
740 };
741
742 void
743 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action)
744 {
745         struct drm_device *dev = encoder->dev;
746         struct radeon_device *rdev = dev->dev_private;
747         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
748         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
749         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
750         union dig_encoder_control args;
751         int index = 0;
752         uint8_t frev, crev;
753         int dp_clock = 0;
754         int dp_lane_count = 0;
755
756         if (connector) {
757                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
758                 struct radeon_connector_atom_dig *dig_connector =
759                         radeon_connector->con_priv;
760
761                 dp_clock = dig_connector->dp_clock;
762                 dp_lane_count = dig_connector->dp_lane_count;
763         }
764
765         /* no dig encoder assigned */
766         if (dig->dig_encoder == -1)
767                 return;
768
769         memset(&args, 0, sizeof(args));
770
771         if (ASIC_IS_DCE4(rdev))
772                 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
773         else {
774                 if (dig->dig_encoder)
775                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
776                 else
777                         index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
778         }
779
780         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
781                 return;
782
783         args.v1.ucAction = action;
784         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
785         args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
786
787         if (args.v1.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
788                 if (dp_clock == 270000)
789                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
790                 args.v1.ucLaneNum = dp_lane_count;
791         } else if (radeon_encoder->pixel_clock > 165000)
792                 args.v1.ucLaneNum = 8;
793         else
794                 args.v1.ucLaneNum = 4;
795
796         if (ASIC_IS_DCE4(rdev)) {
797                 args.v3.acConfig.ucDigSel = dig->dig_encoder;
798                 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
799         } else {
800                 switch (radeon_encoder->encoder_id) {
801                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
802                         args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
803                         break;
804                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
805                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
806                         args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
807                         break;
808                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
809                         args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
810                         break;
811                 }
812                 if (dig->linkb)
813                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
814                 else
815                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
816         }
817
818         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
819
820 }
821
822 union dig_transmitter_control {
823         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
824         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
825         DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
826 };
827
828 void
829 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
830 {
831         struct drm_device *dev = encoder->dev;
832         struct radeon_device *rdev = dev->dev_private;
833         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
834         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
835         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
836         union dig_transmitter_control args;
837         int index = 0;
838         uint8_t frev, crev;
839         bool is_dp = false;
840         int pll_id = 0;
841         int dp_clock = 0;
842         int dp_lane_count = 0;
843         int connector_object_id = 0;
844         int igp_lane_info = 0;
845
846         if (connector) {
847                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
848                 struct radeon_connector_atom_dig *dig_connector =
849                         radeon_connector->con_priv;
850
851                 dp_clock = dig_connector->dp_clock;
852                 dp_lane_count = dig_connector->dp_lane_count;
853                 connector_object_id =
854                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
855                 igp_lane_info = dig_connector->igp_lane_info;
856         }
857
858         /* no dig encoder assigned */
859         if (dig->dig_encoder == -1)
860                 return;
861
862         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP)
863                 is_dp = true;
864
865         memset(&args, 0, sizeof(args));
866
867         switch (radeon_encoder->encoder_id) {
868         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
869                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
870                 break;
871         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
872         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
873         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
874                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
875                 break;
876         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
877                 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
878                 break;
879         }
880
881         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
882                 return;
883
884         args.v1.ucAction = action;
885         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
886                 args.v1.usInitInfo = connector_object_id;
887         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
888                 args.v1.asMode.ucLaneSel = lane_num;
889                 args.v1.asMode.ucLaneSet = lane_set;
890         } else {
891                 if (is_dp)
892                         args.v1.usPixelClock =
893                                 cpu_to_le16(dp_clock / 10);
894                 else if (radeon_encoder->pixel_clock > 165000)
895                         args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
896                 else
897                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
898         }
899         if (ASIC_IS_DCE4(rdev)) {
900                 if (is_dp)
901                         args.v3.ucLaneNum = dp_lane_count;
902                 else if (radeon_encoder->pixel_clock > 165000)
903                         args.v3.ucLaneNum = 8;
904                 else
905                         args.v3.ucLaneNum = 4;
906
907                 if (dig->linkb) {
908                         args.v3.acConfig.ucLinkSel = 1;
909                         args.v3.acConfig.ucEncoderSel = 1;
910                 }
911
912                 /* Select the PLL for the PHY
913                  * DP PHY should be clocked from external src if there is
914                  * one.
915                  */
916                 if (encoder->crtc) {
917                         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
918                         pll_id = radeon_crtc->pll_id;
919                 }
920                 if (is_dp && rdev->clock.dp_extclk)
921                         args.v3.acConfig.ucRefClkSource = 2; /* external src */
922                 else
923                         args.v3.acConfig.ucRefClkSource = pll_id;
924
925                 switch (radeon_encoder->encoder_id) {
926                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
927                         args.v3.acConfig.ucTransmitterSel = 0;
928                         break;
929                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
930                         args.v3.acConfig.ucTransmitterSel = 1;
931                         break;
932                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
933                         args.v3.acConfig.ucTransmitterSel = 2;
934                         break;
935                 }
936
937                 if (is_dp)
938                         args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
939                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
940                         if (dig->coherent_mode)
941                                 args.v3.acConfig.fCoherentMode = 1;
942                         if (radeon_encoder->pixel_clock > 165000)
943                                 args.v3.acConfig.fDualLinkConnector = 1;
944                 }
945         } else if (ASIC_IS_DCE32(rdev)) {
946                 args.v2.acConfig.ucEncoderSel = dig->dig_encoder;
947                 if (dig->linkb)
948                         args.v2.acConfig.ucLinkSel = 1;
949
950                 switch (radeon_encoder->encoder_id) {
951                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
952                         args.v2.acConfig.ucTransmitterSel = 0;
953                         break;
954                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
955                         args.v2.acConfig.ucTransmitterSel = 1;
956                         break;
957                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
958                         args.v2.acConfig.ucTransmitterSel = 2;
959                         break;
960                 }
961
962                 if (is_dp)
963                         args.v2.acConfig.fCoherentMode = 1;
964                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
965                         if (dig->coherent_mode)
966                                 args.v2.acConfig.fCoherentMode = 1;
967                         if (radeon_encoder->pixel_clock > 165000)
968                                 args.v2.acConfig.fDualLinkConnector = 1;
969                 }
970         } else {
971                 args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
972
973                 if (dig->dig_encoder)
974                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
975                 else
976                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
977
978                 if ((rdev->flags & RADEON_IS_IGP) &&
979                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
980                         if (is_dp || (radeon_encoder->pixel_clock <= 165000)) {
981                                 if (igp_lane_info & 0x1)
982                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
983                                 else if (igp_lane_info & 0x2)
984                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
985                                 else if (igp_lane_info & 0x4)
986                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
987                                 else if (igp_lane_info & 0x8)
988                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
989                         } else {
990                                 if (igp_lane_info & 0x3)
991                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
992                                 else if (igp_lane_info & 0xc)
993                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
994                         }
995                 }
996
997                 if (dig->linkb)
998                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
999                 else
1000                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1001
1002                 if (is_dp)
1003                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1004                 else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1005                         if (dig->coherent_mode)
1006                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1007                         if (radeon_encoder->pixel_clock > 165000)
1008                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1009                 }
1010         }
1011
1012         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1013 }
1014
1015 void
1016 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1017 {
1018         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1019         struct drm_device *dev = radeon_connector->base.dev;
1020         struct radeon_device *rdev = dev->dev_private;
1021         union dig_transmitter_control args;
1022         int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1023         uint8_t frev, crev;
1024
1025         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1026                 return;
1027
1028         if (!ASIC_IS_DCE4(rdev))
1029                 return;
1030
1031         if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) ||
1032             (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1033                 return;
1034
1035         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1036                 return;
1037
1038         memset(&args, 0, sizeof(args));
1039
1040         args.v1.ucAction = action;
1041
1042         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1043 }
1044
1045 union external_encoder_control {
1046         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1047 };
1048
1049 static void
1050 atombios_external_encoder_setup(struct drm_encoder *encoder,
1051                                 struct drm_encoder *ext_encoder,
1052                                 int action)
1053 {
1054         struct drm_device *dev = encoder->dev;
1055         struct radeon_device *rdev = dev->dev_private;
1056         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1057         union external_encoder_control args;
1058         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1059         int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1060         u8 frev, crev;
1061         int dp_clock = 0;
1062         int dp_lane_count = 0;
1063         int connector_object_id = 0;
1064
1065         if (connector) {
1066                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1067                 struct radeon_connector_atom_dig *dig_connector =
1068                         radeon_connector->con_priv;
1069
1070                 dp_clock = dig_connector->dp_clock;
1071                 dp_lane_count = dig_connector->dp_lane_count;
1072                 connector_object_id =
1073                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1074         }
1075
1076         memset(&args, 0, sizeof(args));
1077
1078         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1079                 return;
1080
1081         switch (frev) {
1082         case 1:
1083                 /* no params on frev 1 */
1084                 break;
1085         case 2:
1086                 switch (crev) {
1087                 case 1:
1088                 case 2:
1089                         args.v1.sDigEncoder.ucAction = action;
1090                         args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1091                         args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1092
1093                         if (args.v1.sDigEncoder.ucEncoderMode == ATOM_ENCODER_MODE_DP) {
1094                                 if (dp_clock == 270000)
1095                                         args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1096                                 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1097                         } else if (radeon_encoder->pixel_clock > 165000)
1098                                 args.v1.sDigEncoder.ucLaneNum = 8;
1099                         else
1100                                 args.v1.sDigEncoder.ucLaneNum = 4;
1101                         break;
1102                 default:
1103                         DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1104                         return;
1105                 }
1106                 break;
1107         default:
1108                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1109                 return;
1110         }
1111         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1112 }
1113
1114 static void
1115 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1116 {
1117         struct drm_device *dev = encoder->dev;
1118         struct radeon_device *rdev = dev->dev_private;
1119         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1120         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1121         ENABLE_YUV_PS_ALLOCATION args;
1122         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1123         uint32_t temp, reg;
1124
1125         memset(&args, 0, sizeof(args));
1126
1127         if (rdev->family >= CHIP_R600)
1128                 reg = R600_BIOS_3_SCRATCH;
1129         else
1130                 reg = RADEON_BIOS_3_SCRATCH;
1131
1132         /* XXX: fix up scratch reg handling */
1133         temp = RREG32(reg);
1134         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1135                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1136                              (radeon_crtc->crtc_id << 18)));
1137         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1138                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1139         else
1140                 WREG32(reg, 0);
1141
1142         if (enable)
1143                 args.ucEnable = ATOM_ENABLE;
1144         args.ucCRTC = radeon_crtc->crtc_id;
1145
1146         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1147
1148         WREG32(reg, temp);
1149 }
1150
1151 static void
1152 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1153 {
1154         struct drm_device *dev = encoder->dev;
1155         struct radeon_device *rdev = dev->dev_private;
1156         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1157         struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1158         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1159         int index = 0;
1160         bool is_dig = false;
1161
1162         memset(&args, 0, sizeof(args));
1163
1164         DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1165                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1166                   radeon_encoder->active_device);
1167         switch (radeon_encoder->encoder_id) {
1168         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1169         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1170                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1171                 break;
1172         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1173         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1174         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1175         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1176                 is_dig = true;
1177                 break;
1178         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1179         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1180                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1181                 break;
1182         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1183                 if (ASIC_IS_DCE3(rdev))
1184                         is_dig = true;
1185                 else
1186                         index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1187                 break;
1188         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1189                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1190                 break;
1191         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1192                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1193                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1194                 else
1195                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1196                 break;
1197         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1198         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1199                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1200                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1201                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1202                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1203                 else
1204                         index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1205                 break;
1206         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1207         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1208                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1209                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1210                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1211                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1212                 else
1213                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1214                 break;
1215         }
1216
1217         if (is_dig) {
1218                 switch (mode) {
1219                 case DRM_MODE_DPMS_ON:
1220                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1221                         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1222                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1223
1224                                 if (connector &&
1225                                     (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
1226                                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1227                                         struct radeon_connector_atom_dig *radeon_dig_connector =
1228                                                 radeon_connector->con_priv;
1229                                         atombios_set_edp_panel_power(connector,
1230                                                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
1231                                         radeon_dig_connector->edp_on = true;
1232                                 }
1233                                 dp_link_train(encoder, connector);
1234                                 if (ASIC_IS_DCE4(rdev))
1235                                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON);
1236                         }
1237                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1238                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1239                         break;
1240                 case DRM_MODE_DPMS_STANDBY:
1241                 case DRM_MODE_DPMS_SUSPEND:
1242                 case DRM_MODE_DPMS_OFF:
1243                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1244                         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_DP) {
1245                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1246
1247                                 if (ASIC_IS_DCE4(rdev))
1248                                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF);
1249                                 if (connector &&
1250                                     (connector->connector_type == DRM_MODE_CONNECTOR_eDP)) {
1251                                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1252                                         struct radeon_connector_atom_dig *radeon_dig_connector =
1253                                                 radeon_connector->con_priv;
1254                                         atombios_set_edp_panel_power(connector,
1255                                                                      ATOM_TRANSMITTER_ACTION_POWER_OFF);
1256                                         radeon_dig_connector->edp_on = false;
1257                                 }
1258                         }
1259                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1260                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1261                         break;
1262                 }
1263         } else {
1264                 switch (mode) {
1265                 case DRM_MODE_DPMS_ON:
1266                         args.ucAction = ATOM_ENABLE;
1267                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1268                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1269                                 args.ucAction = ATOM_LCD_BLON;
1270                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1271                         }
1272                         break;
1273                 case DRM_MODE_DPMS_STANDBY:
1274                 case DRM_MODE_DPMS_SUSPEND:
1275                 case DRM_MODE_DPMS_OFF:
1276                         args.ucAction = ATOM_DISABLE;
1277                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1278                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1279                                 args.ucAction = ATOM_LCD_BLOFF;
1280                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1281                         }
1282                         break;
1283                 }
1284         }
1285
1286         if (ext_encoder) {
1287                 int action;
1288
1289                 switch (mode) {
1290                 case DRM_MODE_DPMS_ON:
1291                 default:
1292                         action = ATOM_ENABLE;
1293                         break;
1294                 case DRM_MODE_DPMS_STANDBY:
1295                 case DRM_MODE_DPMS_SUSPEND:
1296                 case DRM_MODE_DPMS_OFF:
1297                         action = ATOM_DISABLE;
1298                         break;
1299                 }
1300                 atombios_external_encoder_setup(encoder, ext_encoder, action);
1301         }
1302
1303         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1304
1305 }
1306
1307 union crtc_source_param {
1308         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1309         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1310 };
1311
1312 static void
1313 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1314 {
1315         struct drm_device *dev = encoder->dev;
1316         struct radeon_device *rdev = dev->dev_private;
1317         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1318         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1319         union crtc_source_param args;
1320         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1321         uint8_t frev, crev;
1322         struct radeon_encoder_atom_dig *dig;
1323
1324         memset(&args, 0, sizeof(args));
1325
1326         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1327                 return;
1328
1329         switch (frev) {
1330         case 1:
1331                 switch (crev) {
1332                 case 1:
1333                 default:
1334                         if (ASIC_IS_AVIVO(rdev))
1335                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
1336                         else {
1337                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1338                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
1339                                 } else {
1340                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1341                                 }
1342                         }
1343                         switch (radeon_encoder->encoder_id) {
1344                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1345                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1346                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1347                                 break;
1348                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1349                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1350                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1351                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1352                                 else
1353                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1354                                 break;
1355                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1356                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1357                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1358                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1359                                 break;
1360                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1361                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1362                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1363                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1364                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1365                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1366                                 else
1367                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1368                                 break;
1369                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1370                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1371                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1372                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1373                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1374                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1375                                 else
1376                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1377                                 break;
1378                         }
1379                         break;
1380                 case 2:
1381                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1382                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1383                         switch (radeon_encoder->encoder_id) {
1384                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1385                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1386                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1387                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1388                                 dig = radeon_encoder->enc_priv;
1389                                 switch (dig->dig_encoder) {
1390                                 case 0:
1391                                         args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1392                                         break;
1393                                 case 1:
1394                                         args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1395                                         break;
1396                                 case 2:
1397                                         args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1398                                         break;
1399                                 case 3:
1400                                         args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1401                                         break;
1402                                 case 4:
1403                                         args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1404                                         break;
1405                                 case 5:
1406                                         args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1407                                         break;
1408                                 }
1409                                 break;
1410                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1411                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1412                                 break;
1413                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1414                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1415                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1416                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1417                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1418                                 else
1419                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1420                                 break;
1421                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1422                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1423                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1424                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1425                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1426                                 else
1427                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1428                                 break;
1429                         }
1430                         break;
1431                 }
1432                 break;
1433         default:
1434                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1435                 return;
1436         }
1437
1438         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1439
1440         /* update scratch regs with new routing */
1441         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1442 }
1443
1444 static void
1445 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1446                               struct drm_display_mode *mode)
1447 {
1448         struct drm_device *dev = encoder->dev;
1449         struct radeon_device *rdev = dev->dev_private;
1450         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1451         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1452
1453         /* Funky macbooks */
1454         if ((dev->pdev->device == 0x71C5) &&
1455             (dev->pdev->subsystem_vendor == 0x106b) &&
1456             (dev->pdev->subsystem_device == 0x0080)) {
1457                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1458                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1459
1460                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1461                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1462
1463                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1464                 }
1465         }
1466
1467         /* set scaler clears this on some chips */
1468         /* XXX check DCE4 */
1469         if (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))) {
1470                 if (ASIC_IS_AVIVO(rdev) && (mode->flags & DRM_MODE_FLAG_INTERLACE))
1471                         WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1472                                AVIVO_D1MODE_INTERLEAVE_EN);
1473         }
1474 }
1475
1476 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1477 {
1478         struct drm_device *dev = encoder->dev;
1479         struct radeon_device *rdev = dev->dev_private;
1480         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1481         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1482         struct drm_encoder *test_encoder;
1483         struct radeon_encoder_atom_dig *dig;
1484         uint32_t dig_enc_in_use = 0;
1485
1486         if (ASIC_IS_DCE4(rdev)) {
1487                 dig = radeon_encoder->enc_priv;
1488                 switch (radeon_encoder->encoder_id) {
1489                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1490                         if (dig->linkb)
1491                                 return 1;
1492                         else
1493                                 return 0;
1494                         break;
1495                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1496                         if (dig->linkb)
1497                                 return 3;
1498                         else
1499                                 return 2;
1500                         break;
1501                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1502                         if (dig->linkb)
1503                                 return 5;
1504                         else
1505                                 return 4;
1506                         break;
1507                 }
1508         }
1509
1510         /* on DCE32 and encoder can driver any block so just crtc id */
1511         if (ASIC_IS_DCE32(rdev)) {
1512                 return radeon_crtc->crtc_id;
1513         }
1514
1515         /* on DCE3 - LVTMA can only be driven by DIGB */
1516         list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1517                 struct radeon_encoder *radeon_test_encoder;
1518
1519                 if (encoder == test_encoder)
1520                         continue;
1521
1522                 if (!radeon_encoder_is_digital(test_encoder))
1523                         continue;
1524
1525                 radeon_test_encoder = to_radeon_encoder(test_encoder);
1526                 dig = radeon_test_encoder->enc_priv;
1527
1528                 if (dig->dig_encoder >= 0)
1529                         dig_enc_in_use |= (1 << dig->dig_encoder);
1530         }
1531
1532         if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1533                 if (dig_enc_in_use & 0x2)
1534                         DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1535                 return 1;
1536         }
1537         if (!(dig_enc_in_use & 1))
1538                 return 0;
1539         return 1;
1540 }
1541
1542 static void
1543 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1544                              struct drm_display_mode *mode,
1545                              struct drm_display_mode *adjusted_mode)
1546 {
1547         struct drm_device *dev = encoder->dev;
1548         struct radeon_device *rdev = dev->dev_private;
1549         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1550         struct drm_encoder *ext_encoder = radeon_atom_get_external_encoder(encoder);
1551
1552         radeon_encoder->pixel_clock = adjusted_mode->clock;
1553
1554         if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1555                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1556                         atombios_yuv_setup(encoder, true);
1557                 else
1558                         atombios_yuv_setup(encoder, false);
1559         }
1560
1561         switch (radeon_encoder->encoder_id) {
1562         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1563         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1564         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1565         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1566                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1567                 break;
1568         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1569         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1570         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1571         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1572                 if (ASIC_IS_DCE4(rdev)) {
1573                         /* disable the transmitter */
1574                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1575                         /* setup and enable the encoder */
1576                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP);
1577
1578                         /* init and enable the transmitter */
1579                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1580                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1581                 } else {
1582                         /* disable the encoder and transmitter */
1583                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1584                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1585
1586                         /* setup and enable the encoder and transmitter */
1587                         atombios_dig_encoder_setup(encoder, ATOM_ENABLE);
1588                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1589                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1590                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1591                 }
1592                 break;
1593         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1594         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1595         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1596                 atombios_dvo_setup(encoder, ATOM_ENABLE);
1597                 break;
1598         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1599         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1600         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1601         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1602                 atombios_dac_setup(encoder, ATOM_ENABLE);
1603                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1604                         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1605                                 atombios_tv_setup(encoder, ATOM_ENABLE);
1606                         else
1607                                 atombios_tv_setup(encoder, ATOM_DISABLE);
1608                 }
1609                 break;
1610         }
1611
1612         if (ext_encoder) {
1613                 atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1614         }
1615
1616         atombios_apply_encoder_quirks(encoder, adjusted_mode);
1617
1618         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1619                 r600_hdmi_enable(encoder);
1620                 r600_hdmi_setmode(encoder, adjusted_mode);
1621         }
1622 }
1623
1624 static bool
1625 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1626 {
1627         struct drm_device *dev = encoder->dev;
1628         struct radeon_device *rdev = dev->dev_private;
1629         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1630         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1631
1632         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1633                                        ATOM_DEVICE_CV_SUPPORT |
1634                                        ATOM_DEVICE_CRT_SUPPORT)) {
1635                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1636                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1637                 uint8_t frev, crev;
1638
1639                 memset(&args, 0, sizeof(args));
1640
1641                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1642                         return false;
1643
1644                 args.sDacload.ucMisc = 0;
1645
1646                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1647                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1648                         args.sDacload.ucDacType = ATOM_DAC_A;
1649                 else
1650                         args.sDacload.ucDacType = ATOM_DAC_B;
1651
1652                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1653                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1654                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1655                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1656                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1657                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1658                         if (crev >= 3)
1659                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1660                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1661                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1662                         if (crev >= 3)
1663                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1664                 }
1665
1666                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1667
1668                 return true;
1669         } else
1670                 return false;
1671 }
1672
1673 static enum drm_connector_status
1674 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1675 {
1676         struct drm_device *dev = encoder->dev;
1677         struct radeon_device *rdev = dev->dev_private;
1678         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1679         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1680         uint32_t bios_0_scratch;
1681
1682         if (!atombios_dac_load_detect(encoder, connector)) {
1683                 DRM_DEBUG_KMS("detect returned false \n");
1684                 return connector_status_unknown;
1685         }
1686
1687         if (rdev->family >= CHIP_R600)
1688                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
1689         else
1690                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
1691
1692         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
1693         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
1694                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
1695                         return connector_status_connected;
1696         }
1697         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
1698                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
1699                         return connector_status_connected;
1700         }
1701         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1702                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
1703                         return connector_status_connected;
1704         }
1705         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1706                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
1707                         return connector_status_connected; /* CTV */
1708                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
1709                         return connector_status_connected; /* STV */
1710         }
1711         return connector_status_disconnected;
1712 }
1713
1714 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
1715 {
1716         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1717         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1718
1719         if (radeon_encoder->active_device &
1720             (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) {
1721                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1722                 if (dig)
1723                         dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
1724         }
1725
1726         radeon_atom_output_lock(encoder, true);
1727         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1728
1729         /* select the clock/data port if it uses a router */
1730         if (connector) {
1731                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1732                 if (radeon_connector->router.cd_valid)
1733                         radeon_router_select_cd_port(radeon_connector);
1734         }
1735
1736         /* this is needed for the pll/ss setup to work correctly in some cases */
1737         atombios_set_encoder_crtc_source(encoder);
1738 }
1739
1740 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
1741 {
1742         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
1743         radeon_atom_output_lock(encoder, false);
1744 }
1745
1746 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
1747 {
1748         struct drm_device *dev = encoder->dev;
1749         struct radeon_device *rdev = dev->dev_private;
1750         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1751         struct radeon_encoder_atom_dig *dig;
1752
1753         /* check for pre-DCE3 cards with shared encoders;
1754          * can't really use the links individually, so don't disable
1755          * the encoder if it's in use by another connector
1756          */
1757         if (!ASIC_IS_DCE3(rdev)) {
1758                 struct drm_encoder *other_encoder;
1759                 struct radeon_encoder *other_radeon_encoder;
1760
1761                 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
1762                         other_radeon_encoder = to_radeon_encoder(other_encoder);
1763                         if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
1764                             drm_helper_encoder_in_use(other_encoder))
1765                                 goto disable_done;
1766                 }
1767         }
1768
1769         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1770
1771         switch (radeon_encoder->encoder_id) {
1772         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1773         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1774         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1775         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1776                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
1777                 break;
1778         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1779         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1780         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1781         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1782                 if (ASIC_IS_DCE4(rdev))
1783                         /* disable the transmitter */
1784                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1785                 else {
1786                         /* disable the encoder and transmitter */
1787                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1788                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE);
1789                 }
1790                 break;
1791         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1792         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1793         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1794                 atombios_dvo_setup(encoder, ATOM_DISABLE);
1795                 break;
1796         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1797         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1798         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1799         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1800                 atombios_dac_setup(encoder, ATOM_DISABLE);
1801                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1802                         atombios_tv_setup(encoder, ATOM_DISABLE);
1803                 break;
1804         }
1805
1806 disable_done:
1807         if (radeon_encoder_is_digital(encoder)) {
1808                 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
1809                         r600_hdmi_disable(encoder);
1810                 dig = radeon_encoder->enc_priv;
1811                 dig->dig_encoder = -1;
1812         }
1813         radeon_encoder->active_device = 0;
1814 }
1815
1816 /* these are handled by the primary encoders */
1817 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
1818 {
1819
1820 }
1821
1822 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
1823 {
1824
1825 }
1826
1827 static void
1828 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
1829                          struct drm_display_mode *mode,
1830                          struct drm_display_mode *adjusted_mode)
1831 {
1832
1833 }
1834
1835 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
1836 {
1837
1838 }
1839
1840 static void
1841 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
1842 {
1843
1844 }
1845
1846 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
1847                                        struct drm_display_mode *mode,
1848                                        struct drm_display_mode *adjusted_mode)
1849 {
1850         return true;
1851 }
1852
1853 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
1854         .dpms = radeon_atom_ext_dpms,
1855         .mode_fixup = radeon_atom_ext_mode_fixup,
1856         .prepare = radeon_atom_ext_prepare,
1857         .mode_set = radeon_atom_ext_mode_set,
1858         .commit = radeon_atom_ext_commit,
1859         .disable = radeon_atom_ext_disable,
1860         /* no detect for TMDS/LVDS yet */
1861 };
1862
1863 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
1864         .dpms = radeon_atom_encoder_dpms,
1865         .mode_fixup = radeon_atom_mode_fixup,
1866         .prepare = radeon_atom_encoder_prepare,
1867         .mode_set = radeon_atom_encoder_mode_set,
1868         .commit = radeon_atom_encoder_commit,
1869         .disable = radeon_atom_encoder_disable,
1870         /* no detect for TMDS/LVDS yet */
1871 };
1872
1873 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
1874         .dpms = radeon_atom_encoder_dpms,
1875         .mode_fixup = radeon_atom_mode_fixup,
1876         .prepare = radeon_atom_encoder_prepare,
1877         .mode_set = radeon_atom_encoder_mode_set,
1878         .commit = radeon_atom_encoder_commit,
1879         .detect = radeon_atom_dac_detect,
1880 };
1881
1882 void radeon_enc_destroy(struct drm_encoder *encoder)
1883 {
1884         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1885         kfree(radeon_encoder->enc_priv);
1886         drm_encoder_cleanup(encoder);
1887         kfree(radeon_encoder);
1888 }
1889
1890 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
1891         .destroy = radeon_enc_destroy,
1892 };
1893
1894 struct radeon_encoder_atom_dac *
1895 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
1896 {
1897         struct drm_device *dev = radeon_encoder->base.dev;
1898         struct radeon_device *rdev = dev->dev_private;
1899         struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
1900
1901         if (!dac)
1902                 return NULL;
1903
1904         dac->tv_std = radeon_atombios_get_tv_info(rdev);
1905         return dac;
1906 }
1907
1908 struct radeon_encoder_atom_dig *
1909 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
1910 {
1911         int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1912         struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1913
1914         if (!dig)
1915                 return NULL;
1916
1917         /* coherent mode by default */
1918         dig->coherent_mode = true;
1919         dig->dig_encoder = -1;
1920
1921         if (encoder_enum == 2)
1922                 dig->linkb = true;
1923         else
1924                 dig->linkb = false;
1925
1926         return dig;
1927 }
1928
1929 void
1930 radeon_add_atom_encoder(struct drm_device *dev, uint32_t encoder_enum, uint32_t supported_device)
1931 {
1932         struct radeon_device *rdev = dev->dev_private;
1933         struct drm_encoder *encoder;
1934         struct radeon_encoder *radeon_encoder;
1935
1936         /* see if we already added it */
1937         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1938                 radeon_encoder = to_radeon_encoder(encoder);
1939                 if (radeon_encoder->encoder_enum == encoder_enum) {
1940                         radeon_encoder->devices |= supported_device;
1941                         return;
1942                 }
1943
1944         }
1945
1946         /* add a new one */
1947         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
1948         if (!radeon_encoder)
1949                 return;
1950
1951         encoder = &radeon_encoder->base;
1952         switch (rdev->num_crtc) {
1953         case 1:
1954                 encoder->possible_crtcs = 0x1;
1955                 break;
1956         case 2:
1957         default:
1958                 encoder->possible_crtcs = 0x3;
1959                 break;
1960         case 6:
1961                 encoder->possible_crtcs = 0x3f;
1962                 break;
1963         }
1964
1965         radeon_encoder->enc_priv = NULL;
1966
1967         radeon_encoder->encoder_enum = encoder_enum;
1968         radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1969         radeon_encoder->devices = supported_device;
1970         radeon_encoder->rmx_type = RMX_OFF;
1971         radeon_encoder->underscan_type = UNDERSCAN_OFF;
1972         radeon_encoder->is_ext_encoder = false;
1973
1974         switch (radeon_encoder->encoder_id) {
1975         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1976         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1977         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1978         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1979                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1980                         radeon_encoder->rmx_type = RMX_FULL;
1981                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
1982                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
1983                 } else {
1984                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
1985                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
1986                         if (ASIC_IS_AVIVO(rdev))
1987                                 radeon_encoder->underscan_type = UNDERSCAN_AUTO;
1988                 }
1989                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
1990                 break;
1991         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1992                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
1993                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
1994                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
1995                 break;
1996         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1997         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1998         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1999                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2000                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2001                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2002                 break;
2003         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2004         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2005         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2006         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2007         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2008         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2009         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2010                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2011                         radeon_encoder->rmx_type = RMX_FULL;
2012                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2013                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2014                 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2015                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2016                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2017                 } else {
2018                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2019                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2020                         if (ASIC_IS_AVIVO(rdev))
2021                                 radeon_encoder->underscan_type = UNDERSCAN_AUTO;
2022                 }
2023                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2024                 break;
2025         case ENCODER_OBJECT_ID_SI170B:
2026         case ENCODER_OBJECT_ID_CH7303:
2027         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2028         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2029         case ENCODER_OBJECT_ID_TITFP513:
2030         case ENCODER_OBJECT_ID_VT1623:
2031         case ENCODER_OBJECT_ID_HDMI_SI1930:
2032                 /* these are handled by the primary encoders */
2033                 radeon_encoder->is_ext_encoder = true;
2034                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2035                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2036                 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2037                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2038                 else
2039                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2040                 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2041                 break;
2042         }
2043 }