drm/radeon/kms: clean up pll struct
[linux-2.6.git] / drivers / gpu / drm / radeon / radeon_display.c
1 /*
2  * Copyright 2007-8 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: Dave Airlie
24  *          Alex Deucher
25  */
26 #include "drmP.h"
27 #include "radeon_drm.h"
28 #include "radeon.h"
29
30 #include "atom.h"
31 #include <asm/div64.h>
32
33 #include "drm_crtc_helper.h"
34 #include "drm_edid.h"
35
36 static int radeon_ddc_dump(struct drm_connector *connector);
37
38 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
39 {
40         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41         struct drm_device *dev = crtc->dev;
42         struct radeon_device *rdev = dev->dev_private;
43         int i;
44
45         DRM_DEBUG("%d\n", radeon_crtc->crtc_id);
46         WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
47
48         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
49         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
50         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
51
52         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
53         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
54         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
55
56         WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
57         WREG32(AVIVO_DC_LUT_RW_MODE, 0);
58         WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
59
60         WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
61         for (i = 0; i < 256; i++) {
62                 WREG32(AVIVO_DC_LUT_30_COLOR,
63                              (radeon_crtc->lut_r[i] << 20) |
64                              (radeon_crtc->lut_g[i] << 10) |
65                              (radeon_crtc->lut_b[i] << 0));
66         }
67
68         WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
69 }
70
71 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
72 {
73         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
74         struct drm_device *dev = crtc->dev;
75         struct radeon_device *rdev = dev->dev_private;
76         int i;
77         uint32_t dac2_cntl;
78
79         dac2_cntl = RREG32(RADEON_DAC_CNTL2);
80         if (radeon_crtc->crtc_id == 0)
81                 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
82         else
83                 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
84         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
85
86         WREG8(RADEON_PALETTE_INDEX, 0);
87         for (i = 0; i < 256; i++) {
88                 WREG32(RADEON_PALETTE_30_DATA,
89                              (radeon_crtc->lut_r[i] << 20) |
90                              (radeon_crtc->lut_g[i] << 10) |
91                              (radeon_crtc->lut_b[i] << 0));
92         }
93 }
94
95 void radeon_crtc_load_lut(struct drm_crtc *crtc)
96 {
97         struct drm_device *dev = crtc->dev;
98         struct radeon_device *rdev = dev->dev_private;
99
100         if (!crtc->enabled)
101                 return;
102
103         if (ASIC_IS_AVIVO(rdev))
104                 avivo_crtc_load_lut(crtc);
105         else
106                 legacy_crtc_load_lut(crtc);
107 }
108
109 /** Sets the color ramps on behalf of fbcon */
110 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
111                               u16 blue, int regno)
112 {
113         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
114
115         radeon_crtc->lut_r[regno] = red >> 6;
116         radeon_crtc->lut_g[regno] = green >> 6;
117         radeon_crtc->lut_b[regno] = blue >> 6;
118 }
119
120 /** Gets the color ramps on behalf of fbcon */
121 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
122                               u16 *blue, int regno)
123 {
124         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
125
126         *red = radeon_crtc->lut_r[regno] << 6;
127         *green = radeon_crtc->lut_g[regno] << 6;
128         *blue = radeon_crtc->lut_b[regno] << 6;
129 }
130
131 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
132                                   u16 *blue, uint32_t size)
133 {
134         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
135         int i;
136
137         if (size != 256) {
138                 return;
139         }
140
141         /* userspace palettes are always correct as is */
142         for (i = 0; i < 256; i++) {
143                 radeon_crtc->lut_r[i] = red[i] >> 6;
144                 radeon_crtc->lut_g[i] = green[i] >> 6;
145                 radeon_crtc->lut_b[i] = blue[i] >> 6;
146         }
147         radeon_crtc_load_lut(crtc);
148 }
149
150 static void radeon_crtc_destroy(struct drm_crtc *crtc)
151 {
152         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
153
154         drm_crtc_cleanup(crtc);
155         kfree(radeon_crtc);
156 }
157
158 static const struct drm_crtc_funcs radeon_crtc_funcs = {
159         .cursor_set = radeon_crtc_cursor_set,
160         .cursor_move = radeon_crtc_cursor_move,
161         .gamma_set = radeon_crtc_gamma_set,
162         .set_config = drm_crtc_helper_set_config,
163         .destroy = radeon_crtc_destroy,
164 };
165
166 static void radeon_crtc_init(struct drm_device *dev, int index)
167 {
168         struct radeon_device *rdev = dev->dev_private;
169         struct radeon_crtc *radeon_crtc;
170         int i;
171
172         radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
173         if (radeon_crtc == NULL)
174                 return;
175
176         drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
177
178         drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
179         radeon_crtc->crtc_id = index;
180         rdev->mode_info.crtcs[index] = radeon_crtc;
181
182 #if 0
183         radeon_crtc->mode_set.crtc = &radeon_crtc->base;
184         radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
185         radeon_crtc->mode_set.num_connectors = 0;
186 #endif
187
188         for (i = 0; i < 256; i++) {
189                 radeon_crtc->lut_r[i] = i << 2;
190                 radeon_crtc->lut_g[i] = i << 2;
191                 radeon_crtc->lut_b[i] = i << 2;
192         }
193
194         if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
195                 radeon_atombios_init_crtc(dev, radeon_crtc);
196         else
197                 radeon_legacy_init_crtc(dev, radeon_crtc);
198 }
199
200 static const char *encoder_names[34] = {
201         "NONE",
202         "INTERNAL_LVDS",
203         "INTERNAL_TMDS1",
204         "INTERNAL_TMDS2",
205         "INTERNAL_DAC1",
206         "INTERNAL_DAC2",
207         "INTERNAL_SDVOA",
208         "INTERNAL_SDVOB",
209         "SI170B",
210         "CH7303",
211         "CH7301",
212         "INTERNAL_DVO1",
213         "EXTERNAL_SDVOA",
214         "EXTERNAL_SDVOB",
215         "TITFP513",
216         "INTERNAL_LVTM1",
217         "VT1623",
218         "HDMI_SI1930",
219         "HDMI_INTERNAL",
220         "INTERNAL_KLDSCP_TMDS1",
221         "INTERNAL_KLDSCP_DVO1",
222         "INTERNAL_KLDSCP_DAC1",
223         "INTERNAL_KLDSCP_DAC2",
224         "SI178",
225         "MVPU_FPGA",
226         "INTERNAL_DDI",
227         "VT1625",
228         "HDMI_SI1932",
229         "DP_AN9801",
230         "DP_DP501",
231         "INTERNAL_UNIPHY",
232         "INTERNAL_KLDSCP_LVTMA",
233         "INTERNAL_UNIPHY1",
234         "INTERNAL_UNIPHY2",
235 };
236
237 static const char *connector_names[15] = {
238         "Unknown",
239         "VGA",
240         "DVI-I",
241         "DVI-D",
242         "DVI-A",
243         "Composite",
244         "S-video",
245         "LVDS",
246         "Component",
247         "DIN",
248         "DisplayPort",
249         "HDMI-A",
250         "HDMI-B",
251         "TV",
252         "eDP",
253 };
254
255 static const char *hpd_names[7] = {
256         "NONE",
257         "HPD1",
258         "HPD2",
259         "HPD3",
260         "HPD4",
261         "HPD5",
262         "HPD6",
263 };
264
265 static void radeon_print_display_setup(struct drm_device *dev)
266 {
267         struct drm_connector *connector;
268         struct radeon_connector *radeon_connector;
269         struct drm_encoder *encoder;
270         struct radeon_encoder *radeon_encoder;
271         uint32_t devices;
272         int i = 0;
273
274         DRM_INFO("Radeon Display Connectors\n");
275         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
276                 radeon_connector = to_radeon_connector(connector);
277                 DRM_INFO("Connector %d:\n", i);
278                 DRM_INFO("  %s\n", connector_names[connector->connector_type]);
279                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
280                         DRM_INFO("  %s\n", hpd_names[radeon_connector->hpd.hpd]);
281                 if (radeon_connector->ddc_bus)
282                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
283                                  radeon_connector->ddc_bus->rec.mask_clk_reg,
284                                  radeon_connector->ddc_bus->rec.mask_data_reg,
285                                  radeon_connector->ddc_bus->rec.a_clk_reg,
286                                  radeon_connector->ddc_bus->rec.a_data_reg,
287                                  radeon_connector->ddc_bus->rec.en_clk_reg,
288                                  radeon_connector->ddc_bus->rec.en_data_reg,
289                                  radeon_connector->ddc_bus->rec.y_clk_reg,
290                                  radeon_connector->ddc_bus->rec.y_data_reg);
291                 DRM_INFO("  Encoders:\n");
292                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
293                         radeon_encoder = to_radeon_encoder(encoder);
294                         devices = radeon_encoder->devices & radeon_connector->devices;
295                         if (devices) {
296                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
297                                         DRM_INFO("    CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
298                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
299                                         DRM_INFO("    CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
300                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
301                                         DRM_INFO("    LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
302                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
303                                         DRM_INFO("    DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
304                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
305                                         DRM_INFO("    DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
306                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
307                                         DRM_INFO("    DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
308                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
309                                         DRM_INFO("    DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
310                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
311                                         DRM_INFO("    DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
312                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
313                                         DRM_INFO("    TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
314                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
315                                         DRM_INFO("    CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
316                         }
317                 }
318                 i++;
319         }
320 }
321
322 static bool radeon_setup_enc_conn(struct drm_device *dev)
323 {
324         struct radeon_device *rdev = dev->dev_private;
325         struct drm_connector *drm_connector;
326         bool ret = false;
327
328         if (rdev->bios) {
329                 if (rdev->is_atom_bios) {
330                         if (rdev->family >= CHIP_R600)
331                                 ret = radeon_get_atom_connector_info_from_object_table(dev);
332                         else
333                                 ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
334                 } else {
335                         ret = radeon_get_legacy_connector_info_from_bios(dev);
336                         if (ret == false)
337                                 ret = radeon_get_legacy_connector_info_from_table(dev);
338                 }
339         } else {
340                 if (!ASIC_IS_AVIVO(rdev))
341                         ret = radeon_get_legacy_connector_info_from_table(dev);
342         }
343         if (ret) {
344                 radeon_setup_encoder_clones(dev);
345                 radeon_print_display_setup(dev);
346                 list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head)
347                         radeon_ddc_dump(drm_connector);
348         }
349
350         return ret;
351 }
352
353 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
354 {
355         int ret = 0;
356
357         if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
358             (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
359                 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
360                 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
361                      dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
362                         radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter);
363         }
364         if (!radeon_connector->ddc_bus)
365                 return -1;
366         if (!radeon_connector->edid) {
367                 radeon_i2c_do_lock(radeon_connector->ddc_bus, 1);
368                 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
369                 radeon_i2c_do_lock(radeon_connector->ddc_bus, 0);
370         }
371
372         if (radeon_connector->edid) {
373                 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
374                 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
375                 return ret;
376         }
377         drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
378         return 0;
379 }
380
381 static int radeon_ddc_dump(struct drm_connector *connector)
382 {
383         struct edid *edid;
384         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
385         int ret = 0;
386
387         if (!radeon_connector->ddc_bus)
388                 return -1;
389         radeon_i2c_do_lock(radeon_connector->ddc_bus, 1);
390         edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter);
391         radeon_i2c_do_lock(radeon_connector->ddc_bus, 0);
392         if (edid) {
393                 kfree(edid);
394         }
395         return ret;
396 }
397
398 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
399 {
400         uint64_t mod;
401
402         n += d / 2;
403
404         mod = do_div(n, d);
405         return n;
406 }
407
408 void radeon_compute_pll(struct radeon_pll *pll,
409                         uint64_t freq,
410                         uint32_t *dot_clock_p,
411                         uint32_t *fb_div_p,
412                         uint32_t *frac_fb_div_p,
413                         uint32_t *ref_div_p,
414                         uint32_t *post_div_p)
415 {
416         uint32_t min_ref_div = pll->min_ref_div;
417         uint32_t max_ref_div = pll->max_ref_div;
418         uint32_t min_post_div = pll->min_post_div;
419         uint32_t max_post_div = pll->max_post_div;
420         uint32_t min_fractional_feed_div = 0;
421         uint32_t max_fractional_feed_div = 0;
422         uint32_t best_vco = pll->best_vco;
423         uint32_t best_post_div = 1;
424         uint32_t best_ref_div = 1;
425         uint32_t best_feedback_div = 1;
426         uint32_t best_frac_feedback_div = 0;
427         uint32_t best_freq = -1;
428         uint32_t best_error = 0xffffffff;
429         uint32_t best_vco_diff = 1;
430         uint32_t post_div;
431
432         DRM_DEBUG("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
433         freq = freq * 1000;
434
435         if (pll->flags & RADEON_PLL_USE_REF_DIV)
436                 min_ref_div = max_ref_div = pll->reference_div;
437         else {
438                 while (min_ref_div < max_ref_div-1) {
439                         uint32_t mid = (min_ref_div + max_ref_div) / 2;
440                         uint32_t pll_in = pll->reference_freq / mid;
441                         if (pll_in < pll->pll_in_min)
442                                 max_ref_div = mid;
443                         else if (pll_in > pll->pll_in_max)
444                                 min_ref_div = mid;
445                         else
446                                 break;
447                 }
448         }
449
450         if (pll->flags & RADEON_PLL_USE_POST_DIV)
451                 min_post_div = max_post_div = pll->post_div;
452
453         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
454                 min_fractional_feed_div = pll->min_frac_feedback_div;
455                 max_fractional_feed_div = pll->max_frac_feedback_div;
456         }
457
458         for (post_div = min_post_div; post_div <= max_post_div; ++post_div) {
459                 uint32_t ref_div;
460
461                 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
462                         continue;
463
464                 /* legacy radeons only have a few post_divs */
465                 if (pll->flags & RADEON_PLL_LEGACY) {
466                         if ((post_div == 5) ||
467                             (post_div == 7) ||
468                             (post_div == 9) ||
469                             (post_div == 10) ||
470                             (post_div == 11) ||
471                             (post_div == 13) ||
472                             (post_div == 14) ||
473                             (post_div == 15))
474                                 continue;
475                 }
476
477                 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
478                         uint32_t feedback_div, current_freq = 0, error, vco_diff;
479                         uint32_t pll_in = pll->reference_freq / ref_div;
480                         uint32_t min_feed_div = pll->min_feedback_div;
481                         uint32_t max_feed_div = pll->max_feedback_div + 1;
482
483                         if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
484                                 continue;
485
486                         while (min_feed_div < max_feed_div) {
487                                 uint32_t vco;
488                                 uint32_t min_frac_feed_div = min_fractional_feed_div;
489                                 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
490                                 uint32_t frac_feedback_div;
491                                 uint64_t tmp;
492
493                                 feedback_div = (min_feed_div + max_feed_div) / 2;
494
495                                 tmp = (uint64_t)pll->reference_freq * feedback_div;
496                                 vco = radeon_div(tmp, ref_div);
497
498                                 if (vco < pll->pll_out_min) {
499                                         min_feed_div = feedback_div + 1;
500                                         continue;
501                                 } else if (vco > pll->pll_out_max) {
502                                         max_feed_div = feedback_div;
503                                         continue;
504                                 }
505
506                                 while (min_frac_feed_div < max_frac_feed_div) {
507                                         frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
508                                         tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
509                                         tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
510                                         current_freq = radeon_div(tmp, ref_div * post_div);
511
512                                         if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
513                                                 error = freq - current_freq;
514                                                 error = error < 0 ? 0xffffffff : error;
515                                         } else
516                                                 error = abs(current_freq - freq);
517                                         vco_diff = abs(vco - best_vco);
518
519                                         if ((best_vco == 0 && error < best_error) ||
520                                             (best_vco != 0 &&
521                                              (error < best_error - 100 ||
522                                               (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
523                                                 best_post_div = post_div;
524                                                 best_ref_div = ref_div;
525                                                 best_feedback_div = feedback_div;
526                                                 best_frac_feedback_div = frac_feedback_div;
527                                                 best_freq = current_freq;
528                                                 best_error = error;
529                                                 best_vco_diff = vco_diff;
530                                         } else if (current_freq == freq) {
531                                                 if (best_freq == -1) {
532                                                         best_post_div = post_div;
533                                                         best_ref_div = ref_div;
534                                                         best_feedback_div = feedback_div;
535                                                         best_frac_feedback_div = frac_feedback_div;
536                                                         best_freq = current_freq;
537                                                         best_error = error;
538                                                         best_vco_diff = vco_diff;
539                                                 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
540                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
541                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
542                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
543                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
544                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
545                                                         best_post_div = post_div;
546                                                         best_ref_div = ref_div;
547                                                         best_feedback_div = feedback_div;
548                                                         best_frac_feedback_div = frac_feedback_div;
549                                                         best_freq = current_freq;
550                                                         best_error = error;
551                                                         best_vco_diff = vco_diff;
552                                                 }
553                                         }
554                                         if (current_freq < freq)
555                                                 min_frac_feed_div = frac_feedback_div + 1;
556                                         else
557                                                 max_frac_feed_div = frac_feedback_div;
558                                 }
559                                 if (current_freq < freq)
560                                         min_feed_div = feedback_div + 1;
561                                 else
562                                         max_feed_div = feedback_div;
563                         }
564                 }
565         }
566
567         *dot_clock_p = best_freq / 10000;
568         *fb_div_p = best_feedback_div;
569         *frac_fb_div_p = best_frac_feedback_div;
570         *ref_div_p = best_ref_div;
571         *post_div_p = best_post_div;
572 }
573
574 void radeon_compute_pll_avivo(struct radeon_pll *pll,
575                               uint64_t freq,
576                               uint32_t *dot_clock_p,
577                               uint32_t *fb_div_p,
578                               uint32_t *frac_fb_div_p,
579                               uint32_t *ref_div_p,
580                               uint32_t *post_div_p)
581 {
582         fixed20_12 m, n, frac_n, p, f_vco, f_pclk, best_freq;
583         fixed20_12 pll_out_max, pll_out_min;
584         fixed20_12 pll_in_max, pll_in_min;
585         fixed20_12 reference_freq;
586         fixed20_12 error, ffreq, a, b;
587
588         pll_out_max.full = rfixed_const(pll->pll_out_max);
589         pll_out_min.full = rfixed_const(pll->pll_out_min);
590         pll_in_max.full = rfixed_const(pll->pll_in_max);
591         pll_in_min.full = rfixed_const(pll->pll_in_min);
592         reference_freq.full = rfixed_const(pll->reference_freq);
593         do_div(freq, 10);
594         ffreq.full = rfixed_const(freq);
595         error.full = rfixed_const(100 * 100);
596
597         /* max p */
598         p.full = rfixed_div(pll_out_max, ffreq);
599         p.full = rfixed_floor(p);
600
601         /* min m */
602         m.full = rfixed_div(reference_freq, pll_in_max);
603         m.full = rfixed_ceil(m);
604
605         while (1) {
606                 n.full = rfixed_div(ffreq, reference_freq);
607                 n.full = rfixed_mul(n, m);
608                 n.full = rfixed_mul(n, p);
609
610                 f_vco.full = rfixed_div(n, m);
611                 f_vco.full = rfixed_mul(f_vco, reference_freq);
612
613                 f_pclk.full = rfixed_div(f_vco, p);
614
615                 if (f_pclk.full > ffreq.full)
616                         error.full = f_pclk.full - ffreq.full;
617                 else
618                         error.full = ffreq.full - f_pclk.full;
619                 error.full = rfixed_div(error, f_pclk);
620                 a.full = rfixed_const(100 * 100);
621                 error.full = rfixed_mul(error, a);
622
623                 a.full = rfixed_mul(m, p);
624                 a.full = rfixed_div(n, a);
625                 best_freq.full = rfixed_mul(reference_freq, a);
626
627                 if (rfixed_trunc(error) < 25)
628                         break;
629
630                 a.full = rfixed_const(1);
631                 m.full = m.full + a.full;
632                 a.full = rfixed_div(reference_freq, m);
633                 if (a.full >= pll_in_min.full)
634                         continue;
635
636                 m.full = rfixed_div(reference_freq, pll_in_max);
637                 m.full = rfixed_ceil(m);
638                 a.full= rfixed_const(1);
639                 p.full = p.full - a.full;
640                 a.full = rfixed_mul(p, ffreq);
641                 if (a.full >= pll_out_min.full)
642                         continue;
643                 else {
644                         DRM_ERROR("Unable to find pll dividers\n");
645                         break;
646                 }
647         }
648
649         a.full = rfixed_const(10);
650         b.full = rfixed_mul(n, a);
651
652         frac_n.full = rfixed_floor(n);
653         frac_n.full = rfixed_mul(frac_n, a);
654         frac_n.full = b.full - frac_n.full;
655
656         *dot_clock_p = rfixed_trunc(best_freq);
657         *fb_div_p = rfixed_trunc(n);
658         *frac_fb_div_p = rfixed_trunc(frac_n);
659         *ref_div_p = rfixed_trunc(m);
660         *post_div_p = rfixed_trunc(p);
661
662         DRM_DEBUG("%u %d.%d, %d, %d\n", *dot_clock_p * 10, *fb_div_p, *frac_fb_div_p, *ref_div_p, *post_div_p);
663 }
664
665 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
666 {
667         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
668         struct drm_device *dev = fb->dev;
669
670         if (fb->fbdev)
671                 radeonfb_remove(dev, fb);
672
673         if (radeon_fb->obj) {
674                 mutex_lock(&dev->struct_mutex);
675                 drm_gem_object_unreference(radeon_fb->obj);
676                 mutex_unlock(&dev->struct_mutex);
677         }
678         drm_framebuffer_cleanup(fb);
679         kfree(radeon_fb);
680 }
681
682 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
683                                                   struct drm_file *file_priv,
684                                                   unsigned int *handle)
685 {
686         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
687
688         return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
689 }
690
691 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
692         .destroy = radeon_user_framebuffer_destroy,
693         .create_handle = radeon_user_framebuffer_create_handle,
694 };
695
696 struct drm_framebuffer *
697 radeon_framebuffer_create(struct drm_device *dev,
698                           struct drm_mode_fb_cmd *mode_cmd,
699                           struct drm_gem_object *obj)
700 {
701         struct radeon_framebuffer *radeon_fb;
702
703         radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
704         if (radeon_fb == NULL) {
705                 return NULL;
706         }
707         drm_framebuffer_init(dev, &radeon_fb->base, &radeon_fb_funcs);
708         drm_helper_mode_fill_fb_struct(&radeon_fb->base, mode_cmd);
709         radeon_fb->obj = obj;
710         return &radeon_fb->base;
711 }
712
713 static struct drm_framebuffer *
714 radeon_user_framebuffer_create(struct drm_device *dev,
715                                struct drm_file *file_priv,
716                                struct drm_mode_fb_cmd *mode_cmd)
717 {
718         struct drm_gem_object *obj;
719
720         obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle);
721         if (obj ==  NULL) {
722                 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
723                         "can't create framebuffer\n", mode_cmd->handle);
724                 return NULL;
725         }
726         return radeon_framebuffer_create(dev, mode_cmd, obj);
727 }
728
729 static const struct drm_mode_config_funcs radeon_mode_funcs = {
730         .fb_create = radeon_user_framebuffer_create,
731         .fb_changed = radeonfb_probe,
732 };
733
734 struct drm_prop_enum_list {
735         int type;
736         char *name;
737 };
738
739 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
740 {       { 0, "driver" },
741         { 1, "bios" },
742 };
743
744 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
745 {       { TV_STD_NTSC, "ntsc" },
746         { TV_STD_PAL, "pal" },
747         { TV_STD_PAL_M, "pal-m" },
748         { TV_STD_PAL_60, "pal-60" },
749         { TV_STD_NTSC_J, "ntsc-j" },
750         { TV_STD_SCART_PAL, "scart-pal" },
751         { TV_STD_PAL_CN, "pal-cn" },
752         { TV_STD_SECAM, "secam" },
753 };
754
755 static int radeon_modeset_create_props(struct radeon_device *rdev)
756 {
757         int i, sz;
758
759         if (rdev->is_atom_bios) {
760                 rdev->mode_info.coherent_mode_property =
761                         drm_property_create(rdev->ddev,
762                                             DRM_MODE_PROP_RANGE,
763                                             "coherent", 2);
764                 if (!rdev->mode_info.coherent_mode_property)
765                         return -ENOMEM;
766
767                 rdev->mode_info.coherent_mode_property->values[0] = 0;
768                 rdev->mode_info.coherent_mode_property->values[1] = 1;
769         }
770
771         if (!ASIC_IS_AVIVO(rdev)) {
772                 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
773                 rdev->mode_info.tmds_pll_property =
774                         drm_property_create(rdev->ddev,
775                                             DRM_MODE_PROP_ENUM,
776                                             "tmds_pll", sz);
777                 for (i = 0; i < sz; i++) {
778                         drm_property_add_enum(rdev->mode_info.tmds_pll_property,
779                                               i,
780                                               radeon_tmds_pll_enum_list[i].type,
781                                               radeon_tmds_pll_enum_list[i].name);
782                 }
783         }
784
785         rdev->mode_info.load_detect_property =
786                 drm_property_create(rdev->ddev,
787                                     DRM_MODE_PROP_RANGE,
788                                     "load detection", 2);
789         if (!rdev->mode_info.load_detect_property)
790                 return -ENOMEM;
791         rdev->mode_info.load_detect_property->values[0] = 0;
792         rdev->mode_info.load_detect_property->values[1] = 1;
793
794         drm_mode_create_scaling_mode_property(rdev->ddev);
795
796         sz = ARRAY_SIZE(radeon_tv_std_enum_list);
797         rdev->mode_info.tv_std_property =
798                 drm_property_create(rdev->ddev,
799                                     DRM_MODE_PROP_ENUM,
800                                     "tv standard", sz);
801         for (i = 0; i < sz; i++) {
802                 drm_property_add_enum(rdev->mode_info.tv_std_property,
803                                       i,
804                                       radeon_tv_std_enum_list[i].type,
805                                       radeon_tv_std_enum_list[i].name);
806         }
807
808         return 0;
809 }
810
811 int radeon_modeset_init(struct radeon_device *rdev)
812 {
813         int num_crtc = 2, i;
814         int ret;
815
816         drm_mode_config_init(rdev->ddev);
817         rdev->mode_info.mode_config_initialized = true;
818
819         rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs;
820
821         if (ASIC_IS_AVIVO(rdev)) {
822                 rdev->ddev->mode_config.max_width = 8192;
823                 rdev->ddev->mode_config.max_height = 8192;
824         } else {
825                 rdev->ddev->mode_config.max_width = 4096;
826                 rdev->ddev->mode_config.max_height = 4096;
827         }
828
829         rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
830
831         ret = radeon_modeset_create_props(rdev);
832         if (ret) {
833                 return ret;
834         }
835
836         if (rdev->flags & RADEON_SINGLE_CRTC)
837                 num_crtc = 1;
838
839         /* allocate crtcs */
840         for (i = 0; i < num_crtc; i++) {
841                 radeon_crtc_init(rdev->ddev, i);
842         }
843
844         /* okay we should have all the bios connectors */
845         ret = radeon_setup_enc_conn(rdev->ddev);
846         if (!ret) {
847                 return ret;
848         }
849         /* initialize hpd */
850         radeon_hpd_init(rdev);
851         drm_helper_initial_config(rdev->ddev);
852         return 0;
853 }
854
855 void radeon_modeset_fini(struct radeon_device *rdev)
856 {
857         if (rdev->mode_info.mode_config_initialized) {
858                 radeon_hpd_fini(rdev);
859                 drm_mode_config_cleanup(rdev->ddev);
860                 rdev->mode_info.mode_config_initialized = false;
861         }
862 }
863
864 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
865                                 struct drm_display_mode *mode,
866                                 struct drm_display_mode *adjusted_mode)
867 {
868         struct drm_device *dev = crtc->dev;
869         struct drm_encoder *encoder;
870         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
871         struct radeon_encoder *radeon_encoder;
872         bool first = true;
873
874         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
875                 radeon_encoder = to_radeon_encoder(encoder);
876                 if (encoder->crtc != crtc)
877                         continue;
878                 if (first) {
879                         /* set scaling */
880                         if (radeon_encoder->rmx_type == RMX_OFF)
881                                 radeon_crtc->rmx_type = RMX_OFF;
882                         else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
883                                  mode->vdisplay < radeon_encoder->native_mode.vdisplay)
884                                 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
885                         else
886                                 radeon_crtc->rmx_type = RMX_OFF;
887                         /* copy native mode */
888                         memcpy(&radeon_crtc->native_mode,
889                                &radeon_encoder->native_mode,
890                                 sizeof(struct drm_display_mode));
891                         first = false;
892                 } else {
893                         if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
894                                 /* WARNING: Right now this can't happen but
895                                  * in the future we need to check that scaling
896                                  * are consistent accross different encoder
897                                  * (ie all encoder can work with the same
898                                  *  scaling).
899                                  */
900                                 DRM_ERROR("Scaling not consistent accross encoder.\n");
901                                 return false;
902                         }
903                 }
904         }
905         if (radeon_crtc->rmx_type != RMX_OFF) {
906                 fixed20_12 a, b;
907                 a.full = rfixed_const(crtc->mode.vdisplay);
908                 b.full = rfixed_const(radeon_crtc->native_mode.hdisplay);
909                 radeon_crtc->vsc.full = rfixed_div(a, b);
910                 a.full = rfixed_const(crtc->mode.hdisplay);
911                 b.full = rfixed_const(radeon_crtc->native_mode.vdisplay);
912                 radeon_crtc->hsc.full = rfixed_div(a, b);
913         } else {
914                 radeon_crtc->vsc.full = rfixed_const(1);
915                 radeon_crtc->hsc.full = rfixed_const(1);
916         }
917         return true;
918 }