Merge branch 'for-davem' of ssh://master.kernel.org/pub/scm/linux/kernel/git/linville...
[linux-2.6.git] / drivers / gpu / drm / radeon / radeon_display.c
1 /*
2  * Copyright 2007-8 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: Dave Airlie
24  *          Alex Deucher
25  */
26 #include "drmP.h"
27 #include "radeon_drm.h"
28 #include "radeon.h"
29
30 #include "atom.h"
31 #include <asm/div64.h>
32
33 #include "drm_crtc_helper.h"
34 #include "drm_edid.h"
35
36 static int radeon_ddc_dump(struct drm_connector *connector);
37
38 static void avivo_crtc_load_lut(struct drm_crtc *crtc)
39 {
40         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41         struct drm_device *dev = crtc->dev;
42         struct radeon_device *rdev = dev->dev_private;
43         int i;
44
45         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
46         WREG32(AVIVO_DC_LUTA_CONTROL + radeon_crtc->crtc_offset, 0);
47
48         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
49         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
50         WREG32(AVIVO_DC_LUTA_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
51
52         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
53         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
54         WREG32(AVIVO_DC_LUTA_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
55
56         WREG32(AVIVO_DC_LUT_RW_SELECT, radeon_crtc->crtc_id);
57         WREG32(AVIVO_DC_LUT_RW_MODE, 0);
58         WREG32(AVIVO_DC_LUT_WRITE_EN_MASK, 0x0000003f);
59
60         WREG8(AVIVO_DC_LUT_RW_INDEX, 0);
61         for (i = 0; i < 256; i++) {
62                 WREG32(AVIVO_DC_LUT_30_COLOR,
63                              (radeon_crtc->lut_r[i] << 20) |
64                              (radeon_crtc->lut_g[i] << 10) |
65                              (radeon_crtc->lut_b[i] << 0));
66         }
67
68         WREG32(AVIVO_D1GRPH_LUT_SEL + radeon_crtc->crtc_offset, radeon_crtc->crtc_id);
69 }
70
71 static void dce4_crtc_load_lut(struct drm_crtc *crtc)
72 {
73         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
74         struct drm_device *dev = crtc->dev;
75         struct radeon_device *rdev = dev->dev_private;
76         int i;
77
78         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
79         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
80
81         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
82         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
83         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
84
85         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
86         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
87         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
88
89         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
90         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
91
92         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
93         for (i = 0; i < 256; i++) {
94                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
95                        (radeon_crtc->lut_r[i] << 20) |
96                        (radeon_crtc->lut_g[i] << 10) |
97                        (radeon_crtc->lut_b[i] << 0));
98         }
99 }
100
101 static void dce5_crtc_load_lut(struct drm_crtc *crtc)
102 {
103         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
104         struct drm_device *dev = crtc->dev;
105         struct radeon_device *rdev = dev->dev_private;
106         int i;
107
108         DRM_DEBUG_KMS("%d\n", radeon_crtc->crtc_id);
109
110         WREG32(NI_INPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
111                (NI_INPUT_CSC_GRPH_MODE(NI_INPUT_CSC_BYPASS) |
112                 NI_INPUT_CSC_OVL_MODE(NI_INPUT_CSC_BYPASS)));
113         WREG32(NI_PRESCALE_GRPH_CONTROL + radeon_crtc->crtc_offset,
114                NI_GRPH_PRESCALE_BYPASS);
115         WREG32(NI_PRESCALE_OVL_CONTROL + radeon_crtc->crtc_offset,
116                NI_OVL_PRESCALE_BYPASS);
117         WREG32(NI_INPUT_GAMMA_CONTROL + radeon_crtc->crtc_offset,
118                (NI_GRPH_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT) |
119                 NI_OVL_INPUT_GAMMA_MODE(NI_INPUT_GAMMA_USE_LUT)));
120
121         WREG32(EVERGREEN_DC_LUT_CONTROL + radeon_crtc->crtc_offset, 0);
122
123         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_BLUE + radeon_crtc->crtc_offset, 0);
124         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_GREEN + radeon_crtc->crtc_offset, 0);
125         WREG32(EVERGREEN_DC_LUT_BLACK_OFFSET_RED + radeon_crtc->crtc_offset, 0);
126
127         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_BLUE + radeon_crtc->crtc_offset, 0xffff);
128         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_GREEN + radeon_crtc->crtc_offset, 0xffff);
129         WREG32(EVERGREEN_DC_LUT_WHITE_OFFSET_RED + radeon_crtc->crtc_offset, 0xffff);
130
131         WREG32(EVERGREEN_DC_LUT_RW_MODE + radeon_crtc->crtc_offset, 0);
132         WREG32(EVERGREEN_DC_LUT_WRITE_EN_MASK + radeon_crtc->crtc_offset, 0x00000007);
133
134         WREG32(EVERGREEN_DC_LUT_RW_INDEX + radeon_crtc->crtc_offset, 0);
135         for (i = 0; i < 256; i++) {
136                 WREG32(EVERGREEN_DC_LUT_30_COLOR + radeon_crtc->crtc_offset,
137                        (radeon_crtc->lut_r[i] << 20) |
138                        (radeon_crtc->lut_g[i] << 10) |
139                        (radeon_crtc->lut_b[i] << 0));
140         }
141
142         WREG32(NI_DEGAMMA_CONTROL + radeon_crtc->crtc_offset,
143                (NI_GRPH_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
144                 NI_OVL_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
145                 NI_ICON_DEGAMMA_MODE(NI_DEGAMMA_BYPASS) |
146                 NI_CURSOR_DEGAMMA_MODE(NI_DEGAMMA_BYPASS)));
147         WREG32(NI_GAMUT_REMAP_CONTROL + radeon_crtc->crtc_offset,
148                (NI_GRPH_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS) |
149                 NI_OVL_GAMUT_REMAP_MODE(NI_GAMUT_REMAP_BYPASS)));
150         WREG32(NI_REGAMMA_CONTROL + radeon_crtc->crtc_offset,
151                (NI_GRPH_REGAMMA_MODE(NI_REGAMMA_BYPASS) |
152                 NI_OVL_REGAMMA_MODE(NI_REGAMMA_BYPASS)));
153         WREG32(NI_OUTPUT_CSC_CONTROL + radeon_crtc->crtc_offset,
154                (NI_OUTPUT_CSC_GRPH_MODE(NI_OUTPUT_CSC_BYPASS) |
155                 NI_OUTPUT_CSC_OVL_MODE(NI_OUTPUT_CSC_BYPASS)));
156         /* XXX match this to the depth of the crtc fmt block, move to modeset? */
157         WREG32(0x6940 + radeon_crtc->crtc_offset, 0);
158
159 }
160
161 static void legacy_crtc_load_lut(struct drm_crtc *crtc)
162 {
163         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
164         struct drm_device *dev = crtc->dev;
165         struct radeon_device *rdev = dev->dev_private;
166         int i;
167         uint32_t dac2_cntl;
168
169         dac2_cntl = RREG32(RADEON_DAC_CNTL2);
170         if (radeon_crtc->crtc_id == 0)
171                 dac2_cntl &= (uint32_t)~RADEON_DAC2_PALETTE_ACC_CTL;
172         else
173                 dac2_cntl |= RADEON_DAC2_PALETTE_ACC_CTL;
174         WREG32(RADEON_DAC_CNTL2, dac2_cntl);
175
176         WREG8(RADEON_PALETTE_INDEX, 0);
177         for (i = 0; i < 256; i++) {
178                 WREG32(RADEON_PALETTE_30_DATA,
179                              (radeon_crtc->lut_r[i] << 20) |
180                              (radeon_crtc->lut_g[i] << 10) |
181                              (radeon_crtc->lut_b[i] << 0));
182         }
183 }
184
185 void radeon_crtc_load_lut(struct drm_crtc *crtc)
186 {
187         struct drm_device *dev = crtc->dev;
188         struct radeon_device *rdev = dev->dev_private;
189
190         if (!crtc->enabled)
191                 return;
192
193         if (ASIC_IS_DCE5(rdev))
194                 dce5_crtc_load_lut(crtc);
195         else if (ASIC_IS_DCE4(rdev))
196                 dce4_crtc_load_lut(crtc);
197         else if (ASIC_IS_AVIVO(rdev))
198                 avivo_crtc_load_lut(crtc);
199         else
200                 legacy_crtc_load_lut(crtc);
201 }
202
203 /** Sets the color ramps on behalf of fbcon */
204 void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
205                               u16 blue, int regno)
206 {
207         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
208
209         radeon_crtc->lut_r[regno] = red >> 6;
210         radeon_crtc->lut_g[regno] = green >> 6;
211         radeon_crtc->lut_b[regno] = blue >> 6;
212 }
213
214 /** Gets the color ramps on behalf of fbcon */
215 void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
216                               u16 *blue, int regno)
217 {
218         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
219
220         *red = radeon_crtc->lut_r[regno] << 6;
221         *green = radeon_crtc->lut_g[regno] << 6;
222         *blue = radeon_crtc->lut_b[regno] << 6;
223 }
224
225 static void radeon_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
226                                   u16 *blue, uint32_t start, uint32_t size)
227 {
228         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
229         int end = (start + size > 256) ? 256 : start + size, i;
230
231         /* userspace palettes are always correct as is */
232         for (i = start; i < end; i++) {
233                 radeon_crtc->lut_r[i] = red[i] >> 6;
234                 radeon_crtc->lut_g[i] = green[i] >> 6;
235                 radeon_crtc->lut_b[i] = blue[i] >> 6;
236         }
237         radeon_crtc_load_lut(crtc);
238 }
239
240 static void radeon_crtc_destroy(struct drm_crtc *crtc)
241 {
242         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
243
244         drm_crtc_cleanup(crtc);
245         kfree(radeon_crtc);
246 }
247
248 /*
249  * Handle unpin events outside the interrupt handler proper.
250  */
251 static void radeon_unpin_work_func(struct work_struct *__work)
252 {
253         struct radeon_unpin_work *work =
254                 container_of(__work, struct radeon_unpin_work, work);
255         int r;
256
257         /* unpin of the old buffer */
258         r = radeon_bo_reserve(work->old_rbo, false);
259         if (likely(r == 0)) {
260                 r = radeon_bo_unpin(work->old_rbo);
261                 if (unlikely(r != 0)) {
262                         DRM_ERROR("failed to unpin buffer after flip\n");
263                 }
264                 radeon_bo_unreserve(work->old_rbo);
265         } else
266                 DRM_ERROR("failed to reserve buffer after flip\n");
267         kfree(work);
268 }
269
270 void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
271 {
272         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
273         struct radeon_unpin_work *work;
274         struct drm_pending_vblank_event *e;
275         struct timeval now;
276         unsigned long flags;
277         u32 update_pending;
278         int vpos, hpos;
279
280         spin_lock_irqsave(&rdev->ddev->event_lock, flags);
281         work = radeon_crtc->unpin_work;
282         if (work == NULL ||
283             !radeon_fence_signaled(work->fence)) {
284                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
285                 return;
286         }
287         /* New pageflip, or just completion of a previous one? */
288         if (!radeon_crtc->deferred_flip_completion) {
289                 /* do the flip (mmio) */
290                 update_pending = radeon_page_flip(rdev, crtc_id, work->new_crtc_base);
291         } else {
292                 /* This is just a completion of a flip queued in crtc
293                  * at last invocation. Make sure we go directly to
294                  * completion routine.
295                  */
296                 update_pending = 0;
297                 radeon_crtc->deferred_flip_completion = 0;
298         }
299
300         /* Has the pageflip already completed in crtc, or is it certain
301          * to complete in this vblank?
302          */
303         if (update_pending &&
304             (DRM_SCANOUTPOS_VALID & radeon_get_crtc_scanoutpos(rdev->ddev, crtc_id,
305                                                                &vpos, &hpos)) &&
306             (vpos >=0) &&
307             (vpos < (99 * rdev->mode_info.crtcs[crtc_id]->base.hwmode.crtc_vdisplay)/100)) {
308                 /* crtc didn't flip in this target vblank interval,
309                  * but flip is pending in crtc. It will complete it
310                  * in next vblank interval, so complete the flip at
311                  * next vblank irq.
312                  */
313                 radeon_crtc->deferred_flip_completion = 1;
314                 spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
315                 return;
316         }
317
318         /* Pageflip (will be) certainly completed in this vblank. Clean up. */
319         radeon_crtc->unpin_work = NULL;
320
321         /* wakeup userspace */
322         if (work->event) {
323                 e = work->event;
324                 e->event.sequence = drm_vblank_count_and_time(rdev->ddev, crtc_id, &now);
325                 e->event.tv_sec = now.tv_sec;
326                 e->event.tv_usec = now.tv_usec;
327                 list_add_tail(&e->base.link, &e->base.file_priv->event_list);
328                 wake_up_interruptible(&e->base.file_priv->event_wait);
329         }
330         spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
331
332         drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
333         radeon_fence_unref(&work->fence);
334         radeon_post_page_flip(work->rdev, work->crtc_id);
335         schedule_work(&work->work);
336 }
337
338 static int radeon_crtc_page_flip(struct drm_crtc *crtc,
339                                  struct drm_framebuffer *fb,
340                                  struct drm_pending_vblank_event *event)
341 {
342         struct drm_device *dev = crtc->dev;
343         struct radeon_device *rdev = dev->dev_private;
344         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
345         struct radeon_framebuffer *old_radeon_fb;
346         struct radeon_framebuffer *new_radeon_fb;
347         struct drm_gem_object *obj;
348         struct radeon_bo *rbo;
349         struct radeon_fence *fence;
350         struct radeon_unpin_work *work;
351         unsigned long flags;
352         u32 tiling_flags, pitch_pixels;
353         u64 base;
354         int r;
355
356         work = kzalloc(sizeof *work, GFP_KERNEL);
357         if (work == NULL)
358                 return -ENOMEM;
359
360         r = radeon_fence_create(rdev, &fence);
361         if (unlikely(r != 0)) {
362                 kfree(work);
363                 DRM_ERROR("flip queue: failed to create fence.\n");
364                 return -ENOMEM;
365         }
366         work->event = event;
367         work->rdev = rdev;
368         work->crtc_id = radeon_crtc->crtc_id;
369         work->fence = radeon_fence_ref(fence);
370         old_radeon_fb = to_radeon_framebuffer(crtc->fb);
371         new_radeon_fb = to_radeon_framebuffer(fb);
372         /* schedule unpin of the old buffer */
373         obj = old_radeon_fb->obj;
374         rbo = obj->driver_private;
375         work->old_rbo = rbo;
376         INIT_WORK(&work->work, radeon_unpin_work_func);
377
378         /* We borrow the event spin lock for protecting unpin_work */
379         spin_lock_irqsave(&dev->event_lock, flags);
380         if (radeon_crtc->unpin_work) {
381                 spin_unlock_irqrestore(&dev->event_lock, flags);
382                 kfree(work);
383                 radeon_fence_unref(&fence);
384
385                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
386                 return -EBUSY;
387         }
388         radeon_crtc->unpin_work = work;
389         radeon_crtc->deferred_flip_completion = 0;
390         spin_unlock_irqrestore(&dev->event_lock, flags);
391
392         /* pin the new buffer */
393         obj = new_radeon_fb->obj;
394         rbo = obj->driver_private;
395
396         DRM_DEBUG_DRIVER("flip-ioctl() cur_fbo = %p, cur_bbo = %p\n",
397                          work->old_rbo, rbo);
398
399         r = radeon_bo_reserve(rbo, false);
400         if (unlikely(r != 0)) {
401                 DRM_ERROR("failed to reserve new rbo buffer before flip\n");
402                 goto pflip_cleanup;
403         }
404         r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &base);
405         if (unlikely(r != 0)) {
406                 radeon_bo_unreserve(rbo);
407                 r = -EINVAL;
408                 DRM_ERROR("failed to pin new rbo buffer before flip\n");
409                 goto pflip_cleanup;
410         }
411         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
412         radeon_bo_unreserve(rbo);
413
414         if (!ASIC_IS_AVIVO(rdev)) {
415                 /* crtc offset is from display base addr not FB location */
416                 base -= radeon_crtc->legacy_display_base_addr;
417                 pitch_pixels = fb->pitch / (fb->bits_per_pixel / 8);
418
419                 if (tiling_flags & RADEON_TILING_MACRO) {
420                         if (ASIC_IS_R300(rdev)) {
421                                 base &= ~0x7ff;
422                         } else {
423                                 int byteshift = fb->bits_per_pixel >> 4;
424                                 int tile_addr = (((crtc->y >> 3) * pitch_pixels +  crtc->x) >> (8 - byteshift)) << 11;
425                                 base += tile_addr + ((crtc->x << byteshift) % 256) + ((crtc->y % 8) << 8);
426                         }
427                 } else {
428                         int offset = crtc->y * pitch_pixels + crtc->x;
429                         switch (fb->bits_per_pixel) {
430                         case 8:
431                         default:
432                                 offset *= 1;
433                                 break;
434                         case 15:
435                         case 16:
436                                 offset *= 2;
437                                 break;
438                         case 24:
439                                 offset *= 3;
440                                 break;
441                         case 32:
442                                 offset *= 4;
443                                 break;
444                         }
445                         base += offset;
446                 }
447                 base &= ~7;
448         }
449
450         spin_lock_irqsave(&dev->event_lock, flags);
451         work->new_crtc_base = base;
452         spin_unlock_irqrestore(&dev->event_lock, flags);
453
454         /* update crtc fb */
455         crtc->fb = fb;
456
457         r = drm_vblank_get(dev, radeon_crtc->crtc_id);
458         if (r) {
459                 DRM_ERROR("failed to get vblank before flip\n");
460                 goto pflip_cleanup1;
461         }
462
463         /* 32 ought to cover us */
464         r = radeon_ring_lock(rdev, 32);
465         if (r) {
466                 DRM_ERROR("failed to lock the ring before flip\n");
467                 goto pflip_cleanup2;
468         }
469
470         /* emit the fence */
471         radeon_fence_emit(rdev, fence);
472         /* set the proper interrupt */
473         radeon_pre_page_flip(rdev, radeon_crtc->crtc_id);
474         /* fire the ring */
475         radeon_ring_unlock_commit(rdev);
476
477         return 0;
478
479 pflip_cleanup2:
480         drm_vblank_put(dev, radeon_crtc->crtc_id);
481
482 pflip_cleanup1:
483         r = radeon_bo_reserve(rbo, false);
484         if (unlikely(r != 0)) {
485                 DRM_ERROR("failed to reserve new rbo in error path\n");
486                 goto pflip_cleanup;
487         }
488         r = radeon_bo_unpin(rbo);
489         if (unlikely(r != 0)) {
490                 radeon_bo_unreserve(rbo);
491                 r = -EINVAL;
492                 DRM_ERROR("failed to unpin new rbo in error path\n");
493                 goto pflip_cleanup;
494         }
495         radeon_bo_unreserve(rbo);
496
497 pflip_cleanup:
498         spin_lock_irqsave(&dev->event_lock, flags);
499         radeon_crtc->unpin_work = NULL;
500         spin_unlock_irqrestore(&dev->event_lock, flags);
501         radeon_fence_unref(&fence);
502         kfree(work);
503
504         return r;
505 }
506
507 static const struct drm_crtc_funcs radeon_crtc_funcs = {
508         .cursor_set = radeon_crtc_cursor_set,
509         .cursor_move = radeon_crtc_cursor_move,
510         .gamma_set = radeon_crtc_gamma_set,
511         .set_config = drm_crtc_helper_set_config,
512         .destroy = radeon_crtc_destroy,
513         .page_flip = radeon_crtc_page_flip,
514 };
515
516 static void radeon_crtc_init(struct drm_device *dev, int index)
517 {
518         struct radeon_device *rdev = dev->dev_private;
519         struct radeon_crtc *radeon_crtc;
520         int i;
521
522         radeon_crtc = kzalloc(sizeof(struct radeon_crtc) + (RADEONFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
523         if (radeon_crtc == NULL)
524                 return;
525
526         drm_crtc_init(dev, &radeon_crtc->base, &radeon_crtc_funcs);
527
528         drm_mode_crtc_set_gamma_size(&radeon_crtc->base, 256);
529         radeon_crtc->crtc_id = index;
530         rdev->mode_info.crtcs[index] = radeon_crtc;
531
532 #if 0
533         radeon_crtc->mode_set.crtc = &radeon_crtc->base;
534         radeon_crtc->mode_set.connectors = (struct drm_connector **)(radeon_crtc + 1);
535         radeon_crtc->mode_set.num_connectors = 0;
536 #endif
537
538         for (i = 0; i < 256; i++) {
539                 radeon_crtc->lut_r[i] = i << 2;
540                 radeon_crtc->lut_g[i] = i << 2;
541                 radeon_crtc->lut_b[i] = i << 2;
542         }
543
544         if (rdev->is_atom_bios && (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom))
545                 radeon_atombios_init_crtc(dev, radeon_crtc);
546         else
547                 radeon_legacy_init_crtc(dev, radeon_crtc);
548 }
549
550 static const char *encoder_names[36] = {
551         "NONE",
552         "INTERNAL_LVDS",
553         "INTERNAL_TMDS1",
554         "INTERNAL_TMDS2",
555         "INTERNAL_DAC1",
556         "INTERNAL_DAC2",
557         "INTERNAL_SDVOA",
558         "INTERNAL_SDVOB",
559         "SI170B",
560         "CH7303",
561         "CH7301",
562         "INTERNAL_DVO1",
563         "EXTERNAL_SDVOA",
564         "EXTERNAL_SDVOB",
565         "TITFP513",
566         "INTERNAL_LVTM1",
567         "VT1623",
568         "HDMI_SI1930",
569         "HDMI_INTERNAL",
570         "INTERNAL_KLDSCP_TMDS1",
571         "INTERNAL_KLDSCP_DVO1",
572         "INTERNAL_KLDSCP_DAC1",
573         "INTERNAL_KLDSCP_DAC2",
574         "SI178",
575         "MVPU_FPGA",
576         "INTERNAL_DDI",
577         "VT1625",
578         "HDMI_SI1932",
579         "DP_AN9801",
580         "DP_DP501",
581         "INTERNAL_UNIPHY",
582         "INTERNAL_KLDSCP_LVTMA",
583         "INTERNAL_UNIPHY1",
584         "INTERNAL_UNIPHY2",
585         "NUTMEG",
586         "TRAVIS",
587 };
588
589 static const char *connector_names[15] = {
590         "Unknown",
591         "VGA",
592         "DVI-I",
593         "DVI-D",
594         "DVI-A",
595         "Composite",
596         "S-video",
597         "LVDS",
598         "Component",
599         "DIN",
600         "DisplayPort",
601         "HDMI-A",
602         "HDMI-B",
603         "TV",
604         "eDP",
605 };
606
607 static const char *hpd_names[6] = {
608         "HPD1",
609         "HPD2",
610         "HPD3",
611         "HPD4",
612         "HPD5",
613         "HPD6",
614 };
615
616 static void radeon_print_display_setup(struct drm_device *dev)
617 {
618         struct drm_connector *connector;
619         struct radeon_connector *radeon_connector;
620         struct drm_encoder *encoder;
621         struct radeon_encoder *radeon_encoder;
622         uint32_t devices;
623         int i = 0;
624
625         DRM_INFO("Radeon Display Connectors\n");
626         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
627                 radeon_connector = to_radeon_connector(connector);
628                 DRM_INFO("Connector %d:\n", i);
629                 DRM_INFO("  %s\n", connector_names[connector->connector_type]);
630                 if (radeon_connector->hpd.hpd != RADEON_HPD_NONE)
631                         DRM_INFO("  %s\n", hpd_names[radeon_connector->hpd.hpd]);
632                 if (radeon_connector->ddc_bus) {
633                         DRM_INFO("  DDC: 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n",
634                                  radeon_connector->ddc_bus->rec.mask_clk_reg,
635                                  radeon_connector->ddc_bus->rec.mask_data_reg,
636                                  radeon_connector->ddc_bus->rec.a_clk_reg,
637                                  radeon_connector->ddc_bus->rec.a_data_reg,
638                                  radeon_connector->ddc_bus->rec.en_clk_reg,
639                                  radeon_connector->ddc_bus->rec.en_data_reg,
640                                  radeon_connector->ddc_bus->rec.y_clk_reg,
641                                  radeon_connector->ddc_bus->rec.y_data_reg);
642                         if (radeon_connector->router.ddc_valid)
643                                 DRM_INFO("  DDC Router 0x%x/0x%x\n",
644                                          radeon_connector->router.ddc_mux_control_pin,
645                                          radeon_connector->router.ddc_mux_state);
646                         if (radeon_connector->router.cd_valid)
647                                 DRM_INFO("  Clock/Data Router 0x%x/0x%x\n",
648                                          radeon_connector->router.cd_mux_control_pin,
649                                          radeon_connector->router.cd_mux_state);
650                 } else {
651                         if (connector->connector_type == DRM_MODE_CONNECTOR_VGA ||
652                             connector->connector_type == DRM_MODE_CONNECTOR_DVII ||
653                             connector->connector_type == DRM_MODE_CONNECTOR_DVID ||
654                             connector->connector_type == DRM_MODE_CONNECTOR_DVIA ||
655                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIA ||
656                             connector->connector_type == DRM_MODE_CONNECTOR_HDMIB)
657                                 DRM_INFO("  DDC: no ddc bus - possible BIOS bug - please report to xorg-driver-ati@lists.x.org\n");
658                 }
659                 DRM_INFO("  Encoders:\n");
660                 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
661                         radeon_encoder = to_radeon_encoder(encoder);
662                         devices = radeon_encoder->devices & radeon_connector->devices;
663                         if (devices) {
664                                 if (devices & ATOM_DEVICE_CRT1_SUPPORT)
665                                         DRM_INFO("    CRT1: %s\n", encoder_names[radeon_encoder->encoder_id]);
666                                 if (devices & ATOM_DEVICE_CRT2_SUPPORT)
667                                         DRM_INFO("    CRT2: %s\n", encoder_names[radeon_encoder->encoder_id]);
668                                 if (devices & ATOM_DEVICE_LCD1_SUPPORT)
669                                         DRM_INFO("    LCD1: %s\n", encoder_names[radeon_encoder->encoder_id]);
670                                 if (devices & ATOM_DEVICE_DFP1_SUPPORT)
671                                         DRM_INFO("    DFP1: %s\n", encoder_names[radeon_encoder->encoder_id]);
672                                 if (devices & ATOM_DEVICE_DFP2_SUPPORT)
673                                         DRM_INFO("    DFP2: %s\n", encoder_names[radeon_encoder->encoder_id]);
674                                 if (devices & ATOM_DEVICE_DFP3_SUPPORT)
675                                         DRM_INFO("    DFP3: %s\n", encoder_names[radeon_encoder->encoder_id]);
676                                 if (devices & ATOM_DEVICE_DFP4_SUPPORT)
677                                         DRM_INFO("    DFP4: %s\n", encoder_names[radeon_encoder->encoder_id]);
678                                 if (devices & ATOM_DEVICE_DFP5_SUPPORT)
679                                         DRM_INFO("    DFP5: %s\n", encoder_names[radeon_encoder->encoder_id]);
680                                 if (devices & ATOM_DEVICE_DFP6_SUPPORT)
681                                         DRM_INFO("    DFP6: %s\n", encoder_names[radeon_encoder->encoder_id]);
682                                 if (devices & ATOM_DEVICE_TV1_SUPPORT)
683                                         DRM_INFO("    TV1: %s\n", encoder_names[radeon_encoder->encoder_id]);
684                                 if (devices & ATOM_DEVICE_CV_SUPPORT)
685                                         DRM_INFO("    CV: %s\n", encoder_names[radeon_encoder->encoder_id]);
686                         }
687                 }
688                 i++;
689         }
690 }
691
692 static bool radeon_setup_enc_conn(struct drm_device *dev)
693 {
694         struct radeon_device *rdev = dev->dev_private;
695         struct drm_connector *drm_connector;
696         bool ret = false;
697
698         if (rdev->bios) {
699                 if (rdev->is_atom_bios) {
700                         ret = radeon_get_atom_connector_info_from_supported_devices_table(dev);
701                         if (ret == false)
702                                 ret = radeon_get_atom_connector_info_from_object_table(dev);
703                 } else {
704                         ret = radeon_get_legacy_connector_info_from_bios(dev);
705                         if (ret == false)
706                                 ret = radeon_get_legacy_connector_info_from_table(dev);
707                 }
708         } else {
709                 if (!ASIC_IS_AVIVO(rdev))
710                         ret = radeon_get_legacy_connector_info_from_table(dev);
711         }
712         if (ret) {
713                 radeon_setup_encoder_clones(dev);
714                 radeon_print_display_setup(dev);
715                 list_for_each_entry(drm_connector, &dev->mode_config.connector_list, head)
716                         radeon_ddc_dump(drm_connector);
717         }
718
719         return ret;
720 }
721
722 int radeon_ddc_get_modes(struct radeon_connector *radeon_connector)
723 {
724         struct drm_device *dev = radeon_connector->base.dev;
725         struct radeon_device *rdev = dev->dev_private;
726         int ret = 0;
727
728         /* on hw with routers, select right port */
729         if (radeon_connector->router.ddc_valid)
730                 radeon_router_select_ddc_port(radeon_connector);
731
732         if ((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_DisplayPort) ||
733             (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)) {
734                 struct radeon_connector_atom_dig *dig = radeon_connector->con_priv;
735                 if ((dig->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT ||
736                      dig->dp_sink_type == CONNECTOR_OBJECT_ID_eDP) && dig->dp_i2c_bus)
737                         radeon_connector->edid = drm_get_edid(&radeon_connector->base, &dig->dp_i2c_bus->adapter);
738         }
739         if (!radeon_connector->ddc_bus)
740                 return -1;
741         if (!radeon_connector->edid) {
742                 radeon_connector->edid = drm_get_edid(&radeon_connector->base, &radeon_connector->ddc_bus->adapter);
743         }
744
745         if (!radeon_connector->edid) {
746                 if (rdev->is_atom_bios) {
747                         /* some laptops provide a hardcoded edid in rom for LCDs */
748                         if (((radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_LVDS) ||
749                              (radeon_connector->base.connector_type == DRM_MODE_CONNECTOR_eDP)))
750                                 radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
751                 } else
752                         /* some servers provide a hardcoded edid in rom for KVMs */
753                         radeon_connector->edid = radeon_bios_get_hardcoded_edid(rdev);
754         }
755         if (radeon_connector->edid) {
756                 drm_mode_connector_update_edid_property(&radeon_connector->base, radeon_connector->edid);
757                 ret = drm_add_edid_modes(&radeon_connector->base, radeon_connector->edid);
758                 return ret;
759         }
760         drm_mode_connector_update_edid_property(&radeon_connector->base, NULL);
761         return 0;
762 }
763
764 static int radeon_ddc_dump(struct drm_connector *connector)
765 {
766         struct edid *edid;
767         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
768         int ret = 0;
769
770         /* on hw with routers, select right port */
771         if (radeon_connector->router.ddc_valid)
772                 radeon_router_select_ddc_port(radeon_connector);
773
774         if (!radeon_connector->ddc_bus)
775                 return -1;
776         edid = drm_get_edid(connector, &radeon_connector->ddc_bus->adapter);
777         if (edid) {
778                 kfree(edid);
779         }
780         return ret;
781 }
782
783 /* avivo */
784 static void avivo_get_fb_div(struct radeon_pll *pll,
785                              u32 target_clock,
786                              u32 post_div,
787                              u32 ref_div,
788                              u32 *fb_div,
789                              u32 *frac_fb_div)
790 {
791         u32 tmp = post_div * ref_div;
792
793         tmp *= target_clock;
794         *fb_div = tmp / pll->reference_freq;
795         *frac_fb_div = tmp % pll->reference_freq;
796
797         if (*fb_div > pll->max_feedback_div)
798                 *fb_div = pll->max_feedback_div;
799         else if (*fb_div < pll->min_feedback_div)
800                 *fb_div = pll->min_feedback_div;
801 }
802
803 static u32 avivo_get_post_div(struct radeon_pll *pll,
804                               u32 target_clock)
805 {
806         u32 vco, post_div, tmp;
807
808         if (pll->flags & RADEON_PLL_USE_POST_DIV)
809                 return pll->post_div;
810
811         if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
812                 if (pll->flags & RADEON_PLL_IS_LCD)
813                         vco = pll->lcd_pll_out_min;
814                 else
815                         vco = pll->pll_out_min;
816         } else {
817                 if (pll->flags & RADEON_PLL_IS_LCD)
818                         vco = pll->lcd_pll_out_max;
819                 else
820                         vco = pll->pll_out_max;
821         }
822
823         post_div = vco / target_clock;
824         tmp = vco % target_clock;
825
826         if (pll->flags & RADEON_PLL_PREFER_MINM_OVER_MAXP) {
827                 if (tmp)
828                         post_div++;
829         } else {
830                 if (!tmp)
831                         post_div--;
832         }
833
834         if (post_div > pll->max_post_div)
835                 post_div = pll->max_post_div;
836         else if (post_div < pll->min_post_div)
837                 post_div = pll->min_post_div;
838
839         return post_div;
840 }
841
842 #define MAX_TOLERANCE 10
843
844 void radeon_compute_pll_avivo(struct radeon_pll *pll,
845                               u32 freq,
846                               u32 *dot_clock_p,
847                               u32 *fb_div_p,
848                               u32 *frac_fb_div_p,
849                               u32 *ref_div_p,
850                               u32 *post_div_p)
851 {
852         u32 target_clock = freq / 10;
853         u32 post_div = avivo_get_post_div(pll, target_clock);
854         u32 ref_div = pll->min_ref_div;
855         u32 fb_div = 0, frac_fb_div = 0, tmp;
856
857         if (pll->flags & RADEON_PLL_USE_REF_DIV)
858                 ref_div = pll->reference_div;
859
860         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
861                 avivo_get_fb_div(pll, target_clock, post_div, ref_div, &fb_div, &frac_fb_div);
862                 frac_fb_div = (100 * frac_fb_div) / pll->reference_freq;
863                 if (frac_fb_div >= 5) {
864                         frac_fb_div -= 5;
865                         frac_fb_div = frac_fb_div / 10;
866                         frac_fb_div++;
867                 }
868                 if (frac_fb_div >= 10) {
869                         fb_div++;
870                         frac_fb_div = 0;
871                 }
872         } else {
873                 while (ref_div <= pll->max_ref_div) {
874                         avivo_get_fb_div(pll, target_clock, post_div, ref_div,
875                                          &fb_div, &frac_fb_div);
876                         if (frac_fb_div >= (pll->reference_freq / 2))
877                                 fb_div++;
878                         frac_fb_div = 0;
879                         tmp = (pll->reference_freq * fb_div) / (post_div * ref_div);
880                         tmp = (tmp * 10000) / target_clock;
881
882                         if (tmp > (10000 + MAX_TOLERANCE))
883                                 ref_div++;
884                         else if (tmp >= (10000 - MAX_TOLERANCE))
885                                 break;
886                         else
887                                 ref_div++;
888                 }
889         }
890
891         *dot_clock_p = ((pll->reference_freq * fb_div * 10) + (pll->reference_freq * frac_fb_div)) /
892                 (ref_div * post_div * 10);
893         *fb_div_p = fb_div;
894         *frac_fb_div_p = frac_fb_div;
895         *ref_div_p = ref_div;
896         *post_div_p = post_div;
897         DRM_DEBUG_KMS("%d, pll dividers - fb: %d.%d ref: %d, post %d\n",
898                       *dot_clock_p, fb_div, frac_fb_div, ref_div, post_div);
899 }
900
901 /* pre-avivo */
902 static inline uint32_t radeon_div(uint64_t n, uint32_t d)
903 {
904         uint64_t mod;
905
906         n += d / 2;
907
908         mod = do_div(n, d);
909         return n;
910 }
911
912 void radeon_compute_pll_legacy(struct radeon_pll *pll,
913                                uint64_t freq,
914                                uint32_t *dot_clock_p,
915                                uint32_t *fb_div_p,
916                                uint32_t *frac_fb_div_p,
917                                uint32_t *ref_div_p,
918                                uint32_t *post_div_p)
919 {
920         uint32_t min_ref_div = pll->min_ref_div;
921         uint32_t max_ref_div = pll->max_ref_div;
922         uint32_t min_post_div = pll->min_post_div;
923         uint32_t max_post_div = pll->max_post_div;
924         uint32_t min_fractional_feed_div = 0;
925         uint32_t max_fractional_feed_div = 0;
926         uint32_t best_vco = pll->best_vco;
927         uint32_t best_post_div = 1;
928         uint32_t best_ref_div = 1;
929         uint32_t best_feedback_div = 1;
930         uint32_t best_frac_feedback_div = 0;
931         uint32_t best_freq = -1;
932         uint32_t best_error = 0xffffffff;
933         uint32_t best_vco_diff = 1;
934         uint32_t post_div;
935         u32 pll_out_min, pll_out_max;
936
937         DRM_DEBUG_KMS("PLL freq %llu %u %u\n", freq, pll->min_ref_div, pll->max_ref_div);
938         freq = freq * 1000;
939
940         if (pll->flags & RADEON_PLL_IS_LCD) {
941                 pll_out_min = pll->lcd_pll_out_min;
942                 pll_out_max = pll->lcd_pll_out_max;
943         } else {
944                 pll_out_min = pll->pll_out_min;
945                 pll_out_max = pll->pll_out_max;
946         }
947
948         if (pll_out_min > 64800)
949                 pll_out_min = 64800;
950
951         if (pll->flags & RADEON_PLL_USE_REF_DIV)
952                 min_ref_div = max_ref_div = pll->reference_div;
953         else {
954                 while (min_ref_div < max_ref_div-1) {
955                         uint32_t mid = (min_ref_div + max_ref_div) / 2;
956                         uint32_t pll_in = pll->reference_freq / mid;
957                         if (pll_in < pll->pll_in_min)
958                                 max_ref_div = mid;
959                         else if (pll_in > pll->pll_in_max)
960                                 min_ref_div = mid;
961                         else
962                                 break;
963                 }
964         }
965
966         if (pll->flags & RADEON_PLL_USE_POST_DIV)
967                 min_post_div = max_post_div = pll->post_div;
968
969         if (pll->flags & RADEON_PLL_USE_FRAC_FB_DIV) {
970                 min_fractional_feed_div = pll->min_frac_feedback_div;
971                 max_fractional_feed_div = pll->max_frac_feedback_div;
972         }
973
974         for (post_div = max_post_div; post_div >= min_post_div; --post_div) {
975                 uint32_t ref_div;
976
977                 if ((pll->flags & RADEON_PLL_NO_ODD_POST_DIV) && (post_div & 1))
978                         continue;
979
980                 /* legacy radeons only have a few post_divs */
981                 if (pll->flags & RADEON_PLL_LEGACY) {
982                         if ((post_div == 5) ||
983                             (post_div == 7) ||
984                             (post_div == 9) ||
985                             (post_div == 10) ||
986                             (post_div == 11) ||
987                             (post_div == 13) ||
988                             (post_div == 14) ||
989                             (post_div == 15))
990                                 continue;
991                 }
992
993                 for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) {
994                         uint32_t feedback_div, current_freq = 0, error, vco_diff;
995                         uint32_t pll_in = pll->reference_freq / ref_div;
996                         uint32_t min_feed_div = pll->min_feedback_div;
997                         uint32_t max_feed_div = pll->max_feedback_div + 1;
998
999                         if (pll_in < pll->pll_in_min || pll_in > pll->pll_in_max)
1000                                 continue;
1001
1002                         while (min_feed_div < max_feed_div) {
1003                                 uint32_t vco;
1004                                 uint32_t min_frac_feed_div = min_fractional_feed_div;
1005                                 uint32_t max_frac_feed_div = max_fractional_feed_div + 1;
1006                                 uint32_t frac_feedback_div;
1007                                 uint64_t tmp;
1008
1009                                 feedback_div = (min_feed_div + max_feed_div) / 2;
1010
1011                                 tmp = (uint64_t)pll->reference_freq * feedback_div;
1012                                 vco = radeon_div(tmp, ref_div);
1013
1014                                 if (vco < pll_out_min) {
1015                                         min_feed_div = feedback_div + 1;
1016                                         continue;
1017                                 } else if (vco > pll_out_max) {
1018                                         max_feed_div = feedback_div;
1019                                         continue;
1020                                 }
1021
1022                                 while (min_frac_feed_div < max_frac_feed_div) {
1023                                         frac_feedback_div = (min_frac_feed_div + max_frac_feed_div) / 2;
1024                                         tmp = (uint64_t)pll->reference_freq * 10000 * feedback_div;
1025                                         tmp += (uint64_t)pll->reference_freq * 1000 * frac_feedback_div;
1026                                         current_freq = radeon_div(tmp, ref_div * post_div);
1027
1028                                         if (pll->flags & RADEON_PLL_PREFER_CLOSEST_LOWER) {
1029                                                 if (freq < current_freq)
1030                                                         error = 0xffffffff;
1031                                                 else
1032                                                         error = freq - current_freq;
1033                                         } else
1034                                                 error = abs(current_freq - freq);
1035                                         vco_diff = abs(vco - best_vco);
1036
1037                                         if ((best_vco == 0 && error < best_error) ||
1038                                             (best_vco != 0 &&
1039                                              ((best_error > 100 && error < best_error - 100) ||
1040                                               (abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
1041                                                 best_post_div = post_div;
1042                                                 best_ref_div = ref_div;
1043                                                 best_feedback_div = feedback_div;
1044                                                 best_frac_feedback_div = frac_feedback_div;
1045                                                 best_freq = current_freq;
1046                                                 best_error = error;
1047                                                 best_vco_diff = vco_diff;
1048                                         } else if (current_freq == freq) {
1049                                                 if (best_freq == -1) {
1050                                                         best_post_div = post_div;
1051                                                         best_ref_div = ref_div;
1052                                                         best_feedback_div = feedback_div;
1053                                                         best_frac_feedback_div = frac_feedback_div;
1054                                                         best_freq = current_freq;
1055                                                         best_error = error;
1056                                                         best_vco_diff = vco_diff;
1057                                                 } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
1058                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
1059                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
1060                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
1061                                                            ((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
1062                                                            ((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
1063                                                         best_post_div = post_div;
1064                                                         best_ref_div = ref_div;
1065                                                         best_feedback_div = feedback_div;
1066                                                         best_frac_feedback_div = frac_feedback_div;
1067                                                         best_freq = current_freq;
1068                                                         best_error = error;
1069                                                         best_vco_diff = vco_diff;
1070                                                 }
1071                                         }
1072                                         if (current_freq < freq)
1073                                                 min_frac_feed_div = frac_feedback_div + 1;
1074                                         else
1075                                                 max_frac_feed_div = frac_feedback_div;
1076                                 }
1077                                 if (current_freq < freq)
1078                                         min_feed_div = feedback_div + 1;
1079                                 else
1080                                         max_feed_div = feedback_div;
1081                         }
1082                 }
1083         }
1084
1085         *dot_clock_p = best_freq / 10000;
1086         *fb_div_p = best_feedback_div;
1087         *frac_fb_div_p = best_frac_feedback_div;
1088         *ref_div_p = best_ref_div;
1089         *post_div_p = best_post_div;
1090         DRM_DEBUG_KMS("%d %d, pll dividers - fb: %d.%d ref: %d, post %d\n",
1091                       freq, best_freq / 1000, best_feedback_div, best_frac_feedback_div,
1092                       best_ref_div, best_post_div);
1093
1094 }
1095
1096 static void radeon_user_framebuffer_destroy(struct drm_framebuffer *fb)
1097 {
1098         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1099
1100         if (radeon_fb->obj) {
1101                 drm_gem_object_unreference_unlocked(radeon_fb->obj);
1102         }
1103         drm_framebuffer_cleanup(fb);
1104         kfree(radeon_fb);
1105 }
1106
1107 static int radeon_user_framebuffer_create_handle(struct drm_framebuffer *fb,
1108                                                   struct drm_file *file_priv,
1109                                                   unsigned int *handle)
1110 {
1111         struct radeon_framebuffer *radeon_fb = to_radeon_framebuffer(fb);
1112
1113         return drm_gem_handle_create(file_priv, radeon_fb->obj, handle);
1114 }
1115
1116 static const struct drm_framebuffer_funcs radeon_fb_funcs = {
1117         .destroy = radeon_user_framebuffer_destroy,
1118         .create_handle = radeon_user_framebuffer_create_handle,
1119 };
1120
1121 void
1122 radeon_framebuffer_init(struct drm_device *dev,
1123                         struct radeon_framebuffer *rfb,
1124                         struct drm_mode_fb_cmd *mode_cmd,
1125                         struct drm_gem_object *obj)
1126 {
1127         rfb->obj = obj;
1128         drm_framebuffer_init(dev, &rfb->base, &radeon_fb_funcs);
1129         drm_helper_mode_fill_fb_struct(&rfb->base, mode_cmd);
1130 }
1131
1132 static struct drm_framebuffer *
1133 radeon_user_framebuffer_create(struct drm_device *dev,
1134                                struct drm_file *file_priv,
1135                                struct drm_mode_fb_cmd *mode_cmd)
1136 {
1137         struct drm_gem_object *obj;
1138         struct radeon_framebuffer *radeon_fb;
1139
1140         obj = drm_gem_object_lookup(dev, file_priv, mode_cmd->handle);
1141         if (obj ==  NULL) {
1142                 dev_err(&dev->pdev->dev, "No GEM object associated to handle 0x%08X, "
1143                         "can't create framebuffer\n", mode_cmd->handle);
1144                 return ERR_PTR(-ENOENT);
1145         }
1146
1147         radeon_fb = kzalloc(sizeof(*radeon_fb), GFP_KERNEL);
1148         if (radeon_fb == NULL)
1149                 return ERR_PTR(-ENOMEM);
1150
1151         radeon_framebuffer_init(dev, radeon_fb, mode_cmd, obj);
1152
1153         return &radeon_fb->base;
1154 }
1155
1156 static void radeon_output_poll_changed(struct drm_device *dev)
1157 {
1158         struct radeon_device *rdev = dev->dev_private;
1159         radeon_fb_output_poll_changed(rdev);
1160 }
1161
1162 static const struct drm_mode_config_funcs radeon_mode_funcs = {
1163         .fb_create = radeon_user_framebuffer_create,
1164         .output_poll_changed = radeon_output_poll_changed
1165 };
1166
1167 struct drm_prop_enum_list {
1168         int type;
1169         char *name;
1170 };
1171
1172 static struct drm_prop_enum_list radeon_tmds_pll_enum_list[] =
1173 {       { 0, "driver" },
1174         { 1, "bios" },
1175 };
1176
1177 static struct drm_prop_enum_list radeon_tv_std_enum_list[] =
1178 {       { TV_STD_NTSC, "ntsc" },
1179         { TV_STD_PAL, "pal" },
1180         { TV_STD_PAL_M, "pal-m" },
1181         { TV_STD_PAL_60, "pal-60" },
1182         { TV_STD_NTSC_J, "ntsc-j" },
1183         { TV_STD_SCART_PAL, "scart-pal" },
1184         { TV_STD_PAL_CN, "pal-cn" },
1185         { TV_STD_SECAM, "secam" },
1186 };
1187
1188 static struct drm_prop_enum_list radeon_underscan_enum_list[] =
1189 {       { UNDERSCAN_OFF, "off" },
1190         { UNDERSCAN_ON, "on" },
1191         { UNDERSCAN_AUTO, "auto" },
1192 };
1193
1194 static int radeon_modeset_create_props(struct radeon_device *rdev)
1195 {
1196         int i, sz;
1197
1198         if (rdev->is_atom_bios) {
1199                 rdev->mode_info.coherent_mode_property =
1200                         drm_property_create(rdev->ddev,
1201                                             DRM_MODE_PROP_RANGE,
1202                                             "coherent", 2);
1203                 if (!rdev->mode_info.coherent_mode_property)
1204                         return -ENOMEM;
1205
1206                 rdev->mode_info.coherent_mode_property->values[0] = 0;
1207                 rdev->mode_info.coherent_mode_property->values[1] = 1;
1208         }
1209
1210         if (!ASIC_IS_AVIVO(rdev)) {
1211                 sz = ARRAY_SIZE(radeon_tmds_pll_enum_list);
1212                 rdev->mode_info.tmds_pll_property =
1213                         drm_property_create(rdev->ddev,
1214                                             DRM_MODE_PROP_ENUM,
1215                                             "tmds_pll", sz);
1216                 for (i = 0; i < sz; i++) {
1217                         drm_property_add_enum(rdev->mode_info.tmds_pll_property,
1218                                               i,
1219                                               radeon_tmds_pll_enum_list[i].type,
1220                                               radeon_tmds_pll_enum_list[i].name);
1221                 }
1222         }
1223
1224         rdev->mode_info.load_detect_property =
1225                 drm_property_create(rdev->ddev,
1226                                     DRM_MODE_PROP_RANGE,
1227                                     "load detection", 2);
1228         if (!rdev->mode_info.load_detect_property)
1229                 return -ENOMEM;
1230         rdev->mode_info.load_detect_property->values[0] = 0;
1231         rdev->mode_info.load_detect_property->values[1] = 1;
1232
1233         drm_mode_create_scaling_mode_property(rdev->ddev);
1234
1235         sz = ARRAY_SIZE(radeon_tv_std_enum_list);
1236         rdev->mode_info.tv_std_property =
1237                 drm_property_create(rdev->ddev,
1238                                     DRM_MODE_PROP_ENUM,
1239                                     "tv standard", sz);
1240         for (i = 0; i < sz; i++) {
1241                 drm_property_add_enum(rdev->mode_info.tv_std_property,
1242                                       i,
1243                                       radeon_tv_std_enum_list[i].type,
1244                                       radeon_tv_std_enum_list[i].name);
1245         }
1246
1247         sz = ARRAY_SIZE(radeon_underscan_enum_list);
1248         rdev->mode_info.underscan_property =
1249                 drm_property_create(rdev->ddev,
1250                                     DRM_MODE_PROP_ENUM,
1251                                     "underscan", sz);
1252         for (i = 0; i < sz; i++) {
1253                 drm_property_add_enum(rdev->mode_info.underscan_property,
1254                                       i,
1255                                       radeon_underscan_enum_list[i].type,
1256                                       radeon_underscan_enum_list[i].name);
1257         }
1258
1259         rdev->mode_info.underscan_hborder_property =
1260                 drm_property_create(rdev->ddev,
1261                                         DRM_MODE_PROP_RANGE,
1262                                         "underscan hborder", 2);
1263         if (!rdev->mode_info.underscan_hborder_property)
1264                 return -ENOMEM;
1265         rdev->mode_info.underscan_hborder_property->values[0] = 0;
1266         rdev->mode_info.underscan_hborder_property->values[1] = 128;
1267
1268         rdev->mode_info.underscan_vborder_property =
1269                 drm_property_create(rdev->ddev,
1270                                         DRM_MODE_PROP_RANGE,
1271                                         "underscan vborder", 2);
1272         if (!rdev->mode_info.underscan_vborder_property)
1273                 return -ENOMEM;
1274         rdev->mode_info.underscan_vborder_property->values[0] = 0;
1275         rdev->mode_info.underscan_vborder_property->values[1] = 128;
1276
1277         return 0;
1278 }
1279
1280 void radeon_update_display_priority(struct radeon_device *rdev)
1281 {
1282         /* adjustment options for the display watermarks */
1283         if ((radeon_disp_priority == 0) || (radeon_disp_priority > 2)) {
1284                 /* set display priority to high for r3xx, rv515 chips
1285                  * this avoids flickering due to underflow to the
1286                  * display controllers during heavy acceleration.
1287                  * Don't force high on rs4xx igp chips as it seems to
1288                  * affect the sound card.  See kernel bug 15982.
1289                  */
1290                 if ((ASIC_IS_R300(rdev) || (rdev->family == CHIP_RV515)) &&
1291                     !(rdev->flags & RADEON_IS_IGP))
1292                         rdev->disp_priority = 2;
1293                 else
1294                         rdev->disp_priority = 0;
1295         } else
1296                 rdev->disp_priority = radeon_disp_priority;
1297
1298 }
1299
1300 int radeon_modeset_init(struct radeon_device *rdev)
1301 {
1302         int i;
1303         int ret;
1304
1305         drm_mode_config_init(rdev->ddev);
1306         rdev->mode_info.mode_config_initialized = true;
1307
1308         rdev->ddev->mode_config.funcs = (void *)&radeon_mode_funcs;
1309
1310         if (ASIC_IS_DCE5(rdev)) {
1311                 rdev->ddev->mode_config.max_width = 16384;
1312                 rdev->ddev->mode_config.max_height = 16384;
1313         } else if (ASIC_IS_AVIVO(rdev)) {
1314                 rdev->ddev->mode_config.max_width = 8192;
1315                 rdev->ddev->mode_config.max_height = 8192;
1316         } else {
1317                 rdev->ddev->mode_config.max_width = 4096;
1318                 rdev->ddev->mode_config.max_height = 4096;
1319         }
1320
1321         rdev->ddev->mode_config.fb_base = rdev->mc.aper_base;
1322
1323         ret = radeon_modeset_create_props(rdev);
1324         if (ret) {
1325                 return ret;
1326         }
1327
1328         /* init i2c buses */
1329         radeon_i2c_init(rdev);
1330
1331         /* check combios for a valid hardcoded EDID - Sun servers */
1332         if (!rdev->is_atom_bios) {
1333                 /* check for hardcoded EDID in BIOS */
1334                 radeon_combios_check_hardcoded_edid(rdev);
1335         }
1336
1337         /* allocate crtcs */
1338         for (i = 0; i < rdev->num_crtc; i++) {
1339                 radeon_crtc_init(rdev->ddev, i);
1340         }
1341
1342         /* okay we should have all the bios connectors */
1343         ret = radeon_setup_enc_conn(rdev->ddev);
1344         if (!ret) {
1345                 return ret;
1346         }
1347         /* initialize hpd */
1348         radeon_hpd_init(rdev);
1349
1350         /* Initialize power management */
1351         radeon_pm_init(rdev);
1352
1353         radeon_fbdev_init(rdev);
1354         drm_kms_helper_poll_init(rdev->ddev);
1355
1356         return 0;
1357 }
1358
1359 void radeon_modeset_fini(struct radeon_device *rdev)
1360 {
1361         radeon_fbdev_fini(rdev);
1362         kfree(rdev->mode_info.bios_hardcoded_edid);
1363         radeon_pm_fini(rdev);
1364
1365         if (rdev->mode_info.mode_config_initialized) {
1366                 drm_kms_helper_poll_fini(rdev->ddev);
1367                 radeon_hpd_fini(rdev);
1368                 drm_mode_config_cleanup(rdev->ddev);
1369                 rdev->mode_info.mode_config_initialized = false;
1370         }
1371         /* free i2c buses */
1372         radeon_i2c_fini(rdev);
1373 }
1374
1375 static bool is_hdtv_mode(struct drm_display_mode *mode)
1376 {
1377         /* try and guess if this is a tv or a monitor */
1378         if ((mode->vdisplay == 480 && mode->hdisplay == 720) || /* 480p */
1379             (mode->vdisplay == 576) || /* 576p */
1380             (mode->vdisplay == 720) || /* 720p */
1381             (mode->vdisplay == 1080)) /* 1080p */
1382                 return true;
1383         else
1384                 return false;
1385 }
1386
1387 bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
1388                                 struct drm_display_mode *mode,
1389                                 struct drm_display_mode *adjusted_mode)
1390 {
1391         struct drm_device *dev = crtc->dev;
1392         struct radeon_device *rdev = dev->dev_private;
1393         struct drm_encoder *encoder;
1394         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1395         struct radeon_encoder *radeon_encoder;
1396         struct drm_connector *connector;
1397         struct radeon_connector *radeon_connector;
1398         bool first = true;
1399         u32 src_v = 1, dst_v = 1;
1400         u32 src_h = 1, dst_h = 1;
1401
1402         radeon_crtc->h_border = 0;
1403         radeon_crtc->v_border = 0;
1404
1405         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1406                 if (encoder->crtc != crtc)
1407                         continue;
1408                 radeon_encoder = to_radeon_encoder(encoder);
1409                 connector = radeon_get_connector_for_encoder(encoder);
1410                 radeon_connector = to_radeon_connector(connector);
1411
1412                 if (first) {
1413                         /* set scaling */
1414                         if (radeon_encoder->rmx_type == RMX_OFF)
1415                                 radeon_crtc->rmx_type = RMX_OFF;
1416                         else if (mode->hdisplay < radeon_encoder->native_mode.hdisplay ||
1417                                  mode->vdisplay < radeon_encoder->native_mode.vdisplay)
1418                                 radeon_crtc->rmx_type = radeon_encoder->rmx_type;
1419                         else
1420                                 radeon_crtc->rmx_type = RMX_OFF;
1421                         /* copy native mode */
1422                         memcpy(&radeon_crtc->native_mode,
1423                                &radeon_encoder->native_mode,
1424                                 sizeof(struct drm_display_mode));
1425                         src_v = crtc->mode.vdisplay;
1426                         dst_v = radeon_crtc->native_mode.vdisplay;
1427                         src_h = crtc->mode.hdisplay;
1428                         dst_h = radeon_crtc->native_mode.hdisplay;
1429
1430                         /* fix up for overscan on hdmi */
1431                         if (ASIC_IS_AVIVO(rdev) &&
1432                             (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) &&
1433                             ((radeon_encoder->underscan_type == UNDERSCAN_ON) ||
1434                              ((radeon_encoder->underscan_type == UNDERSCAN_AUTO) &&
1435                               drm_detect_hdmi_monitor(radeon_connector->edid) &&
1436                               is_hdtv_mode(mode)))) {
1437                                 if (radeon_encoder->underscan_hborder != 0)
1438                                         radeon_crtc->h_border = radeon_encoder->underscan_hborder;
1439                                 else
1440                                         radeon_crtc->h_border = (mode->hdisplay >> 5) + 16;
1441                                 if (radeon_encoder->underscan_vborder != 0)
1442                                         radeon_crtc->v_border = radeon_encoder->underscan_vborder;
1443                                 else
1444                                         radeon_crtc->v_border = (mode->vdisplay >> 5) + 16;
1445                                 radeon_crtc->rmx_type = RMX_FULL;
1446                                 src_v = crtc->mode.vdisplay;
1447                                 dst_v = crtc->mode.vdisplay - (radeon_crtc->v_border * 2);
1448                                 src_h = crtc->mode.hdisplay;
1449                                 dst_h = crtc->mode.hdisplay - (radeon_crtc->h_border * 2);
1450                         }
1451                         first = false;
1452                 } else {
1453                         if (radeon_crtc->rmx_type != radeon_encoder->rmx_type) {
1454                                 /* WARNING: Right now this can't happen but
1455                                  * in the future we need to check that scaling
1456                                  * are consistent across different encoder
1457                                  * (ie all encoder can work with the same
1458                                  *  scaling).
1459                                  */
1460                                 DRM_ERROR("Scaling not consistent across encoder.\n");
1461                                 return false;
1462                         }
1463                 }
1464         }
1465         if (radeon_crtc->rmx_type != RMX_OFF) {
1466                 fixed20_12 a, b;
1467                 a.full = dfixed_const(src_v);
1468                 b.full = dfixed_const(dst_v);
1469                 radeon_crtc->vsc.full = dfixed_div(a, b);
1470                 a.full = dfixed_const(src_h);
1471                 b.full = dfixed_const(dst_h);
1472                 radeon_crtc->hsc.full = dfixed_div(a, b);
1473         } else {
1474                 radeon_crtc->vsc.full = dfixed_const(1);
1475                 radeon_crtc->hsc.full = dfixed_const(1);
1476         }
1477         return true;
1478 }
1479
1480 /*
1481  * Retrieve current video scanout position of crtc on a given gpu.
1482  *
1483  * \param dev Device to query.
1484  * \param crtc Crtc to query.
1485  * \param *vpos Location where vertical scanout position should be stored.
1486  * \param *hpos Location where horizontal scanout position should go.
1487  *
1488  * Returns vpos as a positive number while in active scanout area.
1489  * Returns vpos as a negative number inside vblank, counting the number
1490  * of scanlines to go until end of vblank, e.g., -1 means "one scanline
1491  * until start of active scanout / end of vblank."
1492  *
1493  * \return Flags, or'ed together as follows:
1494  *
1495  * DRM_SCANOUTPOS_VALID = Query successfull.
1496  * DRM_SCANOUTPOS_INVBL = Inside vblank.
1497  * DRM_SCANOUTPOS_ACCURATE = Returned position is accurate. A lack of
1498  * this flag means that returned position may be offset by a constant but
1499  * unknown small number of scanlines wrt. real scanout position.
1500  *
1501  */
1502 int radeon_get_crtc_scanoutpos(struct drm_device *dev, int crtc, int *vpos, int *hpos)
1503 {
1504         u32 stat_crtc = 0, vbl = 0, position = 0;
1505         int vbl_start, vbl_end, vtotal, ret = 0;
1506         bool in_vbl = true;
1507
1508         struct radeon_device *rdev = dev->dev_private;
1509
1510         if (ASIC_IS_DCE4(rdev)) {
1511                 if (crtc == 0) {
1512                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1513                                      EVERGREEN_CRTC0_REGISTER_OFFSET);
1514                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1515                                           EVERGREEN_CRTC0_REGISTER_OFFSET);
1516                         ret |= DRM_SCANOUTPOS_VALID;
1517                 }
1518                 if (crtc == 1) {
1519                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1520                                      EVERGREEN_CRTC1_REGISTER_OFFSET);
1521                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1522                                           EVERGREEN_CRTC1_REGISTER_OFFSET);
1523                         ret |= DRM_SCANOUTPOS_VALID;
1524                 }
1525                 if (crtc == 2) {
1526                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1527                                      EVERGREEN_CRTC2_REGISTER_OFFSET);
1528                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1529                                           EVERGREEN_CRTC2_REGISTER_OFFSET);
1530                         ret |= DRM_SCANOUTPOS_VALID;
1531                 }
1532                 if (crtc == 3) {
1533                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1534                                      EVERGREEN_CRTC3_REGISTER_OFFSET);
1535                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1536                                           EVERGREEN_CRTC3_REGISTER_OFFSET);
1537                         ret |= DRM_SCANOUTPOS_VALID;
1538                 }
1539                 if (crtc == 4) {
1540                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1541                                      EVERGREEN_CRTC4_REGISTER_OFFSET);
1542                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1543                                           EVERGREEN_CRTC4_REGISTER_OFFSET);
1544                         ret |= DRM_SCANOUTPOS_VALID;
1545                 }
1546                 if (crtc == 5) {
1547                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
1548                                      EVERGREEN_CRTC5_REGISTER_OFFSET);
1549                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
1550                                           EVERGREEN_CRTC5_REGISTER_OFFSET);
1551                         ret |= DRM_SCANOUTPOS_VALID;
1552                 }
1553         } else if (ASIC_IS_AVIVO(rdev)) {
1554                 if (crtc == 0) {
1555                         vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END);
1556                         position = RREG32(AVIVO_D1CRTC_STATUS_POSITION);
1557                         ret |= DRM_SCANOUTPOS_VALID;
1558                 }
1559                 if (crtc == 1) {
1560                         vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END);
1561                         position = RREG32(AVIVO_D2CRTC_STATUS_POSITION);
1562                         ret |= DRM_SCANOUTPOS_VALID;
1563                 }
1564         } else {
1565                 /* Pre-AVIVO: Different encoding of scanout pos and vblank interval. */
1566                 if (crtc == 0) {
1567                         /* Assume vbl_end == 0, get vbl_start from
1568                          * upper 16 bits.
1569                          */
1570                         vbl = (RREG32(RADEON_CRTC_V_TOTAL_DISP) &
1571                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1572                         /* Only retrieve vpos from upper 16 bits, set hpos == 0. */
1573                         position = (RREG32(RADEON_CRTC_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1574                         stat_crtc = RREG32(RADEON_CRTC_STATUS);
1575                         if (!(stat_crtc & 1))
1576                                 in_vbl = false;
1577
1578                         ret |= DRM_SCANOUTPOS_VALID;
1579                 }
1580                 if (crtc == 1) {
1581                         vbl = (RREG32(RADEON_CRTC2_V_TOTAL_DISP) &
1582                                 RADEON_CRTC_V_DISP) >> RADEON_CRTC_V_DISP_SHIFT;
1583                         position = (RREG32(RADEON_CRTC2_VLINE_CRNT_VLINE) >> 16) & RADEON_CRTC_V_TOTAL;
1584                         stat_crtc = RREG32(RADEON_CRTC2_STATUS);
1585                         if (!(stat_crtc & 1))
1586                                 in_vbl = false;
1587
1588                         ret |= DRM_SCANOUTPOS_VALID;
1589                 }
1590         }
1591
1592         /* Decode into vertical and horizontal scanout position. */
1593         *vpos = position & 0x1fff;
1594         *hpos = (position >> 16) & 0x1fff;
1595
1596         /* Valid vblank area boundaries from gpu retrieved? */
1597         if (vbl > 0) {
1598                 /* Yes: Decode. */
1599                 ret |= DRM_SCANOUTPOS_ACCURATE;
1600                 vbl_start = vbl & 0x1fff;
1601                 vbl_end = (vbl >> 16) & 0x1fff;
1602         }
1603         else {
1604                 /* No: Fake something reasonable which gives at least ok results. */
1605                 vbl_start = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vdisplay;
1606                 vbl_end = 0;
1607         }
1608
1609         /* Test scanout position against vblank region. */
1610         if ((*vpos < vbl_start) && (*vpos >= vbl_end))
1611                 in_vbl = false;
1612
1613         /* Check if inside vblank area and apply corrective offsets:
1614          * vpos will then be >=0 in video scanout area, but negative
1615          * within vblank area, counting down the number of lines until
1616          * start of scanout.
1617          */
1618
1619         /* Inside "upper part" of vblank area? Apply corrective offset if so: */
1620         if (in_vbl && (*vpos >= vbl_start)) {
1621                 vtotal = rdev->mode_info.crtcs[crtc]->base.hwmode.crtc_vtotal;
1622                 *vpos = *vpos - vtotal;
1623         }
1624
1625         /* Correct for shifted end of vbl at vbl_end. */
1626         *vpos = *vpos - vbl_end;
1627
1628         /* In vblank? */
1629         if (in_vbl)
1630                 ret |= DRM_SCANOUTPOS_INVBL;
1631
1632         return ret;
1633 }