f78db5c8008cd42810e477b9b20f015492010087
[linux-2.6.git] / drivers / gpu / drm / radeon / radeon_device.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/console.h>
29 #include <drm/drmP.h>
30 #include <drm/drm_crtc_helper.h>
31 #include <drm/radeon_drm.h>
32 #include "radeon_reg.h"
33 #include "radeon.h"
34 #include "radeon_asic.h"
35 #include "atom.h"
36
37 /*
38  * Clear GPU surface registers.
39  */
40 static void radeon_surface_init(struct radeon_device *rdev)
41 {
42         /* FIXME: check this out */
43         if (rdev->family < CHIP_R600) {
44                 int i;
45
46                 for (i = 0; i < 8; i++) {
47                         WREG32(RADEON_SURFACE0_INFO +
48                                i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO),
49                                0);
50                 }
51                 /* enable surfaces */
52                 WREG32(RADEON_SURFACE_CNTL, 0);
53         }
54 }
55
56 /*
57  * GPU scratch registers helpers function.
58  */
59 static void radeon_scratch_init(struct radeon_device *rdev)
60 {
61         int i;
62
63         /* FIXME: check this out */
64         if (rdev->family < CHIP_R300) {
65                 rdev->scratch.num_reg = 5;
66         } else {
67                 rdev->scratch.num_reg = 7;
68         }
69         for (i = 0; i < rdev->scratch.num_reg; i++) {
70                 rdev->scratch.free[i] = true;
71                 rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
72         }
73 }
74
75 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
76 {
77         int i;
78
79         for (i = 0; i < rdev->scratch.num_reg; i++) {
80                 if (rdev->scratch.free[i]) {
81                         rdev->scratch.free[i] = false;
82                         *reg = rdev->scratch.reg[i];
83                         return 0;
84                 }
85         }
86         return -EINVAL;
87 }
88
89 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
90 {
91         int i;
92
93         for (i = 0; i < rdev->scratch.num_reg; i++) {
94                 if (rdev->scratch.reg[i] == reg) {
95                         rdev->scratch.free[i] = true;
96                         return;
97                 }
98         }
99 }
100
101 /*
102  * MC common functions
103  */
104 int radeon_mc_setup(struct radeon_device *rdev)
105 {
106         uint32_t tmp;
107
108         /* Some chips have an "issue" with the memory controller, the
109          * location must be aligned to the size. We just align it down,
110          * too bad if we walk over the top of system memory, we don't
111          * use DMA without a remapped anyway.
112          * Affected chips are rv280, all r3xx, and all r4xx, but not IGP
113          */
114         /* FGLRX seems to setup like this, VRAM a 0, then GART.
115          */
116         /*
117          * Note: from R6xx the address space is 40bits but here we only
118          * use 32bits (still have to see a card which would exhaust 4G
119          * address space).
120          */
121         if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
122                 /* vram location was already setup try to put gtt after
123                  * if it fits */
124                 tmp = rdev->mc.vram_location + rdev->mc.vram_size;
125                 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
126                 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
127                         rdev->mc.gtt_location = tmp;
128                 } else {
129                         if (rdev->mc.gtt_size >= rdev->mc.vram_location) {
130                                 printk(KERN_ERR "[drm] GTT too big to fit "
131                                        "before or after vram location.\n");
132                                 return -EINVAL;
133                         }
134                         rdev->mc.gtt_location = 0;
135                 }
136         } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
137                 /* gtt location was already setup try to put vram before
138                  * if it fits */
139                 if (rdev->mc.vram_size < rdev->mc.gtt_location) {
140                         rdev->mc.vram_location = 0;
141                 } else {
142                         tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
143                         tmp += (rdev->mc.vram_size - 1);
144                         tmp &= ~(rdev->mc.vram_size - 1);
145                         if ((0xFFFFFFFFUL - tmp) >= rdev->mc.vram_size) {
146                                 rdev->mc.vram_location = tmp;
147                         } else {
148                                 printk(KERN_ERR "[drm] vram too big to fit "
149                                        "before or after GTT location.\n");
150                                 return -EINVAL;
151                         }
152                 }
153         } else {
154                 rdev->mc.vram_location = 0;
155                 rdev->mc.gtt_location = rdev->mc.vram_size;
156         }
157         DRM_INFO("radeon: VRAM %uM\n", rdev->mc.vram_size >> 20);
158         DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
159                  rdev->mc.vram_location,
160                  rdev->mc.vram_location + rdev->mc.vram_size - 1);
161         DRM_INFO("radeon: GTT %uM\n", rdev->mc.gtt_size >> 20);
162         DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
163                  rdev->mc.gtt_location,
164                  rdev->mc.gtt_location + rdev->mc.gtt_size - 1);
165         return 0;
166 }
167
168
169 /*
170  * GPU helpers function.
171  */
172 static bool radeon_card_posted(struct radeon_device *rdev)
173 {
174         uint32_t reg;
175
176         /* first check CRTCs */
177         if (ASIC_IS_AVIVO(rdev)) {
178                 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
179                       RREG32(AVIVO_D2CRTC_CONTROL);
180                 if (reg & AVIVO_CRTC_EN) {
181                         return true;
182                 }
183         } else {
184                 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
185                       RREG32(RADEON_CRTC2_GEN_CNTL);
186                 if (reg & RADEON_CRTC_EN) {
187                         return true;
188                 }
189         }
190
191         /* then check MEM_SIZE, in case the crtcs are off */
192         if (rdev->family >= CHIP_R600)
193                 reg = RREG32(R600_CONFIG_MEMSIZE);
194         else
195                 reg = RREG32(RADEON_CONFIG_MEMSIZE);
196
197         if (reg)
198                 return true;
199
200         return false;
201
202 }
203
204
205 /*
206  * Registers accessors functions.
207  */
208 uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
209 {
210         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
211         BUG_ON(1);
212         return 0;
213 }
214
215 void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
216 {
217         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
218                   reg, v);
219         BUG_ON(1);
220 }
221
222 void radeon_register_accessor_init(struct radeon_device *rdev)
223 {
224         rdev->mm_rreg = &r100_mm_rreg;
225         rdev->mm_wreg = &r100_mm_wreg;
226         rdev->mc_rreg = &radeon_invalid_rreg;
227         rdev->mc_wreg = &radeon_invalid_wreg;
228         rdev->pll_rreg = &radeon_invalid_rreg;
229         rdev->pll_wreg = &radeon_invalid_wreg;
230         rdev->pcie_rreg = &radeon_invalid_rreg;
231         rdev->pcie_wreg = &radeon_invalid_wreg;
232         rdev->pciep_rreg = &radeon_invalid_rreg;
233         rdev->pciep_wreg = &radeon_invalid_wreg;
234
235         /* Don't change order as we are overridding accessor. */
236         if (rdev->family < CHIP_RV515) {
237                 rdev->pcie_rreg = &rv370_pcie_rreg;
238                 rdev->pcie_wreg = &rv370_pcie_wreg;
239         }
240         if (rdev->family >= CHIP_RV515) {
241                 rdev->pcie_rreg = &rv515_pcie_rreg;
242                 rdev->pcie_wreg = &rv515_pcie_wreg;
243         }
244         /* FIXME: not sure here */
245         if (rdev->family <= CHIP_R580) {
246                 rdev->pll_rreg = &r100_pll_rreg;
247                 rdev->pll_wreg = &r100_pll_wreg;
248         }
249         if (rdev->family >= CHIP_RV515) {
250                 rdev->mc_rreg = &rv515_mc_rreg;
251                 rdev->mc_wreg = &rv515_mc_wreg;
252         }
253         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
254                 rdev->mc_rreg = &rs400_mc_rreg;
255                 rdev->mc_wreg = &rs400_mc_wreg;
256         }
257         if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
258                 rdev->mc_rreg = &rs690_mc_rreg;
259                 rdev->mc_wreg = &rs690_mc_wreg;
260         }
261         if (rdev->family == CHIP_RS600) {
262                 rdev->mc_rreg = &rs600_mc_rreg;
263                 rdev->mc_wreg = &rs600_mc_wreg;
264         }
265         if (rdev->family >= CHIP_R600) {
266                 rdev->pciep_rreg = &r600_pciep_rreg;
267                 rdev->pciep_wreg = &r600_pciep_wreg;
268         }
269 }
270
271
272 /*
273  * ASIC
274  */
275 int radeon_asic_init(struct radeon_device *rdev)
276 {
277         radeon_register_accessor_init(rdev);
278         switch (rdev->family) {
279         case CHIP_R100:
280         case CHIP_RV100:
281         case CHIP_RS100:
282         case CHIP_RV200:
283         case CHIP_RS200:
284         case CHIP_R200:
285         case CHIP_RV250:
286         case CHIP_RS300:
287         case CHIP_RV280:
288                 rdev->asic = &r100_asic;
289                 break;
290         case CHIP_R300:
291         case CHIP_R350:
292         case CHIP_RV350:
293         case CHIP_RV380:
294                 rdev->asic = &r300_asic;
295                 break;
296         case CHIP_R420:
297         case CHIP_R423:
298         case CHIP_RV410:
299                 rdev->asic = &r420_asic;
300                 break;
301         case CHIP_RS400:
302         case CHIP_RS480:
303                 rdev->asic = &rs400_asic;
304                 break;
305         case CHIP_RS600:
306                 rdev->asic = &rs600_asic;
307                 break;
308         case CHIP_RS690:
309         case CHIP_RS740:
310                 rdev->asic = &rs690_asic;
311                 break;
312         case CHIP_RV515:
313                 rdev->asic = &rv515_asic;
314                 break;
315         case CHIP_R520:
316         case CHIP_RV530:
317         case CHIP_RV560:
318         case CHIP_RV570:
319         case CHIP_R580:
320                 rdev->asic = &r520_asic;
321                 break;
322         case CHIP_R600:
323         case CHIP_RV610:
324         case CHIP_RV630:
325         case CHIP_RV620:
326         case CHIP_RV635:
327         case CHIP_RV670:
328         case CHIP_RS780:
329         case CHIP_RV770:
330         case CHIP_RV730:
331         case CHIP_RV710:
332         default:
333                 /* FIXME: not supported yet */
334                 return -EINVAL;
335         }
336         return 0;
337 }
338
339
340 /*
341  * Wrapper around modesetting bits.
342  */
343 int radeon_clocks_init(struct radeon_device *rdev)
344 {
345         int r;
346
347         radeon_get_clock_info(rdev->ddev);
348         r = radeon_static_clocks_init(rdev->ddev);
349         if (r) {
350                 return r;
351         }
352         DRM_INFO("Clocks initialized !\n");
353         return 0;
354 }
355
356 void radeon_clocks_fini(struct radeon_device *rdev)
357 {
358 }
359
360 /* ATOM accessor methods */
361 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
362 {
363         struct radeon_device *rdev = info->dev->dev_private;
364         uint32_t r;
365
366         r = rdev->pll_rreg(rdev, reg);
367         return r;
368 }
369
370 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
371 {
372         struct radeon_device *rdev = info->dev->dev_private;
373
374         rdev->pll_wreg(rdev, reg, val);
375 }
376
377 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
378 {
379         struct radeon_device *rdev = info->dev->dev_private;
380         uint32_t r;
381
382         r = rdev->mc_rreg(rdev, reg);
383         return r;
384 }
385
386 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
387 {
388         struct radeon_device *rdev = info->dev->dev_private;
389
390         rdev->mc_wreg(rdev, reg, val);
391 }
392
393 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
394 {
395         struct radeon_device *rdev = info->dev->dev_private;
396
397         WREG32(reg*4, val);
398 }
399
400 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
401 {
402         struct radeon_device *rdev = info->dev->dev_private;
403         uint32_t r;
404
405         r = RREG32(reg*4);
406         return r;
407 }
408
409 static struct card_info atom_card_info = {
410         .dev = NULL,
411         .reg_read = cail_reg_read,
412         .reg_write = cail_reg_write,
413         .mc_read = cail_mc_read,
414         .mc_write = cail_mc_write,
415         .pll_read = cail_pll_read,
416         .pll_write = cail_pll_write,
417 };
418
419 int radeon_atombios_init(struct radeon_device *rdev)
420 {
421         atom_card_info.dev = rdev->ddev;
422         rdev->mode_info.atom_context = atom_parse(&atom_card_info, rdev->bios);
423         radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
424         return 0;
425 }
426
427 void radeon_atombios_fini(struct radeon_device *rdev)
428 {
429         kfree(rdev->mode_info.atom_context);
430 }
431
432 int radeon_combios_init(struct radeon_device *rdev)
433 {
434         radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
435         return 0;
436 }
437
438 void radeon_combios_fini(struct radeon_device *rdev)
439 {
440 }
441
442 int radeon_modeset_init(struct radeon_device *rdev);
443 void radeon_modeset_fini(struct radeon_device *rdev);
444
445
446 /*
447  * Radeon device.
448  */
449 int radeon_device_init(struct radeon_device *rdev,
450                        struct drm_device *ddev,
451                        struct pci_dev *pdev,
452                        uint32_t flags)
453 {
454         int r, ret;
455         int dma_bits;
456
457         DRM_INFO("radeon: Initializing kernel modesetting.\n");
458         rdev->shutdown = false;
459         rdev->ddev = ddev;
460         rdev->pdev = pdev;
461         rdev->flags = flags;
462         rdev->family = flags & RADEON_FAMILY_MASK;
463         rdev->is_atom_bios = false;
464         rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
465         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
466         rdev->gpu_lockup = false;
467         /* mutex initialization are all done here so we
468          * can recall function without having locking issues */
469         mutex_init(&rdev->cs_mutex);
470         mutex_init(&rdev->ib_pool.mutex);
471         mutex_init(&rdev->cp.mutex);
472         rwlock_init(&rdev->fence_drv.lock);
473
474         if (radeon_agpmode == -1) {
475                 rdev->flags &= ~RADEON_IS_AGP;
476                 if (rdev->family > CHIP_RV515 ||
477                     rdev->family == CHIP_RV380 ||
478                     rdev->family == CHIP_RV410 ||
479                     rdev->family == CHIP_R423) {
480                         DRM_INFO("Forcing AGP to PCIE mode\n");
481                         rdev->flags |= RADEON_IS_PCIE;
482                 } else {
483                         DRM_INFO("Forcing AGP to PCI mode\n");
484                         rdev->flags |= RADEON_IS_PCI;
485                 }
486         }
487
488         /* Set asic functions */
489         r = radeon_asic_init(rdev);
490         if (r) {
491                 return r;
492         }
493         r = radeon_init(rdev);
494         if (r) {
495                 return r;
496         }
497
498         /* set DMA mask + need_dma32 flags.
499          * PCIE - can handle 40-bits.
500          * IGP - can handle 40-bits (in theory)
501          * AGP - generally dma32 is safest
502          * PCI - only dma32
503          */
504         rdev->need_dma32 = false;
505         if (rdev->flags & RADEON_IS_AGP)
506                 rdev->need_dma32 = true;
507         if (rdev->flags & RADEON_IS_PCI)
508                 rdev->need_dma32 = true;
509
510         dma_bits = rdev->need_dma32 ? 32 : 40;
511         r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
512         if (r) {
513                 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
514         }
515
516         /* Registers mapping */
517         /* TODO: block userspace mapping of io register */
518         rdev->rmmio_base = drm_get_resource_start(rdev->ddev, 2);
519         rdev->rmmio_size = drm_get_resource_len(rdev->ddev, 2);
520         rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
521         if (rdev->rmmio == NULL) {
522                 return -ENOMEM;
523         }
524         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
525         DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
526
527         /* Setup errata flags */
528         radeon_errata(rdev);
529         /* Initialize scratch registers */
530         radeon_scratch_init(rdev);
531         /* Initialize surface registers */
532         radeon_surface_init(rdev);
533
534         /* TODO: disable VGA need to use VGA request */
535         /* BIOS*/
536         if (!radeon_get_bios(rdev)) {
537                 if (ASIC_IS_AVIVO(rdev))
538                         return -EINVAL;
539         }
540         if (rdev->is_atom_bios) {
541                 r = radeon_atombios_init(rdev);
542                 if (r) {
543                         return r;
544                 }
545         } else {
546                 r = radeon_combios_init(rdev);
547                 if (r) {
548                         return r;
549                 }
550         }
551         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
552         if (radeon_gpu_reset(rdev)) {
553                 /* FIXME: what do we want to do here ? */
554         }
555         /* check if cards are posted or not */
556         if (!radeon_card_posted(rdev) && rdev->bios) {
557                 DRM_INFO("GPU not posted. posting now...\n");
558                 if (rdev->is_atom_bios) {
559                         atom_asic_init(rdev->mode_info.atom_context);
560                 } else {
561                         radeon_combios_asic_init(rdev->ddev);
562                 }
563         }
564         /* Initialize clocks */
565         r = radeon_clocks_init(rdev);
566         if (r) {
567                 return r;
568         }
569         /* Get vram informations */
570         radeon_vram_info(rdev);
571
572         /* Add an MTRR for the VRAM */
573         rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
574                                       MTRR_TYPE_WRCOMB, 1);
575         DRM_INFO("Detected VRAM RAM=%uM, BAR=%uM\n",
576                  rdev->mc.vram_size >> 20,
577                  (unsigned)rdev->mc.aper_size >> 20);
578         DRM_INFO("RAM width %dbits %cDR\n",
579                  rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
580         /* Initialize memory controller (also test AGP) */
581         r = radeon_mc_init(rdev);
582         if (r) {
583                 return r;
584         }
585         /* Fence driver */
586         r = radeon_fence_driver_init(rdev);
587         if (r) {
588                 return r;
589         }
590         r = radeon_irq_kms_init(rdev);
591         if (r) {
592                 return r;
593         }
594         /* Memory manager */
595         r = radeon_object_init(rdev);
596         if (r) {
597                 return r;
598         }
599         /* Initialize GART (initialize after TTM so we can allocate
600          * memory through TTM but finalize after TTM) */
601         r = radeon_gart_enable(rdev);
602         if (!r) {
603                 r = radeon_gem_init(rdev);
604         }
605
606         /* 1M ring buffer */
607         if (!r) {
608                 r = radeon_cp_init(rdev, 1024 * 1024);
609         }
610         if (!r) {
611                 r = radeon_wb_init(rdev);
612                 if (r) {
613                         DRM_ERROR("radeon: failled initializing WB (%d).\n", r);
614                         return r;
615                 }
616         }
617         if (!r) {
618                 r = radeon_ib_pool_init(rdev);
619                 if (r) {
620                         DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
621                         return r;
622                 }
623         }
624         if (!r) {
625                 r = radeon_ib_test(rdev);
626                 if (r) {
627                         DRM_ERROR("radeon: failled testing IB (%d).\n", r);
628                         return r;
629                 }
630         }
631         ret = r;
632         r = radeon_modeset_init(rdev);
633         if (r) {
634                 return r;
635         }
636         if (!ret) {
637                 DRM_INFO("radeon: kernel modesetting successfully initialized.\n");
638         }
639         if (radeon_benchmarking) {
640                 radeon_benchmark(rdev);
641         }
642         return ret;
643 }
644
645 void radeon_device_fini(struct radeon_device *rdev)
646 {
647         if (rdev == NULL || rdev->rmmio == NULL) {
648                 return;
649         }
650         DRM_INFO("radeon: finishing device.\n");
651         rdev->shutdown = true;
652         /* Order matter so becarefull if you rearrange anythings */
653         radeon_modeset_fini(rdev);
654         radeon_ib_pool_fini(rdev);
655         radeon_cp_fini(rdev);
656         radeon_wb_fini(rdev);
657         radeon_gem_fini(rdev);
658         radeon_object_fini(rdev);
659         /* mc_fini must be after object_fini */
660         radeon_mc_fini(rdev);
661 #if __OS_HAS_AGP
662         radeon_agp_fini(rdev);
663 #endif
664         radeon_irq_kms_fini(rdev);
665         radeon_fence_driver_fini(rdev);
666         radeon_clocks_fini(rdev);
667         if (rdev->is_atom_bios) {
668                 radeon_atombios_fini(rdev);
669         } else {
670                 radeon_combios_fini(rdev);
671         }
672         kfree(rdev->bios);
673         rdev->bios = NULL;
674         iounmap(rdev->rmmio);
675         rdev->rmmio = NULL;
676 }
677
678
679 /*
680  * Suspend & resume.
681  */
682 int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
683 {
684         struct radeon_device *rdev = dev->dev_private;
685         struct drm_crtc *crtc;
686
687         if (dev == NULL || rdev == NULL) {
688                 return -ENODEV;
689         }
690         if (state.event == PM_EVENT_PRETHAW) {
691                 return 0;
692         }
693         /* unpin the front buffers */
694         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
695                 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
696                 struct radeon_object *robj;
697
698                 if (rfb == NULL || rfb->obj == NULL) {
699                         continue;
700                 }
701                 robj = rfb->obj->driver_private;
702                 if (robj != rdev->fbdev_robj) {
703                         radeon_object_unpin(robj);
704                 }
705         }
706         /* evict vram memory */
707         radeon_object_evict_vram(rdev);
708         /* wait for gpu to finish processing current batch */
709         radeon_fence_wait_last(rdev);
710
711         radeon_cp_disable(rdev);
712         radeon_gart_disable(rdev);
713
714         /* evict remaining vram memory */
715         radeon_object_evict_vram(rdev);
716
717         rdev->irq.sw_int = false;
718         radeon_irq_set(rdev);
719
720         pci_save_state(dev->pdev);
721         if (state.event == PM_EVENT_SUSPEND) {
722                 /* Shut down the device */
723                 pci_disable_device(dev->pdev);
724                 pci_set_power_state(dev->pdev, PCI_D3hot);
725         }
726         acquire_console_sem();
727         fb_set_suspend(rdev->fbdev_info, 1);
728         release_console_sem();
729         return 0;
730 }
731
732 int radeon_resume_kms(struct drm_device *dev)
733 {
734         struct radeon_device *rdev = dev->dev_private;
735         int r;
736
737         acquire_console_sem();
738         pci_set_power_state(dev->pdev, PCI_D0);
739         pci_restore_state(dev->pdev);
740         if (pci_enable_device(dev->pdev)) {
741                 release_console_sem();
742                 return -1;
743         }
744         pci_set_master(dev->pdev);
745         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
746         if (radeon_gpu_reset(rdev)) {
747                 /* FIXME: what do we want to do here ? */
748         }
749         /* post card */
750         if (rdev->is_atom_bios) {
751                 atom_asic_init(rdev->mode_info.atom_context);
752         } else {
753                 radeon_combios_asic_init(rdev->ddev);
754         }
755         /* Initialize clocks */
756         r = radeon_clocks_init(rdev);
757         if (r) {
758                 release_console_sem();
759                 return r;
760         }
761         /* Enable IRQ */
762         rdev->irq.sw_int = true;
763         radeon_irq_set(rdev);
764         /* Initialize GPU Memory Controller */
765         r = radeon_mc_init(rdev);
766         if (r) {
767                 goto out;
768         }
769         r = radeon_gart_enable(rdev);
770         if (r) {
771                 goto out;
772         }
773         r = radeon_cp_init(rdev, rdev->cp.ring_size);
774         if (r) {
775                 goto out;
776         }
777 out:
778         fb_set_suspend(rdev->fbdev_info, 0);
779         release_console_sem();
780
781         /* blat the mode back in */
782         drm_helper_resume_force_mode(dev);
783         return 0;
784 }
785
786
787 /*
788  * Debugfs
789  */
790 struct radeon_debugfs {
791         struct drm_info_list    *files;
792         unsigned                num_files;
793 };
794 static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES];
795 static unsigned _radeon_debugfs_count = 0;
796
797 int radeon_debugfs_add_files(struct radeon_device *rdev,
798                              struct drm_info_list *files,
799                              unsigned nfiles)
800 {
801         unsigned i;
802
803         for (i = 0; i < _radeon_debugfs_count; i++) {
804                 if (_radeon_debugfs[i].files == files) {
805                         /* Already registered */
806                         return 0;
807                 }
808         }
809         if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) {
810                 DRM_ERROR("Reached maximum number of debugfs files.\n");
811                 DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
812                 return -EINVAL;
813         }
814         _radeon_debugfs[_radeon_debugfs_count].files = files;
815         _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles;
816         _radeon_debugfs_count++;
817 #if defined(CONFIG_DEBUG_FS)
818         drm_debugfs_create_files(files, nfiles,
819                                  rdev->ddev->control->debugfs_root,
820                                  rdev->ddev->control);
821         drm_debugfs_create_files(files, nfiles,
822                                  rdev->ddev->primary->debugfs_root,
823                                  rdev->ddev->primary);
824 #endif
825         return 0;
826 }
827
828 #if defined(CONFIG_DEBUG_FS)
829 int radeon_debugfs_init(struct drm_minor *minor)
830 {
831         return 0;
832 }
833
834 void radeon_debugfs_cleanup(struct drm_minor *minor)
835 {
836         unsigned i;
837
838         for (i = 0; i < _radeon_debugfs_count; i++) {
839                 drm_debugfs_remove_files(_radeon_debugfs[i].files,
840                                          _radeon_debugfs[i].num_files, minor);
841         }
842 }
843 #endif