drm/radeon: command stream checker for r3xx-r5xx hardware
[linux-2.6.git] / drivers / gpu / drm / radeon / radeon_device.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/console.h>
29 #include <drm/drmP.h>
30 #include <drm/drm_crtc_helper.h>
31 #include <drm/radeon_drm.h>
32 #include "radeon_reg.h"
33 #include "radeon.h"
34 #include "radeon_asic.h"
35 #include "atom.h"
36
37 /*
38  * GPU scratch registers helpers function.
39  */
40 static void radeon_scratch_init(struct radeon_device *rdev)
41 {
42         int i;
43
44         /* FIXME: check this out */
45         if (rdev->family < CHIP_R300) {
46                 rdev->scratch.num_reg = 5;
47         } else {
48                 rdev->scratch.num_reg = 7;
49         }
50         for (i = 0; i < rdev->scratch.num_reg; i++) {
51                 rdev->scratch.free[i] = true;
52                 rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4);
53         }
54 }
55
56 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
57 {
58         int i;
59
60         for (i = 0; i < rdev->scratch.num_reg; i++) {
61                 if (rdev->scratch.free[i]) {
62                         rdev->scratch.free[i] = false;
63                         *reg = rdev->scratch.reg[i];
64                         return 0;
65                 }
66         }
67         return -EINVAL;
68 }
69
70 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
71 {
72         int i;
73
74         for (i = 0; i < rdev->scratch.num_reg; i++) {
75                 if (rdev->scratch.reg[i] == reg) {
76                         rdev->scratch.free[i] = true;
77                         return;
78                 }
79         }
80 }
81
82 /*
83  * MC common functions
84  */
85 int radeon_mc_setup(struct radeon_device *rdev)
86 {
87         uint32_t tmp;
88
89         /* Some chips have an "issue" with the memory controller, the
90          * location must be aligned to the size. We just align it down,
91          * too bad if we walk over the top of system memory, we don't
92          * use DMA without a remapped anyway.
93          * Affected chips are rv280, all r3xx, and all r4xx, but not IGP
94          */
95         /* FGLRX seems to setup like this, VRAM a 0, then GART.
96          */
97         /*
98          * Note: from R6xx the address space is 40bits but here we only
99          * use 32bits (still have to see a card which would exhaust 4G
100          * address space).
101          */
102         if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
103                 /* vram location was already setup try to put gtt after
104                  * if it fits */
105                 tmp = rdev->mc.vram_location + rdev->mc.vram_size;
106                 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
107                 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
108                         rdev->mc.gtt_location = tmp;
109                 } else {
110                         if (rdev->mc.gtt_size >= rdev->mc.vram_location) {
111                                 printk(KERN_ERR "[drm] GTT too big to fit "
112                                        "before or after vram location.\n");
113                                 return -EINVAL;
114                         }
115                         rdev->mc.gtt_location = 0;
116                 }
117         } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
118                 /* gtt location was already setup try to put vram before
119                  * if it fits */
120                 if (rdev->mc.vram_size < rdev->mc.gtt_location) {
121                         rdev->mc.vram_location = 0;
122                 } else {
123                         tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
124                         tmp += (rdev->mc.vram_size - 1);
125                         tmp &= ~(rdev->mc.vram_size - 1);
126                         if ((0xFFFFFFFFUL - tmp) >= rdev->mc.vram_size) {
127                                 rdev->mc.vram_location = tmp;
128                         } else {
129                                 printk(KERN_ERR "[drm] vram too big to fit "
130                                        "before or after GTT location.\n");
131                                 return -EINVAL;
132                         }
133                 }
134         } else {
135                 rdev->mc.vram_location = 0;
136                 rdev->mc.gtt_location = rdev->mc.vram_size;
137         }
138         DRM_INFO("radeon: VRAM %uM\n", rdev->mc.vram_size >> 20);
139         DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
140                  rdev->mc.vram_location,
141                  rdev->mc.vram_location + rdev->mc.vram_size - 1);
142         DRM_INFO("radeon: GTT %uM\n", rdev->mc.gtt_size >> 20);
143         DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
144                  rdev->mc.gtt_location,
145                  rdev->mc.gtt_location + rdev->mc.gtt_size - 1);
146         return 0;
147 }
148
149
150 /*
151  * GPU helpers function.
152  */
153 static bool radeon_card_posted(struct radeon_device *rdev)
154 {
155         uint32_t reg;
156
157         /* first check CRTCs */
158         if (ASIC_IS_AVIVO(rdev)) {
159                 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
160                       RREG32(AVIVO_D2CRTC_CONTROL);
161                 if (reg & AVIVO_CRTC_EN) {
162                         return true;
163                 }
164         } else {
165                 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
166                       RREG32(RADEON_CRTC2_GEN_CNTL);
167                 if (reg & RADEON_CRTC_EN) {
168                         return true;
169                 }
170         }
171
172         /* then check MEM_SIZE, in case the crtcs are off */
173         if (rdev->family >= CHIP_R600)
174                 reg = RREG32(R600_CONFIG_MEMSIZE);
175         else
176                 reg = RREG32(RADEON_CONFIG_MEMSIZE);
177
178         if (reg)
179                 return true;
180
181         return false;
182
183 }
184
185
186 /*
187  * Registers accessors functions.
188  */
189 uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
190 {
191         DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
192         BUG_ON(1);
193         return 0;
194 }
195
196 void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
197 {
198         DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
199                   reg, v);
200         BUG_ON(1);
201 }
202
203 void radeon_register_accessor_init(struct radeon_device *rdev)
204 {
205         rdev->mm_rreg = &r100_mm_rreg;
206         rdev->mm_wreg = &r100_mm_wreg;
207         rdev->mc_rreg = &radeon_invalid_rreg;
208         rdev->mc_wreg = &radeon_invalid_wreg;
209         rdev->pll_rreg = &radeon_invalid_rreg;
210         rdev->pll_wreg = &radeon_invalid_wreg;
211         rdev->pcie_rreg = &radeon_invalid_rreg;
212         rdev->pcie_wreg = &radeon_invalid_wreg;
213         rdev->pciep_rreg = &radeon_invalid_rreg;
214         rdev->pciep_wreg = &radeon_invalid_wreg;
215
216         /* Don't change order as we are overridding accessor. */
217         if (rdev->family < CHIP_RV515) {
218                 rdev->pcie_rreg = &rv370_pcie_rreg;
219                 rdev->pcie_wreg = &rv370_pcie_wreg;
220         }
221         if (rdev->family >= CHIP_RV515) {
222                 rdev->pcie_rreg = &rv515_pcie_rreg;
223                 rdev->pcie_wreg = &rv515_pcie_wreg;
224         }
225         /* FIXME: not sure here */
226         if (rdev->family <= CHIP_R580) {
227                 rdev->pll_rreg = &r100_pll_rreg;
228                 rdev->pll_wreg = &r100_pll_wreg;
229         }
230         if (rdev->family >= CHIP_RV515) {
231                 rdev->mc_rreg = &rv515_mc_rreg;
232                 rdev->mc_wreg = &rv515_mc_wreg;
233         }
234         if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
235                 rdev->mc_rreg = &rs400_mc_rreg;
236                 rdev->mc_wreg = &rs400_mc_wreg;
237         }
238         if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
239                 rdev->mc_rreg = &rs690_mc_rreg;
240                 rdev->mc_wreg = &rs690_mc_wreg;
241         }
242         if (rdev->family == CHIP_RS600) {
243                 rdev->mc_rreg = &rs600_mc_rreg;
244                 rdev->mc_wreg = &rs600_mc_wreg;
245         }
246         if (rdev->family >= CHIP_R600) {
247                 rdev->pciep_rreg = &r600_pciep_rreg;
248                 rdev->pciep_wreg = &r600_pciep_wreg;
249         }
250 }
251
252
253 /*
254  * ASIC
255  */
256 int radeon_asic_init(struct radeon_device *rdev)
257 {
258         radeon_register_accessor_init(rdev);
259         switch (rdev->family) {
260         case CHIP_R100:
261         case CHIP_RV100:
262         case CHIP_RS100:
263         case CHIP_RV200:
264         case CHIP_RS200:
265         case CHIP_R200:
266         case CHIP_RV250:
267         case CHIP_RS300:
268         case CHIP_RV280:
269                 rdev->asic = &r100_asic;
270                 break;
271         case CHIP_R300:
272         case CHIP_R350:
273         case CHIP_RV350:
274         case CHIP_RV380:
275                 rdev->asic = &r300_asic;
276                 break;
277         case CHIP_R420:
278         case CHIP_R423:
279         case CHIP_RV410:
280                 rdev->asic = &r420_asic;
281                 break;
282         case CHIP_RS400:
283         case CHIP_RS480:
284                 rdev->asic = &rs400_asic;
285                 break;
286         case CHIP_RS600:
287                 rdev->asic = &rs600_asic;
288                 break;
289         case CHIP_RS690:
290         case CHIP_RS740:
291                 rdev->asic = &rs690_asic;
292                 break;
293         case CHIP_RV515:
294                 rdev->asic = &rv515_asic;
295                 break;
296         case CHIP_R520:
297         case CHIP_RV530:
298         case CHIP_RV560:
299         case CHIP_RV570:
300         case CHIP_R580:
301                 rdev->asic = &r520_asic;
302                 break;
303         case CHIP_R600:
304         case CHIP_RV610:
305         case CHIP_RV630:
306         case CHIP_RV620:
307         case CHIP_RV635:
308         case CHIP_RV670:
309         case CHIP_RS780:
310         case CHIP_RV770:
311         case CHIP_RV730:
312         case CHIP_RV710:
313         default:
314                 /* FIXME: not supported yet */
315                 return -EINVAL;
316         }
317         return 0;
318 }
319
320
321 /*
322  * Wrapper around modesetting bits.
323  */
324 int radeon_clocks_init(struct radeon_device *rdev)
325 {
326         int r;
327
328         radeon_get_clock_info(rdev->ddev);
329         r = radeon_static_clocks_init(rdev->ddev);
330         if (r) {
331                 return r;
332         }
333         DRM_INFO("Clocks initialized !\n");
334         return 0;
335 }
336
337 void radeon_clocks_fini(struct radeon_device *rdev)
338 {
339 }
340
341 /* ATOM accessor methods */
342 static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
343 {
344         struct radeon_device *rdev = info->dev->dev_private;
345         uint32_t r;
346
347         r = rdev->pll_rreg(rdev, reg);
348         return r;
349 }
350
351 static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
352 {
353         struct radeon_device *rdev = info->dev->dev_private;
354
355         rdev->pll_wreg(rdev, reg, val);
356 }
357
358 static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
359 {
360         struct radeon_device *rdev = info->dev->dev_private;
361         uint32_t r;
362
363         r = rdev->mc_rreg(rdev, reg);
364         return r;
365 }
366
367 static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
368 {
369         struct radeon_device *rdev = info->dev->dev_private;
370
371         rdev->mc_wreg(rdev, reg, val);
372 }
373
374 static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
375 {
376         struct radeon_device *rdev = info->dev->dev_private;
377
378         WREG32(reg*4, val);
379 }
380
381 static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
382 {
383         struct radeon_device *rdev = info->dev->dev_private;
384         uint32_t r;
385
386         r = RREG32(reg*4);
387         return r;
388 }
389
390 static struct card_info atom_card_info = {
391         .dev = NULL,
392         .reg_read = cail_reg_read,
393         .reg_write = cail_reg_write,
394         .mc_read = cail_mc_read,
395         .mc_write = cail_mc_write,
396         .pll_read = cail_pll_read,
397         .pll_write = cail_pll_write,
398 };
399
400 int radeon_atombios_init(struct radeon_device *rdev)
401 {
402         atom_card_info.dev = rdev->ddev;
403         rdev->mode_info.atom_context = atom_parse(&atom_card_info, rdev->bios);
404         radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
405         return 0;
406 }
407
408 void radeon_atombios_fini(struct radeon_device *rdev)
409 {
410         kfree(rdev->mode_info.atom_context);
411 }
412
413 int radeon_combios_init(struct radeon_device *rdev)
414 {
415         radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
416         return 0;
417 }
418
419 void radeon_combios_fini(struct radeon_device *rdev)
420 {
421 }
422
423 int radeon_modeset_init(struct radeon_device *rdev);
424 void radeon_modeset_fini(struct radeon_device *rdev);
425
426
427 /*
428  * Radeon device.
429  */
430 int radeon_device_init(struct radeon_device *rdev,
431                        struct drm_device *ddev,
432                        struct pci_dev *pdev,
433                        uint32_t flags)
434 {
435         int r, ret;
436
437         DRM_INFO("radeon: Initializing kernel modesetting.\n");
438         rdev->shutdown = false;
439         rdev->ddev = ddev;
440         rdev->pdev = pdev;
441         rdev->flags = flags;
442         rdev->family = flags & RADEON_FAMILY_MASK;
443         rdev->is_atom_bios = false;
444         rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
445         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
446         rdev->gpu_lockup = false;
447         /* mutex initialization are all done here so we
448          * can recall function without having locking issues */
449         mutex_init(&rdev->cs_mutex);
450         mutex_init(&rdev->ib_pool.mutex);
451         mutex_init(&rdev->cp.mutex);
452         rwlock_init(&rdev->fence_drv.lock);
453
454         if (radeon_agpmode == -1) {
455                 rdev->flags &= ~RADEON_IS_AGP;
456                 if (rdev->family > CHIP_RV515 ||
457                     rdev->family == CHIP_RV380 ||
458                     rdev->family == CHIP_RV410 ||
459                     rdev->family == CHIP_R423) {
460                         DRM_INFO("Forcing AGP to PCIE mode\n");
461                         rdev->flags |= RADEON_IS_PCIE;
462                 } else {
463                         DRM_INFO("Forcing AGP to PCI mode\n");
464                         rdev->flags |= RADEON_IS_PCI;
465                 }
466         }
467
468         /* Set asic functions */
469         r = radeon_asic_init(rdev);
470         if (r) {
471                 return r;
472         }
473         r = radeon_init(rdev);
474         if (r) {
475                 return r;
476         }
477
478         /* Report DMA addressing limitation */
479         r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(32));
480         if (r) {
481                 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
482         }
483
484         /* Registers mapping */
485         /* TODO: block userspace mapping of io register */
486         rdev->rmmio_base = drm_get_resource_start(rdev->ddev, 2);
487         rdev->rmmio_size = drm_get_resource_len(rdev->ddev, 2);
488         rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
489         if (rdev->rmmio == NULL) {
490                 return -ENOMEM;
491         }
492         DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base);
493         DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size);
494
495         /* Setup errata flags */
496         radeon_errata(rdev);
497         /* Initialize scratch registers */
498         radeon_scratch_init(rdev);
499
500         /* TODO: disable VGA need to use VGA request */
501         /* BIOS*/
502         if (!radeon_get_bios(rdev)) {
503                 if (ASIC_IS_AVIVO(rdev))
504                         return -EINVAL;
505         }
506         if (rdev->is_atom_bios) {
507                 r = radeon_atombios_init(rdev);
508                 if (r) {
509                         return r;
510                 }
511         } else {
512                 r = radeon_combios_init(rdev);
513                 if (r) {
514                         return r;
515                 }
516         }
517         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
518         if (radeon_gpu_reset(rdev)) {
519                 /* FIXME: what do we want to do here ? */
520         }
521         /* check if cards are posted or not */
522         if (!radeon_card_posted(rdev) && rdev->bios) {
523                 DRM_INFO("GPU not posted. posting now...\n");
524                 if (rdev->is_atom_bios) {
525                         atom_asic_init(rdev->mode_info.atom_context);
526                 } else {
527                         radeon_combios_asic_init(rdev->ddev);
528                 }
529         }
530         /* Get vram informations */
531         radeon_vram_info(rdev);
532         /* Device is severly broken if aper size > vram size.
533          * for RN50/M6/M7 - Novell bug 204882 ?
534          */
535         if (rdev->mc.vram_size < rdev->mc.aper_size) {
536                 rdev->mc.aper_size = rdev->mc.vram_size;
537         }
538         /* Add an MTRR for the VRAM */
539         rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
540                                       MTRR_TYPE_WRCOMB, 1);
541         DRM_INFO("Detected VRAM RAM=%uM, BAR=%uM\n",
542                  rdev->mc.vram_size >> 20,
543                  (unsigned)rdev->mc.aper_size >> 20);
544         DRM_INFO("RAM width %dbits %cDR\n",
545                  rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
546         /* Initialize clocks */
547         r = radeon_clocks_init(rdev);
548         if (r) {
549                 return r;
550         }
551         /* Initialize memory controller (also test AGP) */
552         r = radeon_mc_init(rdev);
553         if (r) {
554                 return r;
555         }
556         /* Fence driver */
557         r = radeon_fence_driver_init(rdev);
558         if (r) {
559                 return r;
560         }
561         r = radeon_irq_kms_init(rdev);
562         if (r) {
563                 return r;
564         }
565         /* Memory manager */
566         r = radeon_object_init(rdev);
567         if (r) {
568                 return r;
569         }
570         /* Initialize GART (initialize after TTM so we can allocate
571          * memory through TTM but finalize after TTM) */
572         r = radeon_gart_enable(rdev);
573         if (!r) {
574                 r = radeon_gem_init(rdev);
575         }
576
577         /* 1M ring buffer */
578         if (!r) {
579                 r = radeon_cp_init(rdev, 1024 * 1024);
580         }
581         if (!r) {
582                 r = radeon_wb_init(rdev);
583                 if (r) {
584                         DRM_ERROR("radeon: failled initializing WB (%d).\n", r);
585                         return r;
586                 }
587         }
588         if (!r) {
589                 r = radeon_ib_pool_init(rdev);
590                 if (r) {
591                         DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
592                         return r;
593                 }
594         }
595         if (!r) {
596                 r = radeon_ib_test(rdev);
597                 if (r) {
598                         DRM_ERROR("radeon: failled testing IB (%d).\n", r);
599                         return r;
600                 }
601         }
602         ret = r;
603         r = radeon_modeset_init(rdev);
604         if (r) {
605                 return r;
606         }
607         if (rdev->fbdev_rfb && rdev->fbdev_rfb->obj) {
608                 rdev->fbdev_robj = rdev->fbdev_rfb->obj->driver_private;
609         }
610         if (!ret) {
611                 DRM_INFO("radeon: kernel modesetting successfully initialized.\n");
612         }
613         if (radeon_benchmarking) {
614                 radeon_benchmark(rdev);
615         }
616         return ret;
617 }
618
619 void radeon_device_fini(struct radeon_device *rdev)
620 {
621         if (rdev == NULL || rdev->rmmio == NULL) {
622                 return;
623         }
624         DRM_INFO("radeon: finishing device.\n");
625         rdev->shutdown = true;
626         /* Order matter so becarefull if you rearrange anythings */
627         radeon_modeset_fini(rdev);
628         radeon_ib_pool_fini(rdev);
629         radeon_cp_fini(rdev);
630         radeon_wb_fini(rdev);
631         radeon_gem_fini(rdev);
632         radeon_object_fini(rdev);
633         /* mc_fini must be after object_fini */
634         radeon_mc_fini(rdev);
635 #if __OS_HAS_AGP
636         radeon_agp_fini(rdev);
637 #endif
638         radeon_irq_kms_fini(rdev);
639         radeon_fence_driver_fini(rdev);
640         radeon_clocks_fini(rdev);
641         if (rdev->is_atom_bios) {
642                 radeon_atombios_fini(rdev);
643         } else {
644                 radeon_combios_fini(rdev);
645         }
646         kfree(rdev->bios);
647         rdev->bios = NULL;
648         iounmap(rdev->rmmio);
649         rdev->rmmio = NULL;
650 }
651
652
653 /*
654  * Suspend & resume.
655  */
656 int radeon_suspend_kms(struct drm_device *dev, pm_message_t state)
657 {
658         struct radeon_device *rdev = dev->dev_private;
659         struct drm_crtc *crtc;
660
661         if (dev == NULL || rdev == NULL) {
662                 return -ENODEV;
663         }
664         if (state.event == PM_EVENT_PRETHAW) {
665                 return 0;
666         }
667         /* unpin the front buffers */
668         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
669                 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->fb);
670                 struct radeon_object *robj;
671
672                 if (rfb == NULL || rfb->obj == NULL) {
673                         continue;
674                 }
675                 robj = rfb->obj->driver_private;
676                 if (robj != rdev->fbdev_robj) {
677                         radeon_object_unpin(robj);
678                 }
679         }
680         /* evict vram memory */
681         radeon_object_evict_vram(rdev);
682         /* wait for gpu to finish processing current batch */
683         radeon_fence_wait_last(rdev);
684
685         radeon_cp_disable(rdev);
686         radeon_gart_disable(rdev);
687
688         /* evict remaining vram memory */
689         radeon_object_evict_vram(rdev);
690
691         rdev->irq.sw_int = false;
692         radeon_irq_set(rdev);
693
694         pci_save_state(dev->pdev);
695         if (state.event == PM_EVENT_SUSPEND) {
696                 /* Shut down the device */
697                 pci_disable_device(dev->pdev);
698                 pci_set_power_state(dev->pdev, PCI_D3hot);
699         }
700         acquire_console_sem();
701         fb_set_suspend(rdev->fbdev_info, 1);
702         release_console_sem();
703         return 0;
704 }
705
706 int radeon_resume_kms(struct drm_device *dev)
707 {
708         struct radeon_device *rdev = dev->dev_private;
709         int r;
710
711         acquire_console_sem();
712         pci_set_power_state(dev->pdev, PCI_D0);
713         pci_restore_state(dev->pdev);
714         if (pci_enable_device(dev->pdev)) {
715                 release_console_sem();
716                 return -1;
717         }
718         pci_set_master(dev->pdev);
719         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
720         if (radeon_gpu_reset(rdev)) {
721                 /* FIXME: what do we want to do here ? */
722         }
723         /* post card */
724         if (rdev->is_atom_bios) {
725                 atom_asic_init(rdev->mode_info.atom_context);
726         } else {
727                 radeon_combios_asic_init(rdev->ddev);
728         }
729         /* Initialize clocks */
730         r = radeon_clocks_init(rdev);
731         if (r) {
732                 release_console_sem();
733                 return r;
734         }
735         /* Enable IRQ */
736         rdev->irq.sw_int = true;
737         radeon_irq_set(rdev);
738         /* Initialize GPU Memory Controller */
739         r = radeon_mc_init(rdev);
740         if (r) {
741                 goto out;
742         }
743         r = radeon_gart_enable(rdev);
744         if (r) {
745                 goto out;
746         }
747         r = radeon_cp_init(rdev, rdev->cp.ring_size);
748         if (r) {
749                 goto out;
750         }
751 out:
752         fb_set_suspend(rdev->fbdev_info, 0);
753         release_console_sem();
754
755         /* blat the mode back in */
756         drm_helper_resume_force_mode(dev);
757         return 0;
758 }
759
760
761 /*
762  * Debugfs
763  */
764 struct radeon_debugfs {
765         struct drm_info_list    *files;
766         unsigned                num_files;
767 };
768 static struct radeon_debugfs _radeon_debugfs[RADEON_DEBUGFS_MAX_NUM_FILES];
769 static unsigned _radeon_debugfs_count = 0;
770
771 int radeon_debugfs_add_files(struct radeon_device *rdev,
772                              struct drm_info_list *files,
773                              unsigned nfiles)
774 {
775         unsigned i;
776
777         for (i = 0; i < _radeon_debugfs_count; i++) {
778                 if (_radeon_debugfs[i].files == files) {
779                         /* Already registered */
780                         return 0;
781                 }
782         }
783         if ((_radeon_debugfs_count + nfiles) > RADEON_DEBUGFS_MAX_NUM_FILES) {
784                 DRM_ERROR("Reached maximum number of debugfs files.\n");
785                 DRM_ERROR("Report so we increase RADEON_DEBUGFS_MAX_NUM_FILES.\n");
786                 return -EINVAL;
787         }
788         _radeon_debugfs[_radeon_debugfs_count].files = files;
789         _radeon_debugfs[_radeon_debugfs_count].num_files = nfiles;
790         _radeon_debugfs_count++;
791 #if defined(CONFIG_DEBUG_FS)
792         drm_debugfs_create_files(files, nfiles,
793                                  rdev->ddev->control->debugfs_root,
794                                  rdev->ddev->control);
795         drm_debugfs_create_files(files, nfiles,
796                                  rdev->ddev->primary->debugfs_root,
797                                  rdev->ddev->primary);
798 #endif
799         return 0;
800 }
801
802 #if defined(CONFIG_DEBUG_FS)
803 int radeon_debugfs_init(struct drm_minor *minor)
804 {
805         return 0;
806 }
807
808 void radeon_debugfs_cleanup(struct drm_minor *minor)
809 {
810         unsigned i;
811
812         for (i = 0; i < _radeon_debugfs_count; i++) {
813                 drm_debugfs_remove_files(_radeon_debugfs[i].files,
814                                          _radeon_debugfs[i].num_files, minor);
815         }
816 }
817 #endif