fa063d0cfb634dc635697d694b8789495e130dc6
[linux-2.6.git] / drivers / gpu / drm / radeon / radeon_cp.c
1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
2 /*
3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5  * Copyright 2007 Advanced Micro Devices, Inc.
6  * All Rights Reserved.
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a
9  * copy of this software and associated documentation files (the "Software"),
10  * to deal in the Software without restriction, including without limitation
11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12  * and/or sell copies of the Software, and to permit persons to whom the
13  * Software is furnished to do so, subject to the following conditions:
14  *
15  * The above copyright notice and this permission notice (including the next
16  * paragraph) shall be included in all copies or substantial portions of the
17  * Software.
18  *
19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
22  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25  * DEALINGS IN THE SOFTWARE.
26  *
27  * Authors:
28  *    Kevin E. Martin <martin@valinux.com>
29  *    Gareth Hughes <gareth@valinux.com>
30  */
31
32 #include "drmP.h"
33 #include "drm.h"
34 #include "drm_sarea.h"
35 #include "radeon_drm.h"
36 #include "radeon_drv.h"
37 #include "r300_reg.h"
38
39 #define RADEON_FIFO_DEBUG       0
40
41 /* Firmware Names */
42 #define FIRMWARE_R100           "radeon/R100_cp.bin"
43 #define FIRMWARE_R200           "radeon/R200_cp.bin"
44 #define FIRMWARE_R300           "radeon/R300_cp.bin"
45 #define FIRMWARE_R420           "radeon/R420_cp.bin"
46 #define FIRMWARE_RS690          "radeon/RS690_cp.bin"
47 #define FIRMWARE_RS600          "radeon/RS600_cp.bin"
48 #define FIRMWARE_R520           "radeon/R520_cp.bin"
49
50 MODULE_FIRMWARE(FIRMWARE_R100);
51 MODULE_FIRMWARE(FIRMWARE_R200);
52 MODULE_FIRMWARE(FIRMWARE_R300);
53 MODULE_FIRMWARE(FIRMWARE_R420);
54 MODULE_FIRMWARE(FIRMWARE_RS690);
55 MODULE_FIRMWARE(FIRMWARE_RS600);
56 MODULE_FIRMWARE(FIRMWARE_R520);
57
58 static int radeon_do_cleanup_cp(struct drm_device * dev);
59 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
60
61 u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off)
62 {
63         u32 val;
64
65         if (dev_priv->flags & RADEON_IS_AGP) {
66                 val = DRM_READ32(dev_priv->ring_rptr, off);
67         } else {
68                 val = *(((volatile u32 *)
69                          dev_priv->ring_rptr->handle) +
70                         (off / sizeof(u32)));
71                 val = le32_to_cpu(val);
72         }
73         return val;
74 }
75
76 u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv)
77 {
78         if (dev_priv->writeback_works)
79                 return radeon_read_ring_rptr(dev_priv, 0);
80         else {
81                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
82                         return RADEON_READ(R600_CP_RB_RPTR);
83                 else
84                         return RADEON_READ(RADEON_CP_RB_RPTR);
85         }
86 }
87
88 void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val)
89 {
90         if (dev_priv->flags & RADEON_IS_AGP)
91                 DRM_WRITE32(dev_priv->ring_rptr, off, val);
92         else
93                 *(((volatile u32 *) dev_priv->ring_rptr->handle) +
94                   (off / sizeof(u32))) = cpu_to_le32(val);
95 }
96
97 void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val)
98 {
99         radeon_write_ring_rptr(dev_priv, 0, val);
100 }
101
102 u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index)
103 {
104         if (dev_priv->writeback_works) {
105                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
106                         return radeon_read_ring_rptr(dev_priv,
107                                                      R600_SCRATCHOFF(index));
108                 else
109                         return radeon_read_ring_rptr(dev_priv,
110                                                      RADEON_SCRATCHOFF(index));
111         } else {
112                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
113                         return RADEON_READ(R600_SCRATCH_REG0 + 4*index);
114                 else
115                         return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index);
116         }
117 }
118
119 u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr)
120 {
121         u32 ret;
122
123         if (addr < 0x10000)
124                 ret = DRM_READ32(dev_priv->mmio, addr);
125         else {
126                 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, addr);
127                 ret = DRM_READ32(dev_priv->mmio, RADEON_MM_DATA);
128         }
129
130         return ret;
131 }
132
133 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
134 {
135         u32 ret;
136         RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
137         ret = RADEON_READ(R520_MC_IND_DATA);
138         RADEON_WRITE(R520_MC_IND_INDEX, 0);
139         return ret;
140 }
141
142 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
143 {
144         u32 ret;
145         RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
146         ret = RADEON_READ(RS480_NB_MC_DATA);
147         RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
148         return ret;
149 }
150
151 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
152 {
153         u32 ret;
154         RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
155         ret = RADEON_READ(RS690_MC_DATA);
156         RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
157         return ret;
158 }
159
160 static u32 RS600_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
161 {
162         u32 ret;
163         RADEON_WRITE(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) |
164                                       RS600_MC_IND_CITF_ARB0));
165         ret = RADEON_READ(RS600_MC_DATA);
166         return ret;
167 }
168
169 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
170 {
171         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
172             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
173                 return RS690_READ_MCIND(dev_priv, addr);
174         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
175                 return RS600_READ_MCIND(dev_priv, addr);
176         else
177                 return RS480_READ_MCIND(dev_priv, addr);
178 }
179
180 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
181 {
182
183         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
184                 return RADEON_READ(R700_MC_VM_FB_LOCATION);
185         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
186                 return RADEON_READ(R600_MC_VM_FB_LOCATION);
187         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
188                 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
189         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
190                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
191                 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
192         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
193                 return RS600_READ_MCIND(dev_priv, RS600_MC_FB_LOCATION);
194         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
195                 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
196         else
197                 return RADEON_READ(RADEON_MC_FB_LOCATION);
198 }
199
200 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
201 {
202         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
203                 RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc);
204         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
205                 RADEON_WRITE(R600_MC_VM_FB_LOCATION, fb_loc);
206         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
207                 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
208         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
209                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
210                 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
211         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
212                 RS600_WRITE_MCIND(RS600_MC_FB_LOCATION, fb_loc);
213         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
214                 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
215         else
216                 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
217 }
218
219 void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
220 {
221         /*R6xx/R7xx: AGP_TOP and BOT are actually 18 bits each */
222         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
223                 RADEON_WRITE(R700_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
224                 RADEON_WRITE(R700_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
225         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
226                 RADEON_WRITE(R600_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
227                 RADEON_WRITE(R600_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
228         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
229                 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
230         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
231                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
232                 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
233         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
234                 RS600_WRITE_MCIND(RS600_MC_AGP_LOCATION, agp_loc);
235         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
236                 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
237         else
238                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
239 }
240
241 void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
242 {
243         u32 agp_base_hi = upper_32_bits(agp_base);
244         u32 agp_base_lo = agp_base & 0xffffffff;
245         u32 r6xx_agp_base = (agp_base >> 22) & 0x3ffff;
246
247         /* R6xx/R7xx must be aligned to a 4MB boundry */
248         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
249                 RADEON_WRITE(R700_MC_VM_AGP_BASE, r6xx_agp_base);
250         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
251                 RADEON_WRITE(R600_MC_VM_AGP_BASE, r6xx_agp_base);
252         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
253                 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
254                 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
255         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
256                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
257                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
258                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
259         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
260                 RS600_WRITE_MCIND(RS600_AGP_BASE, agp_base_lo);
261                 RS600_WRITE_MCIND(RS600_AGP_BASE_2, agp_base_hi);
262         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
263                 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
264                 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
265         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
266                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
267                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
268                 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
269         } else {
270                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
271                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
272                         RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
273         }
274 }
275
276 void radeon_enable_bm(struct drm_radeon_private *dev_priv)
277 {
278         u32 tmp;
279         /* Turn on bus mastering */
280         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
281             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
282                 /* rs600/rs690/rs740 */
283                 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
284                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
285         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
286                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
287                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
288                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
289                 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
290                 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
291                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
292         } /* PCIE cards appears to not need this */
293 }
294
295 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
296 {
297         drm_radeon_private_t *dev_priv = dev->dev_private;
298
299         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
300         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
301 }
302
303 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
304 {
305         RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
306         return RADEON_READ(RADEON_PCIE_DATA);
307 }
308
309 #if RADEON_FIFO_DEBUG
310 static void radeon_status(drm_radeon_private_t * dev_priv)
311 {
312         printk("%s:\n", __func__);
313         printk("RBBM_STATUS = 0x%08x\n",
314                (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
315         printk("CP_RB_RTPR = 0x%08x\n",
316                (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
317         printk("CP_RB_WTPR = 0x%08x\n",
318                (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
319         printk("AIC_CNTL = 0x%08x\n",
320                (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
321         printk("AIC_STAT = 0x%08x\n",
322                (unsigned int)RADEON_READ(RADEON_AIC_STAT));
323         printk("AIC_PT_BASE = 0x%08x\n",
324                (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
325         printk("TLB_ADDR = 0x%08x\n",
326                (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
327         printk("TLB_DATA = 0x%08x\n",
328                (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
329 }
330 #endif
331
332 /* ================================================================
333  * Engine, FIFO control
334  */
335
336 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
337 {
338         u32 tmp;
339         int i;
340
341         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
342
343         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
344                 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
345                 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
346                 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
347
348                 for (i = 0; i < dev_priv->usec_timeout; i++) {
349                         if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
350                               & RADEON_RB3D_DC_BUSY)) {
351                                 return 0;
352                         }
353                         DRM_UDELAY(1);
354                 }
355         } else {
356                 /* don't flush or purge cache here or lockup */
357                 return 0;
358         }
359
360 #if RADEON_FIFO_DEBUG
361         DRM_ERROR("failed!\n");
362         radeon_status(dev_priv);
363 #endif
364         return -EBUSY;
365 }
366
367 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
368 {
369         int i;
370
371         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
372
373         for (i = 0; i < dev_priv->usec_timeout; i++) {
374                 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
375                              & RADEON_RBBM_FIFOCNT_MASK);
376                 if (slots >= entries)
377                         return 0;
378                 DRM_UDELAY(1);
379         }
380         DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
381                  RADEON_READ(RADEON_RBBM_STATUS),
382                  RADEON_READ(R300_VAP_CNTL_STATUS));
383
384 #if RADEON_FIFO_DEBUG
385         DRM_ERROR("failed!\n");
386         radeon_status(dev_priv);
387 #endif
388         return -EBUSY;
389 }
390
391 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
392 {
393         int i, ret;
394
395         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
396
397         ret = radeon_do_wait_for_fifo(dev_priv, 64);
398         if (ret)
399                 return ret;
400
401         for (i = 0; i < dev_priv->usec_timeout; i++) {
402                 if (!(RADEON_READ(RADEON_RBBM_STATUS)
403                       & RADEON_RBBM_ACTIVE)) {
404                         radeon_do_pixcache_flush(dev_priv);
405                         return 0;
406                 }
407                 DRM_UDELAY(1);
408         }
409         DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
410                  RADEON_READ(RADEON_RBBM_STATUS),
411                  RADEON_READ(R300_VAP_CNTL_STATUS));
412
413 #if RADEON_FIFO_DEBUG
414         DRM_ERROR("failed!\n");
415         radeon_status(dev_priv);
416 #endif
417         return -EBUSY;
418 }
419
420 static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
421 {
422         uint32_t gb_tile_config, gb_pipe_sel = 0;
423
424         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) {
425                 uint32_t z_pipe_sel = RADEON_READ(RV530_GB_PIPE_SELECT2);
426                 if ((z_pipe_sel & 3) == 3)
427                         dev_priv->num_z_pipes = 2;
428                 else
429                         dev_priv->num_z_pipes = 1;
430         } else
431                 dev_priv->num_z_pipes = 1;
432
433         /* RS4xx/RS6xx/R4xx/R5xx */
434         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
435                 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
436                 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
437         } else {
438                 /* R3xx */
439                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
440                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
441                         dev_priv->num_gb_pipes = 2;
442                 } else {
443                         /* R3Vxx */
444                         dev_priv->num_gb_pipes = 1;
445                 }
446         }
447         DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
448
449         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
450
451         switch (dev_priv->num_gb_pipes) {
452         case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
453         case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
454         case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
455         default:
456         case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
457         }
458
459         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
460                 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
461                 RADEON_WRITE(R300_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
462         }
463         RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
464         radeon_do_wait_for_idle(dev_priv);
465         RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
466         RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
467                                                R300_DC_AUTOFLUSH_ENABLE |
468                                                R300_DC_DC_DISABLE_IGNORE_PE));
469
470
471 }
472
473 /* ================================================================
474  * CP control, initialization
475  */
476
477 /* Load the microcode for the CP */
478 static int radeon_cp_init_microcode(drm_radeon_private_t *dev_priv)
479 {
480         struct platform_device *pdev;
481         const char *fw_name = NULL;
482         int err;
483
484         DRM_DEBUG("\n");
485
486         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
487         err = IS_ERR(pdev);
488         if (err) {
489                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
490                 return -EINVAL;
491         }
492
493         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
494             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
495             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
496             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
497             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
498                 DRM_INFO("Loading R100 Microcode\n");
499                 fw_name = FIRMWARE_R100;
500         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
501                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
502                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
503                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
504                 DRM_INFO("Loading R200 Microcode\n");
505                 fw_name = FIRMWARE_R200;
506         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
507                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
508                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
509                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
510                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
511                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
512                 DRM_INFO("Loading R300 Microcode\n");
513                 fw_name = FIRMWARE_R300;
514         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
515                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
516                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
517                 DRM_INFO("Loading R400 Microcode\n");
518                 fw_name = FIRMWARE_R420;
519         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
520                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
521                 DRM_INFO("Loading RS690/RS740 Microcode\n");
522                 fw_name = FIRMWARE_RS690;
523         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
524                 DRM_INFO("Loading RS600 Microcode\n");
525                 fw_name = FIRMWARE_RS600;
526         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
527                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
528                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
529                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
530                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
531                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
532                 DRM_INFO("Loading R500 Microcode\n");
533                 fw_name = FIRMWARE_R520;
534         }
535
536         err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev);
537         platform_device_unregister(pdev);
538         if (err) {
539                 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
540                        fw_name);
541         } else if (dev_priv->me_fw->size % 8) {
542                 printk(KERN_ERR
543                        "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
544                        dev_priv->me_fw->size, fw_name);
545                 err = -EINVAL;
546                 release_firmware(dev_priv->me_fw);
547                 dev_priv->me_fw = NULL;
548         }
549         return err;
550 }
551
552 static void radeon_cp_load_microcode(drm_radeon_private_t *dev_priv)
553 {
554         const __be32 *fw_data;
555         int i, size;
556
557         radeon_do_wait_for_idle(dev_priv);
558
559         if (dev_priv->me_fw) {
560                 size = dev_priv->me_fw->size / 4;
561                 fw_data = (const __be32 *)&dev_priv->me_fw->data[0];
562                 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
563                 for (i = 0; i < size; i += 2) {
564                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
565                                      be32_to_cpup(&fw_data[i]));
566                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
567                                      be32_to_cpup(&fw_data[i + 1]));
568                 }
569         }
570 }
571
572 /* Flush any pending commands to the CP.  This should only be used just
573  * prior to a wait for idle, as it informs the engine that the command
574  * stream is ending.
575  */
576 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
577 {
578         DRM_DEBUG("\n");
579 #if 0
580         u32 tmp;
581
582         tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
583         RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
584 #endif
585 }
586
587 /* Wait for the CP to go idle.
588  */
589 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
590 {
591         RING_LOCALS;
592         DRM_DEBUG("\n");
593
594         BEGIN_RING(6);
595
596         RADEON_PURGE_CACHE();
597         RADEON_PURGE_ZCACHE();
598         RADEON_WAIT_UNTIL_IDLE();
599
600         ADVANCE_RING();
601         COMMIT_RING();
602
603         return radeon_do_wait_for_idle(dev_priv);
604 }
605
606 /* Start the Command Processor.
607  */
608 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
609 {
610         RING_LOCALS;
611         DRM_DEBUG("\n");
612
613         radeon_do_wait_for_idle(dev_priv);
614
615         RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
616
617         dev_priv->cp_running = 1;
618
619         BEGIN_RING(8);
620         /* isync can only be written through cp on r5xx write it here */
621         OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
622         OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
623                  RADEON_ISYNC_ANY3D_IDLE2D |
624                  RADEON_ISYNC_WAIT_IDLEGUI |
625                  RADEON_ISYNC_CPSCRATCH_IDLEGUI);
626         RADEON_PURGE_CACHE();
627         RADEON_PURGE_ZCACHE();
628         RADEON_WAIT_UNTIL_IDLE();
629         ADVANCE_RING();
630         COMMIT_RING();
631
632         dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
633 }
634
635 /* Reset the Command Processor.  This will not flush any pending
636  * commands, so you must wait for the CP command stream to complete
637  * before calling this routine.
638  */
639 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
640 {
641         u32 cur_read_ptr;
642         DRM_DEBUG("\n");
643
644         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
645         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
646         SET_RING_HEAD(dev_priv, cur_read_ptr);
647         dev_priv->ring.tail = cur_read_ptr;
648 }
649
650 /* Stop the Command Processor.  This will not flush any pending
651  * commands, so you must flush the command stream and wait for the CP
652  * to go idle before calling this routine.
653  */
654 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
655 {
656         DRM_DEBUG("\n");
657
658         RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
659
660         dev_priv->cp_running = 0;
661 }
662
663 /* Reset the engine.  This will stop the CP if it is running.
664  */
665 static int radeon_do_engine_reset(struct drm_device * dev)
666 {
667         drm_radeon_private_t *dev_priv = dev->dev_private;
668         u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
669         DRM_DEBUG("\n");
670
671         radeon_do_pixcache_flush(dev_priv);
672
673         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
674                 /* may need something similar for newer chips */
675                 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
676                 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
677
678                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
679                                                     RADEON_FORCEON_MCLKA |
680                                                     RADEON_FORCEON_MCLKB |
681                                                     RADEON_FORCEON_YCLKA |
682                                                     RADEON_FORCEON_YCLKB |
683                                                     RADEON_FORCEON_MC |
684                                                     RADEON_FORCEON_AIC));
685         }
686
687         rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
688
689         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
690                                               RADEON_SOFT_RESET_CP |
691                                               RADEON_SOFT_RESET_HI |
692                                               RADEON_SOFT_RESET_SE |
693                                               RADEON_SOFT_RESET_RE |
694                                               RADEON_SOFT_RESET_PP |
695                                               RADEON_SOFT_RESET_E2 |
696                                               RADEON_SOFT_RESET_RB));
697         RADEON_READ(RADEON_RBBM_SOFT_RESET);
698         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
699                                               ~(RADEON_SOFT_RESET_CP |
700                                                 RADEON_SOFT_RESET_HI |
701                                                 RADEON_SOFT_RESET_SE |
702                                                 RADEON_SOFT_RESET_RE |
703                                                 RADEON_SOFT_RESET_PP |
704                                                 RADEON_SOFT_RESET_E2 |
705                                                 RADEON_SOFT_RESET_RB)));
706         RADEON_READ(RADEON_RBBM_SOFT_RESET);
707
708         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
709                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
710                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
711                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
712         }
713
714         /* setup the raster pipes */
715         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
716             radeon_init_pipes(dev_priv);
717
718         /* Reset the CP ring */
719         radeon_do_cp_reset(dev_priv);
720
721         /* The CP is no longer running after an engine reset */
722         dev_priv->cp_running = 0;
723
724         /* Reset any pending vertex, indirect buffers */
725         radeon_freelist_reset(dev);
726
727         return 0;
728 }
729
730 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
731                                        drm_radeon_private_t *dev_priv,
732                                        struct drm_file *file_priv)
733 {
734         struct drm_radeon_master_private *master_priv;
735         u32 ring_start, cur_read_ptr;
736
737         /* Initialize the memory controller. With new memory map, the fb location
738          * is not changed, it should have been properly initialized already. Part
739          * of the problem is that the code below is bogus, assuming the GART is
740          * always appended to the fb which is not necessarily the case
741          */
742         if (!dev_priv->new_memmap)
743                 radeon_write_fb_location(dev_priv,
744                              ((dev_priv->gart_vm_start - 1) & 0xffff0000)
745                              | (dev_priv->fb_location >> 16));
746
747 #if __OS_HAS_AGP
748         if (dev_priv->flags & RADEON_IS_AGP) {
749                 radeon_write_agp_base(dev_priv, dev->agp->base);
750
751                 radeon_write_agp_location(dev_priv,
752                              (((dev_priv->gart_vm_start - 1 +
753                                 dev_priv->gart_size) & 0xffff0000) |
754                               (dev_priv->gart_vm_start >> 16)));
755
756                 ring_start = (dev_priv->cp_ring->offset
757                               - dev->agp->base
758                               + dev_priv->gart_vm_start);
759         } else
760 #endif
761                 ring_start = (dev_priv->cp_ring->offset
762                               - (unsigned long)dev->sg->virtual
763                               + dev_priv->gart_vm_start);
764
765         RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
766
767         /* Set the write pointer delay */
768         RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
769
770         /* Initialize the ring buffer's read and write pointers */
771         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
772         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
773         SET_RING_HEAD(dev_priv, cur_read_ptr);
774         dev_priv->ring.tail = cur_read_ptr;
775
776 #if __OS_HAS_AGP
777         if (dev_priv->flags & RADEON_IS_AGP) {
778                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
779                              dev_priv->ring_rptr->offset
780                              - dev->agp->base + dev_priv->gart_vm_start);
781         } else
782 #endif
783         {
784                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
785                              dev_priv->ring_rptr->offset
786                              - ((unsigned long) dev->sg->virtual)
787                              + dev_priv->gart_vm_start);
788         }
789
790         /* Set ring buffer size */
791 #ifdef __BIG_ENDIAN
792         RADEON_WRITE(RADEON_CP_RB_CNTL,
793                      RADEON_BUF_SWAP_32BIT |
794                      (dev_priv->ring.fetch_size_l2ow << 18) |
795                      (dev_priv->ring.rptr_update_l2qw << 8) |
796                      dev_priv->ring.size_l2qw);
797 #else
798         RADEON_WRITE(RADEON_CP_RB_CNTL,
799                      (dev_priv->ring.fetch_size_l2ow << 18) |
800                      (dev_priv->ring.rptr_update_l2qw << 8) |
801                      dev_priv->ring.size_l2qw);
802 #endif
803
804
805         /* Initialize the scratch register pointer.  This will cause
806          * the scratch register values to be written out to memory
807          * whenever they are updated.
808          *
809          * We simply put this behind the ring read pointer, this works
810          * with PCI GART as well as (whatever kind of) AGP GART
811          */
812         RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
813                      + RADEON_SCRATCH_REG_OFFSET);
814
815         RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
816
817         radeon_enable_bm(dev_priv);
818
819         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0);
820         RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
821
822         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
823         RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
824
825         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0);
826         RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
827
828         /* reset sarea copies of these */
829         master_priv = file_priv->master->driver_priv;
830         if (master_priv->sarea_priv) {
831                 master_priv->sarea_priv->last_frame = 0;
832                 master_priv->sarea_priv->last_dispatch = 0;
833                 master_priv->sarea_priv->last_clear = 0;
834         }
835
836         radeon_do_wait_for_idle(dev_priv);
837
838         /* Sync everything up */
839         RADEON_WRITE(RADEON_ISYNC_CNTL,
840                      (RADEON_ISYNC_ANY2D_IDLE3D |
841                       RADEON_ISYNC_ANY3D_IDLE2D |
842                       RADEON_ISYNC_WAIT_IDLEGUI |
843                       RADEON_ISYNC_CPSCRATCH_IDLEGUI));
844
845 }
846
847 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
848 {
849         u32 tmp;
850
851         /* Start with assuming that writeback doesn't work */
852         dev_priv->writeback_works = 0;
853
854         /* Writeback doesn't seem to work everywhere, test it here and possibly
855          * enable it if it appears to work
856          */
857         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
858
859         RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
860
861         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
862                 u32 val;
863
864                 val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
865                 if (val == 0xdeadbeef)
866                         break;
867                 DRM_UDELAY(1);
868         }
869
870         if (tmp < dev_priv->usec_timeout) {
871                 dev_priv->writeback_works = 1;
872                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
873         } else {
874                 dev_priv->writeback_works = 0;
875                 DRM_INFO("writeback test failed\n");
876         }
877         if (radeon_no_wb == 1) {
878                 dev_priv->writeback_works = 0;
879                 DRM_INFO("writeback forced off\n");
880         }
881
882         if (!dev_priv->writeback_works) {
883                 /* Disable writeback to avoid unnecessary bus master transfer */
884                 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
885                              RADEON_RB_NO_UPDATE);
886                 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
887         }
888 }
889
890 /* Enable or disable IGP GART on the chip */
891 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
892 {
893         u32 temp;
894
895         if (on) {
896                 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
897                           dev_priv->gart_vm_start,
898                           (long)dev_priv->gart_info.bus_addr,
899                           dev_priv->gart_size);
900
901                 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
902                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
903                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
904                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
905                                                              RS690_BLOCK_GFX_D3_EN));
906                 else
907                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
908
909                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
910                                                                RS480_VA_SIZE_32MB));
911
912                 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
913                 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
914                                                         RS480_TLB_ENABLE |
915                                                         RS480_GTW_LAC_EN |
916                                                         RS480_1LEVEL_GART));
917
918                 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
919                 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
920                 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
921
922                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
923                 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
924                                                       RS480_REQ_TYPE_SNOOP_DIS));
925
926                 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
927
928                 dev_priv->gart_size = 32*1024*1024;
929                 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
930                          0xffff0000) | (dev_priv->gart_vm_start >> 16));
931
932                 radeon_write_agp_location(dev_priv, temp);
933
934                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
935                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
936                                                                RS480_VA_SIZE_32MB));
937
938                 do {
939                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
940                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
941                                 break;
942                         DRM_UDELAY(1);
943                 } while (1);
944
945                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
946                                 RS480_GART_CACHE_INVALIDATE);
947
948                 do {
949                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
950                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
951                                 break;
952                         DRM_UDELAY(1);
953                 } while (1);
954
955                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
956         } else {
957                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
958         }
959 }
960
961 /* Enable or disable IGP GART on the chip */
962 static void rs600_set_igpgart(drm_radeon_private_t *dev_priv, int on)
963 {
964         u32 temp;
965         int i;
966
967         if (on) {
968                 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
969                          dev_priv->gart_vm_start,
970                          (long)dev_priv->gart_info.bus_addr,
971                          dev_priv->gart_size);
972
973                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (RS600_EFFECTIVE_L2_CACHE_SIZE(6) |
974                                                     RS600_EFFECTIVE_L2_QUEUE_SIZE(6)));
975
976                 for (i = 0; i < 19; i++)
977                         IGP_WRITE_MCIND(RS600_MC_PT0_CLIENT0_CNTL + i,
978                                         (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE |
979                                          RS600_SYSTEM_ACCESS_MODE_IN_SYS |
980                                          RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH |
981                                          RS600_EFFECTIVE_L1_CACHE_SIZE(3) |
982                                          RS600_ENABLE_FRAGMENT_PROCESSING |
983                                          RS600_EFFECTIVE_L1_QUEUE_SIZE(3)));
984
985                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL, (RS600_ENABLE_PAGE_TABLE |
986                                                              RS600_PAGE_TABLE_TYPE_FLAT));
987
988                 /* disable all other contexts */
989                 for (i = 1; i < 8; i++)
990                         IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL + i, 0);
991
992                 /* setup the page table aperture */
993                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
994                                 dev_priv->gart_info.bus_addr);
995                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR,
996                                 dev_priv->gart_vm_start);
997                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR,
998                                 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
999                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
1000
1001                 /* setup the system aperture */
1002                 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR,
1003                                 dev_priv->gart_vm_start);
1004                 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR,
1005                                 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
1006
1007                 /* enable page tables */
1008                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1009                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (temp | RS600_ENABLE_PT));
1010
1011                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
1012                 IGP_WRITE_MCIND(RS600_MC_CNTL1, (temp | RS600_ENABLE_PAGE_TABLES));
1013
1014                 /* invalidate the cache */
1015                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1016
1017                 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
1018                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1019                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1020
1021                 temp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE;
1022                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1023                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1024
1025                 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
1026                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1027                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1028
1029         } else {
1030                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, 0);
1031                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
1032                 temp &= ~RS600_ENABLE_PAGE_TABLES;
1033                 IGP_WRITE_MCIND(RS600_MC_CNTL1, temp);
1034         }
1035 }
1036
1037 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
1038 {
1039         u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
1040         if (on) {
1041
1042                 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
1043                           dev_priv->gart_vm_start,
1044                           (long)dev_priv->gart_info.bus_addr,
1045                           dev_priv->gart_size);
1046                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
1047                                   dev_priv->gart_vm_start);
1048                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
1049                                   dev_priv->gart_info.bus_addr);
1050                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
1051                                   dev_priv->gart_vm_start);
1052                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
1053                                   dev_priv->gart_vm_start +
1054                                   dev_priv->gart_size - 1);
1055
1056                 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
1057
1058                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1059                                   RADEON_PCIE_TX_GART_EN);
1060         } else {
1061                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1062                                   tmp & ~RADEON_PCIE_TX_GART_EN);
1063         }
1064 }
1065
1066 /* Enable or disable PCI GART on the chip */
1067 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1068 {
1069         u32 tmp;
1070
1071         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
1072             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
1073             (dev_priv->flags & RADEON_IS_IGPGART)) {
1074                 radeon_set_igpgart(dev_priv, on);
1075                 return;
1076         }
1077
1078         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
1079                 rs600_set_igpgart(dev_priv, on);
1080                 return;
1081         }
1082
1083         if (dev_priv->flags & RADEON_IS_PCIE) {
1084                 radeon_set_pciegart(dev_priv, on);
1085                 return;
1086         }
1087
1088         tmp = RADEON_READ(RADEON_AIC_CNTL);
1089
1090         if (on) {
1091                 RADEON_WRITE(RADEON_AIC_CNTL,
1092                              tmp | RADEON_PCIGART_TRANSLATE_EN);
1093
1094                 /* set PCI GART page-table base address
1095                  */
1096                 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1097
1098                 /* set address range for PCI address translate
1099                  */
1100                 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1101                 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1102                              + dev_priv->gart_size - 1);
1103
1104                 /* Turn off AGP aperture -- is this required for PCI GART?
1105                  */
1106                 radeon_write_agp_location(dev_priv, 0xffffffc0);
1107                 RADEON_WRITE(RADEON_AGP_COMMAND, 0);    /* clear AGP_COMMAND */
1108         } else {
1109                 RADEON_WRITE(RADEON_AIC_CNTL,
1110                              tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1111         }
1112 }
1113
1114 static int radeon_setup_pcigart_surface(drm_radeon_private_t *dev_priv)
1115 {
1116         struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
1117         struct radeon_virt_surface *vp;
1118         int i;
1119
1120         for (i = 0; i < RADEON_MAX_SURFACES * 2; i++) {
1121                 if (!dev_priv->virt_surfaces[i].file_priv ||
1122                     dev_priv->virt_surfaces[i].file_priv == PCIGART_FILE_PRIV)
1123                         break;
1124         }
1125         if (i >= 2 * RADEON_MAX_SURFACES)
1126                 return -ENOMEM;
1127         vp = &dev_priv->virt_surfaces[i];
1128
1129         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1130                 struct radeon_surface *sp = &dev_priv->surfaces[i];
1131                 if (sp->refcount)
1132                         continue;
1133
1134                 vp->surface_index = i;
1135                 vp->lower = gart_info->bus_addr;
1136                 vp->upper = vp->lower + gart_info->table_size;
1137                 vp->flags = 0;
1138                 vp->file_priv = PCIGART_FILE_PRIV;
1139
1140                 sp->refcount = 1;
1141                 sp->lower = vp->lower;
1142                 sp->upper = vp->upper;
1143                 sp->flags = 0;
1144
1145                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, sp->flags);
1146                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * i, sp->lower);
1147                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * i, sp->upper);
1148                 return 0;
1149         }
1150
1151         return -ENOMEM;
1152 }
1153
1154 static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1155                              struct drm_file *file_priv)
1156 {
1157         drm_radeon_private_t *dev_priv = dev->dev_private;
1158         struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
1159
1160         DRM_DEBUG("\n");
1161
1162         /* if we require new memory map but we don't have it fail */
1163         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1164                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1165                 radeon_do_cleanup_cp(dev);
1166                 return -EINVAL;
1167         }
1168
1169         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1170                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1171                 dev_priv->flags &= ~RADEON_IS_AGP;
1172         } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1173                    && !init->is_pci) {
1174                 DRM_DEBUG("Restoring AGP flag\n");
1175                 dev_priv->flags |= RADEON_IS_AGP;
1176         }
1177
1178         if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
1179                 DRM_ERROR("PCI GART memory not allocated!\n");
1180                 radeon_do_cleanup_cp(dev);
1181                 return -EINVAL;
1182         }
1183
1184         dev_priv->usec_timeout = init->usec_timeout;
1185         if (dev_priv->usec_timeout < 1 ||
1186             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1187                 DRM_DEBUG("TIMEOUT problem!\n");
1188                 radeon_do_cleanup_cp(dev);
1189                 return -EINVAL;
1190         }
1191
1192         /* Enable vblank on CRTC1 for older X servers
1193          */
1194         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1195
1196         switch(init->func) {
1197         case RADEON_INIT_R200_CP:
1198                 dev_priv->microcode_version = UCODE_R200;
1199                 break;
1200         case RADEON_INIT_R300_CP:
1201                 dev_priv->microcode_version = UCODE_R300;
1202                 break;
1203         default:
1204                 dev_priv->microcode_version = UCODE_R100;
1205         }
1206
1207         dev_priv->do_boxes = 0;
1208         dev_priv->cp_mode = init->cp_mode;
1209
1210         /* We don't support anything other than bus-mastering ring mode,
1211          * but the ring can be in either AGP or PCI space for the ring
1212          * read pointer.
1213          */
1214         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1215             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1216                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1217                 radeon_do_cleanup_cp(dev);
1218                 return -EINVAL;
1219         }
1220
1221         switch (init->fb_bpp) {
1222         case 16:
1223                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1224                 break;
1225         case 32:
1226         default:
1227                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1228                 break;
1229         }
1230         dev_priv->front_offset = init->front_offset;
1231         dev_priv->front_pitch = init->front_pitch;
1232         dev_priv->back_offset = init->back_offset;
1233         dev_priv->back_pitch = init->back_pitch;
1234
1235         switch (init->depth_bpp) {
1236         case 16:
1237                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1238                 break;
1239         case 32:
1240         default:
1241                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1242                 break;
1243         }
1244         dev_priv->depth_offset = init->depth_offset;
1245         dev_priv->depth_pitch = init->depth_pitch;
1246
1247         /* Hardware state for depth clears.  Remove this if/when we no
1248          * longer clear the depth buffer with a 3D rectangle.  Hard-code
1249          * all values to prevent unwanted 3D state from slipping through
1250          * and screwing with the clear operation.
1251          */
1252         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1253                                            (dev_priv->color_fmt << 10) |
1254                                            (dev_priv->microcode_version ==
1255                                             UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1256
1257         dev_priv->depth_clear.rb3d_zstencilcntl =
1258             (dev_priv->depth_fmt |
1259              RADEON_Z_TEST_ALWAYS |
1260              RADEON_STENCIL_TEST_ALWAYS |
1261              RADEON_STENCIL_S_FAIL_REPLACE |
1262              RADEON_STENCIL_ZPASS_REPLACE |
1263              RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1264
1265         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1266                                          RADEON_BFACE_SOLID |
1267                                          RADEON_FFACE_SOLID |
1268                                          RADEON_FLAT_SHADE_VTX_LAST |
1269                                          RADEON_DIFFUSE_SHADE_FLAT |
1270                                          RADEON_ALPHA_SHADE_FLAT |
1271                                          RADEON_SPECULAR_SHADE_FLAT |
1272                                          RADEON_FOG_SHADE_FLAT |
1273                                          RADEON_VTX_PIX_CENTER_OGL |
1274                                          RADEON_ROUND_MODE_TRUNC |
1275                                          RADEON_ROUND_PREC_8TH_PIX);
1276
1277
1278         dev_priv->ring_offset = init->ring_offset;
1279         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1280         dev_priv->buffers_offset = init->buffers_offset;
1281         dev_priv->gart_textures_offset = init->gart_textures_offset;
1282
1283         master_priv->sarea = drm_getsarea(dev);
1284         if (!master_priv->sarea) {
1285                 DRM_ERROR("could not find sarea!\n");
1286                 radeon_do_cleanup_cp(dev);
1287                 return -EINVAL;
1288         }
1289
1290         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1291         if (!dev_priv->cp_ring) {
1292                 DRM_ERROR("could not find cp ring region!\n");
1293                 radeon_do_cleanup_cp(dev);
1294                 return -EINVAL;
1295         }
1296         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1297         if (!dev_priv->ring_rptr) {
1298                 DRM_ERROR("could not find ring read pointer!\n");
1299                 radeon_do_cleanup_cp(dev);
1300                 return -EINVAL;
1301         }
1302         dev->agp_buffer_token = init->buffers_offset;
1303         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1304         if (!dev->agp_buffer_map) {
1305                 DRM_ERROR("could not find dma buffer region!\n");
1306                 radeon_do_cleanup_cp(dev);
1307                 return -EINVAL;
1308         }
1309
1310         if (init->gart_textures_offset) {
1311                 dev_priv->gart_textures =
1312                     drm_core_findmap(dev, init->gart_textures_offset);
1313                 if (!dev_priv->gart_textures) {
1314                         DRM_ERROR("could not find GART texture region!\n");
1315                         radeon_do_cleanup_cp(dev);
1316                         return -EINVAL;
1317                 }
1318         }
1319
1320 #if __OS_HAS_AGP
1321         if (dev_priv->flags & RADEON_IS_AGP) {
1322                 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1323                 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1324                 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
1325                 if (!dev_priv->cp_ring->handle ||
1326                     !dev_priv->ring_rptr->handle ||
1327                     !dev->agp_buffer_map->handle) {
1328                         DRM_ERROR("could not find ioremap agp regions!\n");
1329                         radeon_do_cleanup_cp(dev);
1330                         return -EINVAL;
1331                 }
1332         } else
1333 #endif
1334         {
1335                 dev_priv->cp_ring->handle =
1336                         (void *)(unsigned long)dev_priv->cp_ring->offset;
1337                 dev_priv->ring_rptr->handle =
1338                         (void *)(unsigned long)dev_priv->ring_rptr->offset;
1339                 dev->agp_buffer_map->handle =
1340                         (void *)(unsigned long)dev->agp_buffer_map->offset;
1341
1342                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1343                           dev_priv->cp_ring->handle);
1344                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1345                           dev_priv->ring_rptr->handle);
1346                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1347                           dev->agp_buffer_map->handle);
1348         }
1349
1350         dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1351         dev_priv->fb_size =
1352                 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1353                 - dev_priv->fb_location;
1354
1355         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1356                                         ((dev_priv->front_offset
1357                                           + dev_priv->fb_location) >> 10));
1358
1359         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1360                                        ((dev_priv->back_offset
1361                                          + dev_priv->fb_location) >> 10));
1362
1363         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1364                                         ((dev_priv->depth_offset
1365                                           + dev_priv->fb_location) >> 10));
1366
1367         dev_priv->gart_size = init->gart_size;
1368
1369         /* New let's set the memory map ... */
1370         if (dev_priv->new_memmap) {
1371                 u32 base = 0;
1372
1373                 DRM_INFO("Setting GART location based on new memory map\n");
1374
1375                 /* If using AGP, try to locate the AGP aperture at the same
1376                  * location in the card and on the bus, though we have to
1377                  * align it down.
1378                  */
1379 #if __OS_HAS_AGP
1380                 if (dev_priv->flags & RADEON_IS_AGP) {
1381                         base = dev->agp->base;
1382                         /* Check if valid */
1383                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1384                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1385                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1386                                          dev->agp->base);
1387                                 base = 0;
1388                         }
1389                 }
1390 #endif
1391                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1392                 if (base == 0) {
1393                         base = dev_priv->fb_location + dev_priv->fb_size;
1394                         if (base < dev_priv->fb_location ||
1395                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1396                                 base = dev_priv->fb_location
1397                                         - dev_priv->gart_size;
1398                 }
1399                 dev_priv->gart_vm_start = base & 0xffc00000u;
1400                 if (dev_priv->gart_vm_start != base)
1401                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1402                                  base, dev_priv->gart_vm_start);
1403         } else {
1404                 DRM_INFO("Setting GART location based on old memory map\n");
1405                 dev_priv->gart_vm_start = dev_priv->fb_location +
1406                         RADEON_READ(RADEON_CONFIG_APER_SIZE);
1407         }
1408
1409 #if __OS_HAS_AGP
1410         if (dev_priv->flags & RADEON_IS_AGP)
1411                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1412                                                  - dev->agp->base
1413                                                  + dev_priv->gart_vm_start);
1414         else
1415 #endif
1416                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1417                                         - (unsigned long)dev->sg->virtual
1418                                         + dev_priv->gart_vm_start);
1419
1420         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1421         DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1422         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1423                   dev_priv->gart_buffers_offset);
1424
1425         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1426         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1427                               + init->ring_size / sizeof(u32));
1428         dev_priv->ring.size = init->ring_size;
1429         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1430
1431         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1432         dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1433
1434         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1435         dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1436         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1437
1438         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1439
1440 #if __OS_HAS_AGP
1441         if (dev_priv->flags & RADEON_IS_AGP) {
1442                 /* Turn off PCI GART */
1443                 radeon_set_pcigart(dev_priv, 0);
1444         } else
1445 #endif
1446         {
1447                 u32 sctrl;
1448                 int ret;
1449
1450                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1451                 /* if we have an offset set from userspace */
1452                 if (dev_priv->pcigart_offset_set) {
1453                         dev_priv->gart_info.bus_addr =
1454                                 (resource_size_t)dev_priv->pcigart_offset + dev_priv->fb_location;
1455                         dev_priv->gart_info.mapping.offset =
1456                             dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1457                         dev_priv->gart_info.mapping.size =
1458                             dev_priv->gart_info.table_size;
1459
1460                         drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1461                         dev_priv->gart_info.addr =
1462                             dev_priv->gart_info.mapping.handle;
1463
1464                         if (dev_priv->flags & RADEON_IS_PCIE)
1465                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1466                         else
1467                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1468                         dev_priv->gart_info.gart_table_location =
1469                             DRM_ATI_GART_FB;
1470
1471                         DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1472                                   dev_priv->gart_info.addr,
1473                                   dev_priv->pcigart_offset);
1474                 } else {
1475                         if (dev_priv->flags & RADEON_IS_IGPGART)
1476                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1477                         else
1478                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1479                         dev_priv->gart_info.gart_table_location =
1480                             DRM_ATI_GART_MAIN;
1481                         dev_priv->gart_info.addr = NULL;
1482                         dev_priv->gart_info.bus_addr = 0;
1483                         if (dev_priv->flags & RADEON_IS_PCIE) {
1484                                 DRM_ERROR
1485                                     ("Cannot use PCI Express without GART in FB memory\n");
1486                                 radeon_do_cleanup_cp(dev);
1487                                 return -EINVAL;
1488                         }
1489                 }
1490
1491                 sctrl = RADEON_READ(RADEON_SURFACE_CNTL);
1492                 RADEON_WRITE(RADEON_SURFACE_CNTL, 0);
1493                 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1494                         ret = r600_page_table_init(dev);
1495                 else
1496                         ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info);
1497                 RADEON_WRITE(RADEON_SURFACE_CNTL, sctrl);
1498
1499                 if (!ret) {
1500                         DRM_ERROR("failed to init PCI GART!\n");
1501                         radeon_do_cleanup_cp(dev);
1502                         return -ENOMEM;
1503                 }
1504
1505                 ret = radeon_setup_pcigart_surface(dev_priv);
1506                 if (ret) {
1507                         DRM_ERROR("failed to setup GART surface!\n");
1508                         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1509                                 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1510                         else
1511                                 drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info);
1512                         radeon_do_cleanup_cp(dev);
1513                         return ret;
1514                 }
1515
1516                 /* Turn on PCI GART */
1517                 radeon_set_pcigart(dev_priv, 1);
1518         }
1519
1520         if (!dev_priv->me_fw) {
1521                 int err = radeon_cp_init_microcode(dev_priv);
1522                 if (err) {
1523                         DRM_ERROR("Failed to load firmware!\n");
1524                         radeon_do_cleanup_cp(dev);
1525                         return err;
1526                 }
1527         }
1528         radeon_cp_load_microcode(dev_priv);
1529         radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1530
1531         dev_priv->last_buf = 0;
1532
1533         radeon_do_engine_reset(dev);
1534         radeon_test_writeback(dev_priv);
1535
1536         return 0;
1537 }
1538
1539 static int radeon_do_cleanup_cp(struct drm_device * dev)
1540 {
1541         drm_radeon_private_t *dev_priv = dev->dev_private;
1542         DRM_DEBUG("\n");
1543
1544         /* Make sure interrupts are disabled here because the uninstall ioctl
1545          * may not have been called from userspace and after dev_private
1546          * is freed, it's too late.
1547          */
1548         if (dev->irq_enabled)
1549                 drm_irq_uninstall(dev);
1550
1551 #if __OS_HAS_AGP
1552         if (dev_priv->flags & RADEON_IS_AGP) {
1553                 if (dev_priv->cp_ring != NULL) {
1554                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1555                         dev_priv->cp_ring = NULL;
1556                 }
1557                 if (dev_priv->ring_rptr != NULL) {
1558                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1559                         dev_priv->ring_rptr = NULL;
1560                 }
1561                 if (dev->agp_buffer_map != NULL) {
1562                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1563                         dev->agp_buffer_map = NULL;
1564                 }
1565         } else
1566 #endif
1567         {
1568
1569                 if (dev_priv->gart_info.bus_addr) {
1570                         /* Turn off PCI GART */
1571                         radeon_set_pcigart(dev_priv, 0);
1572                         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1573                                 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1574                         else {
1575                                 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1576                                         DRM_ERROR("failed to cleanup PCI GART!\n");
1577                         }
1578                 }
1579
1580                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1581                 {
1582                         drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1583                         dev_priv->gart_info.addr = NULL;
1584                 }
1585         }
1586         /* only clear to the start of flags */
1587         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1588
1589         return 0;
1590 }
1591
1592 /* This code will reinit the Radeon CP hardware after a resume from disc.
1593  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1594  * here we make sure that all Radeon hardware initialisation is re-done without
1595  * affecting running applications.
1596  *
1597  * Charl P. Botha <http://cpbotha.net>
1598  */
1599 static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
1600 {
1601         drm_radeon_private_t *dev_priv = dev->dev_private;
1602
1603         if (!dev_priv) {
1604                 DRM_ERROR("Called with no initialization\n");
1605                 return -EINVAL;
1606         }
1607
1608         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1609
1610 #if __OS_HAS_AGP
1611         if (dev_priv->flags & RADEON_IS_AGP) {
1612                 /* Turn off PCI GART */
1613                 radeon_set_pcigart(dev_priv, 0);
1614         } else
1615 #endif
1616         {
1617                 /* Turn on PCI GART */
1618                 radeon_set_pcigart(dev_priv, 1);
1619         }
1620
1621         radeon_cp_load_microcode(dev_priv);
1622         radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1623
1624         radeon_do_engine_reset(dev);
1625         radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1626
1627         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1628
1629         return 0;
1630 }
1631
1632 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1633 {
1634         drm_radeon_private_t *dev_priv = dev->dev_private;
1635         drm_radeon_init_t *init = data;
1636
1637         LOCK_TEST_WITH_RETURN(dev, file_priv);
1638
1639         if (init->func == RADEON_INIT_R300_CP)
1640                 r300_init_reg_flags(dev);
1641
1642         switch (init->func) {
1643         case RADEON_INIT_CP:
1644         case RADEON_INIT_R200_CP:
1645         case RADEON_INIT_R300_CP:
1646                 return radeon_do_init_cp(dev, init, file_priv);
1647         case RADEON_INIT_R600_CP:
1648                 return r600_do_init_cp(dev, init, file_priv);
1649         case RADEON_CLEANUP_CP:
1650                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1651                         return r600_do_cleanup_cp(dev);
1652                 else
1653                         return radeon_do_cleanup_cp(dev);
1654         }
1655
1656         return -EINVAL;
1657 }
1658
1659 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1660 {
1661         drm_radeon_private_t *dev_priv = dev->dev_private;
1662         DRM_DEBUG("\n");
1663
1664         LOCK_TEST_WITH_RETURN(dev, file_priv);
1665
1666         if (dev_priv->cp_running) {
1667                 DRM_DEBUG("while CP running\n");
1668                 return 0;
1669         }
1670         if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1671                 DRM_DEBUG("called with bogus CP mode (%d)\n",
1672                           dev_priv->cp_mode);
1673                 return 0;
1674         }
1675
1676         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1677                 r600_do_cp_start(dev_priv);
1678         else
1679                 radeon_do_cp_start(dev_priv);
1680
1681         return 0;
1682 }
1683
1684 /* Stop the CP.  The engine must have been idled before calling this
1685  * routine.
1686  */
1687 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1688 {
1689         drm_radeon_private_t *dev_priv = dev->dev_private;
1690         drm_radeon_cp_stop_t *stop = data;
1691         int ret;
1692         DRM_DEBUG("\n");
1693
1694         LOCK_TEST_WITH_RETURN(dev, file_priv);
1695
1696         if (!dev_priv->cp_running)
1697                 return 0;
1698
1699         /* Flush any pending CP commands.  This ensures any outstanding
1700          * commands are exectuted by the engine before we turn it off.
1701          */
1702         if (stop->flush) {
1703                 radeon_do_cp_flush(dev_priv);
1704         }
1705
1706         /* If we fail to make the engine go idle, we return an error
1707          * code so that the DRM ioctl wrapper can try again.
1708          */
1709         if (stop->idle) {
1710                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1711                         ret = r600_do_cp_idle(dev_priv);
1712                 else
1713                         ret = radeon_do_cp_idle(dev_priv);
1714                 if (ret)
1715                         return ret;
1716         }
1717
1718         /* Finally, we can turn off the CP.  If the engine isn't idle,
1719          * we will get some dropped triangles as they won't be fully
1720          * rendered before the CP is shut down.
1721          */
1722         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1723                 r600_do_cp_stop(dev_priv);
1724         else
1725                 radeon_do_cp_stop(dev_priv);
1726
1727         /* Reset the engine */
1728         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1729                 r600_do_engine_reset(dev);
1730         else
1731                 radeon_do_engine_reset(dev);
1732
1733         return 0;
1734 }
1735
1736 void radeon_do_release(struct drm_device * dev)
1737 {
1738         drm_radeon_private_t *dev_priv = dev->dev_private;
1739         int i, ret;
1740
1741         if (dev_priv) {
1742                 if (dev_priv->cp_running) {
1743                         /* Stop the cp */
1744                         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1745                                 while ((ret = r600_do_cp_idle(dev_priv)) != 0) {
1746                                         DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1747 #ifdef __linux__
1748                                         schedule();
1749 #else
1750                                         tsleep(&ret, PZERO, "rdnrel", 1);
1751 #endif
1752                                 }
1753                         } else {
1754                                 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1755                                         DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1756 #ifdef __linux__
1757                                         schedule();
1758 #else
1759                                         tsleep(&ret, PZERO, "rdnrel", 1);
1760 #endif
1761                                 }
1762                         }
1763                         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1764                                 r600_do_cp_stop(dev_priv);
1765                                 r600_do_engine_reset(dev);
1766                         } else {
1767                                 radeon_do_cp_stop(dev_priv);
1768                                 radeon_do_engine_reset(dev);
1769                         }
1770                 }
1771
1772                 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) {
1773                         /* Disable *all* interrupts */
1774                         if (dev_priv->mmio)     /* remove this after permanent addmaps */
1775                                 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1776
1777                         if (dev_priv->mmio) {   /* remove all surfaces */
1778                                 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1779                                         RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1780                                         RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1781                                                      16 * i, 0);
1782                                         RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1783                                                      16 * i, 0);
1784                                 }
1785                         }
1786                 }
1787
1788                 /* Free memory heap structures */
1789                 radeon_mem_takedown(&(dev_priv->gart_heap));
1790                 radeon_mem_takedown(&(dev_priv->fb_heap));
1791
1792                 /* deallocate kernel resources */
1793                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1794                         r600_do_cleanup_cp(dev);
1795                 else
1796                         radeon_do_cleanup_cp(dev);
1797                 if (dev_priv->me_fw) {
1798                         release_firmware(dev_priv->me_fw);
1799                         dev_priv->me_fw = NULL;
1800                 }
1801                 if (dev_priv->pfp_fw) {
1802                         release_firmware(dev_priv->pfp_fw);
1803                         dev_priv->pfp_fw = NULL;
1804                 }
1805         }
1806 }
1807
1808 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1809  */
1810 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1811 {
1812         drm_radeon_private_t *dev_priv = dev->dev_private;
1813         DRM_DEBUG("\n");
1814
1815         LOCK_TEST_WITH_RETURN(dev, file_priv);
1816
1817         if (!dev_priv) {
1818                 DRM_DEBUG("called before init done\n");
1819                 return -EINVAL;
1820         }
1821
1822         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1823                 r600_do_cp_reset(dev_priv);
1824         else
1825                 radeon_do_cp_reset(dev_priv);
1826
1827         /* The CP is no longer running after an engine reset */
1828         dev_priv->cp_running = 0;
1829
1830         return 0;
1831 }
1832
1833 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1834 {
1835         drm_radeon_private_t *dev_priv = dev->dev_private;
1836         DRM_DEBUG("\n");
1837
1838         LOCK_TEST_WITH_RETURN(dev, file_priv);
1839
1840         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1841                 return r600_do_cp_idle(dev_priv);
1842         else
1843                 return radeon_do_cp_idle(dev_priv);
1844 }
1845
1846 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1847  */
1848 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1849 {
1850         drm_radeon_private_t *dev_priv = dev->dev_private;
1851         DRM_DEBUG("\n");
1852
1853         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1854                 return r600_do_resume_cp(dev, file_priv);
1855         else
1856                 return radeon_do_resume_cp(dev, file_priv);
1857 }
1858
1859 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1860 {
1861         drm_radeon_private_t *dev_priv = dev->dev_private;
1862         DRM_DEBUG("\n");
1863
1864         LOCK_TEST_WITH_RETURN(dev, file_priv);
1865
1866         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1867                 return r600_do_engine_reset(dev);
1868         else
1869                 return radeon_do_engine_reset(dev);
1870 }
1871
1872 /* ================================================================
1873  * Fullscreen mode
1874  */
1875
1876 /* KW: Deprecated to say the least:
1877  */
1878 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1879 {
1880         return 0;
1881 }
1882
1883 /* ================================================================
1884  * Freelist management
1885  */
1886
1887 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1888  *   bufs until freelist code is used.  Note this hides a problem with
1889  *   the scratch register * (used to keep track of last buffer
1890  *   completed) being written to before * the last buffer has actually
1891  *   completed rendering.
1892  *
1893  * KW:  It's also a good way to find free buffers quickly.
1894  *
1895  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1896  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1897  * we essentially have to do this, else old clients will break.
1898  *
1899  * However, it does leave open a potential deadlock where all the
1900  * buffers are held by other clients, which can't release them because
1901  * they can't get the lock.
1902  */
1903
1904 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1905 {
1906         struct drm_device_dma *dma = dev->dma;
1907         drm_radeon_private_t *dev_priv = dev->dev_private;
1908         drm_radeon_buf_priv_t *buf_priv;
1909         struct drm_buf *buf;
1910         int i, t;
1911         int start;
1912
1913         if (++dev_priv->last_buf >= dma->buf_count)
1914                 dev_priv->last_buf = 0;
1915
1916         start = dev_priv->last_buf;
1917
1918         for (t = 0; t < dev_priv->usec_timeout; t++) {
1919                 u32 done_age = GET_SCRATCH(dev_priv, 1);
1920                 DRM_DEBUG("done_age = %d\n", done_age);
1921                 for (i = start; i < dma->buf_count; i++) {
1922                         buf = dma->buflist[i];
1923                         buf_priv = buf->dev_private;
1924                         if (buf->file_priv == NULL || (buf->pending &&
1925                                                        buf_priv->age <=
1926                                                        done_age)) {
1927                                 dev_priv->stats.requested_bufs++;
1928                                 buf->pending = 0;
1929                                 return buf;
1930                         }
1931                         start = 0;
1932                 }
1933
1934                 if (t) {
1935                         DRM_UDELAY(1);
1936                         dev_priv->stats.freelist_loops++;
1937                 }
1938         }
1939
1940         DRM_DEBUG("returning NULL!\n");
1941         return NULL;
1942 }
1943
1944 #if 0
1945 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1946 {
1947         struct drm_device_dma *dma = dev->dma;
1948         drm_radeon_private_t *dev_priv = dev->dev_private;
1949         drm_radeon_buf_priv_t *buf_priv;
1950         struct drm_buf *buf;
1951         int i, t;
1952         int start;
1953         u32 done_age;
1954
1955         done_age = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
1956         if (++dev_priv->last_buf >= dma->buf_count)
1957                 dev_priv->last_buf = 0;
1958
1959         start = dev_priv->last_buf;
1960         dev_priv->stats.freelist_loops++;
1961
1962         for (t = 0; t < 2; t++) {
1963                 for (i = start; i < dma->buf_count; i++) {
1964                         buf = dma->buflist[i];
1965                         buf_priv = buf->dev_private;
1966                         if (buf->file_priv == 0 || (buf->pending &&
1967                                                     buf_priv->age <=
1968                                                     done_age)) {
1969                                 dev_priv->stats.requested_bufs++;
1970                                 buf->pending = 0;
1971                                 return buf;
1972                         }
1973                 }
1974                 start = 0;
1975         }
1976
1977         return NULL;
1978 }
1979 #endif
1980
1981 void radeon_freelist_reset(struct drm_device * dev)
1982 {
1983         struct drm_device_dma *dma = dev->dma;
1984         drm_radeon_private_t *dev_priv = dev->dev_private;
1985         int i;
1986
1987         dev_priv->last_buf = 0;
1988         for (i = 0; i < dma->buf_count; i++) {
1989                 struct drm_buf *buf = dma->buflist[i];
1990                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1991                 buf_priv->age = 0;
1992         }
1993 }
1994
1995 /* ================================================================
1996  * CP command submission
1997  */
1998
1999 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
2000 {
2001         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
2002         int i;
2003         u32 last_head = GET_RING_HEAD(dev_priv);
2004
2005         for (i = 0; i < dev_priv->usec_timeout; i++) {
2006                 u32 head = GET_RING_HEAD(dev_priv);
2007
2008                 ring->space = (head - ring->tail) * sizeof(u32);
2009                 if (ring->space <= 0)
2010                         ring->space += ring->size;
2011                 if (ring->space > n)
2012                         return 0;
2013
2014                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
2015
2016                 if (head != last_head)
2017                         i = 0;
2018                 last_head = head;
2019
2020                 DRM_UDELAY(1);
2021         }
2022
2023         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
2024 #if RADEON_FIFO_DEBUG
2025         radeon_status(dev_priv);
2026         DRM_ERROR("failed!\n");
2027 #endif
2028         return -EBUSY;
2029 }
2030
2031 static int radeon_cp_get_buffers(struct drm_device *dev,
2032                                  struct drm_file *file_priv,
2033                                  struct drm_dma * d)
2034 {
2035         int i;
2036         struct drm_buf *buf;
2037
2038         for (i = d->granted_count; i < d->request_count; i++) {
2039                 buf = radeon_freelist_get(dev);
2040                 if (!buf)
2041                         return -EBUSY;  /* NOTE: broken client */
2042
2043                 buf->file_priv = file_priv;
2044
2045                 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
2046                                      sizeof(buf->idx)))
2047                         return -EFAULT;
2048                 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
2049                                      sizeof(buf->total)))
2050                         return -EFAULT;
2051
2052                 d->granted_count++;
2053         }
2054         return 0;
2055 }
2056
2057 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
2058 {
2059         struct drm_device_dma *dma = dev->dma;
2060         int ret = 0;
2061         struct drm_dma *d = data;
2062
2063         LOCK_TEST_WITH_RETURN(dev, file_priv);
2064
2065         /* Please don't send us buffers.
2066          */
2067         if (d->send_count != 0) {
2068                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
2069                           DRM_CURRENTPID, d->send_count);
2070                 return -EINVAL;
2071         }
2072
2073         /* We'll send you buffers.
2074          */
2075         if (d->request_count < 0 || d->request_count > dma->buf_count) {
2076                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
2077                           DRM_CURRENTPID, d->request_count, dma->buf_count);
2078                 return -EINVAL;
2079         }
2080
2081         d->granted_count = 0;
2082
2083         if (d->request_count) {
2084                 ret = radeon_cp_get_buffers(dev, file_priv, d);
2085         }
2086
2087         return ret;
2088 }
2089
2090 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
2091 {
2092         drm_radeon_private_t *dev_priv;
2093         int ret = 0;
2094
2095         dev_priv = kzalloc(sizeof(drm_radeon_private_t), GFP_KERNEL);
2096         if (dev_priv == NULL)
2097                 return -ENOMEM;
2098
2099         dev->dev_private = (void *)dev_priv;
2100         dev_priv->flags = flags;
2101
2102         switch (flags & RADEON_FAMILY_MASK) {
2103         case CHIP_R100:
2104         case CHIP_RV200:
2105         case CHIP_R200:
2106         case CHIP_R300:
2107         case CHIP_R350:
2108         case CHIP_R420:
2109         case CHIP_R423:
2110         case CHIP_RV410:
2111         case CHIP_RV515:
2112         case CHIP_R520:
2113         case CHIP_RV570:
2114         case CHIP_R580:
2115                 dev_priv->flags |= RADEON_HAS_HIERZ;
2116                 break;
2117         default:
2118                 /* all other chips have no hierarchical z buffer */
2119                 break;
2120         }
2121
2122         if (drm_device_is_agp(dev))
2123                 dev_priv->flags |= RADEON_IS_AGP;
2124         else if (drm_device_is_pcie(dev))
2125                 dev_priv->flags |= RADEON_IS_PCIE;
2126         else
2127                 dev_priv->flags |= RADEON_IS_PCI;
2128
2129         ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
2130                          drm_get_resource_len(dev, 2), _DRM_REGISTERS,
2131                          _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
2132         if (ret != 0)
2133                 return ret;
2134
2135         ret = drm_vblank_init(dev, 2);
2136         if (ret) {
2137                 radeon_driver_unload(dev);
2138                 return ret;
2139         }
2140
2141         DRM_DEBUG("%s card detected\n",
2142                   ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
2143         return ret;
2144 }
2145
2146 int radeon_master_create(struct drm_device *dev, struct drm_master *master)
2147 {
2148         struct drm_radeon_master_private *master_priv;
2149         unsigned long sareapage;
2150         int ret;
2151
2152         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
2153         if (!master_priv)
2154                 return -ENOMEM;
2155
2156         /* prebuild the SAREA */
2157         sareapage = max_t(unsigned long, SAREA_MAX, PAGE_SIZE);
2158         ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK,
2159                          &master_priv->sarea);
2160         if (ret) {
2161                 DRM_ERROR("SAREA setup failed\n");
2162                 return ret;
2163         }
2164         master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea);
2165         master_priv->sarea_priv->pfCurrentPage = 0;
2166
2167         master->driver_priv = master_priv;
2168         return 0;
2169 }
2170
2171 void radeon_master_destroy(struct drm_device *dev, struct drm_master *master)
2172 {
2173         struct drm_radeon_master_private *master_priv = master->driver_priv;
2174
2175         if (!master_priv)
2176                 return;
2177
2178         if (master_priv->sarea_priv &&
2179             master_priv->sarea_priv->pfCurrentPage != 0)
2180                 radeon_cp_dispatch_flip(dev, master);
2181
2182         master_priv->sarea_priv = NULL;
2183         if (master_priv->sarea)
2184                 drm_rmmap_locked(dev, master_priv->sarea);
2185
2186         kfree(master_priv);
2187
2188         master->driver_priv = NULL;
2189 }
2190
2191 /* Create mappings for registers and framebuffer so userland doesn't necessarily
2192  * have to find them.
2193  */
2194 int radeon_driver_firstopen(struct drm_device *dev)
2195 {
2196         int ret;
2197         drm_local_map_t *map;
2198         drm_radeon_private_t *dev_priv = dev->dev_private;
2199
2200         dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2201
2202         dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
2203         ret = drm_addmap(dev, dev_priv->fb_aper_offset,
2204                          drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
2205                          _DRM_WRITE_COMBINING, &map);
2206         if (ret != 0)
2207                 return ret;
2208
2209         return 0;
2210 }
2211
2212 int radeon_driver_unload(struct drm_device *dev)
2213 {
2214         drm_radeon_private_t *dev_priv = dev->dev_private;
2215
2216         DRM_DEBUG("\n");
2217
2218         drm_rmmap(dev, dev_priv->mmio);
2219
2220         kfree(dev_priv);
2221
2222         dev->dev_private = NULL;
2223         return 0;
2224 }
2225
2226 void radeon_commit_ring(drm_radeon_private_t *dev_priv)
2227 {
2228         int i;
2229         u32 *ring;
2230         int tail_aligned;
2231
2232         /* check if the ring is padded out to 16-dword alignment */
2233
2234         tail_aligned = dev_priv->ring.tail & (RADEON_RING_ALIGN-1);
2235         if (tail_aligned) {
2236                 int num_p2 = RADEON_RING_ALIGN - tail_aligned;
2237
2238                 ring = dev_priv->ring.start;
2239                 /* pad with some CP_PACKET2 */
2240                 for (i = 0; i < num_p2; i++)
2241                         ring[dev_priv->ring.tail + i] = CP_PACKET2();
2242
2243                 dev_priv->ring.tail += i;
2244
2245                 dev_priv->ring.space -= num_p2 * sizeof(u32);
2246         }
2247
2248         dev_priv->ring.tail &= dev_priv->ring.tail_mask;
2249
2250         DRM_MEMORYBARRIER();
2251         GET_RING_HEAD( dev_priv );
2252
2253         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
2254                 RADEON_WRITE(R600_CP_RB_WPTR, dev_priv->ring.tail);
2255                 /* read from PCI bus to ensure correct posting */
2256                 RADEON_READ(R600_CP_RB_RPTR);
2257         } else {
2258                 RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail);
2259                 /* read from PCI bus to ensure correct posting */
2260                 RADEON_READ(RADEON_CP_RB_RPTR);
2261         }
2262 }