a83d7615ba7f39b76750dff3d37640b377c1de2e
[linux-2.6.git] / drivers / gpu / drm / radeon / radeon_cp.c
1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
2 /*
3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5  * Copyright 2007 Advanced Micro Devices, Inc.
6  * All Rights Reserved.
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a
9  * copy of this software and associated documentation files (the "Software"),
10  * to deal in the Software without restriction, including without limitation
11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12  * and/or sell copies of the Software, and to permit persons to whom the
13  * Software is furnished to do so, subject to the following conditions:
14  *
15  * The above copyright notice and this permission notice (including the next
16  * paragraph) shall be included in all copies or substantial portions of the
17  * Software.
18  *
19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
22  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25  * DEALINGS IN THE SOFTWARE.
26  *
27  * Authors:
28  *    Kevin E. Martin <martin@valinux.com>
29  *    Gareth Hughes <gareth@valinux.com>
30  */
31
32 #include "drmP.h"
33 #include "drm.h"
34 #include "radeon_drm.h"
35 #include "radeon_drv.h"
36 #include "r300_reg.h"
37
38 #include "radeon_microcode.h"
39
40 #define RADEON_FIFO_DEBUG       0
41
42 static int radeon_do_cleanup_cp(struct drm_device * dev);
43 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
44
45 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
46 {
47         u32 ret;
48         RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
49         ret = RADEON_READ(R520_MC_IND_DATA);
50         RADEON_WRITE(R520_MC_IND_INDEX, 0);
51         return ret;
52 }
53
54 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
55 {
56         u32 ret;
57         RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
58         ret = RADEON_READ(RS480_NB_MC_DATA);
59         RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
60         return ret;
61 }
62
63 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
64 {
65         u32 ret;
66         RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
67         ret = RADEON_READ(RS690_MC_DATA);
68         RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
69         return ret;
70 }
71
72 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
73 {
74         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
75             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
76                 return RS690_READ_MCIND(dev_priv, addr);
77         else
78                 return RS480_READ_MCIND(dev_priv, addr);
79 }
80
81 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
82 {
83
84         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
85                 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
86         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
87                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
88                 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
89         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
90                 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
91         else
92                 return RADEON_READ(RADEON_MC_FB_LOCATION);
93 }
94
95 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
96 {
97         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
98                 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
99         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
100                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
101                 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
102         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
103                 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
104         else
105                 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
106 }
107
108 static void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
109 {
110         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
111                 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
112         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
113                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
114                 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
115         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
116                 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
117         else
118                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
119 }
120
121 static void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
122 {
123         u32 agp_base_hi = upper_32_bits(agp_base);
124         u32 agp_base_lo = agp_base & 0xffffffff;
125
126         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
127                 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
128                 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
129         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
130                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
131                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
132                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
133         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
134                 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
135                 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
136         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
137                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
138                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
139                 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
140         } else {
141                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
142                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
143                         RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
144         }
145 }
146
147 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
148 {
149         drm_radeon_private_t *dev_priv = dev->dev_private;
150
151         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
152         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
153 }
154
155 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
156 {
157         RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
158         return RADEON_READ(RADEON_PCIE_DATA);
159 }
160
161 #if RADEON_FIFO_DEBUG
162 static void radeon_status(drm_radeon_private_t * dev_priv)
163 {
164         printk("%s:\n", __func__);
165         printk("RBBM_STATUS = 0x%08x\n",
166                (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
167         printk("CP_RB_RTPR = 0x%08x\n",
168                (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
169         printk("CP_RB_WTPR = 0x%08x\n",
170                (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
171         printk("AIC_CNTL = 0x%08x\n",
172                (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
173         printk("AIC_STAT = 0x%08x\n",
174                (unsigned int)RADEON_READ(RADEON_AIC_STAT));
175         printk("AIC_PT_BASE = 0x%08x\n",
176                (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
177         printk("TLB_ADDR = 0x%08x\n",
178                (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
179         printk("TLB_DATA = 0x%08x\n",
180                (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
181 }
182 #endif
183
184 /* ================================================================
185  * Engine, FIFO control
186  */
187
188 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
189 {
190         u32 tmp;
191         int i;
192
193         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
194
195         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
196                 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
197                 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
198                 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
199
200                 for (i = 0; i < dev_priv->usec_timeout; i++) {
201                         if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
202                               & RADEON_RB3D_DC_BUSY)) {
203                                 return 0;
204                         }
205                         DRM_UDELAY(1);
206                 }
207         } else {
208                 /* don't flush or purge cache here or lockup */
209                 return 0;
210         }
211
212 #if RADEON_FIFO_DEBUG
213         DRM_ERROR("failed!\n");
214         radeon_status(dev_priv);
215 #endif
216         return -EBUSY;
217 }
218
219 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
220 {
221         int i;
222
223         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
224
225         for (i = 0; i < dev_priv->usec_timeout; i++) {
226                 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
227                              & RADEON_RBBM_FIFOCNT_MASK);
228                 if (slots >= entries)
229                         return 0;
230                 DRM_UDELAY(1);
231         }
232         DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
233                  RADEON_READ(RADEON_RBBM_STATUS),
234                  RADEON_READ(R300_VAP_CNTL_STATUS));
235
236 #if RADEON_FIFO_DEBUG
237         DRM_ERROR("failed!\n");
238         radeon_status(dev_priv);
239 #endif
240         return -EBUSY;
241 }
242
243 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
244 {
245         int i, ret;
246
247         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
248
249         ret = radeon_do_wait_for_fifo(dev_priv, 64);
250         if (ret)
251                 return ret;
252
253         for (i = 0; i < dev_priv->usec_timeout; i++) {
254                 if (!(RADEON_READ(RADEON_RBBM_STATUS)
255                       & RADEON_RBBM_ACTIVE)) {
256                         radeon_do_pixcache_flush(dev_priv);
257                         return 0;
258                 }
259                 DRM_UDELAY(1);
260         }
261         DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
262                  RADEON_READ(RADEON_RBBM_STATUS),
263                  RADEON_READ(R300_VAP_CNTL_STATUS));
264
265 #if RADEON_FIFO_DEBUG
266         DRM_ERROR("failed!\n");
267         radeon_status(dev_priv);
268 #endif
269         return -EBUSY;
270 }
271
272 static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
273 {
274         uint32_t gb_tile_config, gb_pipe_sel = 0;
275
276         /* RS4xx/RS6xx/R4xx/R5xx */
277         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
278                 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
279                 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
280         } else {
281                 /* R3xx */
282                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
283                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
284                         dev_priv->num_gb_pipes = 2;
285                 } else {
286                         /* R3Vxx */
287                         dev_priv->num_gb_pipes = 1;
288                 }
289         }
290         DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
291
292         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
293
294         switch (dev_priv->num_gb_pipes) {
295         case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
296         case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
297         case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
298         default:
299         case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
300         }
301
302         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
303                 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
304                 RADEON_WRITE(R500_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
305         }
306         RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
307         radeon_do_wait_for_idle(dev_priv);
308         RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
309         RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
310                                                R300_DC_AUTOFLUSH_ENABLE |
311                                                R300_DC_DC_DISABLE_IGNORE_PE));
312
313
314 }
315
316 /* ================================================================
317  * CP control, initialization
318  */
319
320 /* Load the microcode for the CP */
321 static void radeon_cp_load_microcode(drm_radeon_private_t * dev_priv)
322 {
323         int i;
324         DRM_DEBUG("\n");
325
326         radeon_do_wait_for_idle(dev_priv);
327
328         RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
329         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
330             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
331             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
332             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
333             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
334                 DRM_INFO("Loading R100 Microcode\n");
335                 for (i = 0; i < 256; i++) {
336                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
337                                      R100_cp_microcode[i][1]);
338                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
339                                      R100_cp_microcode[i][0]);
340                 }
341         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
342                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
343                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
344                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
345                 DRM_INFO("Loading R200 Microcode\n");
346                 for (i = 0; i < 256; i++) {
347                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
348                                      R200_cp_microcode[i][1]);
349                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
350                                      R200_cp_microcode[i][0]);
351                 }
352         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
353                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
354                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
355                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
356                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
357                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
358                 DRM_INFO("Loading R300 Microcode\n");
359                 for (i = 0; i < 256; i++) {
360                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
361                                      R300_cp_microcode[i][1]);
362                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
363                                      R300_cp_microcode[i][0]);
364                 }
365         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
366                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
367                 DRM_INFO("Loading R400 Microcode\n");
368                 for (i = 0; i < 256; i++) {
369                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
370                                      R420_cp_microcode[i][1]);
371                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
372                                      R420_cp_microcode[i][0]);
373                 }
374         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
375                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
376                 DRM_INFO("Loading RS690/RS740 Microcode\n");
377                 for (i = 0; i < 256; i++) {
378                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
379                                      RS690_cp_microcode[i][1]);
380                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
381                                      RS690_cp_microcode[i][0]);
382                 }
383         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
384                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
385                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
386                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
387                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
388                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
389                 DRM_INFO("Loading R500 Microcode\n");
390                 for (i = 0; i < 256; i++) {
391                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
392                                      R520_cp_microcode[i][1]);
393                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
394                                      R520_cp_microcode[i][0]);
395                 }
396         }
397 }
398
399 /* Flush any pending commands to the CP.  This should only be used just
400  * prior to a wait for idle, as it informs the engine that the command
401  * stream is ending.
402  */
403 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
404 {
405         DRM_DEBUG("\n");
406 #if 0
407         u32 tmp;
408
409         tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
410         RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
411 #endif
412 }
413
414 /* Wait for the CP to go idle.
415  */
416 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
417 {
418         RING_LOCALS;
419         DRM_DEBUG("\n");
420
421         BEGIN_RING(6);
422
423         RADEON_PURGE_CACHE();
424         RADEON_PURGE_ZCACHE();
425         RADEON_WAIT_UNTIL_IDLE();
426
427         ADVANCE_RING();
428         COMMIT_RING();
429
430         return radeon_do_wait_for_idle(dev_priv);
431 }
432
433 /* Start the Command Processor.
434  */
435 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
436 {
437         RING_LOCALS;
438         DRM_DEBUG("\n");
439
440         radeon_do_wait_for_idle(dev_priv);
441
442         RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
443
444         dev_priv->cp_running = 1;
445
446         BEGIN_RING(8);
447         /* isync can only be written through cp on r5xx write it here */
448         OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
449         OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
450                  RADEON_ISYNC_ANY3D_IDLE2D |
451                  RADEON_ISYNC_WAIT_IDLEGUI |
452                  RADEON_ISYNC_CPSCRATCH_IDLEGUI);
453         RADEON_PURGE_CACHE();
454         RADEON_PURGE_ZCACHE();
455         RADEON_WAIT_UNTIL_IDLE();
456         ADVANCE_RING();
457         COMMIT_RING();
458
459         dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
460 }
461
462 /* Reset the Command Processor.  This will not flush any pending
463  * commands, so you must wait for the CP command stream to complete
464  * before calling this routine.
465  */
466 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
467 {
468         u32 cur_read_ptr;
469         DRM_DEBUG("\n");
470
471         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
472         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
473         SET_RING_HEAD(dev_priv, cur_read_ptr);
474         dev_priv->ring.tail = cur_read_ptr;
475 }
476
477 /* Stop the Command Processor.  This will not flush any pending
478  * commands, so you must flush the command stream and wait for the CP
479  * to go idle before calling this routine.
480  */
481 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
482 {
483         DRM_DEBUG("\n");
484
485         RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
486
487         dev_priv->cp_running = 0;
488 }
489
490 /* Reset the engine.  This will stop the CP if it is running.
491  */
492 static int radeon_do_engine_reset(struct drm_device * dev)
493 {
494         drm_radeon_private_t *dev_priv = dev->dev_private;
495         u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
496         DRM_DEBUG("\n");
497
498         radeon_do_pixcache_flush(dev_priv);
499
500         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
501                 /* may need something similar for newer chips */
502                 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
503                 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
504
505                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
506                                                     RADEON_FORCEON_MCLKA |
507                                                     RADEON_FORCEON_MCLKB |
508                                                     RADEON_FORCEON_YCLKA |
509                                                     RADEON_FORCEON_YCLKB |
510                                                     RADEON_FORCEON_MC |
511                                                     RADEON_FORCEON_AIC));
512         }
513
514         rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
515
516         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
517                                               RADEON_SOFT_RESET_CP |
518                                               RADEON_SOFT_RESET_HI |
519                                               RADEON_SOFT_RESET_SE |
520                                               RADEON_SOFT_RESET_RE |
521                                               RADEON_SOFT_RESET_PP |
522                                               RADEON_SOFT_RESET_E2 |
523                                               RADEON_SOFT_RESET_RB));
524         RADEON_READ(RADEON_RBBM_SOFT_RESET);
525         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
526                                               ~(RADEON_SOFT_RESET_CP |
527                                                 RADEON_SOFT_RESET_HI |
528                                                 RADEON_SOFT_RESET_SE |
529                                                 RADEON_SOFT_RESET_RE |
530                                                 RADEON_SOFT_RESET_PP |
531                                                 RADEON_SOFT_RESET_E2 |
532                                                 RADEON_SOFT_RESET_RB)));
533         RADEON_READ(RADEON_RBBM_SOFT_RESET);
534
535         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
536                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
537                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
538                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
539         }
540
541         /* setup the raster pipes */
542         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
543             radeon_init_pipes(dev_priv);
544
545         /* Reset the CP ring */
546         radeon_do_cp_reset(dev_priv);
547
548         /* The CP is no longer running after an engine reset */
549         dev_priv->cp_running = 0;
550
551         /* Reset any pending vertex, indirect buffers */
552         radeon_freelist_reset(dev);
553
554         return 0;
555 }
556
557 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
558                                        drm_radeon_private_t * dev_priv)
559 {
560         u32 ring_start, cur_read_ptr;
561         u32 tmp;
562
563         /* Initialize the memory controller. With new memory map, the fb location
564          * is not changed, it should have been properly initialized already. Part
565          * of the problem is that the code below is bogus, assuming the GART is
566          * always appended to the fb which is not necessarily the case
567          */
568         if (!dev_priv->new_memmap)
569                 radeon_write_fb_location(dev_priv,
570                              ((dev_priv->gart_vm_start - 1) & 0xffff0000)
571                              | (dev_priv->fb_location >> 16));
572
573 #if __OS_HAS_AGP
574         if (dev_priv->flags & RADEON_IS_AGP) {
575                 radeon_write_agp_base(dev_priv, dev->agp->base);
576
577                 radeon_write_agp_location(dev_priv,
578                              (((dev_priv->gart_vm_start - 1 +
579                                 dev_priv->gart_size) & 0xffff0000) |
580                               (dev_priv->gart_vm_start >> 16)));
581
582                 ring_start = (dev_priv->cp_ring->offset
583                               - dev->agp->base
584                               + dev_priv->gart_vm_start);
585         } else
586 #endif
587                 ring_start = (dev_priv->cp_ring->offset
588                               - (unsigned long)dev->sg->virtual
589                               + dev_priv->gart_vm_start);
590
591         RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
592
593         /* Set the write pointer delay */
594         RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
595
596         /* Initialize the ring buffer's read and write pointers */
597         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
598         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
599         SET_RING_HEAD(dev_priv, cur_read_ptr);
600         dev_priv->ring.tail = cur_read_ptr;
601
602 #if __OS_HAS_AGP
603         if (dev_priv->flags & RADEON_IS_AGP) {
604                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
605                              dev_priv->ring_rptr->offset
606                              - dev->agp->base + dev_priv->gart_vm_start);
607         } else
608 #endif
609         {
610                 struct drm_sg_mem *entry = dev->sg;
611                 unsigned long tmp_ofs, page_ofs;
612
613                 tmp_ofs = dev_priv->ring_rptr->offset -
614                                 (unsigned long)dev->sg->virtual;
615                 page_ofs = tmp_ofs >> PAGE_SHIFT;
616
617                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR, entry->busaddr[page_ofs]);
618                 DRM_DEBUG("ring rptr: offset=0x%08lx handle=0x%08lx\n",
619                           (unsigned long)entry->busaddr[page_ofs],
620                           entry->handle + tmp_ofs);
621         }
622
623         /* Set ring buffer size */
624 #ifdef __BIG_ENDIAN
625         RADEON_WRITE(RADEON_CP_RB_CNTL,
626                      RADEON_BUF_SWAP_32BIT |
627                      (dev_priv->ring.fetch_size_l2ow << 18) |
628                      (dev_priv->ring.rptr_update_l2qw << 8) |
629                      dev_priv->ring.size_l2qw);
630 #else
631         RADEON_WRITE(RADEON_CP_RB_CNTL,
632                      (dev_priv->ring.fetch_size_l2ow << 18) |
633                      (dev_priv->ring.rptr_update_l2qw << 8) |
634                      dev_priv->ring.size_l2qw);
635 #endif
636
637
638         /* Initialize the scratch register pointer.  This will cause
639          * the scratch register values to be written out to memory
640          * whenever they are updated.
641          *
642          * We simply put this behind the ring read pointer, this works
643          * with PCI GART as well as (whatever kind of) AGP GART
644          */
645         RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
646                      + RADEON_SCRATCH_REG_OFFSET);
647
648         dev_priv->scratch = ((__volatile__ u32 *)
649                              dev_priv->ring_rptr->handle +
650                              (RADEON_SCRATCH_REG_OFFSET / sizeof(u32)));
651
652         RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
653
654         /* Turn on bus mastering */
655         tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
656         RADEON_WRITE(RADEON_BUS_CNTL, tmp);
657
658         dev_priv->sarea_priv->last_frame = dev_priv->scratch[0] = 0;
659         RADEON_WRITE(RADEON_LAST_FRAME_REG, dev_priv->sarea_priv->last_frame);
660
661         dev_priv->sarea_priv->last_dispatch = dev_priv->scratch[1] = 0;
662         RADEON_WRITE(RADEON_LAST_DISPATCH_REG,
663                      dev_priv->sarea_priv->last_dispatch);
664
665         dev_priv->sarea_priv->last_clear = dev_priv->scratch[2] = 0;
666         RADEON_WRITE(RADEON_LAST_CLEAR_REG, dev_priv->sarea_priv->last_clear);
667
668         radeon_do_wait_for_idle(dev_priv);
669
670         /* Sync everything up */
671         RADEON_WRITE(RADEON_ISYNC_CNTL,
672                      (RADEON_ISYNC_ANY2D_IDLE3D |
673                       RADEON_ISYNC_ANY3D_IDLE2D |
674                       RADEON_ISYNC_WAIT_IDLEGUI |
675                       RADEON_ISYNC_CPSCRATCH_IDLEGUI));
676
677 }
678
679 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
680 {
681         u32 tmp;
682
683         /* Start with assuming that writeback doesn't work */
684         dev_priv->writeback_works = 0;
685
686         /* Writeback doesn't seem to work everywhere, test it here and possibly
687          * enable it if it appears to work
688          */
689         DRM_WRITE32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1), 0);
690         RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
691
692         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
693                 if (DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1)) ==
694                     0xdeadbeef)
695                         break;
696                 DRM_UDELAY(1);
697         }
698
699         if (tmp < dev_priv->usec_timeout) {
700                 dev_priv->writeback_works = 1;
701                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
702         } else {
703                 dev_priv->writeback_works = 0;
704                 DRM_INFO("writeback test failed\n");
705         }
706         if (radeon_no_wb == 1) {
707                 dev_priv->writeback_works = 0;
708                 DRM_INFO("writeback forced off\n");
709         }
710
711         if (!dev_priv->writeback_works) {
712                 /* Disable writeback to avoid unnecessary bus master transfer */
713                 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
714                              RADEON_RB_NO_UPDATE);
715                 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
716         }
717 }
718
719 /* Enable or disable IGP GART on the chip */
720 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
721 {
722         u32 temp;
723
724         if (on) {
725                 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
726                           dev_priv->gart_vm_start,
727                           (long)dev_priv->gart_info.bus_addr,
728                           dev_priv->gart_size);
729
730                 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
731                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
732                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
733                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
734                                                              RS690_BLOCK_GFX_D3_EN));
735                 else
736                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
737
738                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
739                                                                RS480_VA_SIZE_32MB));
740
741                 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
742                 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
743                                                         RS480_TLB_ENABLE |
744                                                         RS480_GTW_LAC_EN |
745                                                         RS480_1LEVEL_GART));
746
747                 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
748                 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
749                 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
750
751                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
752                 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
753                                                       RS480_REQ_TYPE_SNOOP_DIS));
754
755                 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
756
757                 dev_priv->gart_size = 32*1024*1024;
758                 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
759                          0xffff0000) | (dev_priv->gart_vm_start >> 16));
760
761                 radeon_write_agp_location(dev_priv, temp);
762
763                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
764                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
765                                                                RS480_VA_SIZE_32MB));
766
767                 do {
768                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
769                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
770                                 break;
771                         DRM_UDELAY(1);
772                 } while (1);
773
774                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
775                                 RS480_GART_CACHE_INVALIDATE);
776
777                 do {
778                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
779                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
780                                 break;
781                         DRM_UDELAY(1);
782                 } while (1);
783
784                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
785         } else {
786                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
787         }
788 }
789
790 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
791 {
792         u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
793         if (on) {
794
795                 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
796                           dev_priv->gart_vm_start,
797                           (long)dev_priv->gart_info.bus_addr,
798                           dev_priv->gart_size);
799                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
800                                   dev_priv->gart_vm_start);
801                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
802                                   dev_priv->gart_info.bus_addr);
803                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
804                                   dev_priv->gart_vm_start);
805                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
806                                   dev_priv->gart_vm_start +
807                                   dev_priv->gart_size - 1);
808
809                 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
810
811                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
812                                   RADEON_PCIE_TX_GART_EN);
813         } else {
814                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
815                                   tmp & ~RADEON_PCIE_TX_GART_EN);
816         }
817 }
818
819 /* Enable or disable PCI GART on the chip */
820 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
821 {
822         u32 tmp;
823
824         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
825             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
826             (dev_priv->flags & RADEON_IS_IGPGART)) {
827                 radeon_set_igpgart(dev_priv, on);
828                 return;
829         }
830
831         if (dev_priv->flags & RADEON_IS_PCIE) {
832                 radeon_set_pciegart(dev_priv, on);
833                 return;
834         }
835
836         tmp = RADEON_READ(RADEON_AIC_CNTL);
837
838         if (on) {
839                 RADEON_WRITE(RADEON_AIC_CNTL,
840                              tmp | RADEON_PCIGART_TRANSLATE_EN);
841
842                 /* set PCI GART page-table base address
843                  */
844                 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
845
846                 /* set address range for PCI address translate
847                  */
848                 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
849                 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
850                              + dev_priv->gart_size - 1);
851
852                 /* Turn off AGP aperture -- is this required for PCI GART?
853                  */
854                 radeon_write_agp_location(dev_priv, 0xffffffc0);
855                 RADEON_WRITE(RADEON_AGP_COMMAND, 0);    /* clear AGP_COMMAND */
856         } else {
857                 RADEON_WRITE(RADEON_AIC_CNTL,
858                              tmp & ~RADEON_PCIGART_TRANSLATE_EN);
859         }
860 }
861
862 static int radeon_do_init_cp(struct drm_device * dev, drm_radeon_init_t * init)
863 {
864         drm_radeon_private_t *dev_priv = dev->dev_private;
865
866         DRM_DEBUG("\n");
867
868         /* if we require new memory map but we don't have it fail */
869         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
870                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
871                 radeon_do_cleanup_cp(dev);
872                 return -EINVAL;
873         }
874
875         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
876                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
877                 dev_priv->flags &= ~RADEON_IS_AGP;
878         } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
879                    && !init->is_pci) {
880                 DRM_DEBUG("Restoring AGP flag\n");
881                 dev_priv->flags |= RADEON_IS_AGP;
882         }
883
884         if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
885                 DRM_ERROR("PCI GART memory not allocated!\n");
886                 radeon_do_cleanup_cp(dev);
887                 return -EINVAL;
888         }
889
890         dev_priv->usec_timeout = init->usec_timeout;
891         if (dev_priv->usec_timeout < 1 ||
892             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
893                 DRM_DEBUG("TIMEOUT problem!\n");
894                 radeon_do_cleanup_cp(dev);
895                 return -EINVAL;
896         }
897
898         /* Enable vblank on CRTC1 for older X servers
899          */
900         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
901
902         switch(init->func) {
903         case RADEON_INIT_R200_CP:
904                 dev_priv->microcode_version = UCODE_R200;
905                 break;
906         case RADEON_INIT_R300_CP:
907                 dev_priv->microcode_version = UCODE_R300;
908                 break;
909         default:
910                 dev_priv->microcode_version = UCODE_R100;
911         }
912
913         dev_priv->do_boxes = 0;
914         dev_priv->cp_mode = init->cp_mode;
915
916         /* We don't support anything other than bus-mastering ring mode,
917          * but the ring can be in either AGP or PCI space for the ring
918          * read pointer.
919          */
920         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
921             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
922                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
923                 radeon_do_cleanup_cp(dev);
924                 return -EINVAL;
925         }
926
927         switch (init->fb_bpp) {
928         case 16:
929                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
930                 break;
931         case 32:
932         default:
933                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
934                 break;
935         }
936         dev_priv->front_offset = init->front_offset;
937         dev_priv->front_pitch = init->front_pitch;
938         dev_priv->back_offset = init->back_offset;
939         dev_priv->back_pitch = init->back_pitch;
940
941         switch (init->depth_bpp) {
942         case 16:
943                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
944                 break;
945         case 32:
946         default:
947                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
948                 break;
949         }
950         dev_priv->depth_offset = init->depth_offset;
951         dev_priv->depth_pitch = init->depth_pitch;
952
953         /* Hardware state for depth clears.  Remove this if/when we no
954          * longer clear the depth buffer with a 3D rectangle.  Hard-code
955          * all values to prevent unwanted 3D state from slipping through
956          * and screwing with the clear operation.
957          */
958         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
959                                            (dev_priv->color_fmt << 10) |
960                                            (dev_priv->microcode_version ==
961                                             UCODE_R100 ? RADEON_ZBLOCK16 : 0));
962
963         dev_priv->depth_clear.rb3d_zstencilcntl =
964             (dev_priv->depth_fmt |
965              RADEON_Z_TEST_ALWAYS |
966              RADEON_STENCIL_TEST_ALWAYS |
967              RADEON_STENCIL_S_FAIL_REPLACE |
968              RADEON_STENCIL_ZPASS_REPLACE |
969              RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
970
971         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
972                                          RADEON_BFACE_SOLID |
973                                          RADEON_FFACE_SOLID |
974                                          RADEON_FLAT_SHADE_VTX_LAST |
975                                          RADEON_DIFFUSE_SHADE_FLAT |
976                                          RADEON_ALPHA_SHADE_FLAT |
977                                          RADEON_SPECULAR_SHADE_FLAT |
978                                          RADEON_FOG_SHADE_FLAT |
979                                          RADEON_VTX_PIX_CENTER_OGL |
980                                          RADEON_ROUND_MODE_TRUNC |
981                                          RADEON_ROUND_PREC_8TH_PIX);
982
983
984         dev_priv->ring_offset = init->ring_offset;
985         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
986         dev_priv->buffers_offset = init->buffers_offset;
987         dev_priv->gart_textures_offset = init->gart_textures_offset;
988
989         dev_priv->sarea = drm_getsarea(dev);
990         if (!dev_priv->sarea) {
991                 DRM_ERROR("could not find sarea!\n");
992                 radeon_do_cleanup_cp(dev);
993                 return -EINVAL;
994         }
995
996         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
997         if (!dev_priv->cp_ring) {
998                 DRM_ERROR("could not find cp ring region!\n");
999                 radeon_do_cleanup_cp(dev);
1000                 return -EINVAL;
1001         }
1002         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1003         if (!dev_priv->ring_rptr) {
1004                 DRM_ERROR("could not find ring read pointer!\n");
1005                 radeon_do_cleanup_cp(dev);
1006                 return -EINVAL;
1007         }
1008         dev->agp_buffer_token = init->buffers_offset;
1009         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1010         if (!dev->agp_buffer_map) {
1011                 DRM_ERROR("could not find dma buffer region!\n");
1012                 radeon_do_cleanup_cp(dev);
1013                 return -EINVAL;
1014         }
1015
1016         if (init->gart_textures_offset) {
1017                 dev_priv->gart_textures =
1018                     drm_core_findmap(dev, init->gart_textures_offset);
1019                 if (!dev_priv->gart_textures) {
1020                         DRM_ERROR("could not find GART texture region!\n");
1021                         radeon_do_cleanup_cp(dev);
1022                         return -EINVAL;
1023                 }
1024         }
1025
1026         dev_priv->sarea_priv =
1027             (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->handle +
1028                                     init->sarea_priv_offset);
1029
1030 #if __OS_HAS_AGP
1031         if (dev_priv->flags & RADEON_IS_AGP) {
1032                 drm_core_ioremap(dev_priv->cp_ring, dev);
1033                 drm_core_ioremap(dev_priv->ring_rptr, dev);
1034                 drm_core_ioremap(dev->agp_buffer_map, dev);
1035                 if (!dev_priv->cp_ring->handle ||
1036                     !dev_priv->ring_rptr->handle ||
1037                     !dev->agp_buffer_map->handle) {
1038                         DRM_ERROR("could not find ioremap agp regions!\n");
1039                         radeon_do_cleanup_cp(dev);
1040                         return -EINVAL;
1041                 }
1042         } else
1043 #endif
1044         {
1045                 dev_priv->cp_ring->handle = (void *)dev_priv->cp_ring->offset;
1046                 dev_priv->ring_rptr->handle =
1047                     (void *)dev_priv->ring_rptr->offset;
1048                 dev->agp_buffer_map->handle =
1049                     (void *)dev->agp_buffer_map->offset;
1050
1051                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1052                           dev_priv->cp_ring->handle);
1053                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1054                           dev_priv->ring_rptr->handle);
1055                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1056                           dev->agp_buffer_map->handle);
1057         }
1058
1059         dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1060         dev_priv->fb_size =
1061                 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1062                 - dev_priv->fb_location;
1063
1064         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1065                                         ((dev_priv->front_offset
1066                                           + dev_priv->fb_location) >> 10));
1067
1068         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1069                                        ((dev_priv->back_offset
1070                                          + dev_priv->fb_location) >> 10));
1071
1072         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1073                                         ((dev_priv->depth_offset
1074                                           + dev_priv->fb_location) >> 10));
1075
1076         dev_priv->gart_size = init->gart_size;
1077
1078         /* New let's set the memory map ... */
1079         if (dev_priv->new_memmap) {
1080                 u32 base = 0;
1081
1082                 DRM_INFO("Setting GART location based on new memory map\n");
1083
1084                 /* If using AGP, try to locate the AGP aperture at the same
1085                  * location in the card and on the bus, though we have to
1086                  * align it down.
1087                  */
1088 #if __OS_HAS_AGP
1089                 if (dev_priv->flags & RADEON_IS_AGP) {
1090                         base = dev->agp->base;
1091                         /* Check if valid */
1092                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1093                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1094                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1095                                          dev->agp->base);
1096                                 base = 0;
1097                         }
1098                 }
1099 #endif
1100                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1101                 if (base == 0) {
1102                         base = dev_priv->fb_location + dev_priv->fb_size;
1103                         if (base < dev_priv->fb_location ||
1104                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1105                                 base = dev_priv->fb_location
1106                                         - dev_priv->gart_size;
1107                 }
1108                 dev_priv->gart_vm_start = base & 0xffc00000u;
1109                 if (dev_priv->gart_vm_start != base)
1110                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1111                                  base, dev_priv->gart_vm_start);
1112         } else {
1113                 DRM_INFO("Setting GART location based on old memory map\n");
1114                 dev_priv->gart_vm_start = dev_priv->fb_location +
1115                         RADEON_READ(RADEON_CONFIG_APER_SIZE);
1116         }
1117
1118 #if __OS_HAS_AGP
1119         if (dev_priv->flags & RADEON_IS_AGP)
1120                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1121                                                  - dev->agp->base
1122                                                  + dev_priv->gart_vm_start);
1123         else
1124 #endif
1125                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1126                                         - (unsigned long)dev->sg->virtual
1127                                         + dev_priv->gart_vm_start);
1128
1129         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1130         DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1131         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1132                   dev_priv->gart_buffers_offset);
1133
1134         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1135         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1136                               + init->ring_size / sizeof(u32));
1137         dev_priv->ring.size = init->ring_size;
1138         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1139
1140         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1141         dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1142
1143         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1144         dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1145         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1146
1147         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1148
1149 #if __OS_HAS_AGP
1150         if (dev_priv->flags & RADEON_IS_AGP) {
1151                 /* Turn off PCI GART */
1152                 radeon_set_pcigart(dev_priv, 0);
1153         } else
1154 #endif
1155         {
1156                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1157                 /* if we have an offset set from userspace */
1158                 if (dev_priv->pcigart_offset_set) {
1159                         dev_priv->gart_info.bus_addr =
1160                             dev_priv->pcigart_offset + dev_priv->fb_location;
1161                         dev_priv->gart_info.mapping.offset =
1162                             dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1163                         dev_priv->gart_info.mapping.size =
1164                             dev_priv->gart_info.table_size;
1165
1166                         drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1167                         dev_priv->gart_info.addr =
1168                             dev_priv->gart_info.mapping.handle;
1169
1170                         if (dev_priv->flags & RADEON_IS_PCIE)
1171                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1172                         else
1173                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1174                         dev_priv->gart_info.gart_table_location =
1175                             DRM_ATI_GART_FB;
1176
1177                         DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1178                                   dev_priv->gart_info.addr,
1179                                   dev_priv->pcigart_offset);
1180                 } else {
1181                         if (dev_priv->flags & RADEON_IS_IGPGART)
1182                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1183                         else
1184                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1185                         dev_priv->gart_info.gart_table_location =
1186                             DRM_ATI_GART_MAIN;
1187                         dev_priv->gart_info.addr = NULL;
1188                         dev_priv->gart_info.bus_addr = 0;
1189                         if (dev_priv->flags & RADEON_IS_PCIE) {
1190                                 DRM_ERROR
1191                                     ("Cannot use PCI Express without GART in FB memory\n");
1192                                 radeon_do_cleanup_cp(dev);
1193                                 return -EINVAL;
1194                         }
1195                 }
1196
1197                 if (!drm_ati_pcigart_init(dev, &dev_priv->gart_info)) {
1198                         DRM_ERROR("failed to init PCI GART!\n");
1199                         radeon_do_cleanup_cp(dev);
1200                         return -ENOMEM;
1201                 }
1202
1203                 /* Turn on PCI GART */
1204                 radeon_set_pcigart(dev_priv, 1);
1205         }
1206
1207         radeon_cp_load_microcode(dev_priv);
1208         radeon_cp_init_ring_buffer(dev, dev_priv);
1209
1210         dev_priv->last_buf = 0;
1211
1212         radeon_do_engine_reset(dev);
1213         radeon_test_writeback(dev_priv);
1214
1215         return 0;
1216 }
1217
1218 static int radeon_do_cleanup_cp(struct drm_device * dev)
1219 {
1220         drm_radeon_private_t *dev_priv = dev->dev_private;
1221         DRM_DEBUG("\n");
1222
1223         /* Make sure interrupts are disabled here because the uninstall ioctl
1224          * may not have been called from userspace and after dev_private
1225          * is freed, it's too late.
1226          */
1227         if (dev->irq_enabled)
1228                 drm_irq_uninstall(dev);
1229
1230 #if __OS_HAS_AGP
1231         if (dev_priv->flags & RADEON_IS_AGP) {
1232                 if (dev_priv->cp_ring != NULL) {
1233                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1234                         dev_priv->cp_ring = NULL;
1235                 }
1236                 if (dev_priv->ring_rptr != NULL) {
1237                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1238                         dev_priv->ring_rptr = NULL;
1239                 }
1240                 if (dev->agp_buffer_map != NULL) {
1241                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1242                         dev->agp_buffer_map = NULL;
1243                 }
1244         } else
1245 #endif
1246         {
1247
1248                 if (dev_priv->gart_info.bus_addr) {
1249                         /* Turn off PCI GART */
1250                         radeon_set_pcigart(dev_priv, 0);
1251                         if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1252                                 DRM_ERROR("failed to cleanup PCI GART!\n");
1253                 }
1254
1255                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1256                 {
1257                         drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1258                         dev_priv->gart_info.addr = 0;
1259                 }
1260         }
1261         /* only clear to the start of flags */
1262         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1263
1264         return 0;
1265 }
1266
1267 /* This code will reinit the Radeon CP hardware after a resume from disc.
1268  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1269  * here we make sure that all Radeon hardware initialisation is re-done without
1270  * affecting running applications.
1271  *
1272  * Charl P. Botha <http://cpbotha.net>
1273  */
1274 static int radeon_do_resume_cp(struct drm_device * dev)
1275 {
1276         drm_radeon_private_t *dev_priv = dev->dev_private;
1277
1278         if (!dev_priv) {
1279                 DRM_ERROR("Called with no initialization\n");
1280                 return -EINVAL;
1281         }
1282
1283         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1284
1285 #if __OS_HAS_AGP
1286         if (dev_priv->flags & RADEON_IS_AGP) {
1287                 /* Turn off PCI GART */
1288                 radeon_set_pcigart(dev_priv, 0);
1289         } else
1290 #endif
1291         {
1292                 /* Turn on PCI GART */
1293                 radeon_set_pcigart(dev_priv, 1);
1294         }
1295
1296         radeon_cp_load_microcode(dev_priv);
1297         radeon_cp_init_ring_buffer(dev, dev_priv);
1298
1299         radeon_do_engine_reset(dev);
1300         radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1301
1302         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1303
1304         return 0;
1305 }
1306
1307 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1308 {
1309         drm_radeon_init_t *init = data;
1310
1311         LOCK_TEST_WITH_RETURN(dev, file_priv);
1312
1313         if (init->func == RADEON_INIT_R300_CP)
1314                 r300_init_reg_flags(dev);
1315
1316         switch (init->func) {
1317         case RADEON_INIT_CP:
1318         case RADEON_INIT_R200_CP:
1319         case RADEON_INIT_R300_CP:
1320                 return radeon_do_init_cp(dev, init);
1321         case RADEON_CLEANUP_CP:
1322                 return radeon_do_cleanup_cp(dev);
1323         }
1324
1325         return -EINVAL;
1326 }
1327
1328 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1329 {
1330         drm_radeon_private_t *dev_priv = dev->dev_private;
1331         DRM_DEBUG("\n");
1332
1333         LOCK_TEST_WITH_RETURN(dev, file_priv);
1334
1335         if (dev_priv->cp_running) {
1336                 DRM_DEBUG("while CP running\n");
1337                 return 0;
1338         }
1339         if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1340                 DRM_DEBUG("called with bogus CP mode (%d)\n",
1341                           dev_priv->cp_mode);
1342                 return 0;
1343         }
1344
1345         radeon_do_cp_start(dev_priv);
1346
1347         return 0;
1348 }
1349
1350 /* Stop the CP.  The engine must have been idled before calling this
1351  * routine.
1352  */
1353 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1354 {
1355         drm_radeon_private_t *dev_priv = dev->dev_private;
1356         drm_radeon_cp_stop_t *stop = data;
1357         int ret;
1358         DRM_DEBUG("\n");
1359
1360         LOCK_TEST_WITH_RETURN(dev, file_priv);
1361
1362         if (!dev_priv->cp_running)
1363                 return 0;
1364
1365         /* Flush any pending CP commands.  This ensures any outstanding
1366          * commands are exectuted by the engine before we turn it off.
1367          */
1368         if (stop->flush) {
1369                 radeon_do_cp_flush(dev_priv);
1370         }
1371
1372         /* If we fail to make the engine go idle, we return an error
1373          * code so that the DRM ioctl wrapper can try again.
1374          */
1375         if (stop->idle) {
1376                 ret = radeon_do_cp_idle(dev_priv);
1377                 if (ret)
1378                         return ret;
1379         }
1380
1381         /* Finally, we can turn off the CP.  If the engine isn't idle,
1382          * we will get some dropped triangles as they won't be fully
1383          * rendered before the CP is shut down.
1384          */
1385         radeon_do_cp_stop(dev_priv);
1386
1387         /* Reset the engine */
1388         radeon_do_engine_reset(dev);
1389
1390         return 0;
1391 }
1392
1393 void radeon_do_release(struct drm_device * dev)
1394 {
1395         drm_radeon_private_t *dev_priv = dev->dev_private;
1396         int i, ret;
1397
1398         if (dev_priv) {
1399                 if (dev_priv->cp_running) {
1400                         /* Stop the cp */
1401                         while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1402                                 DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1403 #ifdef __linux__
1404                                 schedule();
1405 #else
1406                                 tsleep(&ret, PZERO, "rdnrel", 1);
1407 #endif
1408                         }
1409                         radeon_do_cp_stop(dev_priv);
1410                         radeon_do_engine_reset(dev);
1411                 }
1412
1413                 /* Disable *all* interrupts */
1414                 if (dev_priv->mmio)     /* remove this after permanent addmaps */
1415                         RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1416
1417                 if (dev_priv->mmio) {   /* remove all surfaces */
1418                         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1419                                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1420                                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1421                                              16 * i, 0);
1422                                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1423                                              16 * i, 0);
1424                         }
1425                 }
1426
1427                 /* Free memory heap structures */
1428                 radeon_mem_takedown(&(dev_priv->gart_heap));
1429                 radeon_mem_takedown(&(dev_priv->fb_heap));
1430
1431                 /* deallocate kernel resources */
1432                 radeon_do_cleanup_cp(dev);
1433         }
1434 }
1435
1436 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1437  */
1438 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1439 {
1440         drm_radeon_private_t *dev_priv = dev->dev_private;
1441         DRM_DEBUG("\n");
1442
1443         LOCK_TEST_WITH_RETURN(dev, file_priv);
1444
1445         if (!dev_priv) {
1446                 DRM_DEBUG("called before init done\n");
1447                 return -EINVAL;
1448         }
1449
1450         radeon_do_cp_reset(dev_priv);
1451
1452         /* The CP is no longer running after an engine reset */
1453         dev_priv->cp_running = 0;
1454
1455         return 0;
1456 }
1457
1458 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1459 {
1460         drm_radeon_private_t *dev_priv = dev->dev_private;
1461         DRM_DEBUG("\n");
1462
1463         LOCK_TEST_WITH_RETURN(dev, file_priv);
1464
1465         return radeon_do_cp_idle(dev_priv);
1466 }
1467
1468 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1469  */
1470 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1471 {
1472
1473         return radeon_do_resume_cp(dev);
1474 }
1475
1476 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1477 {
1478         DRM_DEBUG("\n");
1479
1480         LOCK_TEST_WITH_RETURN(dev, file_priv);
1481
1482         return radeon_do_engine_reset(dev);
1483 }
1484
1485 /* ================================================================
1486  * Fullscreen mode
1487  */
1488
1489 /* KW: Deprecated to say the least:
1490  */
1491 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1492 {
1493         return 0;
1494 }
1495
1496 /* ================================================================
1497  * Freelist management
1498  */
1499
1500 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1501  *   bufs until freelist code is used.  Note this hides a problem with
1502  *   the scratch register * (used to keep track of last buffer
1503  *   completed) being written to before * the last buffer has actually
1504  *   completed rendering.
1505  *
1506  * KW:  It's also a good way to find free buffers quickly.
1507  *
1508  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1509  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1510  * we essentially have to do this, else old clients will break.
1511  *
1512  * However, it does leave open a potential deadlock where all the
1513  * buffers are held by other clients, which can't release them because
1514  * they can't get the lock.
1515  */
1516
1517 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1518 {
1519         struct drm_device_dma *dma = dev->dma;
1520         drm_radeon_private_t *dev_priv = dev->dev_private;
1521         drm_radeon_buf_priv_t *buf_priv;
1522         struct drm_buf *buf;
1523         int i, t;
1524         int start;
1525
1526         if (++dev_priv->last_buf >= dma->buf_count)
1527                 dev_priv->last_buf = 0;
1528
1529         start = dev_priv->last_buf;
1530
1531         for (t = 0; t < dev_priv->usec_timeout; t++) {
1532                 u32 done_age = GET_SCRATCH(1);
1533                 DRM_DEBUG("done_age = %d\n", done_age);
1534                 for (i = start; i < dma->buf_count; i++) {
1535                         buf = dma->buflist[i];
1536                         buf_priv = buf->dev_private;
1537                         if (buf->file_priv == NULL || (buf->pending &&
1538                                                        buf_priv->age <=
1539                                                        done_age)) {
1540                                 dev_priv->stats.requested_bufs++;
1541                                 buf->pending = 0;
1542                                 return buf;
1543                         }
1544                         start = 0;
1545                 }
1546
1547                 if (t) {
1548                         DRM_UDELAY(1);
1549                         dev_priv->stats.freelist_loops++;
1550                 }
1551         }
1552
1553         DRM_DEBUG("returning NULL!\n");
1554         return NULL;
1555 }
1556
1557 #if 0
1558 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1559 {
1560         struct drm_device_dma *dma = dev->dma;
1561         drm_radeon_private_t *dev_priv = dev->dev_private;
1562         drm_radeon_buf_priv_t *buf_priv;
1563         struct drm_buf *buf;
1564         int i, t;
1565         int start;
1566         u32 done_age = DRM_READ32(dev_priv->ring_rptr, RADEON_SCRATCHOFF(1));
1567
1568         if (++dev_priv->last_buf >= dma->buf_count)
1569                 dev_priv->last_buf = 0;
1570
1571         start = dev_priv->last_buf;
1572         dev_priv->stats.freelist_loops++;
1573
1574         for (t = 0; t < 2; t++) {
1575                 for (i = start; i < dma->buf_count; i++) {
1576                         buf = dma->buflist[i];
1577                         buf_priv = buf->dev_private;
1578                         if (buf->file_priv == 0 || (buf->pending &&
1579                                                     buf_priv->age <=
1580                                                     done_age)) {
1581                                 dev_priv->stats.requested_bufs++;
1582                                 buf->pending = 0;
1583                                 return buf;
1584                         }
1585                 }
1586                 start = 0;
1587         }
1588
1589         return NULL;
1590 }
1591 #endif
1592
1593 void radeon_freelist_reset(struct drm_device * dev)
1594 {
1595         struct drm_device_dma *dma = dev->dma;
1596         drm_radeon_private_t *dev_priv = dev->dev_private;
1597         int i;
1598
1599         dev_priv->last_buf = 0;
1600         for (i = 0; i < dma->buf_count; i++) {
1601                 struct drm_buf *buf = dma->buflist[i];
1602                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
1603                 buf_priv->age = 0;
1604         }
1605 }
1606
1607 /* ================================================================
1608  * CP command submission
1609  */
1610
1611 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
1612 {
1613         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
1614         int i;
1615         u32 last_head = GET_RING_HEAD(dev_priv);
1616
1617         for (i = 0; i < dev_priv->usec_timeout; i++) {
1618                 u32 head = GET_RING_HEAD(dev_priv);
1619
1620                 ring->space = (head - ring->tail) * sizeof(u32);
1621                 if (ring->space <= 0)
1622                         ring->space += ring->size;
1623                 if (ring->space > n)
1624                         return 0;
1625
1626                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
1627
1628                 if (head != last_head)
1629                         i = 0;
1630                 last_head = head;
1631
1632                 DRM_UDELAY(1);
1633         }
1634
1635         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
1636 #if RADEON_FIFO_DEBUG
1637         radeon_status(dev_priv);
1638         DRM_ERROR("failed!\n");
1639 #endif
1640         return -EBUSY;
1641 }
1642
1643 static int radeon_cp_get_buffers(struct drm_device *dev,
1644                                  struct drm_file *file_priv,
1645                                  struct drm_dma * d)
1646 {
1647         int i;
1648         struct drm_buf *buf;
1649
1650         for (i = d->granted_count; i < d->request_count; i++) {
1651                 buf = radeon_freelist_get(dev);
1652                 if (!buf)
1653                         return -EBUSY;  /* NOTE: broken client */
1654
1655                 buf->file_priv = file_priv;
1656
1657                 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
1658                                      sizeof(buf->idx)))
1659                         return -EFAULT;
1660                 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
1661                                      sizeof(buf->total)))
1662                         return -EFAULT;
1663
1664                 d->granted_count++;
1665         }
1666         return 0;
1667 }
1668
1669 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1670 {
1671         struct drm_device_dma *dma = dev->dma;
1672         int ret = 0;
1673         struct drm_dma *d = data;
1674
1675         LOCK_TEST_WITH_RETURN(dev, file_priv);
1676
1677         /* Please don't send us buffers.
1678          */
1679         if (d->send_count != 0) {
1680                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1681                           DRM_CURRENTPID, d->send_count);
1682                 return -EINVAL;
1683         }
1684
1685         /* We'll send you buffers.
1686          */
1687         if (d->request_count < 0 || d->request_count > dma->buf_count) {
1688                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1689                           DRM_CURRENTPID, d->request_count, dma->buf_count);
1690                 return -EINVAL;
1691         }
1692
1693         d->granted_count = 0;
1694
1695         if (d->request_count) {
1696                 ret = radeon_cp_get_buffers(dev, file_priv, d);
1697         }
1698
1699         return ret;
1700 }
1701
1702 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
1703 {
1704         drm_radeon_private_t *dev_priv;
1705         int ret = 0;
1706
1707         dev_priv = drm_alloc(sizeof(drm_radeon_private_t), DRM_MEM_DRIVER);
1708         if (dev_priv == NULL)
1709                 return -ENOMEM;
1710
1711         memset(dev_priv, 0, sizeof(drm_radeon_private_t));
1712         dev->dev_private = (void *)dev_priv;
1713         dev_priv->flags = flags;
1714
1715         switch (flags & RADEON_FAMILY_MASK) {
1716         case CHIP_R100:
1717         case CHIP_RV200:
1718         case CHIP_R200:
1719         case CHIP_R300:
1720         case CHIP_R350:
1721         case CHIP_R420:
1722         case CHIP_RV410:
1723         case CHIP_RV515:
1724         case CHIP_R520:
1725         case CHIP_RV570:
1726         case CHIP_R580:
1727                 dev_priv->flags |= RADEON_HAS_HIERZ;
1728                 break;
1729         default:
1730                 /* all other chips have no hierarchical z buffer */
1731                 break;
1732         }
1733
1734         if (drm_device_is_agp(dev))
1735                 dev_priv->flags |= RADEON_IS_AGP;
1736         else if (drm_device_is_pcie(dev))
1737                 dev_priv->flags |= RADEON_IS_PCIE;
1738         else
1739                 dev_priv->flags |= RADEON_IS_PCI;
1740
1741         DRM_DEBUG("%s card detected\n",
1742                   ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
1743         return ret;
1744 }
1745
1746 /* Create mappings for registers and framebuffer so userland doesn't necessarily
1747  * have to find them.
1748  */
1749 int radeon_driver_firstopen(struct drm_device *dev)
1750 {
1751         int ret;
1752         drm_local_map_t *map;
1753         drm_radeon_private_t *dev_priv = dev->dev_private;
1754
1755         dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
1756
1757         ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
1758                          drm_get_resource_len(dev, 2), _DRM_REGISTERS,
1759                          _DRM_READ_ONLY, &dev_priv->mmio);
1760         if (ret != 0)
1761                 return ret;
1762
1763         dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
1764         ret = drm_addmap(dev, dev_priv->fb_aper_offset,
1765                          drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
1766                          _DRM_WRITE_COMBINING, &map);
1767         if (ret != 0)
1768                 return ret;
1769
1770         return 0;
1771 }
1772
1773 int radeon_driver_unload(struct drm_device *dev)
1774 {
1775         drm_radeon_private_t *dev_priv = dev->dev_private;
1776
1777         DRM_DEBUG("\n");
1778         drm_free(dev_priv, sizeof(*dev_priv), DRM_MEM_DRIVER);
1779
1780         dev->dev_private = NULL;
1781         return 0;
1782 }