drm/radeon: some r420s have a CP race with the DMA engine.
[linux-2.6.git] / drivers / gpu / drm / radeon / radeon_cp.c
1 /* radeon_cp.c -- CP support for Radeon -*- linux-c -*- */
2 /*
3  * Copyright 2000 Precision Insight, Inc., Cedar Park, Texas.
4  * Copyright 2000 VA Linux Systems, Inc., Fremont, California.
5  * Copyright 2007 Advanced Micro Devices, Inc.
6  * All Rights Reserved.
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a
9  * copy of this software and associated documentation files (the "Software"),
10  * to deal in the Software without restriction, including without limitation
11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12  * and/or sell copies of the Software, and to permit persons to whom the
13  * Software is furnished to do so, subject to the following conditions:
14  *
15  * The above copyright notice and this permission notice (including the next
16  * paragraph) shall be included in all copies or substantial portions of the
17  * Software.
18  *
19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
22  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25  * DEALINGS IN THE SOFTWARE.
26  *
27  * Authors:
28  *    Kevin E. Martin <martin@valinux.com>
29  *    Gareth Hughes <gareth@valinux.com>
30  */
31
32 #include "drmP.h"
33 #include "drm.h"
34 #include "drm_sarea.h"
35 #include "radeon_drm.h"
36 #include "radeon_drv.h"
37 #include "r300_reg.h"
38
39 #define RADEON_FIFO_DEBUG       0
40
41 /* Firmware Names */
42 #define FIRMWARE_R100           "radeon/R100_cp.bin"
43 #define FIRMWARE_R200           "radeon/R200_cp.bin"
44 #define FIRMWARE_R300           "radeon/R300_cp.bin"
45 #define FIRMWARE_R420           "radeon/R420_cp.bin"
46 #define FIRMWARE_RS690          "radeon/RS690_cp.bin"
47 #define FIRMWARE_RS600          "radeon/RS600_cp.bin"
48 #define FIRMWARE_R520           "radeon/R520_cp.bin"
49
50 MODULE_FIRMWARE(FIRMWARE_R100);
51 MODULE_FIRMWARE(FIRMWARE_R200);
52 MODULE_FIRMWARE(FIRMWARE_R300);
53 MODULE_FIRMWARE(FIRMWARE_R420);
54 MODULE_FIRMWARE(FIRMWARE_RS690);
55 MODULE_FIRMWARE(FIRMWARE_RS600);
56 MODULE_FIRMWARE(FIRMWARE_R520);
57
58 static int radeon_do_cleanup_cp(struct drm_device * dev);
59 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv);
60
61 u32 radeon_read_ring_rptr(drm_radeon_private_t *dev_priv, u32 off)
62 {
63         u32 val;
64
65         if (dev_priv->flags & RADEON_IS_AGP) {
66                 val = DRM_READ32(dev_priv->ring_rptr, off);
67         } else {
68                 val = *(((volatile u32 *)
69                          dev_priv->ring_rptr->handle) +
70                         (off / sizeof(u32)));
71                 val = le32_to_cpu(val);
72         }
73         return val;
74 }
75
76 u32 radeon_get_ring_head(drm_radeon_private_t *dev_priv)
77 {
78         if (dev_priv->writeback_works)
79                 return radeon_read_ring_rptr(dev_priv, 0);
80         else {
81                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
82                         return RADEON_READ(R600_CP_RB_RPTR);
83                 else
84                         return RADEON_READ(RADEON_CP_RB_RPTR);
85         }
86 }
87
88 void radeon_write_ring_rptr(drm_radeon_private_t *dev_priv, u32 off, u32 val)
89 {
90         if (dev_priv->flags & RADEON_IS_AGP)
91                 DRM_WRITE32(dev_priv->ring_rptr, off, val);
92         else
93                 *(((volatile u32 *) dev_priv->ring_rptr->handle) +
94                   (off / sizeof(u32))) = cpu_to_le32(val);
95 }
96
97 void radeon_set_ring_head(drm_radeon_private_t *dev_priv, u32 val)
98 {
99         radeon_write_ring_rptr(dev_priv, 0, val);
100 }
101
102 u32 radeon_get_scratch(drm_radeon_private_t *dev_priv, int index)
103 {
104         if (dev_priv->writeback_works) {
105                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
106                         return radeon_read_ring_rptr(dev_priv,
107                                                      R600_SCRATCHOFF(index));
108                 else
109                         return radeon_read_ring_rptr(dev_priv,
110                                                      RADEON_SCRATCHOFF(index));
111         } else {
112                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
113                         return RADEON_READ(R600_SCRATCH_REG0 + 4*index);
114                 else
115                         return RADEON_READ(RADEON_SCRATCH_REG0 + 4*index);
116         }
117 }
118
119 u32 RADEON_READ_MM(drm_radeon_private_t *dev_priv, int addr)
120 {
121         u32 ret;
122
123         if (addr < 0x10000)
124                 ret = DRM_READ32(dev_priv->mmio, addr);
125         else {
126                 DRM_WRITE32(dev_priv->mmio, RADEON_MM_INDEX, addr);
127                 ret = DRM_READ32(dev_priv->mmio, RADEON_MM_DATA);
128         }
129
130         return ret;
131 }
132
133 static u32 R500_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
134 {
135         u32 ret;
136         RADEON_WRITE(R520_MC_IND_INDEX, 0x7f0000 | (addr & 0xff));
137         ret = RADEON_READ(R520_MC_IND_DATA);
138         RADEON_WRITE(R520_MC_IND_INDEX, 0);
139         return ret;
140 }
141
142 static u32 RS480_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
143 {
144         u32 ret;
145         RADEON_WRITE(RS480_NB_MC_INDEX, addr & 0xff);
146         ret = RADEON_READ(RS480_NB_MC_DATA);
147         RADEON_WRITE(RS480_NB_MC_INDEX, 0xff);
148         return ret;
149 }
150
151 static u32 RS690_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
152 {
153         u32 ret;
154         RADEON_WRITE(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK));
155         ret = RADEON_READ(RS690_MC_DATA);
156         RADEON_WRITE(RS690_MC_INDEX, RS690_MC_INDEX_MASK);
157         return ret;
158 }
159
160 static u32 RS600_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
161 {
162         u32 ret;
163         RADEON_WRITE(RS600_MC_INDEX, ((addr & RS600_MC_ADDR_MASK) |
164                                       RS600_MC_IND_CITF_ARB0));
165         ret = RADEON_READ(RS600_MC_DATA);
166         return ret;
167 }
168
169 static u32 IGP_READ_MCIND(drm_radeon_private_t *dev_priv, int addr)
170 {
171         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
172             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
173                 return RS690_READ_MCIND(dev_priv, addr);
174         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
175                 return RS600_READ_MCIND(dev_priv, addr);
176         else
177                 return RS480_READ_MCIND(dev_priv, addr);
178 }
179
180 u32 radeon_read_fb_location(drm_radeon_private_t *dev_priv)
181 {
182
183         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
184                 return RADEON_READ(R700_MC_VM_FB_LOCATION);
185         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
186                 return RADEON_READ(R600_MC_VM_FB_LOCATION);
187         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
188                 return R500_READ_MCIND(dev_priv, RV515_MC_FB_LOCATION);
189         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
190                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
191                 return RS690_READ_MCIND(dev_priv, RS690_MC_FB_LOCATION);
192         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
193                 return RS600_READ_MCIND(dev_priv, RS600_MC_FB_LOCATION);
194         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
195                 return R500_READ_MCIND(dev_priv, R520_MC_FB_LOCATION);
196         else
197                 return RADEON_READ(RADEON_MC_FB_LOCATION);
198 }
199
200 static void radeon_write_fb_location(drm_radeon_private_t *dev_priv, u32 fb_loc)
201 {
202         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
203                 RADEON_WRITE(R700_MC_VM_FB_LOCATION, fb_loc);
204         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
205                 RADEON_WRITE(R600_MC_VM_FB_LOCATION, fb_loc);
206         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
207                 R500_WRITE_MCIND(RV515_MC_FB_LOCATION, fb_loc);
208         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
209                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
210                 RS690_WRITE_MCIND(RS690_MC_FB_LOCATION, fb_loc);
211         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
212                 RS600_WRITE_MCIND(RS600_MC_FB_LOCATION, fb_loc);
213         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
214                 R500_WRITE_MCIND(R520_MC_FB_LOCATION, fb_loc);
215         else
216                 RADEON_WRITE(RADEON_MC_FB_LOCATION, fb_loc);
217 }
218
219 void radeon_write_agp_location(drm_radeon_private_t *dev_priv, u32 agp_loc)
220 {
221         /*R6xx/R7xx: AGP_TOP and BOT are actually 18 bits each */
222         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
223                 RADEON_WRITE(R700_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
224                 RADEON_WRITE(R700_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
225         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
226                 RADEON_WRITE(R600_MC_VM_AGP_BOT, agp_loc & 0xffff); /* FIX ME */
227                 RADEON_WRITE(R600_MC_VM_AGP_TOP, (agp_loc >> 16) & 0xffff);
228         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515)
229                 R500_WRITE_MCIND(RV515_MC_AGP_LOCATION, agp_loc);
230         else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
231                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
232                 RS690_WRITE_MCIND(RS690_MC_AGP_LOCATION, agp_loc);
233         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
234                 RS600_WRITE_MCIND(RS600_MC_AGP_LOCATION, agp_loc);
235         else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515)
236                 R500_WRITE_MCIND(R520_MC_AGP_LOCATION, agp_loc);
237         else
238                 RADEON_WRITE(RADEON_MC_AGP_LOCATION, agp_loc);
239 }
240
241 void radeon_write_agp_base(drm_radeon_private_t *dev_priv, u64 agp_base)
242 {
243         u32 agp_base_hi = upper_32_bits(agp_base);
244         u32 agp_base_lo = agp_base & 0xffffffff;
245         u32 r6xx_agp_base = (agp_base >> 22) & 0x3ffff;
246
247         /* R6xx/R7xx must be aligned to a 4MB boundry */
248         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
249                 RADEON_WRITE(R700_MC_VM_AGP_BASE, r6xx_agp_base);
250         else if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
251                 RADEON_WRITE(R600_MC_VM_AGP_BASE, r6xx_agp_base);
252         else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) {
253                 R500_WRITE_MCIND(RV515_MC_AGP_BASE, agp_base_lo);
254                 R500_WRITE_MCIND(RV515_MC_AGP_BASE_2, agp_base_hi);
255         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
256                  ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
257                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE, agp_base_lo);
258                 RS690_WRITE_MCIND(RS690_MC_AGP_BASE_2, agp_base_hi);
259         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
260                 RS600_WRITE_MCIND(RS600_AGP_BASE, agp_base_lo);
261                 RS600_WRITE_MCIND(RS600_AGP_BASE_2, agp_base_hi);
262         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_RV515) {
263                 R500_WRITE_MCIND(R520_MC_AGP_BASE, agp_base_lo);
264                 R500_WRITE_MCIND(R520_MC_AGP_BASE_2, agp_base_hi);
265         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
266                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
267                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
268                 RADEON_WRITE(RS480_AGP_BASE_2, agp_base_hi);
269         } else {
270                 RADEON_WRITE(RADEON_AGP_BASE, agp_base_lo);
271                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R200)
272                         RADEON_WRITE(RADEON_AGP_BASE_2, agp_base_hi);
273         }
274 }
275
276 void radeon_enable_bm(struct drm_radeon_private *dev_priv)
277 {
278         u32 tmp;
279         /* Turn on bus mastering */
280         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
281             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
282                 /* rs600/rs690/rs740 */
283                 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS;
284                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
285         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV350) ||
286                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
287                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
288                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
289                 /* r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
290                 tmp = RADEON_READ(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
291                 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
292         } /* PCIE cards appears to not need this */
293 }
294
295 static int RADEON_READ_PLL(struct drm_device * dev, int addr)
296 {
297         drm_radeon_private_t *dev_priv = dev->dev_private;
298
299         RADEON_WRITE8(RADEON_CLOCK_CNTL_INDEX, addr & 0x1f);
300         return RADEON_READ(RADEON_CLOCK_CNTL_DATA);
301 }
302
303 static u32 RADEON_READ_PCIE(drm_radeon_private_t *dev_priv, int addr)
304 {
305         RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff);
306         return RADEON_READ(RADEON_PCIE_DATA);
307 }
308
309 #if RADEON_FIFO_DEBUG
310 static void radeon_status(drm_radeon_private_t * dev_priv)
311 {
312         printk("%s:\n", __func__);
313         printk("RBBM_STATUS = 0x%08x\n",
314                (unsigned int)RADEON_READ(RADEON_RBBM_STATUS));
315         printk("CP_RB_RTPR = 0x%08x\n",
316                (unsigned int)RADEON_READ(RADEON_CP_RB_RPTR));
317         printk("CP_RB_WTPR = 0x%08x\n",
318                (unsigned int)RADEON_READ(RADEON_CP_RB_WPTR));
319         printk("AIC_CNTL = 0x%08x\n",
320                (unsigned int)RADEON_READ(RADEON_AIC_CNTL));
321         printk("AIC_STAT = 0x%08x\n",
322                (unsigned int)RADEON_READ(RADEON_AIC_STAT));
323         printk("AIC_PT_BASE = 0x%08x\n",
324                (unsigned int)RADEON_READ(RADEON_AIC_PT_BASE));
325         printk("TLB_ADDR = 0x%08x\n",
326                (unsigned int)RADEON_READ(RADEON_AIC_TLB_ADDR));
327         printk("TLB_DATA = 0x%08x\n",
328                (unsigned int)RADEON_READ(RADEON_AIC_TLB_DATA));
329 }
330 #endif
331
332 /* ================================================================
333  * Engine, FIFO control
334  */
335
336 static int radeon_do_pixcache_flush(drm_radeon_private_t * dev_priv)
337 {
338         u32 tmp;
339         int i;
340
341         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
342
343         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV280) {
344                 tmp = RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT);
345                 tmp |= RADEON_RB3D_DC_FLUSH_ALL;
346                 RADEON_WRITE(RADEON_RB3D_DSTCACHE_CTLSTAT, tmp);
347
348                 for (i = 0; i < dev_priv->usec_timeout; i++) {
349                         if (!(RADEON_READ(RADEON_RB3D_DSTCACHE_CTLSTAT)
350                               & RADEON_RB3D_DC_BUSY)) {
351                                 return 0;
352                         }
353                         DRM_UDELAY(1);
354                 }
355         } else {
356                 /* don't flush or purge cache here or lockup */
357                 return 0;
358         }
359
360 #if RADEON_FIFO_DEBUG
361         DRM_ERROR("failed!\n");
362         radeon_status(dev_priv);
363 #endif
364         return -EBUSY;
365 }
366
367 static int radeon_do_wait_for_fifo(drm_radeon_private_t * dev_priv, int entries)
368 {
369         int i;
370
371         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
372
373         for (i = 0; i < dev_priv->usec_timeout; i++) {
374                 int slots = (RADEON_READ(RADEON_RBBM_STATUS)
375                              & RADEON_RBBM_FIFOCNT_MASK);
376                 if (slots >= entries)
377                         return 0;
378                 DRM_UDELAY(1);
379         }
380         DRM_DEBUG("wait for fifo failed status : 0x%08X 0x%08X\n",
381                  RADEON_READ(RADEON_RBBM_STATUS),
382                  RADEON_READ(R300_VAP_CNTL_STATUS));
383
384 #if RADEON_FIFO_DEBUG
385         DRM_ERROR("failed!\n");
386         radeon_status(dev_priv);
387 #endif
388         return -EBUSY;
389 }
390
391 static int radeon_do_wait_for_idle(drm_radeon_private_t * dev_priv)
392 {
393         int i, ret;
394
395         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
396
397         ret = radeon_do_wait_for_fifo(dev_priv, 64);
398         if (ret)
399                 return ret;
400
401         for (i = 0; i < dev_priv->usec_timeout; i++) {
402                 if (!(RADEON_READ(RADEON_RBBM_STATUS)
403                       & RADEON_RBBM_ACTIVE)) {
404                         radeon_do_pixcache_flush(dev_priv);
405                         return 0;
406                 }
407                 DRM_UDELAY(1);
408         }
409         DRM_DEBUG("wait idle failed status : 0x%08X 0x%08X\n",
410                  RADEON_READ(RADEON_RBBM_STATUS),
411                  RADEON_READ(R300_VAP_CNTL_STATUS));
412
413 #if RADEON_FIFO_DEBUG
414         DRM_ERROR("failed!\n");
415         radeon_status(dev_priv);
416 #endif
417         return -EBUSY;
418 }
419
420 static void radeon_init_pipes(drm_radeon_private_t *dev_priv)
421 {
422         uint32_t gb_tile_config, gb_pipe_sel = 0;
423
424         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) {
425                 uint32_t z_pipe_sel = RADEON_READ(RV530_GB_PIPE_SELECT2);
426                 if ((z_pipe_sel & 3) == 3)
427                         dev_priv->num_z_pipes = 2;
428                 else
429                         dev_priv->num_z_pipes = 1;
430         } else
431                 dev_priv->num_z_pipes = 1;
432
433         /* RS4xx/RS6xx/R4xx/R5xx */
434         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R420) {
435                 gb_pipe_sel = RADEON_READ(R400_GB_PIPE_SELECT);
436                 dev_priv->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1;
437         } else {
438                 /* R3xx */
439                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
440                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350)) {
441                         dev_priv->num_gb_pipes = 2;
442                 } else {
443                         /* R3Vxx */
444                         dev_priv->num_gb_pipes = 1;
445                 }
446         }
447         DRM_INFO("Num pipes: %d\n", dev_priv->num_gb_pipes);
448
449         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16 /*| R300_SUBPIXEL_1_16*/);
450
451         switch (dev_priv->num_gb_pipes) {
452         case 2: gb_tile_config |= R300_PIPE_COUNT_R300; break;
453         case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break;
454         case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break;
455         default:
456         case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break;
457         }
458
459         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
460                 RADEON_WRITE_PLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4));
461                 RADEON_WRITE(R300_SU_REG_DEST, ((1 << dev_priv->num_gb_pipes) - 1));
462         }
463         RADEON_WRITE(R300_GB_TILE_CONFIG, gb_tile_config);
464         radeon_do_wait_for_idle(dev_priv);
465         RADEON_WRITE(R300_DST_PIPE_CONFIG, RADEON_READ(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG);
466         RADEON_WRITE(R300_RB2D_DSTCACHE_MODE, (RADEON_READ(R300_RB2D_DSTCACHE_MODE) |
467                                                R300_DC_AUTOFLUSH_ENABLE |
468                                                R300_DC_DC_DISABLE_IGNORE_PE));
469
470
471 }
472
473 /* ================================================================
474  * CP control, initialization
475  */
476
477 /* Load the microcode for the CP */
478 static int radeon_cp_init_microcode(drm_radeon_private_t *dev_priv)
479 {
480         struct platform_device *pdev;
481         const char *fw_name = NULL;
482         int err;
483
484         DRM_DEBUG("\n");
485
486         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
487         err = IS_ERR(pdev);
488         if (err) {
489                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
490                 return -EINVAL;
491         }
492
493         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R100) ||
494             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV100) ||
495             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV200) ||
496             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS100) ||
497             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS200)) {
498                 DRM_INFO("Loading R100 Microcode\n");
499                 fw_name = FIRMWARE_R100;
500         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R200) ||
501                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV250) ||
502                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV280) ||
503                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS300)) {
504                 DRM_INFO("Loading R200 Microcode\n");
505                 fw_name = FIRMWARE_R200;
506         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R300) ||
507                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R350) ||
508                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV350) ||
509                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV380) ||
510                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS400) ||
511                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS480)) {
512                 DRM_INFO("Loading R300 Microcode\n");
513                 fw_name = FIRMWARE_R300;
514         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) ||
515                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R423) ||
516                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV410)) {
517                 DRM_INFO("Loading R400 Microcode\n");
518                 fw_name = FIRMWARE_R420;
519         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
520                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740)) {
521                 DRM_INFO("Loading RS690/RS740 Microcode\n");
522                 fw_name = FIRMWARE_RS690;
523         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
524                 DRM_INFO("Loading RS600 Microcode\n");
525                 fw_name = FIRMWARE_RS600;
526         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV515) ||
527                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R520) ||
528                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530) ||
529                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R580) ||
530                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV560) ||
531                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV570)) {
532                 DRM_INFO("Loading R500 Microcode\n");
533                 fw_name = FIRMWARE_R520;
534         }
535
536         err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev);
537         platform_device_unregister(pdev);
538         if (err) {
539                 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
540                        fw_name);
541         } else if (dev_priv->me_fw->size % 8) {
542                 printk(KERN_ERR
543                        "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
544                        dev_priv->me_fw->size, fw_name);
545                 err = -EINVAL;
546                 release_firmware(dev_priv->me_fw);
547                 dev_priv->me_fw = NULL;
548         }
549         return err;
550 }
551
552 static void radeon_cp_load_microcode(drm_radeon_private_t *dev_priv)
553 {
554         const __be32 *fw_data;
555         int i, size;
556
557         radeon_do_wait_for_idle(dev_priv);
558
559         if (dev_priv->me_fw) {
560                 size = dev_priv->me_fw->size / 4;
561                 fw_data = (const __be32 *)&dev_priv->me_fw->data[0];
562                 RADEON_WRITE(RADEON_CP_ME_RAM_ADDR, 0);
563                 for (i = 0; i < size; i += 2) {
564                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAH,
565                                      be32_to_cpup(&fw_data[i]));
566                         RADEON_WRITE(RADEON_CP_ME_RAM_DATAL,
567                                      be32_to_cpup(&fw_data[i + 1]));
568                 }
569         }
570 }
571
572 /* Flush any pending commands to the CP.  This should only be used just
573  * prior to a wait for idle, as it informs the engine that the command
574  * stream is ending.
575  */
576 static void radeon_do_cp_flush(drm_radeon_private_t * dev_priv)
577 {
578         DRM_DEBUG("\n");
579 #if 0
580         u32 tmp;
581
582         tmp = RADEON_READ(RADEON_CP_RB_WPTR) | (1 << 31);
583         RADEON_WRITE(RADEON_CP_RB_WPTR, tmp);
584 #endif
585 }
586
587 /* Wait for the CP to go idle.
588  */
589 int radeon_do_cp_idle(drm_radeon_private_t * dev_priv)
590 {
591         RING_LOCALS;
592         DRM_DEBUG("\n");
593
594         BEGIN_RING(6);
595
596         RADEON_PURGE_CACHE();
597         RADEON_PURGE_ZCACHE();
598         RADEON_WAIT_UNTIL_IDLE();
599
600         ADVANCE_RING();
601         COMMIT_RING();
602
603         return radeon_do_wait_for_idle(dev_priv);
604 }
605
606 /* Start the Command Processor.
607  */
608 static void radeon_do_cp_start(drm_radeon_private_t * dev_priv)
609 {
610         RING_LOCALS;
611         DRM_DEBUG("\n");
612
613         radeon_do_wait_for_idle(dev_priv);
614
615         RADEON_WRITE(RADEON_CP_CSQ_CNTL, dev_priv->cp_mode);
616
617         dev_priv->cp_running = 1;
618
619         /* on r420, any DMA from CP to system memory while 2D is active
620          * can cause a hang.  workaround is to queue a CP RESYNC token
621          */
622         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) {
623                 BEGIN_RING(3);
624                 OUT_RING(CP_PACKET0(R300_CP_RESYNC_ADDR, 1));
625                 OUT_RING(5); /* scratch reg 5 */
626                 OUT_RING(0xdeadbeef);
627                 ADVANCE_RING();
628                 COMMIT_RING();
629         }
630
631         BEGIN_RING(8);
632         /* isync can only be written through cp on r5xx write it here */
633         OUT_RING(CP_PACKET0(RADEON_ISYNC_CNTL, 0));
634         OUT_RING(RADEON_ISYNC_ANY2D_IDLE3D |
635                  RADEON_ISYNC_ANY3D_IDLE2D |
636                  RADEON_ISYNC_WAIT_IDLEGUI |
637                  RADEON_ISYNC_CPSCRATCH_IDLEGUI);
638         RADEON_PURGE_CACHE();
639         RADEON_PURGE_ZCACHE();
640         RADEON_WAIT_UNTIL_IDLE();
641         ADVANCE_RING();
642         COMMIT_RING();
643
644         dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
645 }
646
647 /* Reset the Command Processor.  This will not flush any pending
648  * commands, so you must wait for the CP command stream to complete
649  * before calling this routine.
650  */
651 static void radeon_do_cp_reset(drm_radeon_private_t * dev_priv)
652 {
653         u32 cur_read_ptr;
654         DRM_DEBUG("\n");
655
656         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
657         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
658         SET_RING_HEAD(dev_priv, cur_read_ptr);
659         dev_priv->ring.tail = cur_read_ptr;
660 }
661
662 /* Stop the Command Processor.  This will not flush any pending
663  * commands, so you must flush the command stream and wait for the CP
664  * to go idle before calling this routine.
665  */
666 static void radeon_do_cp_stop(drm_radeon_private_t * dev_priv)
667 {
668         RING_LOCALS;
669         DRM_DEBUG("\n");
670
671         /* finish the pending CP_RESYNC token */
672         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R420) {
673                 BEGIN_RING(2);
674                 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
675                 OUT_RING(R300_RB3D_DC_FINISH);
676                 ADVANCE_RING();
677                 COMMIT_RING();
678                 radeon_do_wait_for_idle(dev_priv);
679         }
680
681         RADEON_WRITE(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIDIS_INDDIS);
682
683         dev_priv->cp_running = 0;
684 }
685
686 /* Reset the engine.  This will stop the CP if it is running.
687  */
688 static int radeon_do_engine_reset(struct drm_device * dev)
689 {
690         drm_radeon_private_t *dev_priv = dev->dev_private;
691         u32 clock_cntl_index = 0, mclk_cntl = 0, rbbm_soft_reset;
692         DRM_DEBUG("\n");
693
694         radeon_do_pixcache_flush(dev_priv);
695
696         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
697                 /* may need something similar for newer chips */
698                 clock_cntl_index = RADEON_READ(RADEON_CLOCK_CNTL_INDEX);
699                 mclk_cntl = RADEON_READ_PLL(dev, RADEON_MCLK_CNTL);
700
701                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, (mclk_cntl |
702                                                     RADEON_FORCEON_MCLKA |
703                                                     RADEON_FORCEON_MCLKB |
704                                                     RADEON_FORCEON_YCLKA |
705                                                     RADEON_FORCEON_YCLKB |
706                                                     RADEON_FORCEON_MC |
707                                                     RADEON_FORCEON_AIC));
708         }
709
710         rbbm_soft_reset = RADEON_READ(RADEON_RBBM_SOFT_RESET);
711
712         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset |
713                                               RADEON_SOFT_RESET_CP |
714                                               RADEON_SOFT_RESET_HI |
715                                               RADEON_SOFT_RESET_SE |
716                                               RADEON_SOFT_RESET_RE |
717                                               RADEON_SOFT_RESET_PP |
718                                               RADEON_SOFT_RESET_E2 |
719                                               RADEON_SOFT_RESET_RB));
720         RADEON_READ(RADEON_RBBM_SOFT_RESET);
721         RADEON_WRITE(RADEON_RBBM_SOFT_RESET, (rbbm_soft_reset &
722                                               ~(RADEON_SOFT_RESET_CP |
723                                                 RADEON_SOFT_RESET_HI |
724                                                 RADEON_SOFT_RESET_SE |
725                                                 RADEON_SOFT_RESET_RE |
726                                                 RADEON_SOFT_RESET_PP |
727                                                 RADEON_SOFT_RESET_E2 |
728                                                 RADEON_SOFT_RESET_RB)));
729         RADEON_READ(RADEON_RBBM_SOFT_RESET);
730
731         if ((dev_priv->flags & RADEON_FAMILY_MASK) <= CHIP_RV410) {
732                 RADEON_WRITE_PLL(RADEON_MCLK_CNTL, mclk_cntl);
733                 RADEON_WRITE(RADEON_CLOCK_CNTL_INDEX, clock_cntl_index);
734                 RADEON_WRITE(RADEON_RBBM_SOFT_RESET, rbbm_soft_reset);
735         }
736
737         /* setup the raster pipes */
738         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R300)
739             radeon_init_pipes(dev_priv);
740
741         /* Reset the CP ring */
742         radeon_do_cp_reset(dev_priv);
743
744         /* The CP is no longer running after an engine reset */
745         dev_priv->cp_running = 0;
746
747         /* Reset any pending vertex, indirect buffers */
748         radeon_freelist_reset(dev);
749
750         return 0;
751 }
752
753 static void radeon_cp_init_ring_buffer(struct drm_device * dev,
754                                        drm_radeon_private_t *dev_priv,
755                                        struct drm_file *file_priv)
756 {
757         struct drm_radeon_master_private *master_priv;
758         u32 ring_start, cur_read_ptr;
759
760         /* Initialize the memory controller. With new memory map, the fb location
761          * is not changed, it should have been properly initialized already. Part
762          * of the problem is that the code below is bogus, assuming the GART is
763          * always appended to the fb which is not necessarily the case
764          */
765         if (!dev_priv->new_memmap)
766                 radeon_write_fb_location(dev_priv,
767                              ((dev_priv->gart_vm_start - 1) & 0xffff0000)
768                              | (dev_priv->fb_location >> 16));
769
770 #if __OS_HAS_AGP
771         if (dev_priv->flags & RADEON_IS_AGP) {
772                 radeon_write_agp_base(dev_priv, dev->agp->base);
773
774                 radeon_write_agp_location(dev_priv,
775                              (((dev_priv->gart_vm_start - 1 +
776                                 dev_priv->gart_size) & 0xffff0000) |
777                               (dev_priv->gart_vm_start >> 16)));
778
779                 ring_start = (dev_priv->cp_ring->offset
780                               - dev->agp->base
781                               + dev_priv->gart_vm_start);
782         } else
783 #endif
784                 ring_start = (dev_priv->cp_ring->offset
785                               - (unsigned long)dev->sg->virtual
786                               + dev_priv->gart_vm_start);
787
788         RADEON_WRITE(RADEON_CP_RB_BASE, ring_start);
789
790         /* Set the write pointer delay */
791         RADEON_WRITE(RADEON_CP_RB_WPTR_DELAY, 0);
792
793         /* Initialize the ring buffer's read and write pointers */
794         cur_read_ptr = RADEON_READ(RADEON_CP_RB_RPTR);
795         RADEON_WRITE(RADEON_CP_RB_WPTR, cur_read_ptr);
796         SET_RING_HEAD(dev_priv, cur_read_ptr);
797         dev_priv->ring.tail = cur_read_ptr;
798
799 #if __OS_HAS_AGP
800         if (dev_priv->flags & RADEON_IS_AGP) {
801                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
802                              dev_priv->ring_rptr->offset
803                              - dev->agp->base + dev_priv->gart_vm_start);
804         } else
805 #endif
806         {
807                 RADEON_WRITE(RADEON_CP_RB_RPTR_ADDR,
808                              dev_priv->ring_rptr->offset
809                              - ((unsigned long) dev->sg->virtual)
810                              + dev_priv->gart_vm_start);
811         }
812
813         /* Set ring buffer size */
814 #ifdef __BIG_ENDIAN
815         RADEON_WRITE(RADEON_CP_RB_CNTL,
816                      RADEON_BUF_SWAP_32BIT |
817                      (dev_priv->ring.fetch_size_l2ow << 18) |
818                      (dev_priv->ring.rptr_update_l2qw << 8) |
819                      dev_priv->ring.size_l2qw);
820 #else
821         RADEON_WRITE(RADEON_CP_RB_CNTL,
822                      (dev_priv->ring.fetch_size_l2ow << 18) |
823                      (dev_priv->ring.rptr_update_l2qw << 8) |
824                      dev_priv->ring.size_l2qw);
825 #endif
826
827
828         /* Initialize the scratch register pointer.  This will cause
829          * the scratch register values to be written out to memory
830          * whenever they are updated.
831          *
832          * We simply put this behind the ring read pointer, this works
833          * with PCI GART as well as (whatever kind of) AGP GART
834          */
835         RADEON_WRITE(RADEON_SCRATCH_ADDR, RADEON_READ(RADEON_CP_RB_RPTR_ADDR)
836                      + RADEON_SCRATCH_REG_OFFSET);
837
838         RADEON_WRITE(RADEON_SCRATCH_UMSK, 0x7);
839
840         radeon_enable_bm(dev_priv);
841
842         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(0), 0);
843         RADEON_WRITE(RADEON_LAST_FRAME_REG, 0);
844
845         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
846         RADEON_WRITE(RADEON_LAST_DISPATCH_REG, 0);
847
848         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(2), 0);
849         RADEON_WRITE(RADEON_LAST_CLEAR_REG, 0);
850
851         /* reset sarea copies of these */
852         master_priv = file_priv->master->driver_priv;
853         if (master_priv->sarea_priv) {
854                 master_priv->sarea_priv->last_frame = 0;
855                 master_priv->sarea_priv->last_dispatch = 0;
856                 master_priv->sarea_priv->last_clear = 0;
857         }
858
859         radeon_do_wait_for_idle(dev_priv);
860
861         /* Sync everything up */
862         RADEON_WRITE(RADEON_ISYNC_CNTL,
863                      (RADEON_ISYNC_ANY2D_IDLE3D |
864                       RADEON_ISYNC_ANY3D_IDLE2D |
865                       RADEON_ISYNC_WAIT_IDLEGUI |
866                       RADEON_ISYNC_CPSCRATCH_IDLEGUI));
867
868 }
869
870 static void radeon_test_writeback(drm_radeon_private_t * dev_priv)
871 {
872         u32 tmp;
873
874         /* Start with assuming that writeback doesn't work */
875         dev_priv->writeback_works = 0;
876
877         /* Writeback doesn't seem to work everywhere, test it here and possibly
878          * enable it if it appears to work
879          */
880         radeon_write_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1), 0);
881
882         RADEON_WRITE(RADEON_SCRATCH_REG1, 0xdeadbeef);
883
884         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
885                 u32 val;
886
887                 val = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
888                 if (val == 0xdeadbeef)
889                         break;
890                 DRM_UDELAY(1);
891         }
892
893         if (tmp < dev_priv->usec_timeout) {
894                 dev_priv->writeback_works = 1;
895                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
896         } else {
897                 dev_priv->writeback_works = 0;
898                 DRM_INFO("writeback test failed\n");
899         }
900         if (radeon_no_wb == 1) {
901                 dev_priv->writeback_works = 0;
902                 DRM_INFO("writeback forced off\n");
903         }
904
905         if (!dev_priv->writeback_works) {
906                 /* Disable writeback to avoid unnecessary bus master transfer */
907                 RADEON_WRITE(RADEON_CP_RB_CNTL, RADEON_READ(RADEON_CP_RB_CNTL) |
908                              RADEON_RB_NO_UPDATE);
909                 RADEON_WRITE(RADEON_SCRATCH_UMSK, 0);
910         }
911 }
912
913 /* Enable or disable IGP GART on the chip */
914 static void radeon_set_igpgart(drm_radeon_private_t * dev_priv, int on)
915 {
916         u32 temp;
917
918         if (on) {
919                 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
920                           dev_priv->gart_vm_start,
921                           (long)dev_priv->gart_info.bus_addr,
922                           dev_priv->gart_size);
923
924                 temp = IGP_READ_MCIND(dev_priv, RS480_MC_MISC_CNTL);
925                 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
926                     ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740))
927                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, (RS480_GART_INDEX_REG_EN |
928                                                              RS690_BLOCK_GFX_D3_EN));
929                 else
930                         IGP_WRITE_MCIND(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN);
931
932                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
933                                                                RS480_VA_SIZE_32MB));
934
935                 temp = IGP_READ_MCIND(dev_priv, RS480_GART_FEATURE_ID);
936                 IGP_WRITE_MCIND(RS480_GART_FEATURE_ID, (RS480_HANG_EN |
937                                                         RS480_TLB_ENABLE |
938                                                         RS480_GTW_LAC_EN |
939                                                         RS480_1LEVEL_GART));
940
941                 temp = dev_priv->gart_info.bus_addr & 0xfffff000;
942                 temp |= (upper_32_bits(dev_priv->gart_info.bus_addr) & 0xff) << 4;
943                 IGP_WRITE_MCIND(RS480_GART_BASE, temp);
944
945                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_MODE_CNTL);
946                 IGP_WRITE_MCIND(RS480_AGP_MODE_CNTL, ((1 << RS480_REQ_TYPE_SNOOP_SHIFT) |
947                                                       RS480_REQ_TYPE_SNOOP_DIS));
948
949                 radeon_write_agp_base(dev_priv, dev_priv->gart_vm_start);
950
951                 dev_priv->gart_size = 32*1024*1024;
952                 temp = (((dev_priv->gart_vm_start - 1 + dev_priv->gart_size) &
953                          0xffff0000) | (dev_priv->gart_vm_start >> 16));
954
955                 radeon_write_agp_location(dev_priv, temp);
956
957                 temp = IGP_READ_MCIND(dev_priv, RS480_AGP_ADDRESS_SPACE_SIZE);
958                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN |
959                                                                RS480_VA_SIZE_32MB));
960
961                 do {
962                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
963                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
964                                 break;
965                         DRM_UDELAY(1);
966                 } while (1);
967
968                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL,
969                                 RS480_GART_CACHE_INVALIDATE);
970
971                 do {
972                         temp = IGP_READ_MCIND(dev_priv, RS480_GART_CACHE_CNTRL);
973                         if ((temp & RS480_GART_CACHE_INVALIDATE) == 0)
974                                 break;
975                         DRM_UDELAY(1);
976                 } while (1);
977
978                 IGP_WRITE_MCIND(RS480_GART_CACHE_CNTRL, 0);
979         } else {
980                 IGP_WRITE_MCIND(RS480_AGP_ADDRESS_SPACE_SIZE, 0);
981         }
982 }
983
984 /* Enable or disable IGP GART on the chip */
985 static void rs600_set_igpgart(drm_radeon_private_t *dev_priv, int on)
986 {
987         u32 temp;
988         int i;
989
990         if (on) {
991                 DRM_DEBUG("programming igp gart %08X %08lX %08X\n",
992                          dev_priv->gart_vm_start,
993                          (long)dev_priv->gart_info.bus_addr,
994                          dev_priv->gart_size);
995
996                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (RS600_EFFECTIVE_L2_CACHE_SIZE(6) |
997                                                     RS600_EFFECTIVE_L2_QUEUE_SIZE(6)));
998
999                 for (i = 0; i < 19; i++)
1000                         IGP_WRITE_MCIND(RS600_MC_PT0_CLIENT0_CNTL + i,
1001                                         (RS600_ENABLE_TRANSLATION_MODE_OVERRIDE |
1002                                          RS600_SYSTEM_ACCESS_MODE_IN_SYS |
1003                                          RS600_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASSTHROUGH |
1004                                          RS600_EFFECTIVE_L1_CACHE_SIZE(3) |
1005                                          RS600_ENABLE_FRAGMENT_PROCESSING |
1006                                          RS600_EFFECTIVE_L1_QUEUE_SIZE(3)));
1007
1008                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL, (RS600_ENABLE_PAGE_TABLE |
1009                                                              RS600_PAGE_TABLE_TYPE_FLAT));
1010
1011                 /* disable all other contexts */
1012                 for (i = 1; i < 8; i++)
1013                         IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_CNTL + i, 0);
1014
1015                 /* setup the page table aperture */
1016                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_BASE_ADDR,
1017                                 dev_priv->gart_info.bus_addr);
1018                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_START_ADDR,
1019                                 dev_priv->gart_vm_start);
1020                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_FLAT_END_ADDR,
1021                                 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
1022                 IGP_WRITE_MCIND(RS600_MC_PT0_CONTEXT0_DEFAULT_READ_ADDR, 0);
1023
1024                 /* setup the system aperture */
1025                 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_LOW_ADDR,
1026                                 dev_priv->gart_vm_start);
1027                 IGP_WRITE_MCIND(RS600_MC_PT0_SYSTEM_APERTURE_HIGH_ADDR,
1028                                 (dev_priv->gart_vm_start + dev_priv->gart_size - 1));
1029
1030                 /* enable page tables */
1031                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1032                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, (temp | RS600_ENABLE_PT));
1033
1034                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
1035                 IGP_WRITE_MCIND(RS600_MC_CNTL1, (temp | RS600_ENABLE_PAGE_TABLES));
1036
1037                 /* invalidate the cache */
1038                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1039
1040                 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
1041                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1042                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1043
1044                 temp |= RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE;
1045                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1046                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1047
1048                 temp &= ~(RS600_INVALIDATE_ALL_L1_TLBS | RS600_INVALIDATE_L2_CACHE);
1049                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, temp);
1050                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_PT0_CNTL);
1051
1052         } else {
1053                 IGP_WRITE_MCIND(RS600_MC_PT0_CNTL, 0);
1054                 temp = IGP_READ_MCIND(dev_priv, RS600_MC_CNTL1);
1055                 temp &= ~RS600_ENABLE_PAGE_TABLES;
1056                 IGP_WRITE_MCIND(RS600_MC_CNTL1, temp);
1057         }
1058 }
1059
1060 static void radeon_set_pciegart(drm_radeon_private_t * dev_priv, int on)
1061 {
1062         u32 tmp = RADEON_READ_PCIE(dev_priv, RADEON_PCIE_TX_GART_CNTL);
1063         if (on) {
1064
1065                 DRM_DEBUG("programming pcie %08X %08lX %08X\n",
1066                           dev_priv->gart_vm_start,
1067                           (long)dev_priv->gart_info.bus_addr,
1068                           dev_priv->gart_size);
1069                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO,
1070                                   dev_priv->gart_vm_start);
1071                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE,
1072                                   dev_priv->gart_info.bus_addr);
1073                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO,
1074                                   dev_priv->gart_vm_start);
1075                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO,
1076                                   dev_priv->gart_vm_start +
1077                                   dev_priv->gart_size - 1);
1078
1079                 radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */
1080
1081                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1082                                   RADEON_PCIE_TX_GART_EN);
1083         } else {
1084                 RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL,
1085                                   tmp & ~RADEON_PCIE_TX_GART_EN);
1086         }
1087 }
1088
1089 /* Enable or disable PCI GART on the chip */
1090 static void radeon_set_pcigart(drm_radeon_private_t * dev_priv, int on)
1091 {
1092         u32 tmp;
1093
1094         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS690) ||
1095             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS740) ||
1096             (dev_priv->flags & RADEON_IS_IGPGART)) {
1097                 radeon_set_igpgart(dev_priv, on);
1098                 return;
1099         }
1100
1101         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600) {
1102                 rs600_set_igpgart(dev_priv, on);
1103                 return;
1104         }
1105
1106         if (dev_priv->flags & RADEON_IS_PCIE) {
1107                 radeon_set_pciegart(dev_priv, on);
1108                 return;
1109         }
1110
1111         tmp = RADEON_READ(RADEON_AIC_CNTL);
1112
1113         if (on) {
1114                 RADEON_WRITE(RADEON_AIC_CNTL,
1115                              tmp | RADEON_PCIGART_TRANSLATE_EN);
1116
1117                 /* set PCI GART page-table base address
1118                  */
1119                 RADEON_WRITE(RADEON_AIC_PT_BASE, dev_priv->gart_info.bus_addr);
1120
1121                 /* set address range for PCI address translate
1122                  */
1123                 RADEON_WRITE(RADEON_AIC_LO_ADDR, dev_priv->gart_vm_start);
1124                 RADEON_WRITE(RADEON_AIC_HI_ADDR, dev_priv->gart_vm_start
1125                              + dev_priv->gart_size - 1);
1126
1127                 /* Turn off AGP aperture -- is this required for PCI GART?
1128                  */
1129                 radeon_write_agp_location(dev_priv, 0xffffffc0);
1130                 RADEON_WRITE(RADEON_AGP_COMMAND, 0);    /* clear AGP_COMMAND */
1131         } else {
1132                 RADEON_WRITE(RADEON_AIC_CNTL,
1133                              tmp & ~RADEON_PCIGART_TRANSLATE_EN);
1134         }
1135 }
1136
1137 static int radeon_setup_pcigart_surface(drm_radeon_private_t *dev_priv)
1138 {
1139         struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
1140         struct radeon_virt_surface *vp;
1141         int i;
1142
1143         for (i = 0; i < RADEON_MAX_SURFACES * 2; i++) {
1144                 if (!dev_priv->virt_surfaces[i].file_priv ||
1145                     dev_priv->virt_surfaces[i].file_priv == PCIGART_FILE_PRIV)
1146                         break;
1147         }
1148         if (i >= 2 * RADEON_MAX_SURFACES)
1149                 return -ENOMEM;
1150         vp = &dev_priv->virt_surfaces[i];
1151
1152         for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1153                 struct radeon_surface *sp = &dev_priv->surfaces[i];
1154                 if (sp->refcount)
1155                         continue;
1156
1157                 vp->surface_index = i;
1158                 vp->lower = gart_info->bus_addr;
1159                 vp->upper = vp->lower + gart_info->table_size;
1160                 vp->flags = 0;
1161                 vp->file_priv = PCIGART_FILE_PRIV;
1162
1163                 sp->refcount = 1;
1164                 sp->lower = vp->lower;
1165                 sp->upper = vp->upper;
1166                 sp->flags = 0;
1167
1168                 RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, sp->flags);
1169                 RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND + 16 * i, sp->lower);
1170                 RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND + 16 * i, sp->upper);
1171                 return 0;
1172         }
1173
1174         return -ENOMEM;
1175 }
1176
1177 static int radeon_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1178                              struct drm_file *file_priv)
1179 {
1180         drm_radeon_private_t *dev_priv = dev->dev_private;
1181         struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
1182
1183         DRM_DEBUG("\n");
1184
1185         /* if we require new memory map but we don't have it fail */
1186         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1187                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1188                 radeon_do_cleanup_cp(dev);
1189                 return -EINVAL;
1190         }
1191
1192         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1193                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1194                 dev_priv->flags &= ~RADEON_IS_AGP;
1195         } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1196                    && !init->is_pci) {
1197                 DRM_DEBUG("Restoring AGP flag\n");
1198                 dev_priv->flags |= RADEON_IS_AGP;
1199         }
1200
1201         if ((!(dev_priv->flags & RADEON_IS_AGP)) && !dev->sg) {
1202                 DRM_ERROR("PCI GART memory not allocated!\n");
1203                 radeon_do_cleanup_cp(dev);
1204                 return -EINVAL;
1205         }
1206
1207         dev_priv->usec_timeout = init->usec_timeout;
1208         if (dev_priv->usec_timeout < 1 ||
1209             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1210                 DRM_DEBUG("TIMEOUT problem!\n");
1211                 radeon_do_cleanup_cp(dev);
1212                 return -EINVAL;
1213         }
1214
1215         /* Enable vblank on CRTC1 for older X servers
1216          */
1217         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1218
1219         switch(init->func) {
1220         case RADEON_INIT_R200_CP:
1221                 dev_priv->microcode_version = UCODE_R200;
1222                 break;
1223         case RADEON_INIT_R300_CP:
1224                 dev_priv->microcode_version = UCODE_R300;
1225                 break;
1226         default:
1227                 dev_priv->microcode_version = UCODE_R100;
1228         }
1229
1230         dev_priv->do_boxes = 0;
1231         dev_priv->cp_mode = init->cp_mode;
1232
1233         /* We don't support anything other than bus-mastering ring mode,
1234          * but the ring can be in either AGP or PCI space for the ring
1235          * read pointer.
1236          */
1237         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1238             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1239                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1240                 radeon_do_cleanup_cp(dev);
1241                 return -EINVAL;
1242         }
1243
1244         switch (init->fb_bpp) {
1245         case 16:
1246                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1247                 break;
1248         case 32:
1249         default:
1250                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1251                 break;
1252         }
1253         dev_priv->front_offset = init->front_offset;
1254         dev_priv->front_pitch = init->front_pitch;
1255         dev_priv->back_offset = init->back_offset;
1256         dev_priv->back_pitch = init->back_pitch;
1257
1258         switch (init->depth_bpp) {
1259         case 16:
1260                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_16BIT_INT_Z;
1261                 break;
1262         case 32:
1263         default:
1264                 dev_priv->depth_fmt = RADEON_DEPTH_FORMAT_24BIT_INT_Z;
1265                 break;
1266         }
1267         dev_priv->depth_offset = init->depth_offset;
1268         dev_priv->depth_pitch = init->depth_pitch;
1269
1270         /* Hardware state for depth clears.  Remove this if/when we no
1271          * longer clear the depth buffer with a 3D rectangle.  Hard-code
1272          * all values to prevent unwanted 3D state from slipping through
1273          * and screwing with the clear operation.
1274          */
1275         dev_priv->depth_clear.rb3d_cntl = (RADEON_PLANE_MASK_ENABLE |
1276                                            (dev_priv->color_fmt << 10) |
1277                                            (dev_priv->microcode_version ==
1278                                             UCODE_R100 ? RADEON_ZBLOCK16 : 0));
1279
1280         dev_priv->depth_clear.rb3d_zstencilcntl =
1281             (dev_priv->depth_fmt |
1282              RADEON_Z_TEST_ALWAYS |
1283              RADEON_STENCIL_TEST_ALWAYS |
1284              RADEON_STENCIL_S_FAIL_REPLACE |
1285              RADEON_STENCIL_ZPASS_REPLACE |
1286              RADEON_STENCIL_ZFAIL_REPLACE | RADEON_Z_WRITE_ENABLE);
1287
1288         dev_priv->depth_clear.se_cntl = (RADEON_FFACE_CULL_CW |
1289                                          RADEON_BFACE_SOLID |
1290                                          RADEON_FFACE_SOLID |
1291                                          RADEON_FLAT_SHADE_VTX_LAST |
1292                                          RADEON_DIFFUSE_SHADE_FLAT |
1293                                          RADEON_ALPHA_SHADE_FLAT |
1294                                          RADEON_SPECULAR_SHADE_FLAT |
1295                                          RADEON_FOG_SHADE_FLAT |
1296                                          RADEON_VTX_PIX_CENTER_OGL |
1297                                          RADEON_ROUND_MODE_TRUNC |
1298                                          RADEON_ROUND_PREC_8TH_PIX);
1299
1300
1301         dev_priv->ring_offset = init->ring_offset;
1302         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1303         dev_priv->buffers_offset = init->buffers_offset;
1304         dev_priv->gart_textures_offset = init->gart_textures_offset;
1305
1306         master_priv->sarea = drm_getsarea(dev);
1307         if (!master_priv->sarea) {
1308                 DRM_ERROR("could not find sarea!\n");
1309                 radeon_do_cleanup_cp(dev);
1310                 return -EINVAL;
1311         }
1312
1313         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1314         if (!dev_priv->cp_ring) {
1315                 DRM_ERROR("could not find cp ring region!\n");
1316                 radeon_do_cleanup_cp(dev);
1317                 return -EINVAL;
1318         }
1319         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1320         if (!dev_priv->ring_rptr) {
1321                 DRM_ERROR("could not find ring read pointer!\n");
1322                 radeon_do_cleanup_cp(dev);
1323                 return -EINVAL;
1324         }
1325         dev->agp_buffer_token = init->buffers_offset;
1326         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1327         if (!dev->agp_buffer_map) {
1328                 DRM_ERROR("could not find dma buffer region!\n");
1329                 radeon_do_cleanup_cp(dev);
1330                 return -EINVAL;
1331         }
1332
1333         if (init->gart_textures_offset) {
1334                 dev_priv->gart_textures =
1335                     drm_core_findmap(dev, init->gart_textures_offset);
1336                 if (!dev_priv->gart_textures) {
1337                         DRM_ERROR("could not find GART texture region!\n");
1338                         radeon_do_cleanup_cp(dev);
1339                         return -EINVAL;
1340                 }
1341         }
1342
1343 #if __OS_HAS_AGP
1344         if (dev_priv->flags & RADEON_IS_AGP) {
1345                 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1346                 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1347                 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
1348                 if (!dev_priv->cp_ring->handle ||
1349                     !dev_priv->ring_rptr->handle ||
1350                     !dev->agp_buffer_map->handle) {
1351                         DRM_ERROR("could not find ioremap agp regions!\n");
1352                         radeon_do_cleanup_cp(dev);
1353                         return -EINVAL;
1354                 }
1355         } else
1356 #endif
1357         {
1358                 dev_priv->cp_ring->handle =
1359                         (void *)(unsigned long)dev_priv->cp_ring->offset;
1360                 dev_priv->ring_rptr->handle =
1361                         (void *)(unsigned long)dev_priv->ring_rptr->offset;
1362                 dev->agp_buffer_map->handle =
1363                         (void *)(unsigned long)dev->agp_buffer_map->offset;
1364
1365                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
1366                           dev_priv->cp_ring->handle);
1367                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
1368                           dev_priv->ring_rptr->handle);
1369                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
1370                           dev->agp_buffer_map->handle);
1371         }
1372
1373         dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 16;
1374         dev_priv->fb_size =
1375                 ((radeon_read_fb_location(dev_priv) & 0xffff0000u) + 0x10000)
1376                 - dev_priv->fb_location;
1377
1378         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1379                                         ((dev_priv->front_offset
1380                                           + dev_priv->fb_location) >> 10));
1381
1382         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1383                                        ((dev_priv->back_offset
1384                                          + dev_priv->fb_location) >> 10));
1385
1386         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1387                                         ((dev_priv->depth_offset
1388                                           + dev_priv->fb_location) >> 10));
1389
1390         dev_priv->gart_size = init->gart_size;
1391
1392         /* New let's set the memory map ... */
1393         if (dev_priv->new_memmap) {
1394                 u32 base = 0;
1395
1396                 DRM_INFO("Setting GART location based on new memory map\n");
1397
1398                 /* If using AGP, try to locate the AGP aperture at the same
1399                  * location in the card and on the bus, though we have to
1400                  * align it down.
1401                  */
1402 #if __OS_HAS_AGP
1403                 if (dev_priv->flags & RADEON_IS_AGP) {
1404                         base = dev->agp->base;
1405                         /* Check if valid */
1406                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1407                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1408                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1409                                          dev->agp->base);
1410                                 base = 0;
1411                         }
1412                 }
1413 #endif
1414                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1415                 if (base == 0) {
1416                         base = dev_priv->fb_location + dev_priv->fb_size;
1417                         if (base < dev_priv->fb_location ||
1418                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1419                                 base = dev_priv->fb_location
1420                                         - dev_priv->gart_size;
1421                 }
1422                 dev_priv->gart_vm_start = base & 0xffc00000u;
1423                 if (dev_priv->gart_vm_start != base)
1424                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
1425                                  base, dev_priv->gart_vm_start);
1426         } else {
1427                 DRM_INFO("Setting GART location based on old memory map\n");
1428                 dev_priv->gart_vm_start = dev_priv->fb_location +
1429                         RADEON_READ(RADEON_CONFIG_APER_SIZE);
1430         }
1431
1432 #if __OS_HAS_AGP
1433         if (dev_priv->flags & RADEON_IS_AGP)
1434                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1435                                                  - dev->agp->base
1436                                                  + dev_priv->gart_vm_start);
1437         else
1438 #endif
1439                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
1440                                         - (unsigned long)dev->sg->virtual
1441                                         + dev_priv->gart_vm_start);
1442
1443         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
1444         DRM_DEBUG("dev_priv->gart_vm_start 0x%x\n", dev_priv->gart_vm_start);
1445         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%lx\n",
1446                   dev_priv->gart_buffers_offset);
1447
1448         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
1449         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
1450                               + init->ring_size / sizeof(u32));
1451         dev_priv->ring.size = init->ring_size;
1452         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
1453
1454         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
1455         dev_priv->ring.rptr_update_l2qw = drm_order( /* init->rptr_update */ 4096 / 8);
1456
1457         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
1458         dev_priv->ring.fetch_size_l2ow = drm_order( /* init->fetch_size */ 32 / 16);
1459         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
1460
1461         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
1462
1463 #if __OS_HAS_AGP
1464         if (dev_priv->flags & RADEON_IS_AGP) {
1465                 /* Turn off PCI GART */
1466                 radeon_set_pcigart(dev_priv, 0);
1467         } else
1468 #endif
1469         {
1470                 u32 sctrl;
1471                 int ret;
1472
1473                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
1474                 /* if we have an offset set from userspace */
1475                 if (dev_priv->pcigart_offset_set) {
1476                         dev_priv->gart_info.bus_addr =
1477                                 (resource_size_t)dev_priv->pcigart_offset + dev_priv->fb_location;
1478                         dev_priv->gart_info.mapping.offset =
1479                             dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
1480                         dev_priv->gart_info.mapping.size =
1481                             dev_priv->gart_info.table_size;
1482
1483                         drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
1484                         dev_priv->gart_info.addr =
1485                             dev_priv->gart_info.mapping.handle;
1486
1487                         if (dev_priv->flags & RADEON_IS_PCIE)
1488                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCIE;
1489                         else
1490                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1491                         dev_priv->gart_info.gart_table_location =
1492                             DRM_ATI_GART_FB;
1493
1494                         DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
1495                                   dev_priv->gart_info.addr,
1496                                   dev_priv->pcigart_offset);
1497                 } else {
1498                         if (dev_priv->flags & RADEON_IS_IGPGART)
1499                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_IGP;
1500                         else
1501                                 dev_priv->gart_info.gart_reg_if = DRM_ATI_GART_PCI;
1502                         dev_priv->gart_info.gart_table_location =
1503                             DRM_ATI_GART_MAIN;
1504                         dev_priv->gart_info.addr = NULL;
1505                         dev_priv->gart_info.bus_addr = 0;
1506                         if (dev_priv->flags & RADEON_IS_PCIE) {
1507                                 DRM_ERROR
1508                                     ("Cannot use PCI Express without GART in FB memory\n");
1509                                 radeon_do_cleanup_cp(dev);
1510                                 return -EINVAL;
1511                         }
1512                 }
1513
1514                 sctrl = RADEON_READ(RADEON_SURFACE_CNTL);
1515                 RADEON_WRITE(RADEON_SURFACE_CNTL, 0);
1516                 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1517                         ret = r600_page_table_init(dev);
1518                 else
1519                         ret = drm_ati_pcigart_init(dev, &dev_priv->gart_info);
1520                 RADEON_WRITE(RADEON_SURFACE_CNTL, sctrl);
1521
1522                 if (!ret) {
1523                         DRM_ERROR("failed to init PCI GART!\n");
1524                         radeon_do_cleanup_cp(dev);
1525                         return -ENOMEM;
1526                 }
1527
1528                 ret = radeon_setup_pcigart_surface(dev_priv);
1529                 if (ret) {
1530                         DRM_ERROR("failed to setup GART surface!\n");
1531                         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1532                                 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1533                         else
1534                                 drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info);
1535                         radeon_do_cleanup_cp(dev);
1536                         return ret;
1537                 }
1538
1539                 /* Turn on PCI GART */
1540                 radeon_set_pcigart(dev_priv, 1);
1541         }
1542
1543         if (!dev_priv->me_fw) {
1544                 int err = radeon_cp_init_microcode(dev_priv);
1545                 if (err) {
1546                         DRM_ERROR("Failed to load firmware!\n");
1547                         radeon_do_cleanup_cp(dev);
1548                         return err;
1549                 }
1550         }
1551         radeon_cp_load_microcode(dev_priv);
1552         radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1553
1554         dev_priv->last_buf = 0;
1555
1556         radeon_do_engine_reset(dev);
1557         radeon_test_writeback(dev_priv);
1558
1559         return 0;
1560 }
1561
1562 static int radeon_do_cleanup_cp(struct drm_device * dev)
1563 {
1564         drm_radeon_private_t *dev_priv = dev->dev_private;
1565         DRM_DEBUG("\n");
1566
1567         /* Make sure interrupts are disabled here because the uninstall ioctl
1568          * may not have been called from userspace and after dev_private
1569          * is freed, it's too late.
1570          */
1571         if (dev->irq_enabled)
1572                 drm_irq_uninstall(dev);
1573
1574 #if __OS_HAS_AGP
1575         if (dev_priv->flags & RADEON_IS_AGP) {
1576                 if (dev_priv->cp_ring != NULL) {
1577                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1578                         dev_priv->cp_ring = NULL;
1579                 }
1580                 if (dev_priv->ring_rptr != NULL) {
1581                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1582                         dev_priv->ring_rptr = NULL;
1583                 }
1584                 if (dev->agp_buffer_map != NULL) {
1585                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1586                         dev->agp_buffer_map = NULL;
1587                 }
1588         } else
1589 #endif
1590         {
1591
1592                 if (dev_priv->gart_info.bus_addr) {
1593                         /* Turn off PCI GART */
1594                         radeon_set_pcigart(dev_priv, 0);
1595                         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS600)
1596                                 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1597                         else {
1598                                 if (!drm_ati_pcigart_cleanup(dev, &dev_priv->gart_info))
1599                                         DRM_ERROR("failed to cleanup PCI GART!\n");
1600                         }
1601                 }
1602
1603                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB)
1604                 {
1605                         drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1606                         dev_priv->gart_info.addr = NULL;
1607                 }
1608         }
1609         /* only clear to the start of flags */
1610         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1611
1612         return 0;
1613 }
1614
1615 /* This code will reinit the Radeon CP hardware after a resume from disc.
1616  * AFAIK, it would be very difficult to pickle the state at suspend time, so
1617  * here we make sure that all Radeon hardware initialisation is re-done without
1618  * affecting running applications.
1619  *
1620  * Charl P. Botha <http://cpbotha.net>
1621  */
1622 static int radeon_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
1623 {
1624         drm_radeon_private_t *dev_priv = dev->dev_private;
1625
1626         if (!dev_priv) {
1627                 DRM_ERROR("Called with no initialization\n");
1628                 return -EINVAL;
1629         }
1630
1631         DRM_DEBUG("Starting radeon_do_resume_cp()\n");
1632
1633 #if __OS_HAS_AGP
1634         if (dev_priv->flags & RADEON_IS_AGP) {
1635                 /* Turn off PCI GART */
1636                 radeon_set_pcigart(dev_priv, 0);
1637         } else
1638 #endif
1639         {
1640                 /* Turn on PCI GART */
1641                 radeon_set_pcigart(dev_priv, 1);
1642         }
1643
1644         radeon_cp_load_microcode(dev_priv);
1645         radeon_cp_init_ring_buffer(dev, dev_priv, file_priv);
1646
1647         radeon_do_engine_reset(dev);
1648         radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
1649
1650         DRM_DEBUG("radeon_do_resume_cp() complete\n");
1651
1652         return 0;
1653 }
1654
1655 int radeon_cp_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
1656 {
1657         drm_radeon_private_t *dev_priv = dev->dev_private;
1658         drm_radeon_init_t *init = data;
1659
1660         LOCK_TEST_WITH_RETURN(dev, file_priv);
1661
1662         if (init->func == RADEON_INIT_R300_CP)
1663                 r300_init_reg_flags(dev);
1664
1665         switch (init->func) {
1666         case RADEON_INIT_CP:
1667         case RADEON_INIT_R200_CP:
1668         case RADEON_INIT_R300_CP:
1669                 return radeon_do_init_cp(dev, init, file_priv);
1670         case RADEON_INIT_R600_CP:
1671                 return r600_do_init_cp(dev, init, file_priv);
1672         case RADEON_CLEANUP_CP:
1673                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1674                         return r600_do_cleanup_cp(dev);
1675                 else
1676                         return radeon_do_cleanup_cp(dev);
1677         }
1678
1679         return -EINVAL;
1680 }
1681
1682 int radeon_cp_start(struct drm_device *dev, void *data, struct drm_file *file_priv)
1683 {
1684         drm_radeon_private_t *dev_priv = dev->dev_private;
1685         DRM_DEBUG("\n");
1686
1687         LOCK_TEST_WITH_RETURN(dev, file_priv);
1688
1689         if (dev_priv->cp_running) {
1690                 DRM_DEBUG("while CP running\n");
1691                 return 0;
1692         }
1693         if (dev_priv->cp_mode == RADEON_CSQ_PRIDIS_INDDIS) {
1694                 DRM_DEBUG("called with bogus CP mode (%d)\n",
1695                           dev_priv->cp_mode);
1696                 return 0;
1697         }
1698
1699         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1700                 r600_do_cp_start(dev_priv);
1701         else
1702                 radeon_do_cp_start(dev_priv);
1703
1704         return 0;
1705 }
1706
1707 /* Stop the CP.  The engine must have been idled before calling this
1708  * routine.
1709  */
1710 int radeon_cp_stop(struct drm_device *dev, void *data, struct drm_file *file_priv)
1711 {
1712         drm_radeon_private_t *dev_priv = dev->dev_private;
1713         drm_radeon_cp_stop_t *stop = data;
1714         int ret;
1715         DRM_DEBUG("\n");
1716
1717         LOCK_TEST_WITH_RETURN(dev, file_priv);
1718
1719         if (!dev_priv->cp_running)
1720                 return 0;
1721
1722         /* Flush any pending CP commands.  This ensures any outstanding
1723          * commands are exectuted by the engine before we turn it off.
1724          */
1725         if (stop->flush) {
1726                 radeon_do_cp_flush(dev_priv);
1727         }
1728
1729         /* If we fail to make the engine go idle, we return an error
1730          * code so that the DRM ioctl wrapper can try again.
1731          */
1732         if (stop->idle) {
1733                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1734                         ret = r600_do_cp_idle(dev_priv);
1735                 else
1736                         ret = radeon_do_cp_idle(dev_priv);
1737                 if (ret)
1738                         return ret;
1739         }
1740
1741         /* Finally, we can turn off the CP.  If the engine isn't idle,
1742          * we will get some dropped triangles as they won't be fully
1743          * rendered before the CP is shut down.
1744          */
1745         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1746                 r600_do_cp_stop(dev_priv);
1747         else
1748                 radeon_do_cp_stop(dev_priv);
1749
1750         /* Reset the engine */
1751         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1752                 r600_do_engine_reset(dev);
1753         else
1754                 radeon_do_engine_reset(dev);
1755
1756         return 0;
1757 }
1758
1759 void radeon_do_release(struct drm_device * dev)
1760 {
1761         drm_radeon_private_t *dev_priv = dev->dev_private;
1762         int i, ret;
1763
1764         if (dev_priv) {
1765                 if (dev_priv->cp_running) {
1766                         /* Stop the cp */
1767                         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1768                                 while ((ret = r600_do_cp_idle(dev_priv)) != 0) {
1769                                         DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1770 #ifdef __linux__
1771                                         schedule();
1772 #else
1773                                         tsleep(&ret, PZERO, "rdnrel", 1);
1774 #endif
1775                                 }
1776                         } else {
1777                                 while ((ret = radeon_do_cp_idle(dev_priv)) != 0) {
1778                                         DRM_DEBUG("radeon_do_cp_idle %d\n", ret);
1779 #ifdef __linux__
1780                                         schedule();
1781 #else
1782                                         tsleep(&ret, PZERO, "rdnrel", 1);
1783 #endif
1784                                 }
1785                         }
1786                         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
1787                                 r600_do_cp_stop(dev_priv);
1788                                 r600_do_engine_reset(dev);
1789                         } else {
1790                                 radeon_do_cp_stop(dev_priv);
1791                                 radeon_do_engine_reset(dev);
1792                         }
1793                 }
1794
1795                 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_R600) {
1796                         /* Disable *all* interrupts */
1797                         if (dev_priv->mmio)     /* remove this after permanent addmaps */
1798                                 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
1799
1800                         if (dev_priv->mmio) {   /* remove all surfaces */
1801                                 for (i = 0; i < RADEON_MAX_SURFACES; i++) {
1802                                         RADEON_WRITE(RADEON_SURFACE0_INFO + 16 * i, 0);
1803                                         RADEON_WRITE(RADEON_SURFACE0_LOWER_BOUND +
1804                                                      16 * i, 0);
1805                                         RADEON_WRITE(RADEON_SURFACE0_UPPER_BOUND +
1806                                                      16 * i, 0);
1807                                 }
1808                         }
1809                 }
1810
1811                 /* Free memory heap structures */
1812                 radeon_mem_takedown(&(dev_priv->gart_heap));
1813                 radeon_mem_takedown(&(dev_priv->fb_heap));
1814
1815                 /* deallocate kernel resources */
1816                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1817                         r600_do_cleanup_cp(dev);
1818                 else
1819                         radeon_do_cleanup_cp(dev);
1820                 if (dev_priv->me_fw) {
1821                         release_firmware(dev_priv->me_fw);
1822                         dev_priv->me_fw = NULL;
1823                 }
1824                 if (dev_priv->pfp_fw) {
1825                         release_firmware(dev_priv->pfp_fw);
1826                         dev_priv->pfp_fw = NULL;
1827                 }
1828         }
1829 }
1830
1831 /* Just reset the CP ring.  Called as part of an X Server engine reset.
1832  */
1833 int radeon_cp_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1834 {
1835         drm_radeon_private_t *dev_priv = dev->dev_private;
1836         DRM_DEBUG("\n");
1837
1838         LOCK_TEST_WITH_RETURN(dev, file_priv);
1839
1840         if (!dev_priv) {
1841                 DRM_DEBUG("called before init done\n");
1842                 return -EINVAL;
1843         }
1844
1845         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1846                 r600_do_cp_reset(dev_priv);
1847         else
1848                 radeon_do_cp_reset(dev_priv);
1849
1850         /* The CP is no longer running after an engine reset */
1851         dev_priv->cp_running = 0;
1852
1853         return 0;
1854 }
1855
1856 int radeon_cp_idle(struct drm_device *dev, void *data, struct drm_file *file_priv)
1857 {
1858         drm_radeon_private_t *dev_priv = dev->dev_private;
1859         DRM_DEBUG("\n");
1860
1861         LOCK_TEST_WITH_RETURN(dev, file_priv);
1862
1863         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1864                 return r600_do_cp_idle(dev_priv);
1865         else
1866                 return radeon_do_cp_idle(dev_priv);
1867 }
1868
1869 /* Added by Charl P. Botha to call radeon_do_resume_cp().
1870  */
1871 int radeon_cp_resume(struct drm_device *dev, void *data, struct drm_file *file_priv)
1872 {
1873         drm_radeon_private_t *dev_priv = dev->dev_private;
1874         DRM_DEBUG("\n");
1875
1876         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1877                 return r600_do_resume_cp(dev, file_priv);
1878         else
1879                 return radeon_do_resume_cp(dev, file_priv);
1880 }
1881
1882 int radeon_engine_reset(struct drm_device *dev, void *data, struct drm_file *file_priv)
1883 {
1884         drm_radeon_private_t *dev_priv = dev->dev_private;
1885         DRM_DEBUG("\n");
1886
1887         LOCK_TEST_WITH_RETURN(dev, file_priv);
1888
1889         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
1890                 return r600_do_engine_reset(dev);
1891         else
1892                 return radeon_do_engine_reset(dev);
1893 }
1894
1895 /* ================================================================
1896  * Fullscreen mode
1897  */
1898
1899 /* KW: Deprecated to say the least:
1900  */
1901 int radeon_fullscreen(struct drm_device *dev, void *data, struct drm_file *file_priv)
1902 {
1903         return 0;
1904 }
1905
1906 /* ================================================================
1907  * Freelist management
1908  */
1909
1910 /* Original comment: FIXME: ROTATE_BUFS is a hack to cycle through
1911  *   bufs until freelist code is used.  Note this hides a problem with
1912  *   the scratch register * (used to keep track of last buffer
1913  *   completed) being written to before * the last buffer has actually
1914  *   completed rendering.
1915  *
1916  * KW:  It's also a good way to find free buffers quickly.
1917  *
1918  * KW: Ideally this loop wouldn't exist, and freelist_get wouldn't
1919  * sleep.  However, bugs in older versions of radeon_accel.c mean that
1920  * we essentially have to do this, else old clients will break.
1921  *
1922  * However, it does leave open a potential deadlock where all the
1923  * buffers are held by other clients, which can't release them because
1924  * they can't get the lock.
1925  */
1926
1927 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1928 {
1929         struct drm_device_dma *dma = dev->dma;
1930         drm_radeon_private_t *dev_priv = dev->dev_private;
1931         drm_radeon_buf_priv_t *buf_priv;
1932         struct drm_buf *buf;
1933         int i, t;
1934         int start;
1935
1936         if (++dev_priv->last_buf >= dma->buf_count)
1937                 dev_priv->last_buf = 0;
1938
1939         start = dev_priv->last_buf;
1940
1941         for (t = 0; t < dev_priv->usec_timeout; t++) {
1942                 u32 done_age = GET_SCRATCH(dev_priv, 1);
1943                 DRM_DEBUG("done_age = %d\n", done_age);
1944                 for (i = start; i < dma->buf_count; i++) {
1945                         buf = dma->buflist[i];
1946                         buf_priv = buf->dev_private;
1947                         if (buf->file_priv == NULL || (buf->pending &&
1948                                                        buf_priv->age <=
1949                                                        done_age)) {
1950                                 dev_priv->stats.requested_bufs++;
1951                                 buf->pending = 0;
1952                                 return buf;
1953                         }
1954                         start = 0;
1955                 }
1956
1957                 if (t) {
1958                         DRM_UDELAY(1);
1959                         dev_priv->stats.freelist_loops++;
1960                 }
1961         }
1962
1963         DRM_DEBUG("returning NULL!\n");
1964         return NULL;
1965 }
1966
1967 #if 0
1968 struct drm_buf *radeon_freelist_get(struct drm_device * dev)
1969 {
1970         struct drm_device_dma *dma = dev->dma;
1971         drm_radeon_private_t *dev_priv = dev->dev_private;
1972         drm_radeon_buf_priv_t *buf_priv;
1973         struct drm_buf *buf;
1974         int i, t;
1975         int start;
1976         u32 done_age;
1977
1978         done_age = radeon_read_ring_rptr(dev_priv, RADEON_SCRATCHOFF(1));
1979         if (++dev_priv->last_buf >= dma->buf_count)
1980                 dev_priv->last_buf = 0;
1981
1982         start = dev_priv->last_buf;
1983         dev_priv->stats.freelist_loops++;
1984
1985         for (t = 0; t < 2; t++) {
1986                 for (i = start; i < dma->buf_count; i++) {
1987                         buf = dma->buflist[i];
1988                         buf_priv = buf->dev_private;
1989                         if (buf->file_priv == 0 || (buf->pending &&
1990                                                     buf_priv->age <=
1991                                                     done_age)) {
1992                                 dev_priv->stats.requested_bufs++;
1993                                 buf->pending = 0;
1994                                 return buf;
1995                         }
1996                 }
1997                 start = 0;
1998         }
1999
2000         return NULL;
2001 }
2002 #endif
2003
2004 void radeon_freelist_reset(struct drm_device * dev)
2005 {
2006         struct drm_device_dma *dma = dev->dma;
2007         drm_radeon_private_t *dev_priv = dev->dev_private;
2008         int i;
2009
2010         dev_priv->last_buf = 0;
2011         for (i = 0; i < dma->buf_count; i++) {
2012                 struct drm_buf *buf = dma->buflist[i];
2013                 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
2014                 buf_priv->age = 0;
2015         }
2016 }
2017
2018 /* ================================================================
2019  * CP command submission
2020  */
2021
2022 int radeon_wait_ring(drm_radeon_private_t * dev_priv, int n)
2023 {
2024         drm_radeon_ring_buffer_t *ring = &dev_priv->ring;
2025         int i;
2026         u32 last_head = GET_RING_HEAD(dev_priv);
2027
2028         for (i = 0; i < dev_priv->usec_timeout; i++) {
2029                 u32 head = GET_RING_HEAD(dev_priv);
2030
2031                 ring->space = (head - ring->tail) * sizeof(u32);
2032                 if (ring->space <= 0)
2033                         ring->space += ring->size;
2034                 if (ring->space > n)
2035                         return 0;
2036
2037                 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
2038
2039                 if (head != last_head)
2040                         i = 0;
2041                 last_head = head;
2042
2043                 DRM_UDELAY(1);
2044         }
2045
2046         /* FIXME: This return value is ignored in the BEGIN_RING macro! */
2047 #if RADEON_FIFO_DEBUG
2048         radeon_status(dev_priv);
2049         DRM_ERROR("failed!\n");
2050 #endif
2051         return -EBUSY;
2052 }
2053
2054 static int radeon_cp_get_buffers(struct drm_device *dev,
2055                                  struct drm_file *file_priv,
2056                                  struct drm_dma * d)
2057 {
2058         int i;
2059         struct drm_buf *buf;
2060
2061         for (i = d->granted_count; i < d->request_count; i++) {
2062                 buf = radeon_freelist_get(dev);
2063                 if (!buf)
2064                         return -EBUSY;  /* NOTE: broken client */
2065
2066                 buf->file_priv = file_priv;
2067
2068                 if (DRM_COPY_TO_USER(&d->request_indices[i], &buf->idx,
2069                                      sizeof(buf->idx)))
2070                         return -EFAULT;
2071                 if (DRM_COPY_TO_USER(&d->request_sizes[i], &buf->total,
2072                                      sizeof(buf->total)))
2073                         return -EFAULT;
2074
2075                 d->granted_count++;
2076         }
2077         return 0;
2078 }
2079
2080 int radeon_cp_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
2081 {
2082         struct drm_device_dma *dma = dev->dma;
2083         int ret = 0;
2084         struct drm_dma *d = data;
2085
2086         LOCK_TEST_WITH_RETURN(dev, file_priv);
2087
2088         /* Please don't send us buffers.
2089          */
2090         if (d->send_count != 0) {
2091                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
2092                           DRM_CURRENTPID, d->send_count);
2093                 return -EINVAL;
2094         }
2095
2096         /* We'll send you buffers.
2097          */
2098         if (d->request_count < 0 || d->request_count > dma->buf_count) {
2099                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
2100                           DRM_CURRENTPID, d->request_count, dma->buf_count);
2101                 return -EINVAL;
2102         }
2103
2104         d->granted_count = 0;
2105
2106         if (d->request_count) {
2107                 ret = radeon_cp_get_buffers(dev, file_priv, d);
2108         }
2109
2110         return ret;
2111 }
2112
2113 int radeon_driver_load(struct drm_device *dev, unsigned long flags)
2114 {
2115         drm_radeon_private_t *dev_priv;
2116         int ret = 0;
2117
2118         dev_priv = kzalloc(sizeof(drm_radeon_private_t), GFP_KERNEL);
2119         if (dev_priv == NULL)
2120                 return -ENOMEM;
2121
2122         dev->dev_private = (void *)dev_priv;
2123         dev_priv->flags = flags;
2124
2125         switch (flags & RADEON_FAMILY_MASK) {
2126         case CHIP_R100:
2127         case CHIP_RV200:
2128         case CHIP_R200:
2129         case CHIP_R300:
2130         case CHIP_R350:
2131         case CHIP_R420:
2132         case CHIP_R423:
2133         case CHIP_RV410:
2134         case CHIP_RV515:
2135         case CHIP_R520:
2136         case CHIP_RV570:
2137         case CHIP_R580:
2138                 dev_priv->flags |= RADEON_HAS_HIERZ;
2139                 break;
2140         default:
2141                 /* all other chips have no hierarchical z buffer */
2142                 break;
2143         }
2144
2145         if (drm_device_is_agp(dev))
2146                 dev_priv->flags |= RADEON_IS_AGP;
2147         else if (drm_device_is_pcie(dev))
2148                 dev_priv->flags |= RADEON_IS_PCIE;
2149         else
2150                 dev_priv->flags |= RADEON_IS_PCI;
2151
2152         ret = drm_addmap(dev, drm_get_resource_start(dev, 2),
2153                          drm_get_resource_len(dev, 2), _DRM_REGISTERS,
2154                          _DRM_READ_ONLY | _DRM_DRIVER, &dev_priv->mmio);
2155         if (ret != 0)
2156                 return ret;
2157
2158         ret = drm_vblank_init(dev, 2);
2159         if (ret) {
2160                 radeon_driver_unload(dev);
2161                 return ret;
2162         }
2163
2164         DRM_DEBUG("%s card detected\n",
2165                   ((dev_priv->flags & RADEON_IS_AGP) ? "AGP" : (((dev_priv->flags & RADEON_IS_PCIE) ? "PCIE" : "PCI"))));
2166         return ret;
2167 }
2168
2169 int radeon_master_create(struct drm_device *dev, struct drm_master *master)
2170 {
2171         struct drm_radeon_master_private *master_priv;
2172         unsigned long sareapage;
2173         int ret;
2174
2175         master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
2176         if (!master_priv)
2177                 return -ENOMEM;
2178
2179         /* prebuild the SAREA */
2180         sareapage = max_t(unsigned long, SAREA_MAX, PAGE_SIZE);
2181         ret = drm_addmap(dev, 0, sareapage, _DRM_SHM, _DRM_CONTAINS_LOCK,
2182                          &master_priv->sarea);
2183         if (ret) {
2184                 DRM_ERROR("SAREA setup failed\n");
2185                 return ret;
2186         }
2187         master_priv->sarea_priv = master_priv->sarea->handle + sizeof(struct drm_sarea);
2188         master_priv->sarea_priv->pfCurrentPage = 0;
2189
2190         master->driver_priv = master_priv;
2191         return 0;
2192 }
2193
2194 void radeon_master_destroy(struct drm_device *dev, struct drm_master *master)
2195 {
2196         struct drm_radeon_master_private *master_priv = master->driver_priv;
2197
2198         if (!master_priv)
2199                 return;
2200
2201         if (master_priv->sarea_priv &&
2202             master_priv->sarea_priv->pfCurrentPage != 0)
2203                 radeon_cp_dispatch_flip(dev, master);
2204
2205         master_priv->sarea_priv = NULL;
2206         if (master_priv->sarea)
2207                 drm_rmmap_locked(dev, master_priv->sarea);
2208
2209         kfree(master_priv);
2210
2211         master->driver_priv = NULL;
2212 }
2213
2214 /* Create mappings for registers and framebuffer so userland doesn't necessarily
2215  * have to find them.
2216  */
2217 int radeon_driver_firstopen(struct drm_device *dev)
2218 {
2219         int ret;
2220         drm_local_map_t *map;
2221         drm_radeon_private_t *dev_priv = dev->dev_private;
2222
2223         dev_priv->gart_info.table_size = RADEON_PCIGART_TABLE_SIZE;
2224
2225         dev_priv->fb_aper_offset = drm_get_resource_start(dev, 0);
2226         ret = drm_addmap(dev, dev_priv->fb_aper_offset,
2227                          drm_get_resource_len(dev, 0), _DRM_FRAME_BUFFER,
2228                          _DRM_WRITE_COMBINING, &map);
2229         if (ret != 0)
2230                 return ret;
2231
2232         return 0;
2233 }
2234
2235 int radeon_driver_unload(struct drm_device *dev)
2236 {
2237         drm_radeon_private_t *dev_priv = dev->dev_private;
2238
2239         DRM_DEBUG("\n");
2240
2241         drm_rmmap(dev, dev_priv->mmio);
2242
2243         kfree(dev_priv);
2244
2245         dev->dev_private = NULL;
2246         return 0;
2247 }
2248
2249 void radeon_commit_ring(drm_radeon_private_t *dev_priv)
2250 {
2251         int i;
2252         u32 *ring;
2253         int tail_aligned;
2254
2255         /* check if the ring is padded out to 16-dword alignment */
2256
2257         tail_aligned = dev_priv->ring.tail & (RADEON_RING_ALIGN-1);
2258         if (tail_aligned) {
2259                 int num_p2 = RADEON_RING_ALIGN - tail_aligned;
2260
2261                 ring = dev_priv->ring.start;
2262                 /* pad with some CP_PACKET2 */
2263                 for (i = 0; i < num_p2; i++)
2264                         ring[dev_priv->ring.tail + i] = CP_PACKET2();
2265
2266                 dev_priv->ring.tail += i;
2267
2268                 dev_priv->ring.space -= num_p2 * sizeof(u32);
2269         }
2270
2271         dev_priv->ring.tail &= dev_priv->ring.tail_mask;
2272
2273         DRM_MEMORYBARRIER();
2274         GET_RING_HEAD( dev_priv );
2275
2276         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600) {
2277                 RADEON_WRITE(R600_CP_RB_WPTR, dev_priv->ring.tail);
2278                 /* read from PCI bus to ensure correct posting */
2279                 RADEON_READ(R600_CP_RB_RPTR);
2280         } else {
2281                 RADEON_WRITE(RADEON_CP_RB_WPTR, dev_priv->ring.tail);
2282                 /* read from PCI bus to ensure correct posting */
2283                 RADEON_READ(RADEON_CP_RB_RPTR);
2284         }
2285 }