drm/radeon: command stream checker for r3xx-r5xx hardware
[linux-2.6.git] / drivers / gpu / drm / radeon / radeon_asic.h
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #ifndef __RADEON_ASIC_H__
29 #define __RADEON_ASIC_H__
30
31 /*
32  * common functions
33  */
34 void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
35 void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
36
37 void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
38 void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
39 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
40
41 /*
42  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
43  */
44 int r100_init(struct radeon_device *rdev);
45 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
46 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
47 void r100_errata(struct radeon_device *rdev);
48 void r100_vram_info(struct radeon_device *rdev);
49 int r100_gpu_reset(struct radeon_device *rdev);
50 int r100_mc_init(struct radeon_device *rdev);
51 void r100_mc_fini(struct radeon_device *rdev);
52 int r100_wb_init(struct radeon_device *rdev);
53 void r100_wb_fini(struct radeon_device *rdev);
54 int r100_gart_enable(struct radeon_device *rdev);
55 void r100_pci_gart_disable(struct radeon_device *rdev);
56 void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
57 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
58 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
59 void r100_cp_fini(struct radeon_device *rdev);
60 void r100_cp_disable(struct radeon_device *rdev);
61 void r100_ring_start(struct radeon_device *rdev);
62 int r100_irq_set(struct radeon_device *rdev);
63 int r100_irq_process(struct radeon_device *rdev);
64 void r100_fence_ring_emit(struct radeon_device *rdev,
65                           struct radeon_fence *fence);
66 int r100_cs_parse(struct radeon_cs_parser *p);
67 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
68 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
69 int r100_copy_blit(struct radeon_device *rdev,
70                    uint64_t src_offset,
71                    uint64_t dst_offset,
72                    unsigned num_pages,
73                    struct radeon_fence *fence);
74
75 static struct radeon_asic r100_asic = {
76         .init = &r100_init,
77         .errata = &r100_errata,
78         .vram_info = &r100_vram_info,
79         .gpu_reset = &r100_gpu_reset,
80         .mc_init = &r100_mc_init,
81         .mc_fini = &r100_mc_fini,
82         .wb_init = &r100_wb_init,
83         .wb_fini = &r100_wb_fini,
84         .gart_enable = &r100_gart_enable,
85         .gart_disable = &r100_pci_gart_disable,
86         .gart_tlb_flush = &r100_pci_gart_tlb_flush,
87         .gart_set_page = &r100_pci_gart_set_page,
88         .cp_init = &r100_cp_init,
89         .cp_fini = &r100_cp_fini,
90         .cp_disable = &r100_cp_disable,
91         .ring_start = &r100_ring_start,
92         .irq_set = &r100_irq_set,
93         .irq_process = &r100_irq_process,
94         .fence_ring_emit = &r100_fence_ring_emit,
95         .cs_parse = &r100_cs_parse,
96         .copy_blit = &r100_copy_blit,
97         .copy_dma = NULL,
98         .copy = &r100_copy_blit,
99         .set_engine_clock = &radeon_legacy_set_engine_clock,
100         .set_memory_clock = NULL,
101         .set_pcie_lanes = NULL,
102         .set_clock_gating = &radeon_legacy_set_clock_gating,
103 };
104
105
106 /*
107  * r300,r350,rv350,rv380
108  */
109 int r300_init(struct radeon_device *rdev);
110 void r300_errata(struct radeon_device *rdev);
111 void r300_vram_info(struct radeon_device *rdev);
112 int r300_gpu_reset(struct radeon_device *rdev);
113 int r300_mc_init(struct radeon_device *rdev);
114 void r300_mc_fini(struct radeon_device *rdev);
115 void r300_ring_start(struct radeon_device *rdev);
116 void r300_fence_ring_emit(struct radeon_device *rdev,
117                           struct radeon_fence *fence);
118 int r300_cs_parse(struct radeon_cs_parser *p);
119 int r300_gart_enable(struct radeon_device *rdev);
120 void rv370_pcie_gart_disable(struct radeon_device *rdev);
121 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
122 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
123 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
124 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
125 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
126 int r300_copy_dma(struct radeon_device *rdev,
127                   uint64_t src_offset,
128                   uint64_t dst_offset,
129                   unsigned num_pages,
130                   struct radeon_fence *fence);
131 static struct radeon_asic r300_asic = {
132         .init = &r300_init,
133         .errata = &r300_errata,
134         .vram_info = &r300_vram_info,
135         .gpu_reset = &r300_gpu_reset,
136         .mc_init = &r300_mc_init,
137         .mc_fini = &r300_mc_fini,
138         .wb_init = &r100_wb_init,
139         .wb_fini = &r100_wb_fini,
140         .gart_enable = &r300_gart_enable,
141         .gart_disable = &r100_pci_gart_disable,
142         .gart_tlb_flush = &r100_pci_gart_tlb_flush,
143         .gart_set_page = &r100_pci_gart_set_page,
144         .cp_init = &r100_cp_init,
145         .cp_fini = &r100_cp_fini,
146         .cp_disable = &r100_cp_disable,
147         .ring_start = &r300_ring_start,
148         .irq_set = &r100_irq_set,
149         .irq_process = &r100_irq_process,
150         .fence_ring_emit = &r300_fence_ring_emit,
151         .cs_parse = &r300_cs_parse,
152         .copy_blit = &r100_copy_blit,
153         .copy_dma = &r300_copy_dma,
154         .copy = &r100_copy_blit,
155         .set_engine_clock = &radeon_legacy_set_engine_clock,
156         .set_memory_clock = NULL,
157         .set_pcie_lanes = &rv370_set_pcie_lanes,
158         .set_clock_gating = &radeon_legacy_set_clock_gating,
159 };
160
161 /*
162  * r420,r423,rv410
163  */
164 void r420_errata(struct radeon_device *rdev);
165 void r420_vram_info(struct radeon_device *rdev);
166 int r420_mc_init(struct radeon_device *rdev);
167 void r420_mc_fini(struct radeon_device *rdev);
168 static struct radeon_asic r420_asic = {
169         .init = &r300_init,
170         .errata = &r420_errata,
171         .vram_info = &r420_vram_info,
172         .gpu_reset = &r300_gpu_reset,
173         .mc_init = &r420_mc_init,
174         .mc_fini = &r420_mc_fini,
175         .wb_init = &r100_wb_init,
176         .wb_fini = &r100_wb_fini,
177         .gart_enable = &r300_gart_enable,
178         .gart_disable = &rv370_pcie_gart_disable,
179         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
180         .gart_set_page = &rv370_pcie_gart_set_page,
181         .cp_init = &r100_cp_init,
182         .cp_fini = &r100_cp_fini,
183         .cp_disable = &r100_cp_disable,
184         .ring_start = &r300_ring_start,
185         .irq_set = &r100_irq_set,
186         .irq_process = &r100_irq_process,
187         .fence_ring_emit = &r300_fence_ring_emit,
188         .cs_parse = &r300_cs_parse,
189         .copy_blit = &r100_copy_blit,
190         .copy_dma = &r300_copy_dma,
191         .copy = &r100_copy_blit,
192         .set_engine_clock = &radeon_atom_set_engine_clock,
193         .set_memory_clock = &radeon_atom_set_memory_clock,
194         .set_pcie_lanes = &rv370_set_pcie_lanes,
195         .set_clock_gating = &radeon_atom_set_clock_gating,
196 };
197
198
199 /*
200  * rs400,rs480
201  */
202 void rs400_errata(struct radeon_device *rdev);
203 void rs400_vram_info(struct radeon_device *rdev);
204 int rs400_mc_init(struct radeon_device *rdev);
205 void rs400_mc_fini(struct radeon_device *rdev);
206 int rs400_gart_enable(struct radeon_device *rdev);
207 void rs400_gart_disable(struct radeon_device *rdev);
208 void rs400_gart_tlb_flush(struct radeon_device *rdev);
209 int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
210 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
211 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
212 static struct radeon_asic rs400_asic = {
213         .init = &r300_init,
214         .errata = &rs400_errata,
215         .vram_info = &rs400_vram_info,
216         .gpu_reset = &r300_gpu_reset,
217         .mc_init = &rs400_mc_init,
218         .mc_fini = &rs400_mc_fini,
219         .wb_init = &r100_wb_init,
220         .wb_fini = &r100_wb_fini,
221         .gart_enable = &rs400_gart_enable,
222         .gart_disable = &rs400_gart_disable,
223         .gart_tlb_flush = &rs400_gart_tlb_flush,
224         .gart_set_page = &rs400_gart_set_page,
225         .cp_init = &r100_cp_init,
226         .cp_fini = &r100_cp_fini,
227         .cp_disable = &r100_cp_disable,
228         .ring_start = &r300_ring_start,
229         .irq_set = &r100_irq_set,
230         .irq_process = &r100_irq_process,
231         .fence_ring_emit = &r300_fence_ring_emit,
232         .cs_parse = &r300_cs_parse,
233         .copy_blit = &r100_copy_blit,
234         .copy_dma = &r300_copy_dma,
235         .copy = &r100_copy_blit,
236         .set_engine_clock = &radeon_legacy_set_engine_clock,
237         .set_memory_clock = NULL,
238         .set_pcie_lanes = NULL,
239         .set_clock_gating = &radeon_legacy_set_clock_gating,
240 };
241
242
243 /*
244  * rs600.
245  */
246 void rs600_errata(struct radeon_device *rdev);
247 void rs600_vram_info(struct radeon_device *rdev);
248 int rs600_mc_init(struct radeon_device *rdev);
249 void rs600_mc_fini(struct radeon_device *rdev);
250 int rs600_irq_set(struct radeon_device *rdev);
251 int rs600_gart_enable(struct radeon_device *rdev);
252 void rs600_gart_disable(struct radeon_device *rdev);
253 void rs600_gart_tlb_flush(struct radeon_device *rdev);
254 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
255 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
256 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
257 static struct radeon_asic rs600_asic = {
258         .init = &r300_init,
259         .errata = &rs600_errata,
260         .vram_info = &rs600_vram_info,
261         .gpu_reset = &r300_gpu_reset,
262         .mc_init = &rs600_mc_init,
263         .mc_fini = &rs600_mc_fini,
264         .wb_init = &r100_wb_init,
265         .wb_fini = &r100_wb_fini,
266         .gart_enable = &rs600_gart_enable,
267         .gart_disable = &rs600_gart_disable,
268         .gart_tlb_flush = &rs600_gart_tlb_flush,
269         .gart_set_page = &rs600_gart_set_page,
270         .cp_init = &r100_cp_init,
271         .cp_fini = &r100_cp_fini,
272         .cp_disable = &r100_cp_disable,
273         .ring_start = &r300_ring_start,
274         .irq_set = &rs600_irq_set,
275         .irq_process = &r100_irq_process,
276         .fence_ring_emit = &r300_fence_ring_emit,
277         .cs_parse = &r300_cs_parse,
278         .copy_blit = &r100_copy_blit,
279         .copy_dma = &r300_copy_dma,
280         .copy = &r100_copy_blit,
281         .set_engine_clock = &radeon_atom_set_engine_clock,
282         .set_memory_clock = &radeon_atom_set_memory_clock,
283         .set_pcie_lanes = NULL,
284         .set_clock_gating = &radeon_atom_set_clock_gating,
285 };
286
287
288 /*
289  * rs690,rs740
290  */
291 void rs690_errata(struct radeon_device *rdev);
292 void rs690_vram_info(struct radeon_device *rdev);
293 int rs690_mc_init(struct radeon_device *rdev);
294 void rs690_mc_fini(struct radeon_device *rdev);
295 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
296 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
297 static struct radeon_asic rs690_asic = {
298         .init = &r300_init,
299         .errata = &rs690_errata,
300         .vram_info = &rs690_vram_info,
301         .gpu_reset = &r300_gpu_reset,
302         .mc_init = &rs690_mc_init,
303         .mc_fini = &rs690_mc_fini,
304         .wb_init = &r100_wb_init,
305         .wb_fini = &r100_wb_fini,
306         .gart_enable = &rs400_gart_enable,
307         .gart_disable = &rs400_gart_disable,
308         .gart_tlb_flush = &rs400_gart_tlb_flush,
309         .gart_set_page = &rs400_gart_set_page,
310         .cp_init = &r100_cp_init,
311         .cp_fini = &r100_cp_fini,
312         .cp_disable = &r100_cp_disable,
313         .ring_start = &r300_ring_start,
314         .irq_set = &rs600_irq_set,
315         .irq_process = &r100_irq_process,
316         .fence_ring_emit = &r300_fence_ring_emit,
317         .cs_parse = &r300_cs_parse,
318         .copy_blit = &r100_copy_blit,
319         .copy_dma = &r300_copy_dma,
320         .copy = &r300_copy_dma,
321         .set_engine_clock = &radeon_atom_set_engine_clock,
322         .set_memory_clock = &radeon_atom_set_memory_clock,
323         .set_pcie_lanes = NULL,
324         .set_clock_gating = &radeon_atom_set_clock_gating,
325 };
326
327
328 /*
329  * rv515
330  */
331 int rv515_init(struct radeon_device *rdev);
332 void rv515_errata(struct radeon_device *rdev);
333 void rv515_vram_info(struct radeon_device *rdev);
334 int rv515_gpu_reset(struct radeon_device *rdev);
335 int rv515_mc_init(struct radeon_device *rdev);
336 void rv515_mc_fini(struct radeon_device *rdev);
337 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
338 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
339 void rv515_ring_start(struct radeon_device *rdev);
340 uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
341 void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
342 static struct radeon_asic rv515_asic = {
343         .init = &rv515_init,
344         .errata = &rv515_errata,
345         .vram_info = &rv515_vram_info,
346         .gpu_reset = &rv515_gpu_reset,
347         .mc_init = &rv515_mc_init,
348         .mc_fini = &rv515_mc_fini,
349         .wb_init = &r100_wb_init,
350         .wb_fini = &r100_wb_fini,
351         .gart_enable = &r300_gart_enable,
352         .gart_disable = &rv370_pcie_gart_disable,
353         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
354         .gart_set_page = &rv370_pcie_gart_set_page,
355         .cp_init = &r100_cp_init,
356         .cp_fini = &r100_cp_fini,
357         .cp_disable = &r100_cp_disable,
358         .ring_start = &rv515_ring_start,
359         .irq_set = &r100_irq_set,
360         .irq_process = &r100_irq_process,
361         .fence_ring_emit = &r300_fence_ring_emit,
362         .cs_parse = &r300_cs_parse,
363         .copy_blit = &r100_copy_blit,
364         .copy_dma = &r300_copy_dma,
365         .copy = &r100_copy_blit,
366         .set_engine_clock = &radeon_atom_set_engine_clock,
367         .set_memory_clock = &radeon_atom_set_memory_clock,
368         .set_pcie_lanes = &rv370_set_pcie_lanes,
369         .set_clock_gating = &radeon_atom_set_clock_gating,
370 };
371
372
373 /*
374  * r520,rv530,rv560,rv570,r580
375  */
376 void r520_errata(struct radeon_device *rdev);
377 void r520_vram_info(struct radeon_device *rdev);
378 int r520_mc_init(struct radeon_device *rdev);
379 void r520_mc_fini(struct radeon_device *rdev);
380 static struct radeon_asic r520_asic = {
381         .init = &rv515_init,
382         .errata = &r520_errata,
383         .vram_info = &r520_vram_info,
384         .gpu_reset = &rv515_gpu_reset,
385         .mc_init = &r520_mc_init,
386         .mc_fini = &r520_mc_fini,
387         .wb_init = &r100_wb_init,
388         .wb_fini = &r100_wb_fini,
389         .gart_enable = &r300_gart_enable,
390         .gart_disable = &rv370_pcie_gart_disable,
391         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
392         .gart_set_page = &rv370_pcie_gart_set_page,
393         .cp_init = &r100_cp_init,
394         .cp_fini = &r100_cp_fini,
395         .cp_disable = &r100_cp_disable,
396         .ring_start = &rv515_ring_start,
397         .irq_set = &r100_irq_set,
398         .irq_process = &r100_irq_process,
399         .fence_ring_emit = &r300_fence_ring_emit,
400         .cs_parse = &r300_cs_parse,
401         .copy_blit = &r100_copy_blit,
402         .copy_dma = &r300_copy_dma,
403         .copy = &r100_copy_blit,
404         .set_engine_clock = &radeon_atom_set_engine_clock,
405         .set_memory_clock = &radeon_atom_set_memory_clock,
406         .set_pcie_lanes = &rv370_set_pcie_lanes,
407         .set_clock_gating = &radeon_atom_set_clock_gating,
408 };
409
410 /*
411  * r600,rv610,rv630,rv620,rv635,rv670,rs780,rv770,rv730,rv710
412  */
413 uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
414 void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
415
416 #endif