5f2a9e6f12c5baeaa36bf2e7e8bc34afcb220a0a
[linux-2.6.git] / drivers / gpu / drm / radeon / radeon_asic.h
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #ifndef __RADEON_ASIC_H__
29 #define __RADEON_ASIC_H__
30
31 /*
32  * common functions
33  */
34 void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
35 void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
36
37 void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
38 void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
39 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
40
41 /*
42  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
43  */
44 int r100_init(struct radeon_device *rdev);
45 int r200_init(struct radeon_device *rdev);
46 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
47 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
48 void r100_errata(struct radeon_device *rdev);
49 void r100_vram_info(struct radeon_device *rdev);
50 int r100_gpu_reset(struct radeon_device *rdev);
51 int r100_mc_init(struct radeon_device *rdev);
52 void r100_mc_fini(struct radeon_device *rdev);
53 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
54 int r100_wb_init(struct radeon_device *rdev);
55 void r100_wb_fini(struct radeon_device *rdev);
56 int r100_pci_gart_init(struct radeon_device *rdev);
57 void r100_pci_gart_fini(struct radeon_device *rdev);
58 int r100_pci_gart_enable(struct radeon_device *rdev);
59 void r100_pci_gart_disable(struct radeon_device *rdev);
60 void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
61 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
62 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
63 void r100_cp_fini(struct radeon_device *rdev);
64 void r100_cp_disable(struct radeon_device *rdev);
65 void r100_cp_commit(struct radeon_device *rdev);
66 void r100_ring_start(struct radeon_device *rdev);
67 int r100_irq_set(struct radeon_device *rdev);
68 int r100_irq_process(struct radeon_device *rdev);
69 void r100_fence_ring_emit(struct radeon_device *rdev,
70                           struct radeon_fence *fence);
71 int r100_cs_parse(struct radeon_cs_parser *p);
72 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
73 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
74 int r100_copy_blit(struct radeon_device *rdev,
75                    uint64_t src_offset,
76                    uint64_t dst_offset,
77                    unsigned num_pages,
78                    struct radeon_fence *fence);
79 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
80                          uint32_t tiling_flags, uint32_t pitch,
81                          uint32_t offset, uint32_t obj_size);
82 int r100_clear_surface_reg(struct radeon_device *rdev, int reg);
83 void r100_bandwidth_update(struct radeon_device *rdev);
84 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
85 int r100_ib_test(struct radeon_device *rdev);
86 int r100_ring_test(struct radeon_device *rdev);
87
88 static struct radeon_asic r100_asic = {
89         .init = &r100_init,
90         .errata = &r100_errata,
91         .vram_info = &r100_vram_info,
92         .gpu_reset = &r100_gpu_reset,
93         .mc_init = &r100_mc_init,
94         .mc_fini = &r100_mc_fini,
95         .wb_init = &r100_wb_init,
96         .wb_fini = &r100_wb_fini,
97         .gart_init = &r100_pci_gart_init,
98         .gart_fini = &r100_pci_gart_fini,
99         .gart_enable = &r100_pci_gart_enable,
100         .gart_disable = &r100_pci_gart_disable,
101         .gart_tlb_flush = &r100_pci_gart_tlb_flush,
102         .gart_set_page = &r100_pci_gart_set_page,
103         .cp_init = &r100_cp_init,
104         .cp_fini = &r100_cp_fini,
105         .cp_disable = &r100_cp_disable,
106         .cp_commit = &r100_cp_commit,
107         .ring_start = &r100_ring_start,
108         .ring_test = &r100_ring_test,
109         .ring_ib_execute = &r100_ring_ib_execute,
110         .ib_test = &r100_ib_test,
111         .irq_set = &r100_irq_set,
112         .irq_process = &r100_irq_process,
113         .get_vblank_counter = &r100_get_vblank_counter,
114         .fence_ring_emit = &r100_fence_ring_emit,
115         .cs_parse = &r100_cs_parse,
116         .copy_blit = &r100_copy_blit,
117         .copy_dma = NULL,
118         .copy = &r100_copy_blit,
119         .set_engine_clock = &radeon_legacy_set_engine_clock,
120         .set_memory_clock = NULL,
121         .set_pcie_lanes = NULL,
122         .set_clock_gating = &radeon_legacy_set_clock_gating,
123         .set_surface_reg = r100_set_surface_reg,
124         .clear_surface_reg = r100_clear_surface_reg,
125         .bandwidth_update = &r100_bandwidth_update,
126 };
127
128
129 /*
130  * r300,r350,rv350,rv380
131  */
132 int r300_init(struct radeon_device *rdev);
133 void r300_errata(struct radeon_device *rdev);
134 void r300_vram_info(struct radeon_device *rdev);
135 int r300_gpu_reset(struct radeon_device *rdev);
136 int r300_mc_init(struct radeon_device *rdev);
137 void r300_mc_fini(struct radeon_device *rdev);
138 void r300_ring_start(struct radeon_device *rdev);
139 void r300_fence_ring_emit(struct radeon_device *rdev,
140                           struct radeon_fence *fence);
141 int r300_cs_parse(struct radeon_cs_parser *p);
142 int rv370_pcie_gart_init(struct radeon_device *rdev);
143 void rv370_pcie_gart_fini(struct radeon_device *rdev);
144 int rv370_pcie_gart_enable(struct radeon_device *rdev);
145 void rv370_pcie_gart_disable(struct radeon_device *rdev);
146 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
147 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
148 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
149 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
150 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
151 int r300_copy_dma(struct radeon_device *rdev,
152                   uint64_t src_offset,
153                   uint64_t dst_offset,
154                   unsigned num_pages,
155                   struct radeon_fence *fence);
156
157 static struct radeon_asic r300_asic = {
158         .init = &r300_init,
159         .errata = &r300_errata,
160         .vram_info = &r300_vram_info,
161         .gpu_reset = &r300_gpu_reset,
162         .mc_init = &r300_mc_init,
163         .mc_fini = &r300_mc_fini,
164         .wb_init = &r100_wb_init,
165         .wb_fini = &r100_wb_fini,
166         .gart_init = &r100_pci_gart_init,
167         .gart_fini = &r100_pci_gart_fini,
168         .gart_enable = &r100_pci_gart_enable,
169         .gart_disable = &r100_pci_gart_disable,
170         .gart_tlb_flush = &r100_pci_gart_tlb_flush,
171         .gart_set_page = &r100_pci_gart_set_page,
172         .cp_init = &r100_cp_init,
173         .cp_fini = &r100_cp_fini,
174         .cp_disable = &r100_cp_disable,
175         .cp_commit = &r100_cp_commit,
176         .ring_start = &r300_ring_start,
177         .ring_test = &r100_ring_test,
178         .ring_ib_execute = &r100_ring_ib_execute,
179         .ib_test = &r100_ib_test,
180         .irq_set = &r100_irq_set,
181         .irq_process = &r100_irq_process,
182         .get_vblank_counter = &r100_get_vblank_counter,
183         .fence_ring_emit = &r300_fence_ring_emit,
184         .cs_parse = &r300_cs_parse,
185         .copy_blit = &r100_copy_blit,
186         .copy_dma = &r300_copy_dma,
187         .copy = &r100_copy_blit,
188         .set_engine_clock = &radeon_legacy_set_engine_clock,
189         .set_memory_clock = NULL,
190         .set_pcie_lanes = &rv370_set_pcie_lanes,
191         .set_clock_gating = &radeon_legacy_set_clock_gating,
192         .set_surface_reg = r100_set_surface_reg,
193         .clear_surface_reg = r100_clear_surface_reg,
194         .bandwidth_update = &r100_bandwidth_update,
195 };
196
197 /*
198  * r420,r423,rv410
199  */
200 extern int r420_init(struct radeon_device *rdev);
201 extern void r420_fini(struct radeon_device *rdev);
202 extern int r420_suspend(struct radeon_device *rdev);
203 extern int r420_resume(struct radeon_device *rdev);
204 static struct radeon_asic r420_asic = {
205         .init = &r420_init,
206         .fini = &r420_fini,
207         .suspend = &r420_suspend,
208         .resume = &r420_resume,
209         .errata = NULL,
210         .vram_info = NULL,
211         .gpu_reset = &r300_gpu_reset,
212         .mc_init = NULL,
213         .mc_fini = NULL,
214         .wb_init = NULL,
215         .wb_fini = NULL,
216         .gart_enable = NULL,
217         .gart_disable = NULL,
218         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
219         .gart_set_page = &rv370_pcie_gart_set_page,
220         .cp_init = NULL,
221         .cp_fini = NULL,
222         .cp_disable = NULL,
223         .cp_commit = &r100_cp_commit,
224         .ring_start = &r300_ring_start,
225         .ring_test = &r100_ring_test,
226         .ring_ib_execute = &r100_ring_ib_execute,
227         .ib_test = NULL,
228         .irq_set = &r100_irq_set,
229         .irq_process = &r100_irq_process,
230         .get_vblank_counter = &r100_get_vblank_counter,
231         .fence_ring_emit = &r300_fence_ring_emit,
232         .cs_parse = &r300_cs_parse,
233         .copy_blit = &r100_copy_blit,
234         .copy_dma = &r300_copy_dma,
235         .copy = &r100_copy_blit,
236         .set_engine_clock = &radeon_atom_set_engine_clock,
237         .set_memory_clock = &radeon_atom_set_memory_clock,
238         .set_pcie_lanes = &rv370_set_pcie_lanes,
239         .set_clock_gating = &radeon_atom_set_clock_gating,
240         .set_surface_reg = r100_set_surface_reg,
241         .clear_surface_reg = r100_clear_surface_reg,
242         .bandwidth_update = &r100_bandwidth_update,
243 };
244
245
246 /*
247  * rs400,rs480
248  */
249 void rs400_errata(struct radeon_device *rdev);
250 void rs400_vram_info(struct radeon_device *rdev);
251 int rs400_mc_init(struct radeon_device *rdev);
252 void rs400_mc_fini(struct radeon_device *rdev);
253 int rs400_gart_init(struct radeon_device *rdev);
254 void rs400_gart_fini(struct radeon_device *rdev);
255 int rs400_gart_enable(struct radeon_device *rdev);
256 void rs400_gart_disable(struct radeon_device *rdev);
257 void rs400_gart_tlb_flush(struct radeon_device *rdev);
258 int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
259 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
260 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
261 static struct radeon_asic rs400_asic = {
262         .init = &r300_init,
263         .errata = &rs400_errata,
264         .vram_info = &rs400_vram_info,
265         .gpu_reset = &r300_gpu_reset,
266         .mc_init = &rs400_mc_init,
267         .mc_fini = &rs400_mc_fini,
268         .wb_init = &r100_wb_init,
269         .wb_fini = &r100_wb_fini,
270         .gart_init = &rs400_gart_init,
271         .gart_fini = &rs400_gart_fini,
272         .gart_enable = &rs400_gart_enable,
273         .gart_disable = &rs400_gart_disable,
274         .gart_tlb_flush = &rs400_gart_tlb_flush,
275         .gart_set_page = &rs400_gart_set_page,
276         .cp_init = &r100_cp_init,
277         .cp_fini = &r100_cp_fini,
278         .cp_disable = &r100_cp_disable,
279         .cp_commit = &r100_cp_commit,
280         .ring_start = &r300_ring_start,
281         .ring_test = &r100_ring_test,
282         .ring_ib_execute = &r100_ring_ib_execute,
283         .ib_test = &r100_ib_test,
284         .irq_set = &r100_irq_set,
285         .irq_process = &r100_irq_process,
286         .get_vblank_counter = &r100_get_vblank_counter,
287         .fence_ring_emit = &r300_fence_ring_emit,
288         .cs_parse = &r300_cs_parse,
289         .copy_blit = &r100_copy_blit,
290         .copy_dma = &r300_copy_dma,
291         .copy = &r100_copy_blit,
292         .set_engine_clock = &radeon_legacy_set_engine_clock,
293         .set_memory_clock = NULL,
294         .set_pcie_lanes = NULL,
295         .set_clock_gating = &radeon_legacy_set_clock_gating,
296         .set_surface_reg = r100_set_surface_reg,
297         .clear_surface_reg = r100_clear_surface_reg,
298         .bandwidth_update = &r100_bandwidth_update,
299 };
300
301
302 /*
303  * rs600.
304  */
305 int rs600_init(struct radeon_device *rdev);
306 void rs600_errata(struct radeon_device *rdev);
307 void rs600_vram_info(struct radeon_device *rdev);
308 int rs600_mc_init(struct radeon_device *rdev);
309 void rs600_mc_fini(struct radeon_device *rdev);
310 int rs600_irq_set(struct radeon_device *rdev);
311 int rs600_irq_process(struct radeon_device *rdev);
312 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
313 int rs600_gart_init(struct radeon_device *rdev);
314 void rs600_gart_fini(struct radeon_device *rdev);
315 int rs600_gart_enable(struct radeon_device *rdev);
316 void rs600_gart_disable(struct radeon_device *rdev);
317 void rs600_gart_tlb_flush(struct radeon_device *rdev);
318 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
319 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
320 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
321 void rs600_bandwidth_update(struct radeon_device *rdev);
322 static struct radeon_asic rs600_asic = {
323         .init = &rs600_init,
324         .errata = &rs600_errata,
325         .vram_info = &rs600_vram_info,
326         .gpu_reset = &r300_gpu_reset,
327         .mc_init = &rs600_mc_init,
328         .mc_fini = &rs600_mc_fini,
329         .wb_init = &r100_wb_init,
330         .wb_fini = &r100_wb_fini,
331         .gart_init = &rs600_gart_init,
332         .gart_fini = &rs600_gart_fini,
333         .gart_enable = &rs600_gart_enable,
334         .gart_disable = &rs600_gart_disable,
335         .gart_tlb_flush = &rs600_gart_tlb_flush,
336         .gart_set_page = &rs600_gart_set_page,
337         .cp_init = &r100_cp_init,
338         .cp_fini = &r100_cp_fini,
339         .cp_disable = &r100_cp_disable,
340         .cp_commit = &r100_cp_commit,
341         .ring_start = &r300_ring_start,
342         .ring_test = &r100_ring_test,
343         .ring_ib_execute = &r100_ring_ib_execute,
344         .ib_test = &r100_ib_test,
345         .irq_set = &rs600_irq_set,
346         .irq_process = &rs600_irq_process,
347         .get_vblank_counter = &rs600_get_vblank_counter,
348         .fence_ring_emit = &r300_fence_ring_emit,
349         .cs_parse = &r300_cs_parse,
350         .copy_blit = &r100_copy_blit,
351         .copy_dma = &r300_copy_dma,
352         .copy = &r100_copy_blit,
353         .set_engine_clock = &radeon_atom_set_engine_clock,
354         .set_memory_clock = &radeon_atom_set_memory_clock,
355         .set_pcie_lanes = NULL,
356         .set_clock_gating = &radeon_atom_set_clock_gating,
357         .bandwidth_update = &rs600_bandwidth_update,
358 };
359
360
361 /*
362  * rs690,rs740
363  */
364 void rs690_errata(struct radeon_device *rdev);
365 void rs690_vram_info(struct radeon_device *rdev);
366 int rs690_mc_init(struct radeon_device *rdev);
367 void rs690_mc_fini(struct radeon_device *rdev);
368 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
369 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
370 void rs690_bandwidth_update(struct radeon_device *rdev);
371 static struct radeon_asic rs690_asic = {
372         .init = &rs600_init,
373         .errata = &rs690_errata,
374         .vram_info = &rs690_vram_info,
375         .gpu_reset = &r300_gpu_reset,
376         .mc_init = &rs690_mc_init,
377         .mc_fini = &rs690_mc_fini,
378         .wb_init = &r100_wb_init,
379         .wb_fini = &r100_wb_fini,
380         .gart_init = &rs400_gart_init,
381         .gart_fini = &rs400_gart_fini,
382         .gart_enable = &rs400_gart_enable,
383         .gart_disable = &rs400_gart_disable,
384         .gart_tlb_flush = &rs400_gart_tlb_flush,
385         .gart_set_page = &rs400_gart_set_page,
386         .cp_init = &r100_cp_init,
387         .cp_fini = &r100_cp_fini,
388         .cp_disable = &r100_cp_disable,
389         .cp_commit = &r100_cp_commit,
390         .ring_start = &r300_ring_start,
391         .ring_test = &r100_ring_test,
392         .ring_ib_execute = &r100_ring_ib_execute,
393         .ib_test = &r100_ib_test,
394         .irq_set = &rs600_irq_set,
395         .irq_process = &rs600_irq_process,
396         .get_vblank_counter = &rs600_get_vblank_counter,
397         .fence_ring_emit = &r300_fence_ring_emit,
398         .cs_parse = &r300_cs_parse,
399         .copy_blit = &r100_copy_blit,
400         .copy_dma = &r300_copy_dma,
401         .copy = &r300_copy_dma,
402         .set_engine_clock = &radeon_atom_set_engine_clock,
403         .set_memory_clock = &radeon_atom_set_memory_clock,
404         .set_pcie_lanes = NULL,
405         .set_clock_gating = &radeon_atom_set_clock_gating,
406         .set_surface_reg = r100_set_surface_reg,
407         .clear_surface_reg = r100_clear_surface_reg,
408         .bandwidth_update = &rs690_bandwidth_update,
409 };
410
411
412 /*
413  * rv515
414  */
415 int rv515_init(struct radeon_device *rdev);
416 void rv515_errata(struct radeon_device *rdev);
417 void rv515_vram_info(struct radeon_device *rdev);
418 int rv515_gpu_reset(struct radeon_device *rdev);
419 int rv515_mc_init(struct radeon_device *rdev);
420 void rv515_mc_fini(struct radeon_device *rdev);
421 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
422 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
423 void rv515_ring_start(struct radeon_device *rdev);
424 uint32_t rv515_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
425 void rv515_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
426 void rv515_bandwidth_update(struct radeon_device *rdev);
427 static struct radeon_asic rv515_asic = {
428         .init = &rv515_init,
429         .errata = &rv515_errata,
430         .vram_info = &rv515_vram_info,
431         .gpu_reset = &rv515_gpu_reset,
432         .mc_init = &rv515_mc_init,
433         .mc_fini = &rv515_mc_fini,
434         .wb_init = &r100_wb_init,
435         .wb_fini = &r100_wb_fini,
436         .gart_init = &rv370_pcie_gart_init,
437         .gart_fini = &rv370_pcie_gart_fini,
438         .gart_enable = &rv370_pcie_gart_enable,
439         .gart_disable = &rv370_pcie_gart_disable,
440         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
441         .gart_set_page = &rv370_pcie_gart_set_page,
442         .cp_init = &r100_cp_init,
443         .cp_fini = &r100_cp_fini,
444         .cp_disable = &r100_cp_disable,
445         .cp_commit = &r100_cp_commit,
446         .ring_start = &rv515_ring_start,
447         .ring_test = &r100_ring_test,
448         .ring_ib_execute = &r100_ring_ib_execute,
449         .ib_test = &r100_ib_test,
450         .irq_set = &rs600_irq_set,
451         .irq_process = &rs600_irq_process,
452         .get_vblank_counter = &rs600_get_vblank_counter,
453         .fence_ring_emit = &r300_fence_ring_emit,
454         .cs_parse = &r300_cs_parse,
455         .copy_blit = &r100_copy_blit,
456         .copy_dma = &r300_copy_dma,
457         .copy = &r100_copy_blit,
458         .set_engine_clock = &radeon_atom_set_engine_clock,
459         .set_memory_clock = &radeon_atom_set_memory_clock,
460         .set_pcie_lanes = &rv370_set_pcie_lanes,
461         .set_clock_gating = &radeon_atom_set_clock_gating,
462         .set_surface_reg = r100_set_surface_reg,
463         .clear_surface_reg = r100_clear_surface_reg,
464         .bandwidth_update = &rv515_bandwidth_update,
465 };
466
467
468 /*
469  * r520,rv530,rv560,rv570,r580
470  */
471 void r520_errata(struct radeon_device *rdev);
472 void r520_vram_info(struct radeon_device *rdev);
473 int r520_mc_init(struct radeon_device *rdev);
474 void r520_mc_fini(struct radeon_device *rdev);
475 void r520_bandwidth_update(struct radeon_device *rdev);
476 static struct radeon_asic r520_asic = {
477         .init = &rv515_init,
478         .errata = &r520_errata,
479         .vram_info = &r520_vram_info,
480         .gpu_reset = &rv515_gpu_reset,
481         .mc_init = &r520_mc_init,
482         .mc_fini = &r520_mc_fini,
483         .wb_init = &r100_wb_init,
484         .wb_fini = &r100_wb_fini,
485         .gart_init = &rv370_pcie_gart_init,
486         .gart_fini = &rv370_pcie_gart_fini,
487         .gart_enable = &rv370_pcie_gart_enable,
488         .gart_disable = &rv370_pcie_gart_disable,
489         .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
490         .gart_set_page = &rv370_pcie_gart_set_page,
491         .cp_init = &r100_cp_init,
492         .cp_fini = &r100_cp_fini,
493         .cp_disable = &r100_cp_disable,
494         .cp_commit = &r100_cp_commit,
495         .ring_start = &rv515_ring_start,
496         .ring_test = &r100_ring_test,
497         .ring_ib_execute = &r100_ring_ib_execute,
498         .ib_test = &r100_ib_test,
499         .irq_set = &rs600_irq_set,
500         .irq_process = &rs600_irq_process,
501         .get_vblank_counter = &rs600_get_vblank_counter,
502         .fence_ring_emit = &r300_fence_ring_emit,
503         .cs_parse = &r300_cs_parse,
504         .copy_blit = &r100_copy_blit,
505         .copy_dma = &r300_copy_dma,
506         .copy = &r100_copy_blit,
507         .set_engine_clock = &radeon_atom_set_engine_clock,
508         .set_memory_clock = &radeon_atom_set_memory_clock,
509         .set_pcie_lanes = &rv370_set_pcie_lanes,
510         .set_clock_gating = &radeon_atom_set_clock_gating,
511         .set_surface_reg = r100_set_surface_reg,
512         .clear_surface_reg = r100_clear_surface_reg,
513         .bandwidth_update = &r520_bandwidth_update,
514 };
515
516 /*
517  * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
518  */
519 int r600_init(struct radeon_device *rdev);
520 void r600_fini(struct radeon_device *rdev);
521 int r600_suspend(struct radeon_device *rdev);
522 int r600_resume(struct radeon_device *rdev);
523 int r600_wb_init(struct radeon_device *rdev);
524 void r600_wb_fini(struct radeon_device *rdev);
525 void r600_cp_commit(struct radeon_device *rdev);
526 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
527 uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
528 void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
529 int r600_cs_parse(struct radeon_cs_parser *p);
530 void r600_fence_ring_emit(struct radeon_device *rdev,
531                           struct radeon_fence *fence);
532 int r600_copy_dma(struct radeon_device *rdev,
533                   uint64_t src_offset,
534                   uint64_t dst_offset,
535                   unsigned num_pages,
536                   struct radeon_fence *fence);
537 int r600_irq_process(struct radeon_device *rdev);
538 int r600_irq_set(struct radeon_device *rdev);
539 int r600_gpu_reset(struct radeon_device *rdev);
540 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
541                          uint32_t tiling_flags, uint32_t pitch,
542                          uint32_t offset, uint32_t obj_size);
543 int r600_clear_surface_reg(struct radeon_device *rdev, int reg);
544 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
545 int r600_ib_test(struct radeon_device *rdev);
546 int r600_ring_test(struct radeon_device *rdev);
547 int r600_copy_blit(struct radeon_device *rdev,
548                    uint64_t src_offset, uint64_t dst_offset,
549                    unsigned num_pages, struct radeon_fence *fence);
550
551 static struct radeon_asic r600_asic = {
552         .errata = NULL,
553         .init = &r600_init,
554         .fini = &r600_fini,
555         .suspend = &r600_suspend,
556         .resume = &r600_resume,
557         .cp_commit = &r600_cp_commit,
558         .vram_info = NULL,
559         .gpu_reset = &r600_gpu_reset,
560         .mc_init = NULL,
561         .mc_fini = NULL,
562         .wb_init = &r600_wb_init,
563         .wb_fini = &r600_wb_fini,
564         .gart_enable = NULL,
565         .gart_disable = NULL,
566         .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
567         .gart_set_page = &rs600_gart_set_page,
568         .cp_init = NULL,
569         .cp_fini = NULL,
570         .cp_disable = NULL,
571         .ring_start = NULL,
572         .ring_test = &r600_ring_test,
573         .ring_ib_execute = &r600_ring_ib_execute,
574         .ib_test = &r600_ib_test,
575         .irq_set = &r600_irq_set,
576         .irq_process = &r600_irq_process,
577         .fence_ring_emit = &r600_fence_ring_emit,
578         .cs_parse = &r600_cs_parse,
579         .copy_blit = &r600_copy_blit,
580         .copy_dma = &r600_copy_blit,
581         .copy = &r600_copy_blit,
582         .set_engine_clock = &radeon_atom_set_engine_clock,
583         .set_memory_clock = &radeon_atom_set_memory_clock,
584         .set_pcie_lanes = NULL,
585         .set_clock_gating = &radeon_atom_set_clock_gating,
586         .set_surface_reg = r600_set_surface_reg,
587         .clear_surface_reg = r600_clear_surface_reg,
588         .bandwidth_update = &r520_bandwidth_update,
589 };
590
591 /*
592  * rv770,rv730,rv710,rv740
593  */
594 int rv770_init(struct radeon_device *rdev);
595 void rv770_fini(struct radeon_device *rdev);
596 int rv770_suspend(struct radeon_device *rdev);
597 int rv770_resume(struct radeon_device *rdev);
598 int rv770_gpu_reset(struct radeon_device *rdev);
599
600 static struct radeon_asic rv770_asic = {
601         .errata = NULL,
602         .init = &rv770_init,
603         .fini = &rv770_fini,
604         .suspend = &rv770_suspend,
605         .resume = &rv770_resume,
606         .cp_commit = &r600_cp_commit,
607         .vram_info = NULL,
608         .gpu_reset = &rv770_gpu_reset,
609         .mc_init = NULL,
610         .mc_fini = NULL,
611         .wb_init = &r600_wb_init,
612         .wb_fini = &r600_wb_fini,
613         .gart_enable = NULL,
614         .gart_disable = NULL,
615         .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
616         .gart_set_page = &rs600_gart_set_page,
617         .cp_init = NULL,
618         .cp_fini = NULL,
619         .cp_disable = NULL,
620         .ring_start = NULL,
621         .ring_test = &r600_ring_test,
622         .ring_ib_execute = &r600_ring_ib_execute,
623         .ib_test = &r600_ib_test,
624         .irq_set = &r600_irq_set,
625         .irq_process = &r600_irq_process,
626         .fence_ring_emit = &r600_fence_ring_emit,
627         .cs_parse = &r600_cs_parse,
628         .copy_blit = &r600_copy_blit,
629         .copy_dma = &r600_copy_blit,
630         .copy = &r600_copy_blit,
631         .set_engine_clock = &radeon_atom_set_engine_clock,
632         .set_memory_clock = &radeon_atom_set_memory_clock,
633         .set_pcie_lanes = NULL,
634         .set_clock_gating = &radeon_atom_set_clock_gating,
635         .set_surface_reg = r600_set_surface_reg,
636         .clear_surface_reg = r600_clear_surface_reg,
637         .bandwidth_update = &r520_bandwidth_update,
638 };
639
640 #endif