Merge branch 'drm-next' of ../drm-next into drm-linus
[linux-2.6.git] / drivers / gpu / drm / radeon / r600d.h
1 /*
2  * Copyright 2009 Advanced Micro Devices, Inc.
3  * Copyright 2009 Red Hat Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: Dave Airlie
24  *          Alex Deucher
25  *          Jerome Glisse
26  */
27 #ifndef R600D_H
28 #define R600D_H
29
30 #define CP_PACKET2                      0x80000000
31 #define         PACKET2_PAD_SHIFT               0
32 #define         PACKET2_PAD_MASK                (0x3fffffff << 0)
33
34 #define PACKET2(v)      (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
35
36 #define R6XX_MAX_SH_GPRS                        256
37 #define R6XX_MAX_TEMP_GPRS                      16
38 #define R6XX_MAX_SH_THREADS                     256
39 #define R6XX_MAX_SH_STACK_ENTRIES               4096
40 #define R6XX_MAX_BACKENDS                       8
41 #define R6XX_MAX_BACKENDS_MASK                  0xff
42 #define R6XX_MAX_SIMDS                          8
43 #define R6XX_MAX_SIMDS_MASK                     0xff
44 #define R6XX_MAX_PIPES                          8
45 #define R6XX_MAX_PIPES_MASK                     0xff
46
47 /* PTE flags */
48 #define PTE_VALID                               (1 << 0)
49 #define PTE_SYSTEM                              (1 << 1)
50 #define PTE_SNOOPED                             (1 << 2)
51 #define PTE_READABLE                            (1 << 5)
52 #define PTE_WRITEABLE                           (1 << 6)
53
54 /* Registers */
55 #define ARB_POP                                         0x2418
56 #define         ENABLE_TC128                                    (1 << 30)
57 #define ARB_GDEC_RD_CNTL                                0x246C
58
59 #define CC_GC_SHADER_PIPE_CONFIG                        0x8950
60 #define CC_RB_BACKEND_DISABLE                           0x98F4
61 #define         BACKEND_DISABLE(x)                              ((x) << 16)
62
63 #define CB_COLOR0_BASE                                  0x28040
64 #define CB_COLOR1_BASE                                  0x28044
65 #define CB_COLOR2_BASE                                  0x28048
66 #define CB_COLOR3_BASE                                  0x2804C
67 #define CB_COLOR4_BASE                                  0x28050
68 #define CB_COLOR5_BASE                                  0x28054
69 #define CB_COLOR6_BASE                                  0x28058
70 #define CB_COLOR7_BASE                                  0x2805C
71 #define CB_COLOR7_FRAG                                  0x280FC
72
73 #define CB_COLOR0_SIZE                                  0x28060
74 #define CB_COLOR0_VIEW                                  0x28080
75 #define CB_COLOR0_INFO                                  0x280a0
76 #define CB_COLOR0_TILE                                  0x280c0
77 #define CB_COLOR0_FRAG                                  0x280e0
78 #define CB_COLOR0_MASK                                  0x28100
79
80 #define CONFIG_MEMSIZE                                  0x5428
81 #define CONFIG_CNTL                                     0x5424
82 #define CP_STAT                                         0x8680
83 #define CP_COHER_BASE                                   0x85F8
84 #define CP_DEBUG                                        0xC1FC
85 #define R_0086D8_CP_ME_CNTL                     0x86D8
86 #define         S_0086D8_CP_ME_HALT(x)                  (((x) & 1)<<28)
87 #define         C_0086D8_CP_ME_HALT(x)                  ((x) & 0xEFFFFFFF)
88 #define CP_ME_RAM_DATA                                  0xC160
89 #define CP_ME_RAM_RADDR                                 0xC158
90 #define CP_ME_RAM_WADDR                                 0xC15C
91 #define CP_MEQ_THRESHOLDS                               0x8764
92 #define         MEQ_END(x)                                      ((x) << 16)
93 #define         ROQ_END(x)                                      ((x) << 24)
94 #define CP_PERFMON_CNTL                                 0x87FC
95 #define CP_PFP_UCODE_ADDR                               0xC150
96 #define CP_PFP_UCODE_DATA                               0xC154
97 #define CP_QUEUE_THRESHOLDS                             0x8760
98 #define         ROQ_IB1_START(x)                                ((x) << 0)
99 #define         ROQ_IB2_START(x)                                ((x) << 8)
100 #define CP_RB_BASE                                      0xC100
101 #define CP_RB_CNTL                                      0xC104
102 #define         RB_BUFSZ(x)                                     ((x)<<0)
103 #define         RB_BLKSZ(x)                                     ((x)<<8)
104 #define         RB_NO_UPDATE                                    (1<<27)
105 #define         RB_RPTR_WR_ENA                                  (1<<31)
106 #define         BUF_SWAP_32BIT                                  (2 << 16)
107 #define CP_RB_RPTR                                      0x8700
108 #define CP_RB_RPTR_ADDR                                 0xC10C
109 #define CP_RB_RPTR_ADDR_HI                              0xC110
110 #define CP_RB_RPTR_WR                                   0xC108
111 #define CP_RB_WPTR                                      0xC114
112 #define CP_RB_WPTR_ADDR                                 0xC118
113 #define CP_RB_WPTR_ADDR_HI                              0xC11C
114 #define CP_RB_WPTR_DELAY                                0x8704
115 #define CP_ROQ_IB1_STAT                                 0x8784
116 #define CP_ROQ_IB2_STAT                                 0x8788
117 #define CP_SEM_WAIT_TIMER                               0x85BC
118
119 #define DB_DEBUG                                        0x9830
120 #define         PREZ_MUST_WAIT_FOR_POSTZ_DONE                   (1 << 31)
121 #define DB_DEPTH_BASE                                   0x2800C
122 #define DB_WATERMARKS                                   0x9838
123 #define         DEPTH_FREE(x)                                   ((x) << 0)
124 #define         DEPTH_FLUSH(x)                                  ((x) << 5)
125 #define         DEPTH_PENDING_FREE(x)                           ((x) << 15)
126 #define         DEPTH_CACHELINE_FREE(x)                         ((x) << 20)
127
128 #define DCP_TILING_CONFIG                               0x6CA0
129 #define         PIPE_TILING(x)                                  ((x) << 1)
130 #define         BANK_TILING(x)                                  ((x) << 4)
131 #define         GROUP_SIZE(x)                                   ((x) << 6)
132 #define         ROW_TILING(x)                                   ((x) << 8)
133 #define         BANK_SWAPS(x)                                   ((x) << 11)
134 #define         SAMPLE_SPLIT(x)                                 ((x) << 14)
135 #define         BACKEND_MAP(x)                                  ((x) << 16)
136
137 #define GB_TILING_CONFIG                                0x98F0
138
139 #define GC_USER_SHADER_PIPE_CONFIG                      0x8954
140 #define         INACTIVE_QD_PIPES(x)                            ((x) << 8)
141 #define         INACTIVE_QD_PIPES_MASK                          0x0000FF00
142 #define         INACTIVE_SIMDS(x)                               ((x) << 16)
143 #define         INACTIVE_SIMDS_MASK                             0x00FF0000
144
145 #define SQ_CONFIG                                         0x8c00
146 #       define VC_ENABLE                                  (1 << 0)
147 #       define EXPORT_SRC_C                               (1 << 1)
148 #       define DX9_CONSTS                                 (1 << 2)
149 #       define ALU_INST_PREFER_VECTOR                     (1 << 3)
150 #       define DX10_CLAMP                                 (1 << 4)
151 #       define CLAUSE_SEQ_PRIO(x)                         ((x) << 8)
152 #       define PS_PRIO(x)                                 ((x) << 24)
153 #       define VS_PRIO(x)                                 ((x) << 26)
154 #       define GS_PRIO(x)                                 ((x) << 28)
155 #       define ES_PRIO(x)                                 ((x) << 30)
156 #define SQ_GPR_RESOURCE_MGMT_1                            0x8c04
157 #       define NUM_PS_GPRS(x)                             ((x) << 0)
158 #       define NUM_VS_GPRS(x)                             ((x) << 16)
159 #       define NUM_CLAUSE_TEMP_GPRS(x)                    ((x) << 28)
160 #define SQ_GPR_RESOURCE_MGMT_2                            0x8c08
161 #       define NUM_GS_GPRS(x)                             ((x) << 0)
162 #       define NUM_ES_GPRS(x)                             ((x) << 16)
163 #define SQ_THREAD_RESOURCE_MGMT                           0x8c0c
164 #       define NUM_PS_THREADS(x)                          ((x) << 0)
165 #       define NUM_VS_THREADS(x)                          ((x) << 8)
166 #       define NUM_GS_THREADS(x)                          ((x) << 16)
167 #       define NUM_ES_THREADS(x)                          ((x) << 24)
168 #define SQ_STACK_RESOURCE_MGMT_1                          0x8c10
169 #       define NUM_PS_STACK_ENTRIES(x)                    ((x) << 0)
170 #       define NUM_VS_STACK_ENTRIES(x)                    ((x) << 16)
171 #define SQ_STACK_RESOURCE_MGMT_2                          0x8c14
172 #       define NUM_GS_STACK_ENTRIES(x)                    ((x) << 0)
173 #       define NUM_ES_STACK_ENTRIES(x)                    ((x) << 16)
174
175 #define GRBM_CNTL                                       0x8000
176 #       define GRBM_READ_TIMEOUT(x)                     ((x) << 0)
177 #define GRBM_STATUS                                     0x8010
178 #define         CMDFIFO_AVAIL_MASK                              0x0000001F
179 #define         GUI_ACTIVE                                      (1<<31)
180 #define GRBM_STATUS2                                    0x8014
181 #define GRBM_SOFT_RESET                                 0x8020
182 #define         SOFT_RESET_CP                                   (1<<0)
183
184 #define HDP_HOST_PATH_CNTL                              0x2C00
185 #define HDP_NONSURFACE_BASE                             0x2C04
186 #define HDP_NONSURFACE_INFO                             0x2C08
187 #define HDP_NONSURFACE_SIZE                             0x2C0C
188 #define HDP_REG_COHERENCY_FLUSH_CNTL                    0x54A0
189 #define HDP_TILING_CONFIG                               0x2F3C
190
191 #define MC_VM_AGP_TOP                                   0x2184
192 #define MC_VM_AGP_BOT                                   0x2188
193 #define MC_VM_AGP_BASE                                  0x218C
194 #define MC_VM_FB_LOCATION                               0x2180
195 #define MC_VM_L1_TLB_MCD_RD_A_CNTL                      0x219C
196 #define         ENABLE_L1_TLB                                   (1 << 0)
197 #define         ENABLE_L1_FRAGMENT_PROCESSING                   (1 << 1)
198 #define         ENABLE_L1_STRICT_ORDERING                       (1 << 2)
199 #define         SYSTEM_ACCESS_MODE_MASK                         0x000000C0
200 #define         SYSTEM_ACCESS_MODE_SHIFT                        6
201 #define         SYSTEM_ACCESS_MODE_PA_ONLY                      (0 << 6)
202 #define         SYSTEM_ACCESS_MODE_USE_SYS_MAP                  (1 << 6)
203 #define         SYSTEM_ACCESS_MODE_IN_SYS                       (2 << 6)
204 #define         SYSTEM_ACCESS_MODE_NOT_IN_SYS                   (3 << 6)
205 #define         SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU       (0 << 8)
206 #define         SYSTEM_APERTURE_UNMAPPED_ACCESS_DEFAULT_PAGE    (1 << 8)
207 #define         ENABLE_SEMAPHORE_MODE                           (1 << 10)
208 #define         ENABLE_WAIT_L2_QUERY                            (1 << 11)
209 #define         EFFECTIVE_L1_TLB_SIZE(x)                        (((x) & 7) << 12)
210 #define         EFFECTIVE_L1_TLB_SIZE_MASK                      0x00007000
211 #define         EFFECTIVE_L1_TLB_SIZE_SHIFT                     12
212 #define         EFFECTIVE_L1_QUEUE_SIZE(x)                      (((x) & 7) << 15)
213 #define         EFFECTIVE_L1_QUEUE_SIZE_MASK                    0x00038000
214 #define         EFFECTIVE_L1_QUEUE_SIZE_SHIFT                   15
215 #define MC_VM_L1_TLB_MCD_RD_B_CNTL                      0x21A0
216 #define MC_VM_L1_TLB_MCB_RD_GFX_CNTL                    0x21FC
217 #define MC_VM_L1_TLB_MCB_RD_HDP_CNTL                    0x2204
218 #define MC_VM_L1_TLB_MCB_RD_PDMA_CNTL                   0x2208
219 #define MC_VM_L1_TLB_MCB_RD_SEM_CNTL                    0x220C
220 #define MC_VM_L1_TLB_MCB_RD_SYS_CNTL                    0x2200
221 #define MC_VM_L1_TLB_MCD_WR_A_CNTL                      0x21A4
222 #define MC_VM_L1_TLB_MCD_WR_B_CNTL                      0x21A8
223 #define MC_VM_L1_TLB_MCB_WR_GFX_CNTL                    0x2210
224 #define MC_VM_L1_TLB_MCB_WR_HDP_CNTL                    0x2218
225 #define MC_VM_L1_TLB_MCB_WR_PDMA_CNTL                   0x221C
226 #define MC_VM_L1_TLB_MCB_WR_SEM_CNTL                    0x2220
227 #define MC_VM_L1_TLB_MCB_WR_SYS_CNTL                    0x2214
228 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR                  0x2190
229 #define         LOGICAL_PAGE_NUMBER_MASK                        0x000FFFFF
230 #define         LOGICAL_PAGE_NUMBER_SHIFT                       0
231 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR                 0x2194
232 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR              0x2198
233
234 #define PA_CL_ENHANCE                                   0x8A14
235 #define         CLIP_VTX_REORDER_ENA                            (1 << 0)
236 #define         NUM_CLIP_SEQ(x)                                 ((x) << 1)
237 #define PA_SC_AA_CONFIG                                 0x28C04
238 #define PA_SC_AA_SAMPLE_LOCS_2S                         0x8B40
239 #define PA_SC_AA_SAMPLE_LOCS_4S                         0x8B44
240 #define PA_SC_AA_SAMPLE_LOCS_8S_WD0                     0x8B48
241 #define PA_SC_AA_SAMPLE_LOCS_8S_WD1                     0x8B4C
242 #define         S0_X(x)                                         ((x) << 0)
243 #define         S0_Y(x)                                         ((x) << 4)
244 #define         S1_X(x)                                         ((x) << 8)
245 #define         S1_Y(x)                                         ((x) << 12)
246 #define         S2_X(x)                                         ((x) << 16)
247 #define         S2_Y(x)                                         ((x) << 20)
248 #define         S3_X(x)                                         ((x) << 24)
249 #define         S3_Y(x)                                         ((x) << 28)
250 #define         S4_X(x)                                         ((x) << 0)
251 #define         S4_Y(x)                                         ((x) << 4)
252 #define         S5_X(x)                                         ((x) << 8)
253 #define         S5_Y(x)                                         ((x) << 12)
254 #define         S6_X(x)                                         ((x) << 16)
255 #define         S6_Y(x)                                         ((x) << 20)
256 #define         S7_X(x)                                         ((x) << 24)
257 #define         S7_Y(x)                                         ((x) << 28)
258 #define PA_SC_CLIPRECT_RULE                             0x2820c
259 #define PA_SC_ENHANCE                                   0x8BF0
260 #define         FORCE_EOV_MAX_CLK_CNT(x)                        ((x) << 0)
261 #define         FORCE_EOV_MAX_TILE_CNT(x)                       ((x) << 12)
262 #define PA_SC_LINE_STIPPLE                              0x28A0C
263 #define PA_SC_LINE_STIPPLE_STATE                        0x8B10
264 #define PA_SC_MODE_CNTL                                 0x28A4C
265 #define PA_SC_MULTI_CHIP_CNTL                           0x8B20
266
267 #define PA_SC_SCREEN_SCISSOR_TL                         0x28030
268 #define PA_SC_GENERIC_SCISSOR_TL                        0x28240
269 #define PA_SC_WINDOW_SCISSOR_TL                         0x28204
270
271 #define PCIE_PORT_INDEX                                 0x0038
272 #define PCIE_PORT_DATA                                  0x003C
273
274 #define RAMCFG                                          0x2408
275 #define         NOOFBANK_SHIFT                                  0
276 #define         NOOFBANK_MASK                                   0x00000001
277 #define         NOOFRANK_SHIFT                                  1
278 #define         NOOFRANK_MASK                                   0x00000002
279 #define         NOOFROWS_SHIFT                                  2
280 #define         NOOFROWS_MASK                                   0x0000001C
281 #define         NOOFCOLS_SHIFT                                  5
282 #define         NOOFCOLS_MASK                                   0x00000060
283 #define         CHANSIZE_SHIFT                                  7
284 #define         CHANSIZE_MASK                                   0x00000080
285 #define         BURSTLENGTH_SHIFT                               8
286 #define         BURSTLENGTH_MASK                                0x00000100
287 #define         CHANSIZE_OVERRIDE                               (1 << 10)
288
289 #define SCRATCH_REG0                                    0x8500
290 #define SCRATCH_REG1                                    0x8504
291 #define SCRATCH_REG2                                    0x8508
292 #define SCRATCH_REG3                                    0x850C
293 #define SCRATCH_REG4                                    0x8510
294 #define SCRATCH_REG5                                    0x8514
295 #define SCRATCH_REG6                                    0x8518
296 #define SCRATCH_REG7                                    0x851C
297 #define SCRATCH_UMSK                                    0x8540
298 #define SCRATCH_ADDR                                    0x8544
299
300 #define SPI_CONFIG_CNTL                                 0x9100
301 #define         GPR_WRITE_PRIORITY(x)                           ((x) << 0)
302 #define         DISABLE_INTERP_1                                (1 << 5)
303 #define SPI_CONFIG_CNTL_1                               0x913C
304 #define         VTX_DONE_DELAY(x)                               ((x) << 0)
305 #define         INTERP_ONE_PRIM_PER_ROW                         (1 << 4)
306 #define SPI_INPUT_Z                                     0x286D8
307 #define SPI_PS_IN_CONTROL_0                             0x286CC
308 #define         NUM_INTERP(x)                                   ((x)<<0)
309 #define         POSITION_ENA                                    (1<<8)
310 #define         POSITION_CENTROID                               (1<<9)
311 #define         POSITION_ADDR(x)                                ((x)<<10)
312 #define         PARAM_GEN(x)                                    ((x)<<15)
313 #define         PARAM_GEN_ADDR(x)                               ((x)<<19)
314 #define         BARYC_SAMPLE_CNTL(x)                            ((x)<<26)
315 #define         PERSP_GRADIENT_ENA                              (1<<28)
316 #define         LINEAR_GRADIENT_ENA                             (1<<29)
317 #define         POSITION_SAMPLE                                 (1<<30)
318 #define         BARYC_AT_SAMPLE_ENA                             (1<<31)
319 #define SPI_PS_IN_CONTROL_1                             0x286D0
320 #define         GEN_INDEX_PIX                                   (1<<0)
321 #define         GEN_INDEX_PIX_ADDR(x)                           ((x)<<1)
322 #define         FRONT_FACE_ENA                                  (1<<8)
323 #define         FRONT_FACE_CHAN(x)                              ((x)<<9)
324 #define         FRONT_FACE_ALL_BITS                             (1<<11)
325 #define         FRONT_FACE_ADDR(x)                              ((x)<<12)
326 #define         FOG_ADDR(x)                                     ((x)<<17)
327 #define         FIXED_PT_POSITION_ENA                           (1<<24)
328 #define         FIXED_PT_POSITION_ADDR(x)                       ((x)<<25)
329
330 #define SQ_MS_FIFO_SIZES                                0x8CF0
331 #define         CACHE_FIFO_SIZE(x)                              ((x) << 0)
332 #define         FETCH_FIFO_HIWATER(x)                           ((x) << 8)
333 #define         DONE_FIFO_HIWATER(x)                            ((x) << 16)
334 #define         ALU_UPDATE_FIFO_HIWATER(x)                      ((x) << 24)
335 #define SQ_PGM_START_ES                                 0x28880
336 #define SQ_PGM_START_FS                                 0x28894
337 #define SQ_PGM_START_GS                                 0x2886C
338 #define SQ_PGM_START_PS                                 0x28840
339 #define SQ_PGM_RESOURCES_PS                             0x28850
340 #define SQ_PGM_EXPORTS_PS                               0x28854
341 #define SQ_PGM_CF_OFFSET_PS                             0x288cc
342 #define SQ_PGM_START_VS                                 0x28858
343 #define SQ_PGM_RESOURCES_VS                             0x28868
344 #define SQ_PGM_CF_OFFSET_VS                             0x288d0
345 #define SQ_VTX_CONSTANT_WORD6_0                         0x38018
346 #define         S__SQ_VTX_CONSTANT_TYPE(x)                      (((x) & 3) << 30)
347 #define         G__SQ_VTX_CONSTANT_TYPE(x)                      (((x) >> 30) & 3)
348 #define                 SQ_TEX_VTX_INVALID_TEXTURE                      0x0
349 #define                 SQ_TEX_VTX_INVALID_BUFFER                       0x1
350 #define                 SQ_TEX_VTX_VALID_TEXTURE                        0x2
351 #define                 SQ_TEX_VTX_VALID_BUFFER                         0x3
352
353
354 #define SX_MISC                                         0x28350
355 #define SX_DEBUG_1                                      0x9054
356 #define         SMX_EVENT_RELEASE                               (1 << 0)
357 #define         ENABLE_NEW_SMX_ADDRESS                          (1 << 16)
358
359 #define TA_CNTL_AUX                                     0x9508
360 #define         DISABLE_CUBE_WRAP                               (1 << 0)
361 #define         DISABLE_CUBE_ANISO                              (1 << 1)
362 #define         SYNC_GRADIENT                                   (1 << 24)
363 #define         SYNC_WALKER                                     (1 << 25)
364 #define         SYNC_ALIGNER                                    (1 << 26)
365 #define         BILINEAR_PRECISION_6_BIT                        (0 << 31)
366 #define         BILINEAR_PRECISION_8_BIT                        (1 << 31)
367
368 #define TC_CNTL                                         0x9608
369 #define         TC_L2_SIZE(x)                                   ((x)<<5)
370 #define         L2_DISABLE_LATE_HIT                             (1<<9)
371
372
373 #define VGT_CACHE_INVALIDATION                          0x88C4
374 #define         CACHE_INVALIDATION(x)                           ((x)<<0)
375 #define                 VC_ONLY                                         0
376 #define                 TC_ONLY                                         1
377 #define                 VC_AND_TC                                       2
378 #define VGT_DMA_BASE                                    0x287E8
379 #define VGT_DMA_BASE_HI                                 0x287E4
380 #define VGT_ES_PER_GS                                   0x88CC
381 #define VGT_GS_PER_ES                                   0x88C8
382 #define VGT_GS_PER_VS                                   0x88E8
383 #define VGT_GS_VERTEX_REUSE                             0x88D4
384 #define VGT_PRIMITIVE_TYPE                              0x8958
385 #define VGT_NUM_INSTANCES                               0x8974
386 #define VGT_OUT_DEALLOC_CNTL                            0x28C5C
387 #define         DEALLOC_DIST_MASK                               0x0000007F
388 #define VGT_STRMOUT_BASE_OFFSET_0                       0x28B10
389 #define VGT_STRMOUT_BASE_OFFSET_1                       0x28B14
390 #define VGT_STRMOUT_BASE_OFFSET_2                       0x28B18
391 #define VGT_STRMOUT_BASE_OFFSET_3                       0x28B1c
392 #define VGT_STRMOUT_BASE_OFFSET_HI_0                    0x28B44
393 #define VGT_STRMOUT_BASE_OFFSET_HI_1                    0x28B48
394 #define VGT_STRMOUT_BASE_OFFSET_HI_2                    0x28B4c
395 #define VGT_STRMOUT_BASE_OFFSET_HI_3                    0x28B50
396 #define VGT_STRMOUT_BUFFER_BASE_0                       0x28AD8
397 #define VGT_STRMOUT_BUFFER_BASE_1                       0x28AE8
398 #define VGT_STRMOUT_BUFFER_BASE_2                       0x28AF8
399 #define VGT_STRMOUT_BUFFER_BASE_3                       0x28B08
400 #define VGT_STRMOUT_BUFFER_OFFSET_0                     0x28ADC
401 #define VGT_STRMOUT_BUFFER_OFFSET_1                     0x28AEC
402 #define VGT_STRMOUT_BUFFER_OFFSET_2                     0x28AFC
403 #define VGT_STRMOUT_BUFFER_OFFSET_3                     0x28B0C
404 #define VGT_STRMOUT_EN                                  0x28AB0
405 #define VGT_VERTEX_REUSE_BLOCK_CNTL                     0x28C58
406 #define         VTX_REUSE_DEPTH_MASK                            0x000000FF
407 #define VGT_EVENT_INITIATOR                             0x28a90
408 #       define CACHE_FLUSH_AND_INV_EVENT                        (0x16 << 0)
409
410 #define VM_CONTEXT0_CNTL                                0x1410
411 #define         ENABLE_CONTEXT                                  (1 << 0)
412 #define         PAGE_TABLE_DEPTH(x)                             (((x) & 3) << 1)
413 #define         RANGE_PROTECTION_FAULT_ENABLE_DEFAULT           (1 << 4)
414 #define VM_CONTEXT0_INVALIDATION_LOW_ADDR               0x1490
415 #define VM_CONTEXT0_INVALIDATION_HIGH_ADDR              0x14B0
416 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR                0x1574
417 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR               0x1594
418 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR                 0x15B4
419 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR       0x1554
420 #define VM_CONTEXT0_REQUEST_RESPONSE                    0x1470
421 #define         REQUEST_TYPE(x)                                 (((x) & 0xf) << 0)
422 #define         RESPONSE_TYPE_MASK                              0x000000F0
423 #define         RESPONSE_TYPE_SHIFT                             4
424 #define VM_L2_CNTL                                      0x1400
425 #define         ENABLE_L2_CACHE                                 (1 << 0)
426 #define         ENABLE_L2_FRAGMENT_PROCESSING                   (1 << 1)
427 #define         ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE         (1 << 9)
428 #define         EFFECTIVE_L2_QUEUE_SIZE(x)                      (((x) & 7) << 13)
429 #define VM_L2_CNTL2                                     0x1404
430 #define         INVALIDATE_ALL_L1_TLBS                          (1 << 0)
431 #define         INVALIDATE_L2_CACHE                             (1 << 1)
432 #define VM_L2_CNTL3                                     0x1408
433 #define         BANK_SELECT_0(x)                                (((x) & 0x1f) << 0)
434 #define         BANK_SELECT_1(x)                                (((x) & 0x1f) << 5)
435 #define         L2_CACHE_UPDATE_MODE(x)                         (((x) & 3) << 10)
436 #define VM_L2_STATUS                                    0x140C
437 #define         L2_BUSY                                         (1 << 0)
438
439 #define WAIT_UNTIL                                      0x8040
440 #define         WAIT_2D_IDLE_bit                                (1 << 14)
441 #define         WAIT_3D_IDLE_bit                                (1 << 15)
442 #define         WAIT_2D_IDLECLEAN_bit                           (1 << 16)
443 #define         WAIT_3D_IDLECLEAN_bit                           (1 << 17)
444
445
446
447 /*
448  * PM4
449  */
450 #define PACKET_TYPE0    0
451 #define PACKET_TYPE1    1
452 #define PACKET_TYPE2    2
453 #define PACKET_TYPE3    3
454
455 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
456 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
457 #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
458 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
459 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) |                         \
460                          (((reg) >> 2) & 0xFFFF) |                      \
461                          ((n) & 0x3FFF) << 16)
462 #define PACKET3(op, n)  ((PACKET_TYPE3 << 30) |                         \
463                          (((op) & 0xFF) << 8) |                         \
464                          ((n) & 0x3FFF) << 16)
465
466 /* Packet 3 types */
467 #define PACKET3_NOP                                     0x10
468 #define PACKET3_INDIRECT_BUFFER_END                     0x17
469 #define PACKET3_SET_PREDICATION                         0x20
470 #define PACKET3_REG_RMW                                 0x21
471 #define PACKET3_COND_EXEC                               0x22
472 #define PACKET3_PRED_EXEC                               0x23
473 #define PACKET3_START_3D_CMDBUF                         0x24
474 #define PACKET3_DRAW_INDEX_2                            0x27
475 #define PACKET3_CONTEXT_CONTROL                         0x28
476 #define PACKET3_DRAW_INDEX_IMMD_BE                      0x29
477 #define PACKET3_INDEX_TYPE                              0x2A
478 #define PACKET3_DRAW_INDEX                              0x2B
479 #define PACKET3_DRAW_INDEX_AUTO                         0x2D
480 #define PACKET3_DRAW_INDEX_IMMD                         0x2E
481 #define PACKET3_NUM_INSTANCES                           0x2F
482 #define PACKET3_STRMOUT_BUFFER_UPDATE                   0x34
483 #define PACKET3_INDIRECT_BUFFER_MP                      0x38
484 #define PACKET3_MEM_SEMAPHORE                           0x39
485 #define PACKET3_MPEG_INDEX                              0x3A
486 #define PACKET3_WAIT_REG_MEM                            0x3C
487 #define PACKET3_MEM_WRITE                               0x3D
488 #define PACKET3_INDIRECT_BUFFER                         0x32
489 #define PACKET3_CP_INTERRUPT                            0x40
490 #define PACKET3_SURFACE_SYNC                            0x43
491 #              define PACKET3_CB0_DEST_BASE_ENA    (1 << 6)
492 #              define PACKET3_TC_ACTION_ENA        (1 << 23)
493 #              define PACKET3_VC_ACTION_ENA        (1 << 24)
494 #              define PACKET3_CB_ACTION_ENA        (1 << 25)
495 #              define PACKET3_DB_ACTION_ENA        (1 << 26)
496 #              define PACKET3_SH_ACTION_ENA        (1 << 27)
497 #              define PACKET3_SMX_ACTION_ENA       (1 << 28)
498 #define PACKET3_ME_INITIALIZE                           0x44
499 #define         PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
500 #define PACKET3_COND_WRITE                              0x45
501 #define PACKET3_EVENT_WRITE                             0x46
502 #define PACKET3_EVENT_WRITE_EOP                         0x47
503 #define PACKET3_ONE_REG_WRITE                           0x57
504 #define PACKET3_SET_CONFIG_REG                          0x68
505 #define         PACKET3_SET_CONFIG_REG_OFFSET                   0x00008000
506 #define         PACKET3_SET_CONFIG_REG_END                      0x0000ac00
507 #define PACKET3_SET_CONTEXT_REG                         0x69
508 #define         PACKET3_SET_CONTEXT_REG_OFFSET                  0x00028000
509 #define         PACKET3_SET_CONTEXT_REG_END                     0x00029000
510 #define PACKET3_SET_ALU_CONST                           0x6A
511 #define         PACKET3_SET_ALU_CONST_OFFSET                    0x00030000
512 #define         PACKET3_SET_ALU_CONST_END                       0x00032000
513 #define PACKET3_SET_BOOL_CONST                          0x6B
514 #define         PACKET3_SET_BOOL_CONST_OFFSET                   0x0003e380
515 #define         PACKET3_SET_BOOL_CONST_END                      0x00040000
516 #define PACKET3_SET_LOOP_CONST                          0x6C
517 #define         PACKET3_SET_LOOP_CONST_OFFSET                   0x0003e200
518 #define         PACKET3_SET_LOOP_CONST_END                      0x0003e380
519 #define PACKET3_SET_RESOURCE                            0x6D
520 #define         PACKET3_SET_RESOURCE_OFFSET                     0x00038000
521 #define         PACKET3_SET_RESOURCE_END                        0x0003c000
522 #define PACKET3_SET_SAMPLER                             0x6E
523 #define         PACKET3_SET_SAMPLER_OFFSET                      0x0003c000
524 #define         PACKET3_SET_SAMPLER_END                         0x0003cff0
525 #define PACKET3_SET_CTL_CONST                           0x6F
526 #define         PACKET3_SET_CTL_CONST_OFFSET                    0x0003cff0
527 #define         PACKET3_SET_CTL_CONST_END                       0x0003e200
528 #define PACKET3_SURFACE_BASE_UPDATE                     0x73
529
530
531 #define R_008020_GRBM_SOFT_RESET                0x8020
532 #define         S_008020_SOFT_RESET_CP(x)               (((x) & 1) << 0)
533 #define         S_008020_SOFT_RESET_CB(x)               (((x) & 1) << 1)
534 #define         S_008020_SOFT_RESET_CR(x)               (((x) & 1) << 2)
535 #define         S_008020_SOFT_RESET_DB(x)               (((x) & 1) << 3)
536 #define         S_008020_SOFT_RESET_PA(x)               (((x) & 1) << 5)
537 #define         S_008020_SOFT_RESET_SC(x)               (((x) & 1) << 6)
538 #define         S_008020_SOFT_RESET_SMX(x)              (((x) & 1) << 7)
539 #define         S_008020_SOFT_RESET_SPI(x)              (((x) & 1) << 8)
540 #define         S_008020_SOFT_RESET_SH(x)               (((x) & 1) << 9)
541 #define         S_008020_SOFT_RESET_SX(x)               (((x) & 1) << 10)
542 #define         S_008020_SOFT_RESET_TC(x)               (((x) & 1) << 11)
543 #define         S_008020_SOFT_RESET_TA(x)               (((x) & 1) << 12)
544 #define         S_008020_SOFT_RESET_VC(x)               (((x) & 1) << 13)
545 #define         S_008020_SOFT_RESET_VGT(x)              (((x) & 1) << 14)
546 #define R_008010_GRBM_STATUS                    0x8010
547 #define         S_008010_CMDFIFO_AVAIL(x)               (((x) & 0x1F) << 0)
548 #define         S_008010_CP_RQ_PENDING(x)               (((x) & 1) << 6)
549 #define         S_008010_CF_RQ_PENDING(x)               (((x) & 1) << 7)
550 #define         S_008010_PF_RQ_PENDING(x)               (((x) & 1) << 8)
551 #define         S_008010_GRBM_EE_BUSY(x)                (((x) & 1) << 10)
552 #define         S_008010_VC_BUSY(x)                     (((x) & 1) << 11)
553 #define         S_008010_DB03_CLEAN(x)                  (((x) & 1) << 12)
554 #define         S_008010_CB03_CLEAN(x)                  (((x) & 1) << 13)
555 #define         S_008010_VGT_BUSY_NO_DMA(x)             (((x) & 1) << 16)
556 #define         S_008010_VGT_BUSY(x)                    (((x) & 1) << 17)
557 #define         S_008010_TA03_BUSY(x)                   (((x) & 1) << 18)
558 #define         S_008010_TC_BUSY(x)                     (((x) & 1) << 19)
559 #define         S_008010_SX_BUSY(x)                     (((x) & 1) << 20)
560 #define         S_008010_SH_BUSY(x)                     (((x) & 1) << 21)
561 #define         S_008010_SPI03_BUSY(x)                  (((x) & 1) << 22)
562 #define         S_008010_SMX_BUSY(x)                    (((x) & 1) << 23)
563 #define         S_008010_SC_BUSY(x)                     (((x) & 1) << 24)
564 #define         S_008010_PA_BUSY(x)                     (((x) & 1) << 25)
565 #define         S_008010_DB03_BUSY(x)                   (((x) & 1) << 26)
566 #define         S_008010_CR_BUSY(x)                     (((x) & 1) << 27)
567 #define         S_008010_CP_COHERENCY_BUSY(x)           (((x) & 1) << 28)
568 #define         S_008010_CP_BUSY(x)                     (((x) & 1) << 29)
569 #define         S_008010_CB03_BUSY(x)                   (((x) & 1) << 30)
570 #define         S_008010_GUI_ACTIVE(x)                  (((x) & 1) << 31)
571 #define         G_008010_CMDFIFO_AVAIL(x)               (((x) >> 0) & 0x1F)
572 #define         G_008010_CP_RQ_PENDING(x)               (((x) >> 6) & 1)
573 #define         G_008010_CF_RQ_PENDING(x)               (((x) >> 7) & 1)
574 #define         G_008010_PF_RQ_PENDING(x)               (((x) >> 8) & 1)
575 #define         G_008010_GRBM_EE_BUSY(x)                (((x) >> 10) & 1)
576 #define         G_008010_VC_BUSY(x)                     (((x) >> 11) & 1)
577 #define         G_008010_DB03_CLEAN(x)                  (((x) >> 12) & 1)
578 #define         G_008010_CB03_CLEAN(x)                  (((x) >> 13) & 1)
579 #define         G_008010_VGT_BUSY_NO_DMA(x)             (((x) >> 16) & 1)
580 #define         G_008010_VGT_BUSY(x)                    (((x) >> 17) & 1)
581 #define         G_008010_TA03_BUSY(x)                   (((x) >> 18) & 1)
582 #define         G_008010_TC_BUSY(x)                     (((x) >> 19) & 1)
583 #define         G_008010_SX_BUSY(x)                     (((x) >> 20) & 1)
584 #define         G_008010_SH_BUSY(x)                     (((x) >> 21) & 1)
585 #define         G_008010_SPI03_BUSY(x)                  (((x) >> 22) & 1)
586 #define         G_008010_SMX_BUSY(x)                    (((x) >> 23) & 1)
587 #define         G_008010_SC_BUSY(x)                     (((x) >> 24) & 1)
588 #define         G_008010_PA_BUSY(x)                     (((x) >> 25) & 1)
589 #define         G_008010_DB03_BUSY(x)                   (((x) >> 26) & 1)
590 #define         G_008010_CR_BUSY(x)                     (((x) >> 27) & 1)
591 #define         G_008010_CP_COHERENCY_BUSY(x)           (((x) >> 28) & 1)
592 #define         G_008010_CP_BUSY(x)                     (((x) >> 29) & 1)
593 #define         G_008010_CB03_BUSY(x)                   (((x) >> 30) & 1)
594 #define         G_008010_GUI_ACTIVE(x)                  (((x) >> 31) & 1)
595 #define R_008014_GRBM_STATUS2                   0x8014
596 #define         S_008014_CR_CLEAN(x)                    (((x) & 1) << 0)
597 #define         S_008014_SMX_CLEAN(x)                   (((x) & 1) << 1)
598 #define         S_008014_SPI0_BUSY(x)                   (((x) & 1) << 8)
599 #define         S_008014_SPI1_BUSY(x)                   (((x) & 1) << 9)
600 #define         S_008014_SPI2_BUSY(x)                   (((x) & 1) << 10)
601 #define         S_008014_SPI3_BUSY(x)                   (((x) & 1) << 11)
602 #define         S_008014_TA0_BUSY(x)                    (((x) & 1) << 12)
603 #define         S_008014_TA1_BUSY(x)                    (((x) & 1) << 13)
604 #define         S_008014_TA2_BUSY(x)                    (((x) & 1) << 14)
605 #define         S_008014_TA3_BUSY(x)                    (((x) & 1) << 15)
606 #define         S_008014_DB0_BUSY(x)                    (((x) & 1) << 16)
607 #define         S_008014_DB1_BUSY(x)                    (((x) & 1) << 17)
608 #define         S_008014_DB2_BUSY(x)                    (((x) & 1) << 18)
609 #define         S_008014_DB3_BUSY(x)                    (((x) & 1) << 19)
610 #define         S_008014_CB0_BUSY(x)                    (((x) & 1) << 20)
611 #define         S_008014_CB1_BUSY(x)                    (((x) & 1) << 21)
612 #define         S_008014_CB2_BUSY(x)                    (((x) & 1) << 22)
613 #define         S_008014_CB3_BUSY(x)                    (((x) & 1) << 23)
614 #define         G_008014_CR_CLEAN(x)                    (((x) >> 0) & 1)
615 #define         G_008014_SMX_CLEAN(x)                   (((x) >> 1) & 1)
616 #define         G_008014_SPI0_BUSY(x)                   (((x) >> 8) & 1)
617 #define         G_008014_SPI1_BUSY(x)                   (((x) >> 9) & 1)
618 #define         G_008014_SPI2_BUSY(x)                   (((x) >> 10) & 1)
619 #define         G_008014_SPI3_BUSY(x)                   (((x) >> 11) & 1)
620 #define         G_008014_TA0_BUSY(x)                    (((x) >> 12) & 1)
621 #define         G_008014_TA1_BUSY(x)                    (((x) >> 13) & 1)
622 #define         G_008014_TA2_BUSY(x)                    (((x) >> 14) & 1)
623 #define         G_008014_TA3_BUSY(x)                    (((x) >> 15) & 1)
624 #define         G_008014_DB0_BUSY(x)                    (((x) >> 16) & 1)
625 #define         G_008014_DB1_BUSY(x)                    (((x) >> 17) & 1)
626 #define         G_008014_DB2_BUSY(x)                    (((x) >> 18) & 1)
627 #define         G_008014_DB3_BUSY(x)                    (((x) >> 19) & 1)
628 #define         G_008014_CB0_BUSY(x)                    (((x) >> 20) & 1)
629 #define         G_008014_CB1_BUSY(x)                    (((x) >> 21) & 1)
630 #define         G_008014_CB2_BUSY(x)                    (((x) >> 22) & 1)
631 #define         G_008014_CB3_BUSY(x)                    (((x) >> 23) & 1)
632 #define R_000E50_SRBM_STATUS                            0x0E50
633 #define         G_000E50_RLC_RQ_PENDING(x)              (((x) >> 3) & 1)
634 #define         G_000E50_RCU_RQ_PENDING(x)              (((x) >> 4) & 1)
635 #define         G_000E50_GRBM_RQ_PENDING(x)             (((x) >> 5) & 1)
636 #define         G_000E50_HI_RQ_PENDING(x)               (((x) >> 6) & 1)
637 #define         G_000E50_IO_EXTERN_SIGNAL(x)            (((x) >> 7) & 1)
638 #define         G_000E50_VMC_BUSY(x)                    (((x) >> 8) & 1)
639 #define         G_000E50_MCB_BUSY(x)                    (((x) >> 9) & 1)
640 #define         G_000E50_MCDZ_BUSY(x)                   (((x) >> 10) & 1)
641 #define         G_000E50_MCDY_BUSY(x)                   (((x) >> 11) & 1)
642 #define         G_000E50_MCDX_BUSY(x)                   (((x) >> 12) & 1)
643 #define         G_000E50_MCDW_BUSY(x)                   (((x) >> 13) & 1)
644 #define         G_000E50_SEM_BUSY(x)                    (((x) >> 14) & 1)
645 #define         G_000E50_RLC_BUSY(x)                    (((x) >> 15) & 1)
646 #define         G_000E50_BIF_BUSY(x)                    (((x) >> 29) & 1)
647 #define R_000E60_SRBM_SOFT_RESET                        0x0E60
648 #define         S_000E60_SOFT_RESET_BIF(x)              (((x) & 1) << 1)
649 #define         S_000E60_SOFT_RESET_CG(x)               (((x) & 1) << 2)
650 #define         S_000E60_SOFT_RESET_CMC(x)              (((x) & 1) << 3)
651 #define         S_000E60_SOFT_RESET_CSC(x)              (((x) & 1) << 4)
652 #define         S_000E60_SOFT_RESET_DC(x)               (((x) & 1) << 5)
653 #define         S_000E60_SOFT_RESET_GRBM(x)             (((x) & 1) << 8)
654 #define         S_000E60_SOFT_RESET_HDP(x)              (((x) & 1) << 9)
655 #define         S_000E60_SOFT_RESET_IH(x)               (((x) & 1) << 10)
656 #define         S_000E60_SOFT_RESET_MC(x)               (((x) & 1) << 11)
657 #define         S_000E60_SOFT_RESET_RLC(x)              (((x) & 1) << 13)
658 #define         S_000E60_SOFT_RESET_ROM(x)              (((x) & 1) << 14)
659 #define         S_000E60_SOFT_RESET_SEM(x)              (((x) & 1) << 15)
660 #define         S_000E60_SOFT_RESET_TSC(x)              (((x) & 1) << 16)
661 #define         S_000E60_SOFT_RESET_VMC(x)              (((x) & 1) << 17)
662
663 #endif