drm/radeon/rv740: fix backend setup
[linux-2.6.git] / drivers / gpu / drm / radeon / r600_cp.c
1 /*
2  * Copyright 2008-2009 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice (including the next
13  * paragraph) shall be included in all copies or substantial portions of the
14  * Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22  * DEALINGS IN THE SOFTWARE.
23  *
24  * Authors:
25  *     Dave Airlie <airlied@redhat.com>
26  *     Alex Deucher <alexander.deucher@amd.com>
27  */
28
29 #include "drmP.h"
30 #include "drm.h"
31 #include "radeon_drm.h"
32 #include "radeon_drv.h"
33
34 #define PFP_UCODE_SIZE 576
35 #define PM4_UCODE_SIZE 1792
36 #define R700_PFP_UCODE_SIZE 848
37 #define R700_PM4_UCODE_SIZE 1360
38
39 /* Firmware Names */
40 MODULE_FIRMWARE("radeon/R600_pfp.bin");
41 MODULE_FIRMWARE("radeon/R600_me.bin");
42 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
43 MODULE_FIRMWARE("radeon/RV610_me.bin");
44 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
45 MODULE_FIRMWARE("radeon/RV630_me.bin");
46 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
47 MODULE_FIRMWARE("radeon/RV620_me.bin");
48 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
49 MODULE_FIRMWARE("radeon/RV635_me.bin");
50 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
51 MODULE_FIRMWARE("radeon/RV670_me.bin");
52 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
53 MODULE_FIRMWARE("radeon/RS780_me.bin");
54 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
55 MODULE_FIRMWARE("radeon/RV770_me.bin");
56 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
57 MODULE_FIRMWARE("radeon/RV730_me.bin");
58 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
59 MODULE_FIRMWARE("radeon/RV710_me.bin");
60
61
62 int r600_cs_legacy(struct drm_device *dev, void *data, struct drm_file *filp,
63                         unsigned family, u32 *ib, int *l);
64 void r600_cs_legacy_init(void);
65
66
67 # define ATI_PCIGART_PAGE_SIZE          4096    /**< PCI GART page size */
68 # define ATI_PCIGART_PAGE_MASK          (~(ATI_PCIGART_PAGE_SIZE-1))
69
70 #define R600_PTE_VALID     (1 << 0)
71 #define R600_PTE_SYSTEM    (1 << 1)
72 #define R600_PTE_SNOOPED   (1 << 2)
73 #define R600_PTE_READABLE  (1 << 5)
74 #define R600_PTE_WRITEABLE (1 << 6)
75
76 /* MAX values used for gfx init */
77 #define R6XX_MAX_SH_GPRS           256
78 #define R6XX_MAX_TEMP_GPRS         16
79 #define R6XX_MAX_SH_THREADS        256
80 #define R6XX_MAX_SH_STACK_ENTRIES  4096
81 #define R6XX_MAX_BACKENDS          8
82 #define R6XX_MAX_BACKENDS_MASK     0xff
83 #define R6XX_MAX_SIMDS             8
84 #define R6XX_MAX_SIMDS_MASK        0xff
85 #define R6XX_MAX_PIPES             8
86 #define R6XX_MAX_PIPES_MASK        0xff
87
88 #define R7XX_MAX_SH_GPRS           256
89 #define R7XX_MAX_TEMP_GPRS         16
90 #define R7XX_MAX_SH_THREADS        256
91 #define R7XX_MAX_SH_STACK_ENTRIES  4096
92 #define R7XX_MAX_BACKENDS          8
93 #define R7XX_MAX_BACKENDS_MASK     0xff
94 #define R7XX_MAX_SIMDS             16
95 #define R7XX_MAX_SIMDS_MASK        0xffff
96 #define R7XX_MAX_PIPES             8
97 #define R7XX_MAX_PIPES_MASK        0xff
98
99 static int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries)
100 {
101         int i;
102
103         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
104
105         for (i = 0; i < dev_priv->usec_timeout; i++) {
106                 int slots;
107                 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
108                         slots = (RADEON_READ(R600_GRBM_STATUS)
109                                  & R700_CMDFIFO_AVAIL_MASK);
110                 else
111                         slots = (RADEON_READ(R600_GRBM_STATUS)
112                                  & R600_CMDFIFO_AVAIL_MASK);
113                 if (slots >= entries)
114                         return 0;
115                 DRM_UDELAY(1);
116         }
117         DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n",
118                  RADEON_READ(R600_GRBM_STATUS),
119                  RADEON_READ(R600_GRBM_STATUS2));
120
121         return -EBUSY;
122 }
123
124 static int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv)
125 {
126         int i, ret;
127
128         dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
129
130         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
131                 ret = r600_do_wait_for_fifo(dev_priv, 8);
132         else
133                 ret = r600_do_wait_for_fifo(dev_priv, 16);
134         if (ret)
135                 return ret;
136         for (i = 0; i < dev_priv->usec_timeout; i++) {
137                 if (!(RADEON_READ(R600_GRBM_STATUS) & R600_GUI_ACTIVE))
138                         return 0;
139                 DRM_UDELAY(1);
140         }
141         DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n",
142                  RADEON_READ(R600_GRBM_STATUS),
143                  RADEON_READ(R600_GRBM_STATUS2));
144
145         return -EBUSY;
146 }
147
148 void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
149 {
150         struct drm_sg_mem *entry = dev->sg;
151         int max_pages;
152         int pages;
153         int i;
154
155         if (!entry)
156                 return;
157
158         if (gart_info->bus_addr) {
159                 max_pages = (gart_info->table_size / sizeof(u64));
160                 pages = (entry->pages <= max_pages)
161                   ? entry->pages : max_pages;
162
163                 for (i = 0; i < pages; i++) {
164                         if (!entry->busaddr[i])
165                                 break;
166                         pci_unmap_page(dev->pdev, entry->busaddr[i],
167                                        PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
168                 }
169                 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN)
170                         gart_info->bus_addr = 0;
171         }
172 }
173
174 /* R600 has page table setup */
175 int r600_page_table_init(struct drm_device *dev)
176 {
177         drm_radeon_private_t *dev_priv = dev->dev_private;
178         struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
179         struct drm_local_map *map = &gart_info->mapping;
180         struct drm_sg_mem *entry = dev->sg;
181         int ret = 0;
182         int i, j;
183         int pages;
184         u64 page_base;
185         dma_addr_t entry_addr;
186         int max_ati_pages, max_real_pages, gart_idx;
187
188         /* okay page table is available - lets rock */
189         max_ati_pages = (gart_info->table_size / sizeof(u64));
190         max_real_pages = max_ati_pages / (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE);
191
192         pages = (entry->pages <= max_real_pages) ?
193                 entry->pages : max_real_pages;
194
195         memset_io((void __iomem *)map->handle, 0, max_ati_pages * sizeof(u64));
196
197         gart_idx = 0;
198         for (i = 0; i < pages; i++) {
199                 entry->busaddr[i] = pci_map_page(dev->pdev,
200                                                  entry->pagelist[i], 0,
201                                                  PAGE_SIZE,
202                                                  PCI_DMA_BIDIRECTIONAL);
203                 if (entry->busaddr[i] == 0) {
204                         DRM_ERROR("unable to map PCIGART pages!\n");
205                         r600_page_table_cleanup(dev, gart_info);
206                         goto done;
207                 }
208                 entry_addr = entry->busaddr[i];
209                 for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
210                         page_base = (u64) entry_addr & ATI_PCIGART_PAGE_MASK;
211                         page_base |= R600_PTE_VALID | R600_PTE_SYSTEM | R600_PTE_SNOOPED;
212                         page_base |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
213
214                         DRM_WRITE64(map, gart_idx * sizeof(u64), page_base);
215
216                         gart_idx++;
217
218                         if ((i % 128) == 0)
219                                 DRM_DEBUG("page entry %d: 0x%016llx\n",
220                                     i, (unsigned long long)page_base);
221                         entry_addr += ATI_PCIGART_PAGE_SIZE;
222                 }
223         }
224         ret = 1;
225 done:
226         return ret;
227 }
228
229 static void r600_vm_flush_gart_range(struct drm_device *dev)
230 {
231         drm_radeon_private_t *dev_priv = dev->dev_private;
232         u32 resp, countdown = 1000;
233         RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12);
234         RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
235         RADEON_WRITE(R600_VM_CONTEXT0_REQUEST_RESPONSE, 2);
236
237         do {
238                 resp = RADEON_READ(R600_VM_CONTEXT0_REQUEST_RESPONSE);
239                 countdown--;
240                 DRM_UDELAY(1);
241         } while (((resp & 0xf0) == 0) && countdown);
242 }
243
244 static void r600_vm_init(struct drm_device *dev)
245 {
246         drm_radeon_private_t *dev_priv = dev->dev_private;
247         /* initialise the VM to use the page table we constructed up there */
248         u32 vm_c0, i;
249         u32 mc_rd_a;
250         u32 vm_l2_cntl, vm_l2_cntl3;
251         /* okay set up the PCIE aperture type thingo */
252         RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
253         RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
254         RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
255
256         /* setup MC RD a */
257         mc_rd_a = R600_MCD_L1_TLB | R600_MCD_L1_FRAG_PROC | R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS |
258                 R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | R600_MCD_EFFECTIVE_L1_TLB_SIZE(5) |
259                 R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(5) | R600_MCD_WAIT_L2_QUERY;
260
261         RADEON_WRITE(R600_MCD_RD_A_CNTL, mc_rd_a);
262         RADEON_WRITE(R600_MCD_RD_B_CNTL, mc_rd_a);
263
264         RADEON_WRITE(R600_MCD_WR_A_CNTL, mc_rd_a);
265         RADEON_WRITE(R600_MCD_WR_B_CNTL, mc_rd_a);
266
267         RADEON_WRITE(R600_MCD_RD_GFX_CNTL, mc_rd_a);
268         RADEON_WRITE(R600_MCD_WR_GFX_CNTL, mc_rd_a);
269
270         RADEON_WRITE(R600_MCD_RD_SYS_CNTL, mc_rd_a);
271         RADEON_WRITE(R600_MCD_WR_SYS_CNTL, mc_rd_a);
272
273         RADEON_WRITE(R600_MCD_RD_HDP_CNTL, mc_rd_a | R600_MCD_L1_STRICT_ORDERING);
274         RADEON_WRITE(R600_MCD_WR_HDP_CNTL, mc_rd_a /*| R600_MCD_L1_STRICT_ORDERING*/);
275
276         RADEON_WRITE(R600_MCD_RD_PDMA_CNTL, mc_rd_a);
277         RADEON_WRITE(R600_MCD_WR_PDMA_CNTL, mc_rd_a);
278
279         RADEON_WRITE(R600_MCD_RD_SEM_CNTL, mc_rd_a | R600_MCD_SEMAPHORE_MODE);
280         RADEON_WRITE(R600_MCD_WR_SEM_CNTL, mc_rd_a);
281
282         vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W;
283         vm_l2_cntl |= R600_VM_L2_CNTL_QUEUE_SIZE(7);
284         RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl);
285
286         RADEON_WRITE(R600_VM_L2_CNTL2, 0);
287         vm_l2_cntl3 = (R600_VM_L2_CNTL3_BANK_SELECT_0(0) |
288                        R600_VM_L2_CNTL3_BANK_SELECT_1(1) |
289                        R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(2));
290         RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3);
291
292         vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT;
293
294         RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0);
295
296         vm_c0 &= ~R600_VM_ENABLE_CONTEXT;
297
298         /* disable all other contexts */
299         for (i = 1; i < 8; i++)
300                 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0);
301
302         RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
303         RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
304         RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
305
306         r600_vm_flush_gart_range(dev);
307 }
308
309 static int r600_cp_init_microcode(drm_radeon_private_t *dev_priv)
310 {
311         struct platform_device *pdev;
312         const char *chip_name;
313         size_t pfp_req_size, me_req_size;
314         char fw_name[30];
315         int err;
316
317         pdev = platform_device_register_simple("r600_cp", 0, NULL, 0);
318         err = IS_ERR(pdev);
319         if (err) {
320                 printk(KERN_ERR "r600_cp: Failed to register firmware\n");
321                 return -EINVAL;
322         }
323
324         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
325         case CHIP_R600:  chip_name = "R600";  break;
326         case CHIP_RV610: chip_name = "RV610"; break;
327         case CHIP_RV630: chip_name = "RV630"; break;
328         case CHIP_RV620: chip_name = "RV620"; break;
329         case CHIP_RV635: chip_name = "RV635"; break;
330         case CHIP_RV670: chip_name = "RV670"; break;
331         case CHIP_RS780:
332         case CHIP_RS880: chip_name = "RS780"; break;
333         case CHIP_RV770: chip_name = "RV770"; break;
334         case CHIP_RV730:
335         case CHIP_RV740: chip_name = "RV730"; break;
336         case CHIP_RV710: chip_name = "RV710"; break;
337         default:         BUG();
338         }
339
340         if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770) {
341                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
342                 me_req_size = R700_PM4_UCODE_SIZE * 4;
343         } else {
344                 pfp_req_size = PFP_UCODE_SIZE * 4;
345                 me_req_size = PM4_UCODE_SIZE * 12;
346         }
347
348         DRM_INFO("Loading %s CP Microcode\n", chip_name);
349
350         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
351         err = request_firmware(&dev_priv->pfp_fw, fw_name, &pdev->dev);
352         if (err)
353                 goto out;
354         if (dev_priv->pfp_fw->size != pfp_req_size) {
355                 printk(KERN_ERR
356                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
357                        dev_priv->pfp_fw->size, fw_name);
358                 err = -EINVAL;
359                 goto out;
360         }
361
362         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
363         err = request_firmware(&dev_priv->me_fw, fw_name, &pdev->dev);
364         if (err)
365                 goto out;
366         if (dev_priv->me_fw->size != me_req_size) {
367                 printk(KERN_ERR
368                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
369                        dev_priv->me_fw->size, fw_name);
370                 err = -EINVAL;
371         }
372 out:
373         platform_device_unregister(pdev);
374
375         if (err) {
376                 if (err != -EINVAL)
377                         printk(KERN_ERR
378                                "r600_cp: Failed to load firmware \"%s\"\n",
379                                fw_name);
380                 release_firmware(dev_priv->pfp_fw);
381                 dev_priv->pfp_fw = NULL;
382                 release_firmware(dev_priv->me_fw);
383                 dev_priv->me_fw = NULL;
384         }
385         return err;
386 }
387
388 static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
389 {
390         const __be32 *fw_data;
391         int i;
392
393         if (!dev_priv->me_fw || !dev_priv->pfp_fw)
394                 return;
395
396         r600_do_cp_stop(dev_priv);
397
398         RADEON_WRITE(R600_CP_RB_CNTL,
399                      R600_RB_NO_UPDATE |
400                      R600_RB_BLKSZ(15) |
401                      R600_RB_BUFSZ(3));
402
403         RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
404         RADEON_READ(R600_GRBM_SOFT_RESET);
405         DRM_UDELAY(15000);
406         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
407
408         fw_data = (const __be32 *)dev_priv->me_fw->data;
409         RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
410         for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
411                 RADEON_WRITE(R600_CP_ME_RAM_DATA,
412                              be32_to_cpup(fw_data++));
413
414         fw_data = (const __be32 *)dev_priv->pfp_fw->data;
415         RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
416         for (i = 0; i < PFP_UCODE_SIZE; i++)
417                 RADEON_WRITE(R600_CP_PFP_UCODE_DATA,
418                              be32_to_cpup(fw_data++));
419
420         RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
421         RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
422         RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
423
424 }
425
426 static void r700_vm_init(struct drm_device *dev)
427 {
428         drm_radeon_private_t *dev_priv = dev->dev_private;
429         /* initialise the VM to use the page table we constructed up there */
430         u32 vm_c0, i;
431         u32 mc_vm_md_l1;
432         u32 vm_l2_cntl, vm_l2_cntl3;
433         /* okay set up the PCIE aperture type thingo */
434         RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
435         RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
436         RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
437
438         mc_vm_md_l1 = R700_ENABLE_L1_TLB |
439             R700_ENABLE_L1_FRAGMENT_PROCESSING |
440             R700_SYSTEM_ACCESS_MODE_IN_SYS |
441             R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
442             R700_EFFECTIVE_L1_TLB_SIZE(5) |
443             R700_EFFECTIVE_L1_QUEUE_SIZE(5);
444
445         RADEON_WRITE(R700_MC_VM_MD_L1_TLB0_CNTL, mc_vm_md_l1);
446         RADEON_WRITE(R700_MC_VM_MD_L1_TLB1_CNTL, mc_vm_md_l1);
447         RADEON_WRITE(R700_MC_VM_MD_L1_TLB2_CNTL, mc_vm_md_l1);
448         RADEON_WRITE(R700_MC_VM_MB_L1_TLB0_CNTL, mc_vm_md_l1);
449         RADEON_WRITE(R700_MC_VM_MB_L1_TLB1_CNTL, mc_vm_md_l1);
450         RADEON_WRITE(R700_MC_VM_MB_L1_TLB2_CNTL, mc_vm_md_l1);
451         RADEON_WRITE(R700_MC_VM_MB_L1_TLB3_CNTL, mc_vm_md_l1);
452
453         vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W;
454         vm_l2_cntl |= R700_VM_L2_CNTL_QUEUE_SIZE(7);
455         RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl);
456
457         RADEON_WRITE(R600_VM_L2_CNTL2, 0);
458         vm_l2_cntl3 = R700_VM_L2_CNTL3_BANK_SELECT(0) | R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(2);
459         RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3);
460
461         vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT;
462
463         RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0);
464
465         vm_c0 &= ~R600_VM_ENABLE_CONTEXT;
466
467         /* disable all other contexts */
468         for (i = 1; i < 8; i++)
469                 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0);
470
471         RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
472         RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
473         RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
474
475         r600_vm_flush_gart_range(dev);
476 }
477
478 static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
479 {
480         const __be32 *fw_data;
481         int i;
482
483         if (!dev_priv->me_fw || !dev_priv->pfp_fw)
484                 return;
485
486         r600_do_cp_stop(dev_priv);
487
488         RADEON_WRITE(R600_CP_RB_CNTL,
489                      R600_RB_NO_UPDATE |
490                      (15 << 8) |
491                      (3 << 0));
492
493         RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
494         RADEON_READ(R600_GRBM_SOFT_RESET);
495         DRM_UDELAY(15000);
496         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
497
498         fw_data = (const __be32 *)dev_priv->pfp_fw->data;
499         RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
500         for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
501                 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
502         RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
503
504         fw_data = (const __be32 *)dev_priv->me_fw->data;
505         RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
506         for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
507                 RADEON_WRITE(R600_CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
508         RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
509
510         RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
511         RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
512         RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
513
514 }
515
516 static void r600_test_writeback(drm_radeon_private_t *dev_priv)
517 {
518         u32 tmp;
519
520         /* Start with assuming that writeback doesn't work */
521         dev_priv->writeback_works = 0;
522
523         /* Writeback doesn't seem to work everywhere, test it here and possibly
524          * enable it if it appears to work
525          */
526         radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
527
528         RADEON_WRITE(R600_SCRATCH_REG1, 0xdeadbeef);
529
530         for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
531                 u32 val;
532
533                 val = radeon_read_ring_rptr(dev_priv, R600_SCRATCHOFF(1));
534                 if (val == 0xdeadbeef)
535                         break;
536                 DRM_UDELAY(1);
537         }
538
539         if (tmp < dev_priv->usec_timeout) {
540                 dev_priv->writeback_works = 1;
541                 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
542         } else {
543                 dev_priv->writeback_works = 0;
544                 DRM_INFO("writeback test failed\n");
545         }
546         if (radeon_no_wb == 1) {
547                 dev_priv->writeback_works = 0;
548                 DRM_INFO("writeback forced off\n");
549         }
550
551         if (!dev_priv->writeback_works) {
552                 /* Disable writeback to avoid unnecessary bus master transfer */
553                 RADEON_WRITE(R600_CP_RB_CNTL, RADEON_READ(R600_CP_RB_CNTL) |
554                              RADEON_RB_NO_UPDATE);
555                 RADEON_WRITE(R600_SCRATCH_UMSK, 0);
556         }
557 }
558
559 int r600_do_engine_reset(struct drm_device *dev)
560 {
561         drm_radeon_private_t *dev_priv = dev->dev_private;
562         u32 cp_ptr, cp_me_cntl, cp_rb_cntl;
563
564         DRM_INFO("Resetting GPU\n");
565
566         cp_ptr = RADEON_READ(R600_CP_RB_WPTR);
567         cp_me_cntl = RADEON_READ(R600_CP_ME_CNTL);
568         RADEON_WRITE(R600_CP_ME_CNTL, R600_CP_ME_HALT);
569
570         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0x7fff);
571         RADEON_READ(R600_GRBM_SOFT_RESET);
572         DRM_UDELAY(50);
573         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
574         RADEON_READ(R600_GRBM_SOFT_RESET);
575
576         RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
577         cp_rb_cntl = RADEON_READ(R600_CP_RB_CNTL);
578         RADEON_WRITE(R600_CP_RB_CNTL, R600_RB_RPTR_WR_ENA);
579
580         RADEON_WRITE(R600_CP_RB_RPTR_WR, cp_ptr);
581         RADEON_WRITE(R600_CP_RB_WPTR, cp_ptr);
582         RADEON_WRITE(R600_CP_RB_CNTL, cp_rb_cntl);
583         RADEON_WRITE(R600_CP_ME_CNTL, cp_me_cntl);
584
585         /* Reset the CP ring */
586         r600_do_cp_reset(dev_priv);
587
588         /* The CP is no longer running after an engine reset */
589         dev_priv->cp_running = 0;
590
591         /* Reset any pending vertex, indirect buffers */
592         radeon_freelist_reset(dev);
593
594         return 0;
595
596 }
597
598 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
599                                              u32 num_backends,
600                                              u32 backend_disable_mask)
601 {
602         u32 backend_map = 0;
603         u32 enabled_backends_mask;
604         u32 enabled_backends_count;
605         u32 cur_pipe;
606         u32 swizzle_pipe[R6XX_MAX_PIPES];
607         u32 cur_backend;
608         u32 i;
609
610         if (num_tile_pipes > R6XX_MAX_PIPES)
611                 num_tile_pipes = R6XX_MAX_PIPES;
612         if (num_tile_pipes < 1)
613                 num_tile_pipes = 1;
614         if (num_backends > R6XX_MAX_BACKENDS)
615                 num_backends = R6XX_MAX_BACKENDS;
616         if (num_backends < 1)
617                 num_backends = 1;
618
619         enabled_backends_mask = 0;
620         enabled_backends_count = 0;
621         for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
622                 if (((backend_disable_mask >> i) & 1) == 0) {
623                         enabled_backends_mask |= (1 << i);
624                         ++enabled_backends_count;
625                 }
626                 if (enabled_backends_count == num_backends)
627                         break;
628         }
629
630         if (enabled_backends_count == 0) {
631                 enabled_backends_mask = 1;
632                 enabled_backends_count = 1;
633         }
634
635         if (enabled_backends_count != num_backends)
636                 num_backends = enabled_backends_count;
637
638         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
639         switch (num_tile_pipes) {
640         case 1:
641                 swizzle_pipe[0] = 0;
642                 break;
643         case 2:
644                 swizzle_pipe[0] = 0;
645                 swizzle_pipe[1] = 1;
646                 break;
647         case 3:
648                 swizzle_pipe[0] = 0;
649                 swizzle_pipe[1] = 1;
650                 swizzle_pipe[2] = 2;
651                 break;
652         case 4:
653                 swizzle_pipe[0] = 0;
654                 swizzle_pipe[1] = 1;
655                 swizzle_pipe[2] = 2;
656                 swizzle_pipe[3] = 3;
657                 break;
658         case 5:
659                 swizzle_pipe[0] = 0;
660                 swizzle_pipe[1] = 1;
661                 swizzle_pipe[2] = 2;
662                 swizzle_pipe[3] = 3;
663                 swizzle_pipe[4] = 4;
664                 break;
665         case 6:
666                 swizzle_pipe[0] = 0;
667                 swizzle_pipe[1] = 2;
668                 swizzle_pipe[2] = 4;
669                 swizzle_pipe[3] = 5;
670                 swizzle_pipe[4] = 1;
671                 swizzle_pipe[5] = 3;
672                 break;
673         case 7:
674                 swizzle_pipe[0] = 0;
675                 swizzle_pipe[1] = 2;
676                 swizzle_pipe[2] = 4;
677                 swizzle_pipe[3] = 6;
678                 swizzle_pipe[4] = 1;
679                 swizzle_pipe[5] = 3;
680                 swizzle_pipe[6] = 5;
681                 break;
682         case 8:
683                 swizzle_pipe[0] = 0;
684                 swizzle_pipe[1] = 2;
685                 swizzle_pipe[2] = 4;
686                 swizzle_pipe[3] = 6;
687                 swizzle_pipe[4] = 1;
688                 swizzle_pipe[5] = 3;
689                 swizzle_pipe[6] = 5;
690                 swizzle_pipe[7] = 7;
691                 break;
692         }
693
694         cur_backend = 0;
695         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
696                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
697                         cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
698
699                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
700
701                 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
702         }
703
704         return backend_map;
705 }
706
707 static int r600_count_pipe_bits(uint32_t val)
708 {
709         int i, ret = 0;
710         for (i = 0; i < 32; i++) {
711                 ret += val & 1;
712                 val >>= 1;
713         }
714         return ret;
715 }
716
717 static void r600_gfx_init(struct drm_device *dev,
718                           drm_radeon_private_t *dev_priv)
719 {
720         int i, j, num_qd_pipes;
721         u32 sx_debug_1;
722         u32 tc_cntl;
723         u32 arb_pop;
724         u32 num_gs_verts_per_thread;
725         u32 vgt_gs_per_es;
726         u32 gs_prim_buffer_depth = 0;
727         u32 sq_ms_fifo_sizes;
728         u32 sq_config;
729         u32 sq_gpr_resource_mgmt_1 = 0;
730         u32 sq_gpr_resource_mgmt_2 = 0;
731         u32 sq_thread_resource_mgmt = 0;
732         u32 sq_stack_resource_mgmt_1 = 0;
733         u32 sq_stack_resource_mgmt_2 = 0;
734         u32 hdp_host_path_cntl;
735         u32 backend_map;
736         u32 gb_tiling_config = 0;
737         u32 cc_rb_backend_disable = 0;
738         u32 cc_gc_shader_pipe_config = 0;
739         u32 ramcfg;
740
741         /* setup chip specs */
742         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
743         case CHIP_R600:
744                 dev_priv->r600_max_pipes = 4;
745                 dev_priv->r600_max_tile_pipes = 8;
746                 dev_priv->r600_max_simds = 4;
747                 dev_priv->r600_max_backends = 4;
748                 dev_priv->r600_max_gprs = 256;
749                 dev_priv->r600_max_threads = 192;
750                 dev_priv->r600_max_stack_entries = 256;
751                 dev_priv->r600_max_hw_contexts = 8;
752                 dev_priv->r600_max_gs_threads = 16;
753                 dev_priv->r600_sx_max_export_size = 128;
754                 dev_priv->r600_sx_max_export_pos_size = 16;
755                 dev_priv->r600_sx_max_export_smx_size = 128;
756                 dev_priv->r600_sq_num_cf_insts = 2;
757                 break;
758         case CHIP_RV630:
759         case CHIP_RV635:
760                 dev_priv->r600_max_pipes = 2;
761                 dev_priv->r600_max_tile_pipes = 2;
762                 dev_priv->r600_max_simds = 3;
763                 dev_priv->r600_max_backends = 1;
764                 dev_priv->r600_max_gprs = 128;
765                 dev_priv->r600_max_threads = 192;
766                 dev_priv->r600_max_stack_entries = 128;
767                 dev_priv->r600_max_hw_contexts = 8;
768                 dev_priv->r600_max_gs_threads = 4;
769                 dev_priv->r600_sx_max_export_size = 128;
770                 dev_priv->r600_sx_max_export_pos_size = 16;
771                 dev_priv->r600_sx_max_export_smx_size = 128;
772                 dev_priv->r600_sq_num_cf_insts = 2;
773                 break;
774         case CHIP_RV610:
775         case CHIP_RS780:
776         case CHIP_RS880:
777         case CHIP_RV620:
778                 dev_priv->r600_max_pipes = 1;
779                 dev_priv->r600_max_tile_pipes = 1;
780                 dev_priv->r600_max_simds = 2;
781                 dev_priv->r600_max_backends = 1;
782                 dev_priv->r600_max_gprs = 128;
783                 dev_priv->r600_max_threads = 192;
784                 dev_priv->r600_max_stack_entries = 128;
785                 dev_priv->r600_max_hw_contexts = 4;
786                 dev_priv->r600_max_gs_threads = 4;
787                 dev_priv->r600_sx_max_export_size = 128;
788                 dev_priv->r600_sx_max_export_pos_size = 16;
789                 dev_priv->r600_sx_max_export_smx_size = 128;
790                 dev_priv->r600_sq_num_cf_insts = 1;
791                 break;
792         case CHIP_RV670:
793                 dev_priv->r600_max_pipes = 4;
794                 dev_priv->r600_max_tile_pipes = 4;
795                 dev_priv->r600_max_simds = 4;
796                 dev_priv->r600_max_backends = 4;
797                 dev_priv->r600_max_gprs = 192;
798                 dev_priv->r600_max_threads = 192;
799                 dev_priv->r600_max_stack_entries = 256;
800                 dev_priv->r600_max_hw_contexts = 8;
801                 dev_priv->r600_max_gs_threads = 16;
802                 dev_priv->r600_sx_max_export_size = 128;
803                 dev_priv->r600_sx_max_export_pos_size = 16;
804                 dev_priv->r600_sx_max_export_smx_size = 128;
805                 dev_priv->r600_sq_num_cf_insts = 2;
806                 break;
807         default:
808                 break;
809         }
810
811         /* Initialize HDP */
812         j = 0;
813         for (i = 0; i < 32; i++) {
814                 RADEON_WRITE((0x2c14 + j), 0x00000000);
815                 RADEON_WRITE((0x2c18 + j), 0x00000000);
816                 RADEON_WRITE((0x2c1c + j), 0x00000000);
817                 RADEON_WRITE((0x2c20 + j), 0x00000000);
818                 RADEON_WRITE((0x2c24 + j), 0x00000000);
819                 j += 0x18;
820         }
821
822         RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff));
823
824         /* setup tiling, simd, pipe config */
825         ramcfg = RADEON_READ(R600_RAMCFG);
826
827         switch (dev_priv->r600_max_tile_pipes) {
828         case 1:
829                 gb_tiling_config |= R600_PIPE_TILING(0);
830                 break;
831         case 2:
832                 gb_tiling_config |= R600_PIPE_TILING(1);
833                 break;
834         case 4:
835                 gb_tiling_config |= R600_PIPE_TILING(2);
836                 break;
837         case 8:
838                 gb_tiling_config |= R600_PIPE_TILING(3);
839                 break;
840         default:
841                 break;
842         }
843
844         gb_tiling_config |= R600_BANK_TILING((ramcfg >> R600_NOOFBANK_SHIFT) & R600_NOOFBANK_MASK);
845
846         gb_tiling_config |= R600_GROUP_SIZE(0);
847
848         if (((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK) > 3) {
849                 gb_tiling_config |= R600_ROW_TILING(3);
850                 gb_tiling_config |= R600_SAMPLE_SPLIT(3);
851         } else {
852                 gb_tiling_config |=
853                         R600_ROW_TILING(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK));
854                 gb_tiling_config |=
855                         R600_SAMPLE_SPLIT(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK));
856         }
857
858         gb_tiling_config |= R600_BANK_SWAPS(1);
859
860         backend_map = r600_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes,
861                                                         dev_priv->r600_max_backends,
862                                                         (0xff << dev_priv->r600_max_backends) & 0xff);
863         gb_tiling_config |= R600_BACKEND_MAP(backend_map);
864
865         cc_gc_shader_pipe_config =
866                 R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R6XX_MAX_PIPES_MASK);
867         cc_gc_shader_pipe_config |=
868                 R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R6XX_MAX_SIMDS_MASK);
869
870         cc_rb_backend_disable =
871                 R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R6XX_MAX_BACKENDS_MASK);
872
873         RADEON_WRITE(R600_GB_TILING_CONFIG,      gb_tiling_config);
874         RADEON_WRITE(R600_DCP_TILING_CONFIG,    (gb_tiling_config & 0xffff));
875         RADEON_WRITE(R600_HDP_TILING_CONFIG,    (gb_tiling_config & 0xffff));
876         if (gb_tiling_config & 0xc0) {
877                 dev_priv->r600_group_size = 512;
878         } else {
879                 dev_priv->r600_group_size = 256;
880         }
881         dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7);
882         if (gb_tiling_config & 0x30) {
883                 dev_priv->r600_nbanks = 8;
884         } else {
885                 dev_priv->r600_nbanks = 4;
886         }
887
888         RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
889         RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
890         RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
891
892         num_qd_pipes =
893                 R6XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK);
894         RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK);
895         RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK);
896
897         /* set HW defaults for 3D engine */
898         RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) |
899                                                 R600_ROQ_IB2_START(0x2b)));
900
901         RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, (R600_MEQ_END(0x40) |
902                                               R600_ROQ_END(0x40)));
903
904         RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO |
905                                         R600_SYNC_GRADIENT |
906                                         R600_SYNC_WALKER |
907                                         R600_SYNC_ALIGNER));
908
909         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670)
910                 RADEON_WRITE(R600_ARB_GDEC_RD_CNTL, 0x00000021);
911
912         sx_debug_1 = RADEON_READ(R600_SX_DEBUG_1);
913         sx_debug_1 |= R600_SMX_EVENT_RELEASE;
914         if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600))
915                 sx_debug_1 |= R600_ENABLE_NEW_SMX_ADDRESS;
916         RADEON_WRITE(R600_SX_DEBUG_1, sx_debug_1);
917
918         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
919             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
920             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
921             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
922             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
923             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))
924                 RADEON_WRITE(R600_DB_DEBUG, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE);
925         else
926                 RADEON_WRITE(R600_DB_DEBUG, 0);
927
928         RADEON_WRITE(R600_DB_WATERMARKS, (R600_DEPTH_FREE(4) |
929                                           R600_DEPTH_FLUSH(16) |
930                                           R600_DEPTH_PENDING_FREE(4) |
931                                           R600_DEPTH_CACHELINE_FREE(16)));
932         RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
933         RADEON_WRITE(R600_VGT_NUM_INSTANCES, 0);
934
935         RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0));
936         RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(0));
937
938         sq_ms_fifo_sizes = RADEON_READ(R600_SQ_MS_FIFO_SIZES);
939         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
940             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
941             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
942             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
943                 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(0xa) |
944                                     R600_FETCH_FIFO_HIWATER(0xa) |
945                                     R600_DONE_FIFO_HIWATER(0xe0) |
946                                     R600_ALU_UPDATE_FIFO_HIWATER(0x8));
947         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
948                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) {
949                 sq_ms_fifo_sizes &= ~R600_DONE_FIFO_HIWATER(0xff);
950                 sq_ms_fifo_sizes |= R600_DONE_FIFO_HIWATER(0x4);
951         }
952         RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
953
954         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
955          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
956          */
957         sq_config = RADEON_READ(R600_SQ_CONFIG);
958         sq_config &= ~(R600_PS_PRIO(3) |
959                        R600_VS_PRIO(3) |
960                        R600_GS_PRIO(3) |
961                        R600_ES_PRIO(3));
962         sq_config |= (R600_DX9_CONSTS |
963                       R600_VC_ENABLE |
964                       R600_PS_PRIO(0) |
965                       R600_VS_PRIO(1) |
966                       R600_GS_PRIO(2) |
967                       R600_ES_PRIO(3));
968
969         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) {
970                 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(124) |
971                                           R600_NUM_VS_GPRS(124) |
972                                           R600_NUM_CLAUSE_TEMP_GPRS(4));
973                 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(0) |
974                                           R600_NUM_ES_GPRS(0));
975                 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(136) |
976                                            R600_NUM_VS_THREADS(48) |
977                                            R600_NUM_GS_THREADS(4) |
978                                            R600_NUM_ES_THREADS(4));
979                 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(128) |
980                                             R600_NUM_VS_STACK_ENTRIES(128));
981                 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(0) |
982                                             R600_NUM_ES_STACK_ENTRIES(0));
983         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
984                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
985                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
986                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
987                 /* no vertex cache */
988                 sq_config &= ~R600_VC_ENABLE;
989
990                 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
991                                           R600_NUM_VS_GPRS(44) |
992                                           R600_NUM_CLAUSE_TEMP_GPRS(2));
993                 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) |
994                                           R600_NUM_ES_GPRS(17));
995                 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
996                                            R600_NUM_VS_THREADS(78) |
997                                            R600_NUM_GS_THREADS(4) |
998                                            R600_NUM_ES_THREADS(31));
999                 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) |
1000                                             R600_NUM_VS_STACK_ENTRIES(40));
1001                 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) |
1002                                             R600_NUM_ES_STACK_ENTRIES(16));
1003         } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
1004                    ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) {
1005                 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
1006                                           R600_NUM_VS_GPRS(44) |
1007                                           R600_NUM_CLAUSE_TEMP_GPRS(2));
1008                 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(18) |
1009                                           R600_NUM_ES_GPRS(18));
1010                 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
1011                                            R600_NUM_VS_THREADS(78) |
1012                                            R600_NUM_GS_THREADS(4) |
1013                                            R600_NUM_ES_THREADS(31));
1014                 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) |
1015                                             R600_NUM_VS_STACK_ENTRIES(40));
1016                 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) |
1017                                             R600_NUM_ES_STACK_ENTRIES(16));
1018         } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) {
1019                 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
1020                                           R600_NUM_VS_GPRS(44) |
1021                                           R600_NUM_CLAUSE_TEMP_GPRS(2));
1022                 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) |
1023                                           R600_NUM_ES_GPRS(17));
1024                 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
1025                                            R600_NUM_VS_THREADS(78) |
1026                                            R600_NUM_GS_THREADS(4) |
1027                                            R600_NUM_ES_THREADS(31));
1028                 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(64) |
1029                                             R600_NUM_VS_STACK_ENTRIES(64));
1030                 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(64) |
1031                                             R600_NUM_ES_STACK_ENTRIES(64));
1032         }
1033
1034         RADEON_WRITE(R600_SQ_CONFIG, sq_config);
1035         RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
1036         RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
1037         RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1038         RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1039         RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1040
1041         if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
1042             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
1043             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
1044             ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))
1045                 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_TC_ONLY));
1046         else
1047                 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_VC_AND_TC));
1048
1049         RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_2S, (R600_S0_X(0xc) |
1050                                                     R600_S0_Y(0x4) |
1051                                                     R600_S1_X(0x4) |
1052                                                     R600_S1_Y(0xc)));
1053         RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_4S, (R600_S0_X(0xe) |
1054                                                     R600_S0_Y(0xe) |
1055                                                     R600_S1_X(0x2) |
1056                                                     R600_S1_Y(0x2) |
1057                                                     R600_S2_X(0xa) |
1058                                                     R600_S2_Y(0x6) |
1059                                                     R600_S3_X(0x6) |
1060                                                     R600_S3_Y(0xa)));
1061         RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0, (R600_S0_X(0xe) |
1062                                                         R600_S0_Y(0xb) |
1063                                                         R600_S1_X(0x4) |
1064                                                         R600_S1_Y(0xc) |
1065                                                         R600_S2_X(0x1) |
1066                                                         R600_S2_Y(0x6) |
1067                                                         R600_S3_X(0xa) |
1068                                                         R600_S3_Y(0xe)));
1069         RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1, (R600_S4_X(0x6) |
1070                                                         R600_S4_Y(0x1) |
1071                                                         R600_S5_X(0x0) |
1072                                                         R600_S5_Y(0x0) |
1073                                                         R600_S6_X(0xb) |
1074                                                         R600_S6_Y(0x4) |
1075                                                         R600_S7_X(0x7) |
1076                                                         R600_S7_Y(0x8)));
1077
1078
1079         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1080         case CHIP_R600:
1081         case CHIP_RV630:
1082         case CHIP_RV635:
1083                 gs_prim_buffer_depth = 0;
1084                 break;
1085         case CHIP_RV610:
1086         case CHIP_RS780:
1087         case CHIP_RS880:
1088         case CHIP_RV620:
1089                 gs_prim_buffer_depth = 32;
1090                 break;
1091         case CHIP_RV670:
1092                 gs_prim_buffer_depth = 128;
1093                 break;
1094         default:
1095                 break;
1096         }
1097
1098         num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1099         vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1100         /* Max value for this is 256 */
1101         if (vgt_gs_per_es > 256)
1102                 vgt_gs_per_es = 256;
1103
1104         RADEON_WRITE(R600_VGT_ES_PER_GS, 128);
1105         RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es);
1106         RADEON_WRITE(R600_VGT_GS_PER_VS, 2);
1107         RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16);
1108
1109         /* more default values. 2D/3D driver should adjust as needed */
1110         RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0);
1111         RADEON_WRITE(R600_VGT_STRMOUT_EN, 0);
1112         RADEON_WRITE(R600_SX_MISC, 0);
1113         RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0);
1114         RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0);
1115         RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0);
1116         RADEON_WRITE(R600_SPI_INPUT_Z, 0);
1117         RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2));
1118         RADEON_WRITE(R600_CB_COLOR7_FRAG, 0);
1119
1120         /* clear render buffer base addresses */
1121         RADEON_WRITE(R600_CB_COLOR0_BASE, 0);
1122         RADEON_WRITE(R600_CB_COLOR1_BASE, 0);
1123         RADEON_WRITE(R600_CB_COLOR2_BASE, 0);
1124         RADEON_WRITE(R600_CB_COLOR3_BASE, 0);
1125         RADEON_WRITE(R600_CB_COLOR4_BASE, 0);
1126         RADEON_WRITE(R600_CB_COLOR5_BASE, 0);
1127         RADEON_WRITE(R600_CB_COLOR6_BASE, 0);
1128         RADEON_WRITE(R600_CB_COLOR7_BASE, 0);
1129
1130         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1131         case CHIP_RV610:
1132         case CHIP_RS780:
1133         case CHIP_RS880:
1134         case CHIP_RV620:
1135                 tc_cntl = R600_TC_L2_SIZE(8);
1136                 break;
1137         case CHIP_RV630:
1138         case CHIP_RV635:
1139                 tc_cntl = R600_TC_L2_SIZE(4);
1140                 break;
1141         case CHIP_R600:
1142                 tc_cntl = R600_TC_L2_SIZE(0) | R600_L2_DISABLE_LATE_HIT;
1143                 break;
1144         default:
1145                 tc_cntl = R600_TC_L2_SIZE(0);
1146                 break;
1147         }
1148
1149         RADEON_WRITE(R600_TC_CNTL, tc_cntl);
1150
1151         hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);
1152         RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1153
1154         arb_pop = RADEON_READ(R600_ARB_POP);
1155         arb_pop |= R600_ENABLE_TC128;
1156         RADEON_WRITE(R600_ARB_POP, arb_pop);
1157
1158         RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1159         RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA |
1160                                           R600_NUM_CLIP_SEQ(3)));
1161         RADEON_WRITE(R600_PA_SC_ENHANCE, R600_FORCE_EOV_MAX_CLK_CNT(4095));
1162
1163 }
1164
1165 static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1166                                              u32 num_backends,
1167                                              u32 backend_disable_mask)
1168 {
1169         u32 backend_map = 0;
1170         u32 enabled_backends_mask;
1171         u32 enabled_backends_count;
1172         u32 cur_pipe;
1173         u32 swizzle_pipe[R7XX_MAX_PIPES];
1174         u32 cur_backend;
1175         u32 i;
1176
1177         if (num_tile_pipes > R7XX_MAX_PIPES)
1178                 num_tile_pipes = R7XX_MAX_PIPES;
1179         if (num_tile_pipes < 1)
1180                 num_tile_pipes = 1;
1181         if (num_backends > R7XX_MAX_BACKENDS)
1182                 num_backends = R7XX_MAX_BACKENDS;
1183         if (num_backends < 1)
1184                 num_backends = 1;
1185
1186         enabled_backends_mask = 0;
1187         enabled_backends_count = 0;
1188         for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
1189                 if (((backend_disable_mask >> i) & 1) == 0) {
1190                         enabled_backends_mask |= (1 << i);
1191                         ++enabled_backends_count;
1192                 }
1193                 if (enabled_backends_count == num_backends)
1194                         break;
1195         }
1196
1197         if (enabled_backends_count == 0) {
1198                 enabled_backends_mask = 1;
1199                 enabled_backends_count = 1;
1200         }
1201
1202         if (enabled_backends_count != num_backends)
1203                 num_backends = enabled_backends_count;
1204
1205         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
1206         switch (num_tile_pipes) {
1207         case 1:
1208                 swizzle_pipe[0] = 0;
1209                 break;
1210         case 2:
1211                 swizzle_pipe[0] = 0;
1212                 swizzle_pipe[1] = 1;
1213                 break;
1214         case 3:
1215                 swizzle_pipe[0] = 0;
1216                 swizzle_pipe[1] = 2;
1217                 swizzle_pipe[2] = 1;
1218                 break;
1219         case 4:
1220                 swizzle_pipe[0] = 0;
1221                 swizzle_pipe[1] = 2;
1222                 swizzle_pipe[2] = 3;
1223                 swizzle_pipe[3] = 1;
1224                 break;
1225         case 5:
1226                 swizzle_pipe[0] = 0;
1227                 swizzle_pipe[1] = 2;
1228                 swizzle_pipe[2] = 4;
1229                 swizzle_pipe[3] = 1;
1230                 swizzle_pipe[4] = 3;
1231                 break;
1232         case 6:
1233                 swizzle_pipe[0] = 0;
1234                 swizzle_pipe[1] = 2;
1235                 swizzle_pipe[2] = 4;
1236                 swizzle_pipe[3] = 5;
1237                 swizzle_pipe[4] = 3;
1238                 swizzle_pipe[5] = 1;
1239                 break;
1240         case 7:
1241                 swizzle_pipe[0] = 0;
1242                 swizzle_pipe[1] = 2;
1243                 swizzle_pipe[2] = 4;
1244                 swizzle_pipe[3] = 6;
1245                 swizzle_pipe[4] = 3;
1246                 swizzle_pipe[5] = 1;
1247                 swizzle_pipe[6] = 5;
1248                 break;
1249         case 8:
1250                 swizzle_pipe[0] = 0;
1251                 swizzle_pipe[1] = 2;
1252                 swizzle_pipe[2] = 4;
1253                 swizzle_pipe[3] = 6;
1254                 swizzle_pipe[4] = 3;
1255                 swizzle_pipe[5] = 1;
1256                 swizzle_pipe[6] = 7;
1257                 swizzle_pipe[7] = 5;
1258                 break;
1259         }
1260
1261         cur_backend = 0;
1262         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1263                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1264                         cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
1265
1266                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1267
1268                 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
1269         }
1270
1271         return backend_map;
1272 }
1273
1274 static void r700_gfx_init(struct drm_device *dev,
1275                           drm_radeon_private_t *dev_priv)
1276 {
1277         int i, j, num_qd_pipes;
1278         u32 sx_debug_1;
1279         u32 smx_dc_ctl0;
1280         u32 num_gs_verts_per_thread;
1281         u32 vgt_gs_per_es;
1282         u32 gs_prim_buffer_depth = 0;
1283         u32 sq_ms_fifo_sizes;
1284         u32 sq_config;
1285         u32 sq_thread_resource_mgmt;
1286         u32 hdp_host_path_cntl;
1287         u32 sq_dyn_gpr_size_simd_ab_0;
1288         u32 backend_map;
1289         u32 gb_tiling_config = 0;
1290         u32 cc_rb_backend_disable = 0;
1291         u32 cc_gc_shader_pipe_config = 0;
1292         u32 mc_arb_ramcfg;
1293         u32 db_debug4;
1294
1295         /* setup chip specs */
1296         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1297         case CHIP_RV770:
1298                 dev_priv->r600_max_pipes = 4;
1299                 dev_priv->r600_max_tile_pipes = 8;
1300                 dev_priv->r600_max_simds = 10;
1301                 dev_priv->r600_max_backends = 4;
1302                 dev_priv->r600_max_gprs = 256;
1303                 dev_priv->r600_max_threads = 248;
1304                 dev_priv->r600_max_stack_entries = 512;
1305                 dev_priv->r600_max_hw_contexts = 8;
1306                 dev_priv->r600_max_gs_threads = 16 * 2;
1307                 dev_priv->r600_sx_max_export_size = 128;
1308                 dev_priv->r600_sx_max_export_pos_size = 16;
1309                 dev_priv->r600_sx_max_export_smx_size = 112;
1310                 dev_priv->r600_sq_num_cf_insts = 2;
1311
1312                 dev_priv->r700_sx_num_of_sets = 7;
1313                 dev_priv->r700_sc_prim_fifo_size = 0xF9;
1314                 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1315                 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1316                 break;
1317         case CHIP_RV730:
1318                 dev_priv->r600_max_pipes = 2;
1319                 dev_priv->r600_max_tile_pipes = 4;
1320                 dev_priv->r600_max_simds = 8;
1321                 dev_priv->r600_max_backends = 2;
1322                 dev_priv->r600_max_gprs = 128;
1323                 dev_priv->r600_max_threads = 248;
1324                 dev_priv->r600_max_stack_entries = 256;
1325                 dev_priv->r600_max_hw_contexts = 8;
1326                 dev_priv->r600_max_gs_threads = 16 * 2;
1327                 dev_priv->r600_sx_max_export_size = 256;
1328                 dev_priv->r600_sx_max_export_pos_size = 32;
1329                 dev_priv->r600_sx_max_export_smx_size = 224;
1330                 dev_priv->r600_sq_num_cf_insts = 2;
1331
1332                 dev_priv->r700_sx_num_of_sets = 7;
1333                 dev_priv->r700_sc_prim_fifo_size = 0xf9;
1334                 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1335                 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1336                 if (dev_priv->r600_sx_max_export_pos_size > 16) {
1337                         dev_priv->r600_sx_max_export_pos_size -= 16;
1338                         dev_priv->r600_sx_max_export_smx_size += 16;
1339                 }
1340                 break;
1341         case CHIP_RV710:
1342                 dev_priv->r600_max_pipes = 2;
1343                 dev_priv->r600_max_tile_pipes = 2;
1344                 dev_priv->r600_max_simds = 2;
1345                 dev_priv->r600_max_backends = 1;
1346                 dev_priv->r600_max_gprs = 256;
1347                 dev_priv->r600_max_threads = 192;
1348                 dev_priv->r600_max_stack_entries = 256;
1349                 dev_priv->r600_max_hw_contexts = 4;
1350                 dev_priv->r600_max_gs_threads = 8 * 2;
1351                 dev_priv->r600_sx_max_export_size = 128;
1352                 dev_priv->r600_sx_max_export_pos_size = 16;
1353                 dev_priv->r600_sx_max_export_smx_size = 112;
1354                 dev_priv->r600_sq_num_cf_insts = 1;
1355
1356                 dev_priv->r700_sx_num_of_sets = 7;
1357                 dev_priv->r700_sc_prim_fifo_size = 0x40;
1358                 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1359                 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1360                 break;
1361         case CHIP_RV740:
1362                 dev_priv->r600_max_pipes = 4;
1363                 dev_priv->r600_max_tile_pipes = 4;
1364                 dev_priv->r600_max_simds = 8;
1365                 dev_priv->r600_max_backends = 4;
1366                 dev_priv->r600_max_gprs = 256;
1367                 dev_priv->r600_max_threads = 248;
1368                 dev_priv->r600_max_stack_entries = 512;
1369                 dev_priv->r600_max_hw_contexts = 8;
1370                 dev_priv->r600_max_gs_threads = 16 * 2;
1371                 dev_priv->r600_sx_max_export_size = 256;
1372                 dev_priv->r600_sx_max_export_pos_size = 32;
1373                 dev_priv->r600_sx_max_export_smx_size = 224;
1374                 dev_priv->r600_sq_num_cf_insts = 2;
1375
1376                 dev_priv->r700_sx_num_of_sets = 7;
1377                 dev_priv->r700_sc_prim_fifo_size = 0x100;
1378                 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1379                 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1380
1381                 if (dev_priv->r600_sx_max_export_pos_size > 16) {
1382                         dev_priv->r600_sx_max_export_pos_size -= 16;
1383                         dev_priv->r600_sx_max_export_smx_size += 16;
1384                 }
1385                 break;
1386         default:
1387                 break;
1388         }
1389
1390         /* Initialize HDP */
1391         j = 0;
1392         for (i = 0; i < 32; i++) {
1393                 RADEON_WRITE((0x2c14 + j), 0x00000000);
1394                 RADEON_WRITE((0x2c18 + j), 0x00000000);
1395                 RADEON_WRITE((0x2c1c + j), 0x00000000);
1396                 RADEON_WRITE((0x2c20 + j), 0x00000000);
1397                 RADEON_WRITE((0x2c24 + j), 0x00000000);
1398                 j += 0x18;
1399         }
1400
1401         RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff));
1402
1403         /* setup tiling, simd, pipe config */
1404         mc_arb_ramcfg = RADEON_READ(R700_MC_ARB_RAMCFG);
1405
1406         switch (dev_priv->r600_max_tile_pipes) {
1407         case 1:
1408                 gb_tiling_config |= R600_PIPE_TILING(0);
1409                 break;
1410         case 2:
1411                 gb_tiling_config |= R600_PIPE_TILING(1);
1412                 break;
1413         case 4:
1414                 gb_tiling_config |= R600_PIPE_TILING(2);
1415                 break;
1416         case 8:
1417                 gb_tiling_config |= R600_PIPE_TILING(3);
1418                 break;
1419         default:
1420                 break;
1421         }
1422
1423         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)
1424                 gb_tiling_config |= R600_BANK_TILING(1);
1425         else
1426                 gb_tiling_config |= R600_BANK_TILING((mc_arb_ramcfg >> R700_NOOFBANK_SHIFT) & R700_NOOFBANK_MASK);
1427
1428         gb_tiling_config |= R600_GROUP_SIZE(0);
1429
1430         if (((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK) > 3) {
1431                 gb_tiling_config |= R600_ROW_TILING(3);
1432                 gb_tiling_config |= R600_SAMPLE_SPLIT(3);
1433         } else {
1434                 gb_tiling_config |=
1435                         R600_ROW_TILING(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK));
1436                 gb_tiling_config |=
1437                         R600_SAMPLE_SPLIT(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK));
1438         }
1439
1440         gb_tiling_config |= R600_BANK_SWAPS(1);
1441
1442         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV740)
1443                 backend_map = 0x28;
1444         else
1445                 backend_map = r700_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes,
1446                                                                 dev_priv->r600_max_backends,
1447                                                                 (0xff << dev_priv->r600_max_backends) & 0xff);
1448         gb_tiling_config |= R600_BACKEND_MAP(backend_map);
1449
1450         cc_gc_shader_pipe_config =
1451                 R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R7XX_MAX_PIPES_MASK);
1452         cc_gc_shader_pipe_config |=
1453                 R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R7XX_MAX_SIMDS_MASK);
1454
1455         cc_rb_backend_disable =
1456                 R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R7XX_MAX_BACKENDS_MASK);
1457
1458         RADEON_WRITE(R600_GB_TILING_CONFIG,      gb_tiling_config);
1459         RADEON_WRITE(R600_DCP_TILING_CONFIG,    (gb_tiling_config & 0xffff));
1460         RADEON_WRITE(R600_HDP_TILING_CONFIG,    (gb_tiling_config & 0xffff));
1461         if (gb_tiling_config & 0xc0) {
1462                 dev_priv->r600_group_size = 512;
1463         } else {
1464                 dev_priv->r600_group_size = 256;
1465         }
1466         dev_priv->r600_npipes = 1 << ((gb_tiling_config >> 1) & 0x7);
1467         if (gb_tiling_config & 0x30) {
1468                 dev_priv->r600_nbanks = 8;
1469         } else {
1470                 dev_priv->r600_nbanks = 4;
1471         }
1472
1473         RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
1474         RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
1475         RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1476
1477         RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1478         RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE, 0);
1479         RADEON_WRITE(R700_CGTS_TCC_DISABLE, 0);
1480         RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE, 0);
1481         RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE, 0);
1482
1483         num_qd_pipes =
1484                 R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK);
1485         RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK);
1486         RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK);
1487
1488         /* set HW defaults for 3D engine */
1489         RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) |
1490                                                 R600_ROQ_IB2_START(0x2b)));
1491
1492         RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, R700_STQ_SPLIT(0x30));
1493
1494         RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO |
1495                                         R600_SYNC_GRADIENT |
1496                                         R600_SYNC_WALKER |
1497                                         R600_SYNC_ALIGNER));
1498
1499         sx_debug_1 = RADEON_READ(R700_SX_DEBUG_1);
1500         sx_debug_1 |= R700_ENABLE_NEW_SMX_ADDRESS;
1501         RADEON_WRITE(R700_SX_DEBUG_1, sx_debug_1);
1502
1503         smx_dc_ctl0 = RADEON_READ(R600_SMX_DC_CTL0);
1504         smx_dc_ctl0 &= ~R700_CACHE_DEPTH(0x1ff);
1505         smx_dc_ctl0 |= R700_CACHE_DEPTH((dev_priv->r700_sx_num_of_sets * 64) - 1);
1506         RADEON_WRITE(R600_SMX_DC_CTL0, smx_dc_ctl0);
1507
1508         RADEON_WRITE(R700_SMX_EVENT_CTL, (R700_ES_FLUSH_CTL(4) |
1509                                           R700_GS_FLUSH_CTL(4) |
1510                                           R700_ACK_FLUSH_CTL(3) |
1511                                           R700_SYNC_FLUSH_CTL));
1512
1513         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)
1514                 RADEON_WRITE(R700_DB_DEBUG3, R700_DB_CLK_OFF_DELAY(0x1f));
1515         else {
1516                 db_debug4 = RADEON_READ(RV700_DB_DEBUG4);
1517                 db_debug4 |= RV700_DISABLE_TILE_COVERED_FOR_PS_ITER;
1518                 RADEON_WRITE(RV700_DB_DEBUG4, db_debug4);
1519         }
1520
1521         RADEON_WRITE(R600_SX_EXPORT_BUFFER_SIZES, (R600_COLOR_BUFFER_SIZE((dev_priv->r600_sx_max_export_size / 4) - 1) |
1522                                                    R600_POSITION_BUFFER_SIZE((dev_priv->r600_sx_max_export_pos_size / 4) - 1) |
1523                                                    R600_SMX_BUFFER_SIZE((dev_priv->r600_sx_max_export_smx_size / 4) - 1)));
1524
1525         RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX, (R700_SC_PRIM_FIFO_SIZE(dev_priv->r700_sc_prim_fifo_size) |
1526                                                  R700_SC_HIZ_TILE_FIFO_SIZE(dev_priv->r700_sc_hiz_tile_fifo_size) |
1527                                                  R700_SC_EARLYZ_TILE_FIFO_SIZE(dev_priv->r700_sc_earlyz_tile_fifo_fize)));
1528
1529         RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1530
1531         RADEON_WRITE(R600_VGT_NUM_INSTANCES, 1);
1532
1533         RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0));
1534
1535         RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(4));
1536
1537         RADEON_WRITE(R600_CP_PERFMON_CNTL, 0);
1538
1539         sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(16 * dev_priv->r600_sq_num_cf_insts) |
1540                             R600_DONE_FIFO_HIWATER(0xe0) |
1541                             R600_ALU_UPDATE_FIFO_HIWATER(0x8));
1542         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1543         case CHIP_RV770:
1544                 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x1);
1545                 break;
1546         case CHIP_RV730:
1547         case CHIP_RV710:
1548         case CHIP_RV740:
1549         default:
1550                 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x4);
1551                 break;
1552         }
1553         RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
1554
1555         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1556          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1557          */
1558         sq_config = RADEON_READ(R600_SQ_CONFIG);
1559         sq_config &= ~(R600_PS_PRIO(3) |
1560                        R600_VS_PRIO(3) |
1561                        R600_GS_PRIO(3) |
1562                        R600_ES_PRIO(3));
1563         sq_config |= (R600_DX9_CONSTS |
1564                       R600_VC_ENABLE |
1565                       R600_EXPORT_SRC_C |
1566                       R600_PS_PRIO(0) |
1567                       R600_VS_PRIO(1) |
1568                       R600_GS_PRIO(2) |
1569                       R600_ES_PRIO(3));
1570         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1571                 /* no vertex cache */
1572                 sq_config &= ~R600_VC_ENABLE;
1573
1574         RADEON_WRITE(R600_SQ_CONFIG, sq_config);
1575
1576         RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1,  (R600_NUM_PS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1577                                                     R600_NUM_VS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1578                                                     R600_NUM_CLAUSE_TEMP_GPRS(((dev_priv->r600_max_gprs * 24)/64)/2)));
1579
1580         RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2,  (R600_NUM_GS_GPRS((dev_priv->r600_max_gprs * 7)/64) |
1581                                                     R600_NUM_ES_GPRS((dev_priv->r600_max_gprs * 7)/64)));
1582
1583         sq_thread_resource_mgmt = (R600_NUM_PS_THREADS((dev_priv->r600_max_threads * 4)/8) |
1584                                    R600_NUM_VS_THREADS((dev_priv->r600_max_threads * 2)/8) |
1585                                    R600_NUM_ES_THREADS((dev_priv->r600_max_threads * 1)/8));
1586         if (((dev_priv->r600_max_threads * 1) / 8) > dev_priv->r600_max_gs_threads)
1587                 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS(dev_priv->r600_max_gs_threads);
1588         else
1589                 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS((dev_priv->r600_max_gs_threads * 1)/8);
1590         RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1591
1592         RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, (R600_NUM_PS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1593                                                      R600_NUM_VS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1594
1595         RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, (R600_NUM_GS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1596                                                      R600_NUM_ES_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1597
1598         sq_dyn_gpr_size_simd_ab_0 = (R700_SIMDA_RING0((dev_priv->r600_max_gprs * 38)/64) |
1599                                      R700_SIMDA_RING1((dev_priv->r600_max_gprs * 38)/64) |
1600                                      R700_SIMDB_RING0((dev_priv->r600_max_gprs * 38)/64) |
1601                                      R700_SIMDB_RING1((dev_priv->r600_max_gprs * 38)/64));
1602
1603         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
1604         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
1605         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
1606         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
1607         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
1608         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
1609         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
1610         RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
1611
1612         RADEON_WRITE(R700_PA_SC_FORCE_EOV_MAX_CNTS, (R700_FORCE_EOV_MAX_CLK_CNT(4095) |
1613                                                      R700_FORCE_EOV_MAX_REZ_CNT(255)));
1614
1615         if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1616                 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_TC_ONLY) |
1617                                                            R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO)));
1618         else
1619                 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_VC_AND_TC) |
1620                                                            R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO)));
1621
1622         switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1623         case CHIP_RV770:
1624         case CHIP_RV730:
1625         case CHIP_RV740:
1626                 gs_prim_buffer_depth = 384;
1627                 break;
1628         case CHIP_RV710:
1629                 gs_prim_buffer_depth = 128;
1630                 break;
1631         default:
1632                 break;
1633         }
1634
1635         num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1636         vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1637         /* Max value for this is 256 */
1638         if (vgt_gs_per_es > 256)
1639                 vgt_gs_per_es = 256;
1640
1641         RADEON_WRITE(R600_VGT_ES_PER_GS, 128);
1642         RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es);
1643         RADEON_WRITE(R600_VGT_GS_PER_VS, 2);
1644
1645         /* more default values. 2D/3D driver should adjust as needed */
1646         RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16);
1647         RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0);
1648         RADEON_WRITE(R600_VGT_STRMOUT_EN, 0);
1649         RADEON_WRITE(R600_SX_MISC, 0);
1650         RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0);
1651         RADEON_WRITE(R700_PA_SC_EDGERULE, 0xaaaaaaaa);
1652         RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0);
1653         RADEON_WRITE(R600_PA_SC_CLIPRECT_RULE, 0xffff);
1654         RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0);
1655         RADEON_WRITE(R600_SPI_INPUT_Z, 0);
1656         RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2));
1657         RADEON_WRITE(R600_CB_COLOR7_FRAG, 0);
1658
1659         /* clear render buffer base addresses */
1660         RADEON_WRITE(R600_CB_COLOR0_BASE, 0);
1661         RADEON_WRITE(R600_CB_COLOR1_BASE, 0);
1662         RADEON_WRITE(R600_CB_COLOR2_BASE, 0);
1663         RADEON_WRITE(R600_CB_COLOR3_BASE, 0);
1664         RADEON_WRITE(R600_CB_COLOR4_BASE, 0);
1665         RADEON_WRITE(R600_CB_COLOR5_BASE, 0);
1666         RADEON_WRITE(R600_CB_COLOR6_BASE, 0);
1667         RADEON_WRITE(R600_CB_COLOR7_BASE, 0);
1668
1669         RADEON_WRITE(R700_TCP_CNTL, 0);
1670
1671         hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);
1672         RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1673
1674         RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1675
1676         RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA |
1677                                           R600_NUM_CLIP_SEQ(3)));
1678
1679 }
1680
1681 static void r600_cp_init_ring_buffer(struct drm_device *dev,
1682                                        drm_radeon_private_t *dev_priv,
1683                                        struct drm_file *file_priv)
1684 {
1685         struct drm_radeon_master_private *master_priv;
1686         u32 ring_start;
1687         u64 rptr_addr;
1688
1689         if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
1690                 r700_gfx_init(dev, dev_priv);
1691         else
1692                 r600_gfx_init(dev, dev_priv);
1693
1694         RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
1695         RADEON_READ(R600_GRBM_SOFT_RESET);
1696         DRM_UDELAY(15000);
1697         RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
1698
1699
1700         /* Set ring buffer size */
1701 #ifdef __BIG_ENDIAN
1702         RADEON_WRITE(R600_CP_RB_CNTL,
1703                      RADEON_BUF_SWAP_32BIT |
1704                      RADEON_RB_NO_UPDATE |
1705                      (dev_priv->ring.rptr_update_l2qw << 8) |
1706                      dev_priv->ring.size_l2qw);
1707 #else
1708         RADEON_WRITE(R600_CP_RB_CNTL,
1709                      RADEON_RB_NO_UPDATE |
1710                      (dev_priv->ring.rptr_update_l2qw << 8) |
1711                      dev_priv->ring.size_l2qw);
1712 #endif
1713
1714         RADEON_WRITE(R600_CP_SEM_WAIT_TIMER, 0x4);
1715
1716         /* Set the write pointer delay */
1717         RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
1718
1719 #ifdef __BIG_ENDIAN
1720         RADEON_WRITE(R600_CP_RB_CNTL,
1721                      RADEON_BUF_SWAP_32BIT |
1722                      RADEON_RB_NO_UPDATE |
1723                      RADEON_RB_RPTR_WR_ENA |
1724                      (dev_priv->ring.rptr_update_l2qw << 8) |
1725                      dev_priv->ring.size_l2qw);
1726 #else
1727         RADEON_WRITE(R600_CP_RB_CNTL,
1728                      RADEON_RB_NO_UPDATE |
1729                      RADEON_RB_RPTR_WR_ENA |
1730                      (dev_priv->ring.rptr_update_l2qw << 8) |
1731                      dev_priv->ring.size_l2qw);
1732 #endif
1733
1734         /* Initialize the ring buffer's read and write pointers */
1735         RADEON_WRITE(R600_CP_RB_RPTR_WR, 0);
1736         RADEON_WRITE(R600_CP_RB_WPTR, 0);
1737         SET_RING_HEAD(dev_priv, 0);
1738         dev_priv->ring.tail = 0;
1739
1740 #if __OS_HAS_AGP
1741         if (dev_priv->flags & RADEON_IS_AGP) {
1742                 rptr_addr = dev_priv->ring_rptr->offset
1743                         - dev->agp->base +
1744                         dev_priv->gart_vm_start;
1745         } else
1746 #endif
1747         {
1748                 rptr_addr = dev_priv->ring_rptr->offset
1749                         - ((unsigned long) dev->sg->virtual)
1750                         + dev_priv->gart_vm_start;
1751         }
1752         RADEON_WRITE(R600_CP_RB_RPTR_ADDR,
1753                      rptr_addr & 0xffffffff);
1754         RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI,
1755                      upper_32_bits(rptr_addr));
1756
1757 #ifdef __BIG_ENDIAN
1758         RADEON_WRITE(R600_CP_RB_CNTL,
1759                      RADEON_BUF_SWAP_32BIT |
1760                      (dev_priv->ring.rptr_update_l2qw << 8) |
1761                      dev_priv->ring.size_l2qw);
1762 #else
1763         RADEON_WRITE(R600_CP_RB_CNTL,
1764                      (dev_priv->ring.rptr_update_l2qw << 8) |
1765                      dev_priv->ring.size_l2qw);
1766 #endif
1767
1768 #if __OS_HAS_AGP
1769         if (dev_priv->flags & RADEON_IS_AGP) {
1770                 /* XXX */
1771                 radeon_write_agp_base(dev_priv, dev->agp->base);
1772
1773                 /* XXX */
1774                 radeon_write_agp_location(dev_priv,
1775                              (((dev_priv->gart_vm_start - 1 +
1776                                 dev_priv->gart_size) & 0xffff0000) |
1777                               (dev_priv->gart_vm_start >> 16)));
1778
1779                 ring_start = (dev_priv->cp_ring->offset
1780                               - dev->agp->base
1781                               + dev_priv->gart_vm_start);
1782         } else
1783 #endif
1784                 ring_start = (dev_priv->cp_ring->offset
1785                               - (unsigned long)dev->sg->virtual
1786                               + dev_priv->gart_vm_start);
1787
1788         RADEON_WRITE(R600_CP_RB_BASE, ring_start >> 8);
1789
1790         RADEON_WRITE(R600_CP_ME_CNTL, 0xff);
1791
1792         RADEON_WRITE(R600_CP_DEBUG, (1 << 27) | (1 << 28));
1793
1794         /* Initialize the scratch register pointer.  This will cause
1795          * the scratch register values to be written out to memory
1796          * whenever they are updated.
1797          *
1798          * We simply put this behind the ring read pointer, this works
1799          * with PCI GART as well as (whatever kind of) AGP GART
1800          */
1801         {
1802                 u64 scratch_addr;
1803
1804                 scratch_addr = RADEON_READ(R600_CP_RB_RPTR_ADDR);
1805                 scratch_addr |= ((u64)RADEON_READ(R600_CP_RB_RPTR_ADDR_HI)) << 32;
1806                 scratch_addr += R600_SCRATCH_REG_OFFSET;
1807                 scratch_addr >>= 8;
1808                 scratch_addr &= 0xffffffff;
1809
1810                 RADEON_WRITE(R600_SCRATCH_ADDR, (uint32_t)scratch_addr);
1811         }
1812
1813         RADEON_WRITE(R600_SCRATCH_UMSK, 0x7);
1814
1815         /* Turn on bus mastering */
1816         radeon_enable_bm(dev_priv);
1817
1818         radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(0), 0);
1819         RADEON_WRITE(R600_LAST_FRAME_REG, 0);
1820
1821         radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
1822         RADEON_WRITE(R600_LAST_DISPATCH_REG, 0);
1823
1824         radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(2), 0);
1825         RADEON_WRITE(R600_LAST_CLEAR_REG, 0);
1826
1827         /* reset sarea copies of these */
1828         master_priv = file_priv->master->driver_priv;
1829         if (master_priv->sarea_priv) {
1830                 master_priv->sarea_priv->last_frame = 0;
1831                 master_priv->sarea_priv->last_dispatch = 0;
1832                 master_priv->sarea_priv->last_clear = 0;
1833         }
1834
1835         r600_do_wait_for_idle(dev_priv);
1836
1837 }
1838
1839 int r600_do_cleanup_cp(struct drm_device *dev)
1840 {
1841         drm_radeon_private_t *dev_priv = dev->dev_private;
1842         DRM_DEBUG("\n");
1843
1844         /* Make sure interrupts are disabled here because the uninstall ioctl
1845          * may not have been called from userspace and after dev_private
1846          * is freed, it's too late.
1847          */
1848         if (dev->irq_enabled)
1849                 drm_irq_uninstall(dev);
1850
1851 #if __OS_HAS_AGP
1852         if (dev_priv->flags & RADEON_IS_AGP) {
1853                 if (dev_priv->cp_ring != NULL) {
1854                         drm_core_ioremapfree(dev_priv->cp_ring, dev);
1855                         dev_priv->cp_ring = NULL;
1856                 }
1857                 if (dev_priv->ring_rptr != NULL) {
1858                         drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1859                         dev_priv->ring_rptr = NULL;
1860                 }
1861                 if (dev->agp_buffer_map != NULL) {
1862                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
1863                         dev->agp_buffer_map = NULL;
1864                 }
1865         } else
1866 #endif
1867         {
1868
1869                 if (dev_priv->gart_info.bus_addr)
1870                         r600_page_table_cleanup(dev, &dev_priv->gart_info);
1871
1872                 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) {
1873                         drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1874                         dev_priv->gart_info.addr = NULL;
1875                 }
1876         }
1877         /* only clear to the start of flags */
1878         memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1879
1880         return 0;
1881 }
1882
1883 int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1884                     struct drm_file *file_priv)
1885 {
1886         drm_radeon_private_t *dev_priv = dev->dev_private;
1887         struct drm_radeon_master_private *master_priv = file_priv->master->driver_priv;
1888
1889         DRM_DEBUG("\n");
1890
1891         mutex_init(&dev_priv->cs_mutex);
1892         r600_cs_legacy_init();
1893         /* if we require new memory map but we don't have it fail */
1894         if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1895                 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1896                 r600_do_cleanup_cp(dev);
1897                 return -EINVAL;
1898         }
1899
1900         if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1901                 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1902                 dev_priv->flags &= ~RADEON_IS_AGP;
1903                 /* The writeback test succeeds, but when writeback is enabled,
1904                  * the ring buffer read ptr update fails after first 128 bytes.
1905                  */
1906                 radeon_no_wb = 1;
1907         } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1908                  && !init->is_pci) {
1909                 DRM_DEBUG("Restoring AGP flag\n");
1910                 dev_priv->flags |= RADEON_IS_AGP;
1911         }
1912
1913         dev_priv->usec_timeout = init->usec_timeout;
1914         if (dev_priv->usec_timeout < 1 ||
1915             dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1916                 DRM_DEBUG("TIMEOUT problem!\n");
1917                 r600_do_cleanup_cp(dev);
1918                 return -EINVAL;
1919         }
1920
1921         /* Enable vblank on CRTC1 for older X servers
1922          */
1923         dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1924         dev_priv->do_boxes = 0;
1925         dev_priv->cp_mode = init->cp_mode;
1926
1927         /* We don't support anything other than bus-mastering ring mode,
1928          * but the ring can be in either AGP or PCI space for the ring
1929          * read pointer.
1930          */
1931         if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1932             (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1933                 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1934                 r600_do_cleanup_cp(dev);
1935                 return -EINVAL;
1936         }
1937
1938         switch (init->fb_bpp) {
1939         case 16:
1940                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1941                 break;
1942         case 32:
1943         default:
1944                 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1945                 break;
1946         }
1947         dev_priv->front_offset = init->front_offset;
1948         dev_priv->front_pitch = init->front_pitch;
1949         dev_priv->back_offset = init->back_offset;
1950         dev_priv->back_pitch = init->back_pitch;
1951
1952         dev_priv->ring_offset = init->ring_offset;
1953         dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1954         dev_priv->buffers_offset = init->buffers_offset;
1955         dev_priv->gart_textures_offset = init->gart_textures_offset;
1956
1957         master_priv->sarea = drm_getsarea(dev);
1958         if (!master_priv->sarea) {
1959                 DRM_ERROR("could not find sarea!\n");
1960                 r600_do_cleanup_cp(dev);
1961                 return -EINVAL;
1962         }
1963
1964         dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1965         if (!dev_priv->cp_ring) {
1966                 DRM_ERROR("could not find cp ring region!\n");
1967                 r600_do_cleanup_cp(dev);
1968                 return -EINVAL;
1969         }
1970         dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1971         if (!dev_priv->ring_rptr) {
1972                 DRM_ERROR("could not find ring read pointer!\n");
1973                 r600_do_cleanup_cp(dev);
1974                 return -EINVAL;
1975         }
1976         dev->agp_buffer_token = init->buffers_offset;
1977         dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1978         if (!dev->agp_buffer_map) {
1979                 DRM_ERROR("could not find dma buffer region!\n");
1980                 r600_do_cleanup_cp(dev);
1981                 return -EINVAL;
1982         }
1983
1984         if (init->gart_textures_offset) {
1985                 dev_priv->gart_textures =
1986                     drm_core_findmap(dev, init->gart_textures_offset);
1987                 if (!dev_priv->gart_textures) {
1988                         DRM_ERROR("could not find GART texture region!\n");
1989                         r600_do_cleanup_cp(dev);
1990                         return -EINVAL;
1991                 }
1992         }
1993
1994 #if __OS_HAS_AGP
1995         /* XXX */
1996         if (dev_priv->flags & RADEON_IS_AGP) {
1997                 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1998                 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1999                 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
2000                 if (!dev_priv->cp_ring->handle ||
2001                     !dev_priv->ring_rptr->handle ||
2002                     !dev->agp_buffer_map->handle) {
2003                         DRM_ERROR("could not find ioremap agp regions!\n");
2004                         r600_do_cleanup_cp(dev);
2005                         return -EINVAL;
2006                 }
2007         } else
2008 #endif
2009         {
2010                 dev_priv->cp_ring->handle = (void *)(unsigned long)dev_priv->cp_ring->offset;
2011                 dev_priv->ring_rptr->handle =
2012                         (void *)(unsigned long)dev_priv->ring_rptr->offset;
2013                 dev->agp_buffer_map->handle =
2014                         (void *)(unsigned long)dev->agp_buffer_map->offset;
2015
2016                 DRM_DEBUG("dev_priv->cp_ring->handle %p\n",
2017                           dev_priv->cp_ring->handle);
2018                 DRM_DEBUG("dev_priv->ring_rptr->handle %p\n",
2019                           dev_priv->ring_rptr->handle);
2020                 DRM_DEBUG("dev->agp_buffer_map->handle %p\n",
2021                           dev->agp_buffer_map->handle);
2022         }
2023
2024         dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 24;
2025         dev_priv->fb_size =
2026                 (((radeon_read_fb_location(dev_priv) & 0xffff0000u) << 8) + 0x1000000)
2027                 - dev_priv->fb_location;
2028
2029         dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
2030                                         ((dev_priv->front_offset
2031                                           + dev_priv->fb_location) >> 10));
2032
2033         dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
2034                                        ((dev_priv->back_offset
2035                                          + dev_priv->fb_location) >> 10));
2036
2037         dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
2038                                         ((dev_priv->depth_offset
2039                                           + dev_priv->fb_location) >> 10));
2040
2041         dev_priv->gart_size = init->gart_size;
2042
2043         /* New let's set the memory map ... */
2044         if (dev_priv->new_memmap) {
2045                 u32 base = 0;
2046
2047                 DRM_INFO("Setting GART location based on new memory map\n");
2048
2049                 /* If using AGP, try to locate the AGP aperture at the same
2050                  * location in the card and on the bus, though we have to
2051                  * align it down.
2052                  */
2053 #if __OS_HAS_AGP
2054                 /* XXX */
2055                 if (dev_priv->flags & RADEON_IS_AGP) {
2056                         base = dev->agp->base;
2057                         /* Check if valid */
2058                         if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
2059                             base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
2060                                 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
2061                                          dev->agp->base);
2062                                 base = 0;
2063                         }
2064                 }
2065 #endif
2066                 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
2067                 if (base == 0) {
2068                         base = dev_priv->fb_location + dev_priv->fb_size;
2069                         if (base < dev_priv->fb_location ||
2070                             ((base + dev_priv->gart_size) & 0xfffffffful) < base)
2071                                 base = dev_priv->fb_location
2072                                         - dev_priv->gart_size;
2073                 }
2074                 dev_priv->gart_vm_start = base & 0xffc00000u;
2075                 if (dev_priv->gart_vm_start != base)
2076                         DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
2077                                  base, dev_priv->gart_vm_start);
2078         }
2079
2080 #if __OS_HAS_AGP
2081         /* XXX */
2082         if (dev_priv->flags & RADEON_IS_AGP)
2083                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
2084                                                  - dev->agp->base
2085                                                  + dev_priv->gart_vm_start);
2086         else
2087 #endif
2088                 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
2089                                                  - (unsigned long)dev->sg->virtual
2090                                                  + dev_priv->gart_vm_start);
2091
2092         DRM_DEBUG("fb 0x%08x size %d\n",
2093                   (unsigned int) dev_priv->fb_location,
2094                   (unsigned int) dev_priv->fb_size);
2095         DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
2096         DRM_DEBUG("dev_priv->gart_vm_start 0x%08x\n",
2097                   (unsigned int) dev_priv->gart_vm_start);
2098         DRM_DEBUG("dev_priv->gart_buffers_offset 0x%08lx\n",
2099                   dev_priv->gart_buffers_offset);
2100
2101         dev_priv->ring.start = (u32 *) dev_priv->cp_ring->handle;
2102         dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->handle
2103                               + init->ring_size / sizeof(u32));
2104         dev_priv->ring.size = init->ring_size;
2105         dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
2106
2107         dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
2108         dev_priv->ring.rptr_update_l2qw = drm_order(/* init->rptr_update */ 4096 / 8);
2109
2110         dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
2111         dev_priv->ring.fetch_size_l2ow = drm_order(/* init->fetch_size */ 32 / 16);
2112
2113         dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
2114
2115         dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
2116
2117 #if __OS_HAS_AGP
2118         if (dev_priv->flags & RADEON_IS_AGP) {
2119                 /* XXX turn off pcie gart */
2120         } else
2121 #endif
2122         {
2123                 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
2124                 /* if we have an offset set from userspace */
2125                 if (!dev_priv->pcigart_offset_set) {
2126                         DRM_ERROR("Need gart offset from userspace\n");
2127                         r600_do_cleanup_cp(dev);
2128                         return -EINVAL;
2129                 }
2130
2131                 DRM_DEBUG("Using gart offset 0x%08lx\n", dev_priv->pcigart_offset);
2132
2133                 dev_priv->gart_info.bus_addr =
2134                         dev_priv->pcigart_offset + dev_priv->fb_location;
2135                 dev_priv->gart_info.mapping.offset =
2136                         dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
2137                 dev_priv->gart_info.mapping.size =
2138                         dev_priv->gart_info.table_size;
2139
2140                 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
2141                 if (!dev_priv->gart_info.mapping.handle) {
2142                         DRM_ERROR("ioremap failed.\n");
2143                         r600_do_cleanup_cp(dev);
2144                         return -EINVAL;
2145                 }
2146
2147                 dev_priv->gart_info.addr =
2148                         dev_priv->gart_info.mapping.handle;
2149
2150                 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
2151                           dev_priv->gart_info.addr,
2152                           dev_priv->pcigart_offset);
2153
2154                 if (!r600_page_table_init(dev)) {
2155                         DRM_ERROR("Failed to init GART table\n");
2156                         r600_do_cleanup_cp(dev);
2157                         return -EINVAL;
2158                 }
2159
2160                 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2161                         r700_vm_init(dev);
2162                 else
2163                         r600_vm_init(dev);
2164         }
2165
2166         if (!dev_priv->me_fw || !dev_priv->pfp_fw) {
2167                 int err = r600_cp_init_microcode(dev_priv);
2168                 if (err) {
2169                         DRM_ERROR("Failed to load firmware!\n");
2170                         r600_do_cleanup_cp(dev);
2171                         return err;
2172                 }
2173         }
2174         if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2175                 r700_cp_load_microcode(dev_priv);
2176         else
2177                 r600_cp_load_microcode(dev_priv);
2178
2179         r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
2180
2181         dev_priv->last_buf = 0;
2182
2183         r600_do_engine_reset(dev);
2184         r600_test_writeback(dev_priv);
2185
2186         return 0;
2187 }
2188
2189 int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
2190 {
2191         drm_radeon_private_t *dev_priv = dev->dev_private;
2192
2193         DRM_DEBUG("\n");
2194         if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) {
2195                 r700_vm_init(dev);
2196                 r700_cp_load_microcode(dev_priv);
2197         } else {
2198                 r600_vm_init(dev);
2199                 r600_cp_load_microcode(dev_priv);
2200         }
2201         r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
2202         r600_do_engine_reset(dev);
2203
2204         return 0;
2205 }
2206
2207 /* Wait for the CP to go idle.
2208  */
2209 int r600_do_cp_idle(drm_radeon_private_t *dev_priv)
2210 {
2211         RING_LOCALS;
2212         DRM_DEBUG("\n");
2213
2214         BEGIN_RING(5);
2215         OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
2216         OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
2217         /* wait for 3D idle clean */
2218         OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
2219         OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2);
2220         OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN);
2221
2222         ADVANCE_RING();
2223         COMMIT_RING();
2224
2225         return r600_do_wait_for_idle(dev_priv);
2226 }
2227
2228 /* Start the Command Processor.
2229  */
2230 void r600_do_cp_start(drm_radeon_private_t *dev_priv)
2231 {
2232         u32 cp_me;
2233         RING_LOCALS;
2234         DRM_DEBUG("\n");
2235
2236         BEGIN_RING(7);
2237         OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5));
2238         OUT_RING(0x00000001);
2239         if (((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770))
2240                 OUT_RING(0x00000003);
2241         else
2242                 OUT_RING(0x00000000);
2243         OUT_RING((dev_priv->r600_max_hw_contexts - 1));
2244         OUT_RING(R600_ME_INITIALIZE_DEVICE_ID(1));
2245         OUT_RING(0x00000000);
2246         OUT_RING(0x00000000);
2247         ADVANCE_RING();
2248         COMMIT_RING();
2249
2250         /* set the mux and reset the halt bit */
2251         cp_me = 0xff;
2252         RADEON_WRITE(R600_CP_ME_CNTL, cp_me);
2253
2254         dev_priv->cp_running = 1;
2255
2256 }
2257
2258 void r600_do_cp_reset(drm_radeon_private_t *dev_priv)
2259 {
2260         u32 cur_read_ptr;
2261         DRM_DEBUG("\n");
2262
2263         cur_read_ptr = RADEON_READ(R600_CP_RB_RPTR);
2264         RADEON_WRITE(R600_CP_RB_WPTR, cur_read_ptr);
2265         SET_RING_HEAD(dev_priv, cur_read_ptr);
2266         dev_priv->ring.tail = cur_read_ptr;
2267 }
2268
2269 void r600_do_cp_stop(drm_radeon_private_t *dev_priv)
2270 {
2271         uint32_t cp_me;
2272
2273         DRM_DEBUG("\n");
2274
2275         cp_me = 0xff | R600_CP_ME_HALT;
2276
2277         RADEON_WRITE(R600_CP_ME_CNTL, cp_me);
2278
2279         dev_priv->cp_running = 0;
2280 }
2281
2282 int r600_cp_dispatch_indirect(struct drm_device *dev,
2283                               struct drm_buf *buf, int start, int end)
2284 {
2285         drm_radeon_private_t *dev_priv = dev->dev_private;
2286         RING_LOCALS;
2287
2288         if (start != end) {
2289                 unsigned long offset = (dev_priv->gart_buffers_offset
2290                                         + buf->offset + start);
2291                 int dwords = (end - start + 3) / sizeof(u32);
2292
2293                 DRM_DEBUG("dwords:%d\n", dwords);
2294                 DRM_DEBUG("offset 0x%lx\n", offset);
2295
2296
2297                 /* Indirect buffer data must be a multiple of 16 dwords.
2298                  * pad the data with a Type-2 CP packet.
2299                  */
2300                 while (dwords & 0xf) {
2301                         u32 *data = (u32 *)
2302                             ((char *)dev->agp_buffer_map->handle
2303                              + buf->offset + start);
2304                         data[dwords++] = RADEON_CP_PACKET2;
2305                 }
2306
2307                 /* Fire off the indirect buffer */
2308                 BEGIN_RING(4);
2309                 OUT_RING(CP_PACKET3(R600_IT_INDIRECT_BUFFER, 2));
2310                 OUT_RING((offset & 0xfffffffc));
2311                 OUT_RING((upper_32_bits(offset) & 0xff));
2312                 OUT_RING(dwords);
2313                 ADVANCE_RING();
2314         }
2315
2316         return 0;
2317 }
2318
2319 void r600_cp_dispatch_swap(struct drm_device *dev, struct drm_file *file_priv)
2320 {
2321         drm_radeon_private_t *dev_priv = dev->dev_private;
2322         struct drm_master *master = file_priv->master;
2323         struct drm_radeon_master_private *master_priv = master->driver_priv;
2324         drm_radeon_sarea_t *sarea_priv = master_priv->sarea_priv;
2325         int nbox = sarea_priv->nbox;
2326         struct drm_clip_rect *pbox = sarea_priv->boxes;
2327         int i, cpp, src_pitch, dst_pitch;
2328         uint64_t src, dst;
2329         RING_LOCALS;
2330         DRM_DEBUG("\n");
2331
2332         if (dev_priv->color_fmt == RADEON_COLOR_FORMAT_ARGB8888)
2333                 cpp = 4;
2334         else
2335                 cpp = 2;
2336
2337         if (sarea_priv->pfCurrentPage == 0) {
2338                 src_pitch = dev_priv->back_pitch;
2339                 dst_pitch = dev_priv->front_pitch;
2340                 src = dev_priv->back_offset + dev_priv->fb_location;
2341                 dst = dev_priv->front_offset + dev_priv->fb_location;
2342         } else {
2343                 src_pitch = dev_priv->front_pitch;
2344                 dst_pitch = dev_priv->back_pitch;
2345                 src = dev_priv->front_offset + dev_priv->fb_location;
2346                 dst = dev_priv->back_offset + dev_priv->fb_location;
2347         }
2348
2349         if (r600_prepare_blit_copy(dev, file_priv)) {
2350                 DRM_ERROR("unable to allocate vertex buffer for swap buffer\n");
2351                 return;
2352         }
2353         for (i = 0; i < nbox; i++) {
2354                 int x = pbox[i].x1;
2355                 int y = pbox[i].y1;
2356                 int w = pbox[i].x2 - x;
2357                 int h = pbox[i].y2 - y;
2358
2359                 DRM_DEBUG("%d,%d-%d,%d\n", x, y, w, h);
2360
2361                 r600_blit_swap(dev,
2362                                src, dst,
2363                                x, y, x, y, w, h,
2364                                src_pitch, dst_pitch, cpp);
2365         }
2366         r600_done_blit_copy(dev);
2367
2368         /* Increment the frame counter.  The client-side 3D driver must
2369          * throttle the framerate by waiting for this value before
2370          * performing the swapbuffer ioctl.
2371          */
2372         sarea_priv->last_frame++;
2373
2374         BEGIN_RING(3);
2375         R600_FRAME_AGE(sarea_priv->last_frame);
2376         ADVANCE_RING();
2377 }
2378
2379 int r600_cp_dispatch_texture(struct drm_device *dev,
2380                              struct drm_file *file_priv,
2381                              drm_radeon_texture_t *tex,
2382                              drm_radeon_tex_image_t *image)
2383 {
2384         drm_radeon_private_t *dev_priv = dev->dev_private;
2385         struct drm_buf *buf;
2386         u32 *buffer;
2387         const u8 __user *data;
2388         int size, pass_size;
2389         u64 src_offset, dst_offset;
2390
2391         if (!radeon_check_offset(dev_priv, tex->offset)) {
2392                 DRM_ERROR("Invalid destination offset\n");
2393                 return -EINVAL;
2394         }
2395
2396         /* this might fail for zero-sized uploads - are those illegal? */
2397         if (!radeon_check_offset(dev_priv, tex->offset + tex->height * tex->pitch - 1)) {
2398                 DRM_ERROR("Invalid final destination offset\n");
2399                 return -EINVAL;
2400         }
2401
2402         size = tex->height * tex->pitch;
2403
2404         if (size == 0)
2405                 return 0;
2406
2407         dst_offset = tex->offset;
2408
2409         if (r600_prepare_blit_copy(dev, file_priv)) {
2410                 DRM_ERROR("unable to allocate vertex buffer for swap buffer\n");
2411                 return -EAGAIN;
2412         }
2413         do {
2414                 data = (const u8 __user *)image->data;
2415                 pass_size = size;
2416
2417                 buf = radeon_freelist_get(dev);
2418                 if (!buf) {
2419                         DRM_DEBUG("EAGAIN\n");
2420                         if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image)))
2421                                 return -EFAULT;
2422                         return -EAGAIN;
2423                 }
2424
2425                 if (pass_size > buf->total)
2426                         pass_size = buf->total;
2427
2428                 /* Dispatch the indirect buffer.
2429                  */
2430                 buffer =
2431                     (u32 *) ((char *)dev->agp_buffer_map->handle + buf->offset);
2432
2433                 if (DRM_COPY_FROM_USER(buffer, data, pass_size)) {
2434                         DRM_ERROR("EFAULT on pad, %d bytes\n", pass_size);
2435                         return -EFAULT;
2436                 }
2437
2438                 buf->file_priv = file_priv;
2439                 buf->used = pass_size;
2440                 src_offset = dev_priv->gart_buffers_offset + buf->offset;
2441
2442                 r600_blit_copy(dev, src_offset, dst_offset, pass_size);
2443
2444                 radeon_cp_discard_buffer(dev, file_priv->master, buf);
2445
2446                 /* Update the input parameters for next time */
2447                 image->data = (const u8 __user *)image->data + pass_size;
2448                 dst_offset += pass_size;
2449                 size -= pass_size;
2450         } while (size > 0);
2451         r600_done_blit_copy(dev);
2452
2453         return 0;
2454 }
2455
2456 /*
2457  * Legacy cs ioctl
2458  */
2459 static u32 radeon_cs_id_get(struct drm_radeon_private *radeon)
2460 {
2461         /* FIXME: check if wrap affect last reported wrap & sequence */
2462         radeon->cs_id_scnt = (radeon->cs_id_scnt + 1) & 0x00FFFFFF;
2463         if (!radeon->cs_id_scnt) {
2464                 /* increment wrap counter */
2465                 radeon->cs_id_wcnt += 0x01000000;
2466                 /* valid sequence counter start at 1 */
2467                 radeon->cs_id_scnt = 1;
2468         }
2469         return (radeon->cs_id_scnt | radeon->cs_id_wcnt);
2470 }
2471
2472 static void r600_cs_id_emit(drm_radeon_private_t *dev_priv, u32 *id)
2473 {
2474         RING_LOCALS;
2475
2476         *id = radeon_cs_id_get(dev_priv);
2477
2478         /* SCRATCH 2 */
2479         BEGIN_RING(3);
2480         R600_CLEAR_AGE(*id);
2481         ADVANCE_RING();
2482         COMMIT_RING();
2483 }
2484
2485 static int r600_ib_get(struct drm_device *dev,
2486                         struct drm_file *fpriv,
2487                         struct drm_buf **buffer)
2488 {
2489         struct drm_buf *buf;
2490
2491         *buffer = NULL;
2492         buf = radeon_freelist_get(dev);
2493         if (!buf) {
2494                 return -EBUSY;
2495         }
2496         buf->file_priv = fpriv;
2497         *buffer = buf;
2498         return 0;
2499 }
2500
2501 static void r600_ib_free(struct drm_device *dev, struct drm_buf *buf,
2502                         struct drm_file *fpriv, int l, int r)
2503 {
2504         drm_radeon_private_t *dev_priv = dev->dev_private;
2505
2506         if (buf) {
2507                 if (!r)
2508                         r600_cp_dispatch_indirect(dev, buf, 0, l * 4);
2509                 radeon_cp_discard_buffer(dev, fpriv->master, buf);
2510                 COMMIT_RING();
2511         }
2512 }
2513
2514 int r600_cs_legacy_ioctl(struct drm_device *dev, void *data, struct drm_file *fpriv)
2515 {
2516         struct drm_radeon_private *dev_priv = dev->dev_private;
2517         struct drm_radeon_cs *cs = data;
2518         struct drm_buf *buf;
2519         unsigned family;
2520         int l, r = 0;
2521         u32 *ib, cs_id = 0;
2522
2523         if (dev_priv == NULL) {
2524                 DRM_ERROR("called with no initialization\n");
2525                 return -EINVAL;
2526         }
2527         family = dev_priv->flags & RADEON_FAMILY_MASK;
2528         if (family < CHIP_R600) {
2529                 DRM_ERROR("cs ioctl valid only for R6XX & R7XX in legacy mode\n");
2530                 return -EINVAL;
2531         }
2532         mutex_lock(&dev_priv->cs_mutex);
2533         /* get ib */
2534         r = r600_ib_get(dev, fpriv, &buf);
2535         if (r) {
2536                 DRM_ERROR("ib_get failed\n");
2537                 goto out;
2538         }
2539         ib = dev->agp_buffer_map->handle + buf->offset;
2540         /* now parse command stream */
2541         r = r600_cs_legacy(dev, data,  fpriv, family, ib, &l);
2542         if (r) {
2543                 goto out;
2544         }
2545
2546 out:
2547         r600_ib_free(dev, buf, fpriv, l, r);
2548         /* emit cs id sequence */
2549         r600_cs_id_emit(dev_priv, &cs_id);
2550         cs->cs_id = cs_id;
2551         mutex_unlock(&dev_priv->cs_mutex);
2552         return r;
2553 }
2554
2555 void r600_cs_legacy_get_tiling_conf(struct drm_device *dev, u32 *npipes, u32 *nbanks, u32 *group_size)
2556 {
2557         struct drm_radeon_private *dev_priv = dev->dev_private;
2558
2559         *npipes = dev_priv->r600_npipes;
2560         *nbanks = dev_priv->r600_nbanks;
2561         *group_size = dev_priv->r600_group_size;
2562 }