drm/radeon/kms: cleanup - remove radeon_share.h
[linux-2.6.git] / drivers / gpu / drm / radeon / r600.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/seq_file.h>
29 #include <linux/firmware.h>
30 #include <linux/platform_device.h>
31 #include "drmP.h"
32 #include "radeon_drm.h"
33 #include "radeon.h"
34 #include "radeon_mode.h"
35 #include "r600d.h"
36 #include "avivod.h"
37 #include "atom.h"
38
39 #define PFP_UCODE_SIZE 576
40 #define PM4_UCODE_SIZE 1792
41 #define R700_PFP_UCODE_SIZE 848
42 #define R700_PM4_UCODE_SIZE 1360
43
44 /* Firmware Names */
45 MODULE_FIRMWARE("radeon/R600_pfp.bin");
46 MODULE_FIRMWARE("radeon/R600_me.bin");
47 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
48 MODULE_FIRMWARE("radeon/RV610_me.bin");
49 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
50 MODULE_FIRMWARE("radeon/RV630_me.bin");
51 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
52 MODULE_FIRMWARE("radeon/RV620_me.bin");
53 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
54 MODULE_FIRMWARE("radeon/RV635_me.bin");
55 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
56 MODULE_FIRMWARE("radeon/RV670_me.bin");
57 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
58 MODULE_FIRMWARE("radeon/RS780_me.bin");
59 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
60 MODULE_FIRMWARE("radeon/RV770_me.bin");
61 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
62 MODULE_FIRMWARE("radeon/RV730_me.bin");
63 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
64 MODULE_FIRMWARE("radeon/RV710_me.bin");
65
66 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
67
68 /* This files gather functions specifics to:
69  * r600,rv610,rv630,rv620,rv635,rv670
70  *
71  * Some of these functions might be used by newer ASICs.
72  */
73 int r600_mc_wait_for_idle(struct radeon_device *rdev);
74 void r600_gpu_init(struct radeon_device *rdev);
75 void r600_fini(struct radeon_device *rdev);
76
77
78 /*
79  * R600 PCIE GART
80  */
81 int r600_gart_clear_page(struct radeon_device *rdev, int i)
82 {
83         void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
84         u64 pte;
85
86         if (i < 0 || i > rdev->gart.num_gpu_pages)
87                 return -EINVAL;
88         pte = 0;
89         writeq(pte, ((void __iomem *)ptr) + (i * 8));
90         return 0;
91 }
92
93 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
94 {
95         unsigned i;
96         u32 tmp;
97
98         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
99         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
100         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
101         for (i = 0; i < rdev->usec_timeout; i++) {
102                 /* read MC_STATUS */
103                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
104                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
105                 if (tmp == 2) {
106                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
107                         return;
108                 }
109                 if (tmp) {
110                         return;
111                 }
112                 udelay(1);
113         }
114 }
115
116 int r600_pcie_gart_enable(struct radeon_device *rdev)
117 {
118         u32 tmp;
119         int r, i;
120
121         /* Initialize common gart structure */
122         r = radeon_gart_init(rdev);
123         if (r) {
124                 return r;
125         }
126         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
127         r = radeon_gart_table_vram_alloc(rdev);
128         if (r) {
129                 return r;
130         }
131         for (i = 0; i < rdev->gart.num_gpu_pages; i++)
132                 r600_gart_clear_page(rdev, i);
133         /* Setup L2 cache */
134         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
135                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
136                                 EFFECTIVE_L2_QUEUE_SIZE(7));
137         WREG32(VM_L2_CNTL2, 0);
138         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
139         /* Setup TLB control */
140         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
141                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
142                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
143                 ENABLE_WAIT_L2_QUERY;
144         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
145         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
146         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
147         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
148         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
149         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
150         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
151         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
152         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
153         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
154         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
155         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
156         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
157         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
158         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
159         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, (rdev->mc.gtt_end - 1) >> 12);
160         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
161         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
162                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
163         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
164                         (u32)(rdev->dummy_page.addr >> 12));
165         for (i = 1; i < 7; i++)
166                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
167
168         r600_pcie_gart_tlb_flush(rdev);
169         rdev->gart.ready = true;
170         return 0;
171 }
172
173 void r600_pcie_gart_disable(struct radeon_device *rdev)
174 {
175         u32 tmp;
176         int i;
177
178         /* Clear ptes*/
179         for (i = 0; i < rdev->gart.num_gpu_pages; i++)
180                 r600_gart_clear_page(rdev, i);
181         r600_pcie_gart_tlb_flush(rdev);
182         /* Disable all tables */
183         for (i = 0; i < 7; i++)
184                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
185
186         /* Disable L2 cache */
187         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
188                                 EFFECTIVE_L2_QUEUE_SIZE(7));
189         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
190         /* Setup L1 TLB control */
191         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
192                 ENABLE_WAIT_L2_QUERY;
193         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
194         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
195         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
196         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
197         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
198         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
199         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
200         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
201         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
202         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
203         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
204         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
205         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
206         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
207 }
208
209 int r600_mc_wait_for_idle(struct radeon_device *rdev)
210 {
211         unsigned i;
212         u32 tmp;
213
214         for (i = 0; i < rdev->usec_timeout; i++) {
215                 /* read MC_STATUS */
216                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
217                 if (!tmp)
218                         return 0;
219                 udelay(1);
220         }
221         return -1;
222 }
223
224 static void r600_mc_resume(struct radeon_device *rdev)
225 {
226         u32 d1vga_control, d2vga_control;
227         u32 vga_render_control, vga_hdp_control;
228         u32 d1crtc_control, d2crtc_control;
229         u32 new_d1grph_primary, new_d1grph_secondary;
230         u32 new_d2grph_primary, new_d2grph_secondary;
231         u64 old_vram_start;
232         u32 tmp;
233         int i, j;
234
235         /* Initialize HDP */
236         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
237                 WREG32((0x2c14 + j), 0x00000000);
238                 WREG32((0x2c18 + j), 0x00000000);
239                 WREG32((0x2c1c + j), 0x00000000);
240                 WREG32((0x2c20 + j), 0x00000000);
241                 WREG32((0x2c24 + j), 0x00000000);
242         }
243         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
244
245         d1vga_control = RREG32(D1VGA_CONTROL);
246         d2vga_control = RREG32(D2VGA_CONTROL);
247         vga_render_control = RREG32(VGA_RENDER_CONTROL);
248         vga_hdp_control = RREG32(VGA_HDP_CONTROL);
249         d1crtc_control = RREG32(D1CRTC_CONTROL);
250         d2crtc_control = RREG32(D2CRTC_CONTROL);
251         old_vram_start = (u64)(RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
252         new_d1grph_primary = RREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS);
253         new_d1grph_secondary = RREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS);
254         new_d1grph_primary += rdev->mc.vram_start - old_vram_start;
255         new_d1grph_secondary += rdev->mc.vram_start - old_vram_start;
256         new_d2grph_primary = RREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS);
257         new_d2grph_secondary = RREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS);
258         new_d2grph_primary += rdev->mc.vram_start - old_vram_start;
259         new_d2grph_secondary += rdev->mc.vram_start - old_vram_start;
260
261         /* Stop all video */
262         WREG32(D1VGA_CONTROL, 0);
263         WREG32(D2VGA_CONTROL, 0);
264         WREG32(VGA_RENDER_CONTROL, 0);
265         WREG32(D1CRTC_UPDATE_LOCK, 1);
266         WREG32(D2CRTC_UPDATE_LOCK, 1);
267         WREG32(D1CRTC_CONTROL, 0);
268         WREG32(D2CRTC_CONTROL, 0);
269         WREG32(D1CRTC_UPDATE_LOCK, 0);
270         WREG32(D2CRTC_UPDATE_LOCK, 0);
271
272         mdelay(1);
273         if (r600_mc_wait_for_idle(rdev)) {
274                 printk(KERN_WARNING "[drm] MC not idle !\n");
275         }
276
277         /* Lockout access through VGA aperture*/
278         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
279
280         /* Update configuration */
281         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
282         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (rdev->mc.vram_end - 1) >> 12);
283         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
284         tmp = (((rdev->mc.vram_end - 1) >> 24) & 0xFFFF) << 16;
285         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
286         WREG32(MC_VM_FB_LOCATION, tmp);
287         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
288         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
289         WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);
290         if (rdev->flags & RADEON_IS_AGP) {
291                 WREG32(MC_VM_AGP_TOP, (rdev->mc.gtt_end - 1) >> 16);
292                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
293                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
294         } else {
295                 WREG32(MC_VM_AGP_BASE, 0);
296                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
297                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
298         }
299         WREG32(D1GRPH_PRIMARY_SURFACE_ADDRESS, new_d1grph_primary);
300         WREG32(D1GRPH_SECONDARY_SURFACE_ADDRESS, new_d1grph_secondary);
301         WREG32(D2GRPH_PRIMARY_SURFACE_ADDRESS, new_d2grph_primary);
302         WREG32(D2GRPH_SECONDARY_SURFACE_ADDRESS, new_d2grph_secondary);
303         WREG32(VGA_MEMORY_BASE_ADDRESS, rdev->mc.vram_start);
304
305         /* Unlock host access */
306         WREG32(VGA_HDP_CONTROL, vga_hdp_control);
307
308         mdelay(1);
309         if (r600_mc_wait_for_idle(rdev)) {
310                 printk(KERN_WARNING "[drm] MC not idle !\n");
311         }
312
313         /* Restore video state */
314         WREG32(D1CRTC_UPDATE_LOCK, 1);
315         WREG32(D2CRTC_UPDATE_LOCK, 1);
316         WREG32(D1CRTC_CONTROL, d1crtc_control);
317         WREG32(D2CRTC_CONTROL, d2crtc_control);
318         WREG32(D1CRTC_UPDATE_LOCK, 0);
319         WREG32(D2CRTC_UPDATE_LOCK, 0);
320         WREG32(D1VGA_CONTROL, d1vga_control);
321         WREG32(D2VGA_CONTROL, d2vga_control);
322         WREG32(VGA_RENDER_CONTROL, vga_render_control);
323 }
324
325 int r600_mc_init(struct radeon_device *rdev)
326 {
327         fixed20_12 a;
328         u32 tmp;
329         int chansize;
330         int r;
331
332         /* Get VRAM informations */
333         rdev->mc.vram_width = 128;
334         rdev->mc.vram_is_ddr = true;
335         tmp = RREG32(RAMCFG);
336         if (tmp & CHANSIZE_OVERRIDE) {
337                 chansize = 16;
338         } else if (tmp & CHANSIZE_MASK) {
339                 chansize = 64;
340         } else {
341                 chansize = 32;
342         }
343         if (rdev->family == CHIP_R600) {
344                 rdev->mc.vram_width = 8 * chansize;
345         } else if (rdev->family == CHIP_RV670) {
346                 rdev->mc.vram_width = 4 * chansize;
347         } else if ((rdev->family == CHIP_RV610) ||
348                         (rdev->family == CHIP_RV620)) {
349                 rdev->mc.vram_width = chansize;
350         } else if ((rdev->family == CHIP_RV630) ||
351                         (rdev->family == CHIP_RV635)) {
352                 rdev->mc.vram_width = 2 * chansize;
353         }
354         /* Could aper size report 0 ? */
355         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
356         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
357         /* Setup GPU memory space */
358         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
359         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
360         if (rdev->flags & RADEON_IS_AGP) {
361                 r = radeon_agp_init(rdev);
362                 if (r)
363                         return r;
364                 /* gtt_size is setup by radeon_agp_init */
365                 rdev->mc.gtt_location = rdev->mc.agp_base;
366                 tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size;
367                 /* Try to put vram before or after AGP because we
368                  * we want SYSTEM_APERTURE to cover both VRAM and
369                  * AGP so that GPU can catch out of VRAM/AGP access
370                  */
371                 if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) {
372                         /* Enought place before */
373                         rdev->mc.vram_location = rdev->mc.gtt_location -
374                                                         rdev->mc.mc_vram_size;
375                 } else if (tmp > rdev->mc.mc_vram_size) {
376                         /* Enought place after */
377                         rdev->mc.vram_location = rdev->mc.gtt_location +
378                                                         rdev->mc.gtt_size;
379                 } else {
380                         /* Try to setup VRAM then AGP might not
381                          * not work on some card
382                          */
383                         rdev->mc.vram_location = 0x00000000UL;
384                         rdev->mc.gtt_location = rdev->mc.mc_vram_size;
385                 }
386         } else {
387                 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
388                         rdev->mc.vram_location = (RREG32(MC_VM_FB_LOCATION) &
389                                                                 0xFFFF) << 24;
390                         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
391                         tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
392                         if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
393                                 /* Enough place after vram */
394                                 rdev->mc.gtt_location = tmp;
395                         } else if (rdev->mc.vram_location >= rdev->mc.gtt_size) {
396                                 /* Enough place before vram */
397                                 rdev->mc.gtt_location = 0;
398                         } else {
399                                 /* Not enough place after or before shrink
400                                  * gart size
401                                  */
402                                 if (rdev->mc.vram_location > (0xFFFFFFFFUL - tmp)) {
403                                         rdev->mc.gtt_location = 0;
404                                         rdev->mc.gtt_size = rdev->mc.vram_location;
405                                 } else {
406                                         rdev->mc.gtt_location = tmp;
407                                         rdev->mc.gtt_size = 0xFFFFFFFFUL - tmp;
408                                 }
409                         }
410                         rdev->mc.gtt_location = rdev->mc.mc_vram_size;
411                 } else {
412                         rdev->mc.vram_location = 0x00000000UL;
413                         rdev->mc.gtt_location = rdev->mc.mc_vram_size;
414                         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
415                 }
416         }
417         rdev->mc.vram_start = rdev->mc.vram_location;
418         rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size;
419         rdev->mc.gtt_start = rdev->mc.gtt_location;
420         rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size;
421         /* FIXME: we should enforce default clock in case GPU is not in
422          * default setup
423          */
424         a.full = rfixed_const(100);
425         rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
426         rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
427         return 0;
428 }
429
430 /* We doesn't check that the GPU really needs a reset we simply do the
431  * reset, it's up to the caller to determine if the GPU needs one. We
432  * might add an helper function to check that.
433  */
434 int r600_gpu_soft_reset(struct radeon_device *rdev)
435 {
436         u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
437                                 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
438                                 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
439                                 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
440                                 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
441                                 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
442                                 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
443                                 S_008010_GUI_ACTIVE(1);
444         u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
445                         S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
446                         S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
447                         S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
448                         S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
449                         S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
450                         S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
451                         S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
452         u32 srbm_reset = 0;
453
454         /* Disable CP parsing/prefetching */
455         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(0xff));
456         /* Check if any of the rendering block is busy and reset it */
457         if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
458             (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
459                 WREG32(R_008020_GRBM_SOFT_RESET, S_008020_SOFT_RESET_CR(1) |
460                         S_008020_SOFT_RESET_DB(1) |
461                         S_008020_SOFT_RESET_CB(1) |
462                         S_008020_SOFT_RESET_PA(1) |
463                         S_008020_SOFT_RESET_SC(1) |
464                         S_008020_SOFT_RESET_SMX(1) |
465                         S_008020_SOFT_RESET_SPI(1) |
466                         S_008020_SOFT_RESET_SX(1) |
467                         S_008020_SOFT_RESET_SH(1) |
468                         S_008020_SOFT_RESET_TC(1) |
469                         S_008020_SOFT_RESET_TA(1) |
470                         S_008020_SOFT_RESET_VC(1) |
471                         S_008020_SOFT_RESET_VGT(1));
472                 (void)RREG32(R_008020_GRBM_SOFT_RESET);
473                 udelay(50);
474                 WREG32(R_008020_GRBM_SOFT_RESET, 0);
475                 (void)RREG32(R_008020_GRBM_SOFT_RESET);
476         }
477         /* Reset CP (we always reset CP) */
478         WREG32(R_008020_GRBM_SOFT_RESET, S_008020_SOFT_RESET_CP(1));
479         (void)RREG32(R_008020_GRBM_SOFT_RESET);
480         udelay(50);
481         WREG32(R_008020_GRBM_SOFT_RESET, 0);
482         (void)RREG32(R_008020_GRBM_SOFT_RESET);
483         /* Reset others GPU block if necessary */
484         if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
485                 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
486         if (G_000E50_GRBM_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
487                 srbm_reset |= S_000E60_SOFT_RESET_GRBM(1);
488         if (G_000E50_HI_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
489                 srbm_reset |= S_000E60_SOFT_RESET_IH(1);
490         if (G_000E50_VMC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
491                 srbm_reset |= S_000E60_SOFT_RESET_VMC(1);
492         if (G_000E50_MCB_BUSY(RREG32(R_000E50_SRBM_STATUS)))
493                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
494         if (G_000E50_MCDZ_BUSY(RREG32(R_000E50_SRBM_STATUS)))
495                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
496         if (G_000E50_MCDY_BUSY(RREG32(R_000E50_SRBM_STATUS)))
497                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
498         if (G_000E50_MCDX_BUSY(RREG32(R_000E50_SRBM_STATUS)))
499                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
500         if (G_000E50_MCDW_BUSY(RREG32(R_000E50_SRBM_STATUS)))
501                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
502         if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
503                 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
504         if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS)))
505                 srbm_reset |= S_000E60_SOFT_RESET_SEM(1);
506         WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
507         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
508         udelay(50);
509         WREG32(R_000E60_SRBM_SOFT_RESET, 0);
510         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
511         /* Wait a little for things to settle down */
512         udelay(50);
513         return 0;
514 }
515
516 int r600_gpu_reset(struct radeon_device *rdev)
517 {
518         return r600_gpu_soft_reset(rdev);
519 }
520
521 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
522                                              u32 num_backends,
523                                              u32 backend_disable_mask)
524 {
525         u32 backend_map = 0;
526         u32 enabled_backends_mask;
527         u32 enabled_backends_count;
528         u32 cur_pipe;
529         u32 swizzle_pipe[R6XX_MAX_PIPES];
530         u32 cur_backend;
531         u32 i;
532
533         if (num_tile_pipes > R6XX_MAX_PIPES)
534                 num_tile_pipes = R6XX_MAX_PIPES;
535         if (num_tile_pipes < 1)
536                 num_tile_pipes = 1;
537         if (num_backends > R6XX_MAX_BACKENDS)
538                 num_backends = R6XX_MAX_BACKENDS;
539         if (num_backends < 1)
540                 num_backends = 1;
541
542         enabled_backends_mask = 0;
543         enabled_backends_count = 0;
544         for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
545                 if (((backend_disable_mask >> i) & 1) == 0) {
546                         enabled_backends_mask |= (1 << i);
547                         ++enabled_backends_count;
548                 }
549                 if (enabled_backends_count == num_backends)
550                         break;
551         }
552
553         if (enabled_backends_count == 0) {
554                 enabled_backends_mask = 1;
555                 enabled_backends_count = 1;
556         }
557
558         if (enabled_backends_count != num_backends)
559                 num_backends = enabled_backends_count;
560
561         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
562         switch (num_tile_pipes) {
563         case 1:
564                 swizzle_pipe[0] = 0;
565                 break;
566         case 2:
567                 swizzle_pipe[0] = 0;
568                 swizzle_pipe[1] = 1;
569                 break;
570         case 3:
571                 swizzle_pipe[0] = 0;
572                 swizzle_pipe[1] = 1;
573                 swizzle_pipe[2] = 2;
574                 break;
575         case 4:
576                 swizzle_pipe[0] = 0;
577                 swizzle_pipe[1] = 1;
578                 swizzle_pipe[2] = 2;
579                 swizzle_pipe[3] = 3;
580                 break;
581         case 5:
582                 swizzle_pipe[0] = 0;
583                 swizzle_pipe[1] = 1;
584                 swizzle_pipe[2] = 2;
585                 swizzle_pipe[3] = 3;
586                 swizzle_pipe[4] = 4;
587                 break;
588         case 6:
589                 swizzle_pipe[0] = 0;
590                 swizzle_pipe[1] = 2;
591                 swizzle_pipe[2] = 4;
592                 swizzle_pipe[3] = 5;
593                 swizzle_pipe[4] = 1;
594                 swizzle_pipe[5] = 3;
595                 break;
596         case 7:
597                 swizzle_pipe[0] = 0;
598                 swizzle_pipe[1] = 2;
599                 swizzle_pipe[2] = 4;
600                 swizzle_pipe[3] = 6;
601                 swizzle_pipe[4] = 1;
602                 swizzle_pipe[5] = 3;
603                 swizzle_pipe[6] = 5;
604                 break;
605         case 8:
606                 swizzle_pipe[0] = 0;
607                 swizzle_pipe[1] = 2;
608                 swizzle_pipe[2] = 4;
609                 swizzle_pipe[3] = 6;
610                 swizzle_pipe[4] = 1;
611                 swizzle_pipe[5] = 3;
612                 swizzle_pipe[6] = 5;
613                 swizzle_pipe[7] = 7;
614                 break;
615         }
616
617         cur_backend = 0;
618         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
619                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
620                         cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
621
622                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
623
624                 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
625         }
626
627         return backend_map;
628 }
629
630 int r600_count_pipe_bits(uint32_t val)
631 {
632         int i, ret = 0;
633
634         for (i = 0; i < 32; i++) {
635                 ret += val & 1;
636                 val >>= 1;
637         }
638         return ret;
639 }
640
641 void r600_gpu_init(struct radeon_device *rdev)
642 {
643         u32 tiling_config;
644         u32 ramcfg;
645         u32 tmp;
646         int i, j;
647         u32 sq_config;
648         u32 sq_gpr_resource_mgmt_1 = 0;
649         u32 sq_gpr_resource_mgmt_2 = 0;
650         u32 sq_thread_resource_mgmt = 0;
651         u32 sq_stack_resource_mgmt_1 = 0;
652         u32 sq_stack_resource_mgmt_2 = 0;
653
654         /* FIXME: implement */
655         switch (rdev->family) {
656         case CHIP_R600:
657                 rdev->config.r600.max_pipes = 4;
658                 rdev->config.r600.max_tile_pipes = 8;
659                 rdev->config.r600.max_simds = 4;
660                 rdev->config.r600.max_backends = 4;
661                 rdev->config.r600.max_gprs = 256;
662                 rdev->config.r600.max_threads = 192;
663                 rdev->config.r600.max_stack_entries = 256;
664                 rdev->config.r600.max_hw_contexts = 8;
665                 rdev->config.r600.max_gs_threads = 16;
666                 rdev->config.r600.sx_max_export_size = 128;
667                 rdev->config.r600.sx_max_export_pos_size = 16;
668                 rdev->config.r600.sx_max_export_smx_size = 128;
669                 rdev->config.r600.sq_num_cf_insts = 2;
670                 break;
671         case CHIP_RV630:
672         case CHIP_RV635:
673                 rdev->config.r600.max_pipes = 2;
674                 rdev->config.r600.max_tile_pipes = 2;
675                 rdev->config.r600.max_simds = 3;
676                 rdev->config.r600.max_backends = 1;
677                 rdev->config.r600.max_gprs = 128;
678                 rdev->config.r600.max_threads = 192;
679                 rdev->config.r600.max_stack_entries = 128;
680                 rdev->config.r600.max_hw_contexts = 8;
681                 rdev->config.r600.max_gs_threads = 4;
682                 rdev->config.r600.sx_max_export_size = 128;
683                 rdev->config.r600.sx_max_export_pos_size = 16;
684                 rdev->config.r600.sx_max_export_smx_size = 128;
685                 rdev->config.r600.sq_num_cf_insts = 2;
686                 break;
687         case CHIP_RV610:
688         case CHIP_RV620:
689         case CHIP_RS780:
690         case CHIP_RS880:
691                 rdev->config.r600.max_pipes = 1;
692                 rdev->config.r600.max_tile_pipes = 1;
693                 rdev->config.r600.max_simds = 2;
694                 rdev->config.r600.max_backends = 1;
695                 rdev->config.r600.max_gprs = 128;
696                 rdev->config.r600.max_threads = 192;
697                 rdev->config.r600.max_stack_entries = 128;
698                 rdev->config.r600.max_hw_contexts = 4;
699                 rdev->config.r600.max_gs_threads = 4;
700                 rdev->config.r600.sx_max_export_size = 128;
701                 rdev->config.r600.sx_max_export_pos_size = 16;
702                 rdev->config.r600.sx_max_export_smx_size = 128;
703                 rdev->config.r600.sq_num_cf_insts = 1;
704                 break;
705         case CHIP_RV670:
706                 rdev->config.r600.max_pipes = 4;
707                 rdev->config.r600.max_tile_pipes = 4;
708                 rdev->config.r600.max_simds = 4;
709                 rdev->config.r600.max_backends = 4;
710                 rdev->config.r600.max_gprs = 192;
711                 rdev->config.r600.max_threads = 192;
712                 rdev->config.r600.max_stack_entries = 256;
713                 rdev->config.r600.max_hw_contexts = 8;
714                 rdev->config.r600.max_gs_threads = 16;
715                 rdev->config.r600.sx_max_export_size = 128;
716                 rdev->config.r600.sx_max_export_pos_size = 16;
717                 rdev->config.r600.sx_max_export_smx_size = 128;
718                 rdev->config.r600.sq_num_cf_insts = 2;
719                 break;
720         default:
721                 break;
722         }
723
724         /* Initialize HDP */
725         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
726                 WREG32((0x2c14 + j), 0x00000000);
727                 WREG32((0x2c18 + j), 0x00000000);
728                 WREG32((0x2c1c + j), 0x00000000);
729                 WREG32((0x2c20 + j), 0x00000000);
730                 WREG32((0x2c24 + j), 0x00000000);
731         }
732
733         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
734
735         /* Setup tiling */
736         tiling_config = 0;
737         ramcfg = RREG32(RAMCFG);
738         switch (rdev->config.r600.max_tile_pipes) {
739         case 1:
740                 tiling_config |= PIPE_TILING(0);
741                 break;
742         case 2:
743                 tiling_config |= PIPE_TILING(1);
744                 break;
745         case 4:
746                 tiling_config |= PIPE_TILING(2);
747                 break;
748         case 8:
749                 tiling_config |= PIPE_TILING(3);
750                 break;
751         default:
752                 break;
753         }
754         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
755         tiling_config |= GROUP_SIZE(0);
756         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
757         if (tmp > 3) {
758                 tiling_config |= ROW_TILING(3);
759                 tiling_config |= SAMPLE_SPLIT(3);
760         } else {
761                 tiling_config |= ROW_TILING(tmp);
762                 tiling_config |= SAMPLE_SPLIT(tmp);
763         }
764         tiling_config |= BANK_SWAPS(1);
765         tmp = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
766                                                 rdev->config.r600.max_backends,
767                                                 (0xff << rdev->config.r600.max_backends) & 0xff);
768         tiling_config |= BACKEND_MAP(tmp);
769         WREG32(GB_TILING_CONFIG, tiling_config);
770         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
771         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
772
773         tmp = BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
774         WREG32(CC_RB_BACKEND_DISABLE, tmp);
775
776         /* Setup pipes */
777         tmp = INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
778         tmp |= INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
779         WREG32(CC_GC_SHADER_PIPE_CONFIG, tmp);
780         WREG32(GC_USER_SHADER_PIPE_CONFIG, tmp);
781
782         tmp = R6XX_MAX_BACKENDS - r600_count_pipe_bits(tmp & INACTIVE_QD_PIPES_MASK);
783         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
784         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
785
786         /* Setup some CP states */
787         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
788         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
789
790         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
791                              SYNC_WALKER | SYNC_ALIGNER));
792         /* Setup various GPU states */
793         if (rdev->family == CHIP_RV670)
794                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
795
796         tmp = RREG32(SX_DEBUG_1);
797         tmp |= SMX_EVENT_RELEASE;
798         if ((rdev->family > CHIP_R600))
799                 tmp |= ENABLE_NEW_SMX_ADDRESS;
800         WREG32(SX_DEBUG_1, tmp);
801
802         if (((rdev->family) == CHIP_R600) ||
803             ((rdev->family) == CHIP_RV630) ||
804             ((rdev->family) == CHIP_RV610) ||
805             ((rdev->family) == CHIP_RV620) ||
806             ((rdev->family) == CHIP_RS780)) {
807                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
808         } else {
809                 WREG32(DB_DEBUG, 0);
810         }
811         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
812                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
813
814         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
815         WREG32(VGT_NUM_INSTANCES, 0);
816
817         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
818         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
819
820         tmp = RREG32(SQ_MS_FIFO_SIZES);
821         if (((rdev->family) == CHIP_RV610) ||
822             ((rdev->family) == CHIP_RV620) ||
823             ((rdev->family) == CHIP_RS780)) {
824                 tmp = (CACHE_FIFO_SIZE(0xa) |
825                        FETCH_FIFO_HIWATER(0xa) |
826                        DONE_FIFO_HIWATER(0xe0) |
827                        ALU_UPDATE_FIFO_HIWATER(0x8));
828         } else if (((rdev->family) == CHIP_R600) ||
829                    ((rdev->family) == CHIP_RV630)) {
830                 tmp &= ~DONE_FIFO_HIWATER(0xff);
831                 tmp |= DONE_FIFO_HIWATER(0x4);
832         }
833         WREG32(SQ_MS_FIFO_SIZES, tmp);
834
835         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
836          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
837          */
838         sq_config = RREG32(SQ_CONFIG);
839         sq_config &= ~(PS_PRIO(3) |
840                        VS_PRIO(3) |
841                        GS_PRIO(3) |
842                        ES_PRIO(3));
843         sq_config |= (DX9_CONSTS |
844                       VC_ENABLE |
845                       PS_PRIO(0) |
846                       VS_PRIO(1) |
847                       GS_PRIO(2) |
848                       ES_PRIO(3));
849
850         if ((rdev->family) == CHIP_R600) {
851                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
852                                           NUM_VS_GPRS(124) |
853                                           NUM_CLAUSE_TEMP_GPRS(4));
854                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
855                                           NUM_ES_GPRS(0));
856                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
857                                            NUM_VS_THREADS(48) |
858                                            NUM_GS_THREADS(4) |
859                                            NUM_ES_THREADS(4));
860                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
861                                             NUM_VS_STACK_ENTRIES(128));
862                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
863                                             NUM_ES_STACK_ENTRIES(0));
864         } else if (((rdev->family) == CHIP_RV610) ||
865                    ((rdev->family) == CHIP_RV620) ||
866                    ((rdev->family) == CHIP_RS780)) {
867                 /* no vertex cache */
868                 sq_config &= ~VC_ENABLE;
869
870                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
871                                           NUM_VS_GPRS(44) |
872                                           NUM_CLAUSE_TEMP_GPRS(2));
873                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
874                                           NUM_ES_GPRS(17));
875                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
876                                            NUM_VS_THREADS(78) |
877                                            NUM_GS_THREADS(4) |
878                                            NUM_ES_THREADS(31));
879                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
880                                             NUM_VS_STACK_ENTRIES(40));
881                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
882                                             NUM_ES_STACK_ENTRIES(16));
883         } else if (((rdev->family) == CHIP_RV630) ||
884                    ((rdev->family) == CHIP_RV635)) {
885                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
886                                           NUM_VS_GPRS(44) |
887                                           NUM_CLAUSE_TEMP_GPRS(2));
888                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
889                                           NUM_ES_GPRS(18));
890                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
891                                            NUM_VS_THREADS(78) |
892                                            NUM_GS_THREADS(4) |
893                                            NUM_ES_THREADS(31));
894                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
895                                             NUM_VS_STACK_ENTRIES(40));
896                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
897                                             NUM_ES_STACK_ENTRIES(16));
898         } else if ((rdev->family) == CHIP_RV670) {
899                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
900                                           NUM_VS_GPRS(44) |
901                                           NUM_CLAUSE_TEMP_GPRS(2));
902                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
903                                           NUM_ES_GPRS(17));
904                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
905                                            NUM_VS_THREADS(78) |
906                                            NUM_GS_THREADS(4) |
907                                            NUM_ES_THREADS(31));
908                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
909                                             NUM_VS_STACK_ENTRIES(64));
910                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
911                                             NUM_ES_STACK_ENTRIES(64));
912         }
913
914         WREG32(SQ_CONFIG, sq_config);
915         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
916         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
917         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
918         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
919         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
920
921         if (((rdev->family) == CHIP_RV610) ||
922             ((rdev->family) == CHIP_RV620) ||
923             ((rdev->family) == CHIP_RS780)) {
924                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
925         } else {
926                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
927         }
928
929         /* More default values. 2D/3D driver should adjust as needed */
930         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
931                                          S1_X(0x4) | S1_Y(0xc)));
932         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
933                                          S1_X(0x2) | S1_Y(0x2) |
934                                          S2_X(0xa) | S2_Y(0x6) |
935                                          S3_X(0x6) | S3_Y(0xa)));
936         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
937                                              S1_X(0x4) | S1_Y(0xc) |
938                                              S2_X(0x1) | S2_Y(0x6) |
939                                              S3_X(0xa) | S3_Y(0xe)));
940         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
941                                              S5_X(0x0) | S5_Y(0x0) |
942                                              S6_X(0xb) | S6_Y(0x4) |
943                                              S7_X(0x7) | S7_Y(0x8)));
944
945         WREG32(VGT_STRMOUT_EN, 0);
946         tmp = rdev->config.r600.max_pipes * 16;
947         switch (rdev->family) {
948         case CHIP_RV610:
949         case CHIP_RS780:
950         case CHIP_RV620:
951                 tmp += 32;
952                 break;
953         case CHIP_RV670:
954                 tmp += 128;
955                 break;
956         default:
957                 break;
958         }
959         if (tmp > 256) {
960                 tmp = 256;
961         }
962         WREG32(VGT_ES_PER_GS, 128);
963         WREG32(VGT_GS_PER_ES, tmp);
964         WREG32(VGT_GS_PER_VS, 2);
965         WREG32(VGT_GS_VERTEX_REUSE, 16);
966
967         /* more default values. 2D/3D driver should adjust as needed */
968         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
969         WREG32(VGT_STRMOUT_EN, 0);
970         WREG32(SX_MISC, 0);
971         WREG32(PA_SC_MODE_CNTL, 0);
972         WREG32(PA_SC_AA_CONFIG, 0);
973         WREG32(PA_SC_LINE_STIPPLE, 0);
974         WREG32(SPI_INPUT_Z, 0);
975         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
976         WREG32(CB_COLOR7_FRAG, 0);
977
978         /* Clear render buffer base addresses */
979         WREG32(CB_COLOR0_BASE, 0);
980         WREG32(CB_COLOR1_BASE, 0);
981         WREG32(CB_COLOR2_BASE, 0);
982         WREG32(CB_COLOR3_BASE, 0);
983         WREG32(CB_COLOR4_BASE, 0);
984         WREG32(CB_COLOR5_BASE, 0);
985         WREG32(CB_COLOR6_BASE, 0);
986         WREG32(CB_COLOR7_BASE, 0);
987         WREG32(CB_COLOR7_FRAG, 0);
988
989         switch (rdev->family) {
990         case CHIP_RV610:
991         case CHIP_RS780:
992         case CHIP_RV620:
993                 tmp = TC_L2_SIZE(8);
994                 break;
995         case CHIP_RV630:
996         case CHIP_RV635:
997                 tmp = TC_L2_SIZE(4);
998                 break;
999         case CHIP_R600:
1000                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1001                 break;
1002         default:
1003                 tmp = TC_L2_SIZE(0);
1004                 break;
1005         }
1006         WREG32(TC_CNTL, tmp);
1007
1008         tmp = RREG32(HDP_HOST_PATH_CNTL);
1009         WREG32(HDP_HOST_PATH_CNTL, tmp);
1010
1011         tmp = RREG32(ARB_POP);
1012         tmp |= ENABLE_TC128;
1013         WREG32(ARB_POP, tmp);
1014
1015         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1016         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1017                                NUM_CLIP_SEQ(3)));
1018         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1019 }
1020
1021
1022 /*
1023  * Indirect registers accessor
1024  */
1025 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1026 {
1027         u32 r;
1028
1029         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1030         (void)RREG32(PCIE_PORT_INDEX);
1031         r = RREG32(PCIE_PORT_DATA);
1032         return r;
1033 }
1034
1035 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1036 {
1037         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1038         (void)RREG32(PCIE_PORT_INDEX);
1039         WREG32(PCIE_PORT_DATA, (v));
1040         (void)RREG32(PCIE_PORT_DATA);
1041 }
1042
1043
1044 /*
1045  * CP & Ring
1046  */
1047 void r600_cp_stop(struct radeon_device *rdev)
1048 {
1049         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1050 }
1051
1052 int r600_cp_init_microcode(struct radeon_device *rdev)
1053 {
1054         struct platform_device *pdev;
1055         const char *chip_name;
1056         size_t pfp_req_size, me_req_size;
1057         char fw_name[30];
1058         int err;
1059
1060         DRM_DEBUG("\n");
1061
1062         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1063         err = IS_ERR(pdev);
1064         if (err) {
1065                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1066                 return -EINVAL;
1067         }
1068
1069         switch (rdev->family) {
1070         case CHIP_R600: chip_name = "R600"; break;
1071         case CHIP_RV610: chip_name = "RV610"; break;
1072         case CHIP_RV630: chip_name = "RV630"; break;
1073         case CHIP_RV620: chip_name = "RV620"; break;
1074         case CHIP_RV635: chip_name = "RV635"; break;
1075         case CHIP_RV670: chip_name = "RV670"; break;
1076         case CHIP_RS780:
1077         case CHIP_RS880: chip_name = "RS780"; break;
1078         case CHIP_RV770: chip_name = "RV770"; break;
1079         case CHIP_RV730:
1080         case CHIP_RV740: chip_name = "RV730"; break;
1081         case CHIP_RV710: chip_name = "RV710"; break;
1082         default: BUG();
1083         }
1084
1085         if (rdev->family >= CHIP_RV770) {
1086                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1087                 me_req_size = R700_PM4_UCODE_SIZE * 4;
1088         } else {
1089                 pfp_req_size = PFP_UCODE_SIZE * 4;
1090                 me_req_size = PM4_UCODE_SIZE * 12;
1091         }
1092
1093         DRM_INFO("Loading %s CP Microcode\n", chip_name);
1094
1095         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1096         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
1097         if (err)
1098                 goto out;
1099         if (rdev->pfp_fw->size != pfp_req_size) {
1100                 printk(KERN_ERR
1101                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1102                        rdev->pfp_fw->size, fw_name);
1103                 err = -EINVAL;
1104                 goto out;
1105         }
1106
1107         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1108         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1109         if (err)
1110                 goto out;
1111         if (rdev->me_fw->size != me_req_size) {
1112                 printk(KERN_ERR
1113                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1114                        rdev->me_fw->size, fw_name);
1115                 err = -EINVAL;
1116         }
1117 out:
1118         platform_device_unregister(pdev);
1119
1120         if (err) {
1121                 if (err != -EINVAL)
1122                         printk(KERN_ERR
1123                                "r600_cp: Failed to load firmware \"%s\"\n",
1124                                fw_name);
1125                 release_firmware(rdev->pfp_fw);
1126                 rdev->pfp_fw = NULL;
1127                 release_firmware(rdev->me_fw);
1128                 rdev->me_fw = NULL;
1129         }
1130         return err;
1131 }
1132
1133 static int r600_cp_load_microcode(struct radeon_device *rdev)
1134 {
1135         const __be32 *fw_data;
1136         int i;
1137
1138         if (!rdev->me_fw || !rdev->pfp_fw)
1139                 return -EINVAL;
1140
1141         r600_cp_stop(rdev);
1142
1143         WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1144
1145         /* Reset cp */
1146         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1147         RREG32(GRBM_SOFT_RESET);
1148         mdelay(15);
1149         WREG32(GRBM_SOFT_RESET, 0);
1150
1151         WREG32(CP_ME_RAM_WADDR, 0);
1152
1153         fw_data = (const __be32 *)rdev->me_fw->data;
1154         WREG32(CP_ME_RAM_WADDR, 0);
1155         for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
1156                 WREG32(CP_ME_RAM_DATA,
1157                        be32_to_cpup(fw_data++));
1158
1159         fw_data = (const __be32 *)rdev->pfp_fw->data;
1160         WREG32(CP_PFP_UCODE_ADDR, 0);
1161         for (i = 0; i < PFP_UCODE_SIZE; i++)
1162                 WREG32(CP_PFP_UCODE_DATA,
1163                        be32_to_cpup(fw_data++));
1164
1165         WREG32(CP_PFP_UCODE_ADDR, 0);
1166         WREG32(CP_ME_RAM_WADDR, 0);
1167         WREG32(CP_ME_RAM_RADDR, 0);
1168         return 0;
1169 }
1170
1171 int r600_cp_start(struct radeon_device *rdev)
1172 {
1173         int r;
1174         uint32_t cp_me;
1175
1176         r = radeon_ring_lock(rdev, 7);
1177         if (r) {
1178                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1179                 return r;
1180         }
1181         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1182         radeon_ring_write(rdev, 0x1);
1183         if (rdev->family < CHIP_RV770) {
1184                 radeon_ring_write(rdev, 0x3);
1185                 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
1186         } else {
1187                 radeon_ring_write(rdev, 0x0);
1188                 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
1189         }
1190         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1191         radeon_ring_write(rdev, 0);
1192         radeon_ring_write(rdev, 0);
1193         radeon_ring_unlock_commit(rdev);
1194
1195         cp_me = 0xff;
1196         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
1197         return 0;
1198 }
1199
1200 int r600_cp_resume(struct radeon_device *rdev)
1201 {
1202         u32 tmp;
1203         u32 rb_bufsz;
1204         int r;
1205
1206         /* Reset cp */
1207         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1208         RREG32(GRBM_SOFT_RESET);
1209         mdelay(15);
1210         WREG32(GRBM_SOFT_RESET, 0);
1211
1212         /* Set ring buffer size */
1213         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1214 #ifdef __BIG_ENDIAN
1215         WREG32(CP_RB_CNTL, BUF_SWAP_32BIT | RB_NO_UPDATE |
1216                 (drm_order(4096/8) << 8) | rb_bufsz);
1217 #else
1218         WREG32(CP_RB_CNTL, RB_NO_UPDATE | (drm_order(4096/8) << 8) | rb_bufsz);
1219 #endif
1220         WREG32(CP_SEM_WAIT_TIMER, 0x4);
1221
1222         /* Set the write pointer delay */
1223         WREG32(CP_RB_WPTR_DELAY, 0);
1224
1225         /* Initialize the ring buffer's read and write pointers */
1226         tmp = RREG32(CP_RB_CNTL);
1227         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1228         WREG32(CP_RB_RPTR_WR, 0);
1229         WREG32(CP_RB_WPTR, 0);
1230         WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
1231         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
1232         mdelay(1);
1233         WREG32(CP_RB_CNTL, tmp);
1234
1235         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1236         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1237
1238         rdev->cp.rptr = RREG32(CP_RB_RPTR);
1239         rdev->cp.wptr = RREG32(CP_RB_WPTR);
1240
1241         r600_cp_start(rdev);
1242         rdev->cp.ready = true;
1243         r = radeon_ring_test(rdev);
1244         if (r) {
1245                 rdev->cp.ready = false;
1246                 return r;
1247         }
1248         return 0;
1249 }
1250
1251 void r600_cp_commit(struct radeon_device *rdev)
1252 {
1253         WREG32(CP_RB_WPTR, rdev->cp.wptr);
1254         (void)RREG32(CP_RB_WPTR);
1255 }
1256
1257 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
1258 {
1259         u32 rb_bufsz;
1260
1261         /* Align ring size */
1262         rb_bufsz = drm_order(ring_size / 8);
1263         ring_size = (1 << (rb_bufsz + 1)) * 4;
1264         rdev->cp.ring_size = ring_size;
1265         rdev->cp.align_mask = 16 - 1;
1266 }
1267
1268
1269 /*
1270  * GPU scratch registers helpers function.
1271  */
1272 void r600_scratch_init(struct radeon_device *rdev)
1273 {
1274         int i;
1275
1276         rdev->scratch.num_reg = 7;
1277         for (i = 0; i < rdev->scratch.num_reg; i++) {
1278                 rdev->scratch.free[i] = true;
1279                 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
1280         }
1281 }
1282
1283 int r600_ring_test(struct radeon_device *rdev)
1284 {
1285         uint32_t scratch;
1286         uint32_t tmp = 0;
1287         unsigned i;
1288         int r;
1289
1290         r = radeon_scratch_get(rdev, &scratch);
1291         if (r) {
1292                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
1293                 return r;
1294         }
1295         WREG32(scratch, 0xCAFEDEAD);
1296         r = radeon_ring_lock(rdev, 3);
1297         if (r) {
1298                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1299                 radeon_scratch_free(rdev, scratch);
1300                 return r;
1301         }
1302         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1303         radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1304         radeon_ring_write(rdev, 0xDEADBEEF);
1305         radeon_ring_unlock_commit(rdev);
1306         for (i = 0; i < rdev->usec_timeout; i++) {
1307                 tmp = RREG32(scratch);
1308                 if (tmp == 0xDEADBEEF)
1309                         break;
1310                 DRM_UDELAY(1);
1311         }
1312         if (i < rdev->usec_timeout) {
1313                 DRM_INFO("ring test succeeded in %d usecs\n", i);
1314         } else {
1315                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
1316                           scratch, tmp);
1317                 r = -EINVAL;
1318         }
1319         radeon_scratch_free(rdev, scratch);
1320         return r;
1321 }
1322
1323 /*
1324  * Writeback
1325  */
1326 int r600_wb_init(struct radeon_device *rdev)
1327 {
1328         int r;
1329
1330         if (rdev->wb.wb_obj == NULL) {
1331                 r = radeon_object_create(rdev, NULL, 4096,
1332                                          true,
1333                                          RADEON_GEM_DOMAIN_GTT,
1334                                          false, &rdev->wb.wb_obj);
1335                 if (r) {
1336                         DRM_ERROR("radeon: failed to create WB buffer (%d).\n", r);
1337                         return r;
1338                 }
1339                 r = radeon_object_pin(rdev->wb.wb_obj,
1340                                       RADEON_GEM_DOMAIN_GTT,
1341                                       &rdev->wb.gpu_addr);
1342                 if (r) {
1343                         DRM_ERROR("radeon: failed to pin WB buffer (%d).\n", r);
1344                         return r;
1345                 }
1346                 r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
1347                 if (r) {
1348                         DRM_ERROR("radeon: failed to map WB buffer (%d).\n", r);
1349                         return r;
1350                 }
1351         }
1352         WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
1353         WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
1354         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
1355         WREG32(SCRATCH_UMSK, 0xff);
1356         return 0;
1357 }
1358
1359 void r600_wb_fini(struct radeon_device *rdev)
1360 {
1361         if (rdev->wb.wb_obj) {
1362                 radeon_object_kunmap(rdev->wb.wb_obj);
1363                 radeon_object_unpin(rdev->wb.wb_obj);
1364                 radeon_object_unref(&rdev->wb.wb_obj);
1365                 rdev->wb.wb = NULL;
1366                 rdev->wb.wb_obj = NULL;
1367         }
1368 }
1369
1370
1371 /*
1372  * CS
1373  */
1374 void r600_fence_ring_emit(struct radeon_device *rdev,
1375                           struct radeon_fence *fence)
1376 {
1377         /* Emit fence sequence & fire IRQ */
1378         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1379         radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1380         radeon_ring_write(rdev, fence->seq);
1381 }
1382
1383 int r600_copy_dma(struct radeon_device *rdev,
1384                   uint64_t src_offset,
1385                   uint64_t dst_offset,
1386                   unsigned num_pages,
1387                   struct radeon_fence *fence)
1388 {
1389         /* FIXME: implement */
1390         return 0;
1391 }
1392
1393 int r600_copy_blit(struct radeon_device *rdev,
1394                    uint64_t src_offset, uint64_t dst_offset,
1395                    unsigned num_pages, struct radeon_fence *fence)
1396 {
1397         r600_blit_prepare_copy(rdev, num_pages * 4096);
1398         r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * 4096);
1399         r600_blit_done_copy(rdev, fence);
1400         return 0;
1401 }
1402
1403 int r600_irq_process(struct radeon_device *rdev)
1404 {
1405         /* FIXME: implement */
1406         return 0;
1407 }
1408
1409 int r600_irq_set(struct radeon_device *rdev)
1410 {
1411         /* FIXME: implement */
1412         return 0;
1413 }
1414
1415 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
1416                          uint32_t tiling_flags, uint32_t pitch,
1417                          uint32_t offset, uint32_t obj_size)
1418 {
1419         /* FIXME: implement */
1420         return 0;
1421 }
1422
1423 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
1424 {
1425         /* FIXME: implement */
1426 }
1427
1428
1429 bool r600_card_posted(struct radeon_device *rdev)
1430 {
1431         uint32_t reg;
1432
1433         /* first check CRTCs */
1434         reg = RREG32(D1CRTC_CONTROL) |
1435                 RREG32(D2CRTC_CONTROL);
1436         if (reg & CRTC_EN)
1437                 return true;
1438
1439         /* then check MEM_SIZE, in case the crtcs are off */
1440         if (RREG32(CONFIG_MEMSIZE))
1441                 return true;
1442
1443         return false;
1444 }
1445
1446 int r600_resume(struct radeon_device *rdev)
1447 {
1448         int r;
1449
1450         r600_gpu_reset(rdev);
1451         r600_mc_resume(rdev);
1452         r = r600_pcie_gart_enable(rdev);
1453         if (r)
1454                 return r;
1455         r600_gpu_init(rdev);
1456         r = radeon_ring_init(rdev, rdev->cp.ring_size);
1457         if (r)
1458                 return r;
1459         r = r600_cp_load_microcode(rdev);
1460         if (r)
1461                 return r;
1462         r = r600_cp_resume(rdev);
1463         if (r)
1464                 return r;
1465         r = r600_wb_init(rdev);
1466         if (r)
1467                 return r;
1468         return 0;
1469 }
1470
1471 int r600_suspend(struct radeon_device *rdev)
1472 {
1473         /* FIXME: we should wait for ring to be empty */
1474         r600_cp_stop(rdev);
1475         return 0;
1476 }
1477
1478 /* Plan is to move initialization in that function and use
1479  * helper function so that radeon_device_init pretty much
1480  * do nothing more than calling asic specific function. This
1481  * should also allow to remove a bunch of callback function
1482  * like vram_info.
1483  */
1484 int r600_init(struct radeon_device *rdev)
1485 {
1486         int r;
1487
1488         rdev->new_init_path = true;
1489         r = radeon_dummy_page_init(rdev);
1490         if (r)
1491                 return r;
1492         if (r600_debugfs_mc_info_init(rdev)) {
1493                 DRM_ERROR("Failed to register debugfs file for mc !\n");
1494         }
1495         /* This don't do much */
1496         r = radeon_gem_init(rdev);
1497         if (r)
1498                 return r;
1499         /* Read BIOS */
1500         if (!radeon_get_bios(rdev)) {
1501                 if (ASIC_IS_AVIVO(rdev))
1502                         return -EINVAL;
1503         }
1504         /* Must be an ATOMBIOS */
1505         if (!rdev->is_atom_bios)
1506                 return -EINVAL;
1507         r = radeon_atombios_init(rdev);
1508         if (r)
1509                 return r;
1510         /* Post card if necessary */
1511         if (!r600_card_posted(rdev) && rdev->bios) {
1512                 DRM_INFO("GPU not posted. posting now...\n");
1513                 atom_asic_init(rdev->mode_info.atom_context);
1514         }
1515         /* Initialize scratch registers */
1516         r600_scratch_init(rdev);
1517         /* Initialize surface registers */
1518         radeon_surface_init(rdev);
1519         r = radeon_clocks_init(rdev);
1520         if (r)
1521                 return r;
1522         /* Fence driver */
1523         r = radeon_fence_driver_init(rdev);
1524         if (r)
1525                 return r;
1526         r = r600_mc_init(rdev);
1527         if (r) {
1528                 if (rdev->flags & RADEON_IS_AGP) {
1529                         /* Retry with disabling AGP */
1530                         r600_fini(rdev);
1531                         rdev->flags &= ~RADEON_IS_AGP;
1532                         return r600_init(rdev);
1533                 }
1534                 return r;
1535         }
1536         /* Memory manager */
1537         r = radeon_object_init(rdev);
1538         if (r)
1539                 return r;
1540         rdev->cp.ring_obj = NULL;
1541         r600_ring_init(rdev, 1024 * 1024);
1542
1543         if (!rdev->me_fw || !rdev->pfp_fw) {
1544                 r = r600_cp_init_microcode(rdev);
1545                 if (r) {
1546                         DRM_ERROR("Failed to load firmware!\n");
1547                         return r;
1548                 }
1549         }
1550
1551         r = r600_resume(rdev);
1552         if (r) {
1553                 if (rdev->flags & RADEON_IS_AGP) {
1554                         /* Retry with disabling AGP */
1555                         r600_fini(rdev);
1556                         rdev->flags &= ~RADEON_IS_AGP;
1557                         return r600_init(rdev);
1558                 }
1559                 return r;
1560         }
1561         r = radeon_ib_pool_init(rdev);
1562         if (r) {
1563                 DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r);
1564                 return r;
1565         }
1566         r = r600_blit_init(rdev);
1567         if (r) {
1568                 DRM_ERROR("radeon: failled blitter (%d).\n", r);
1569                 return r;
1570         }
1571         r = radeon_ib_test(rdev);
1572         if (r) {
1573                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1574                         return r;
1575         }
1576         return 0;
1577 }
1578
1579 void r600_fini(struct radeon_device *rdev)
1580 {
1581         /* Suspend operations */
1582         r600_suspend(rdev);
1583
1584         r600_blit_fini(rdev);
1585         radeon_ring_fini(rdev);
1586         r600_pcie_gart_disable(rdev);
1587         radeon_gart_table_vram_free(rdev);
1588         radeon_gart_fini(rdev);
1589         radeon_gem_fini(rdev);
1590         radeon_fence_driver_fini(rdev);
1591         radeon_clocks_fini(rdev);
1592 #if __OS_HAS_AGP
1593         if (rdev->flags & RADEON_IS_AGP)
1594                 radeon_agp_fini(rdev);
1595 #endif
1596         radeon_object_fini(rdev);
1597         if (rdev->is_atom_bios)
1598                 radeon_atombios_fini(rdev);
1599         else
1600                 radeon_combios_fini(rdev);
1601         kfree(rdev->bios);
1602         rdev->bios = NULL;
1603         radeon_dummy_page_fini(rdev);
1604 }
1605
1606
1607 /*
1608  * CS stuff
1609  */
1610 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1611 {
1612         /* FIXME: implement */
1613         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1614         radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
1615         radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
1616         radeon_ring_write(rdev, ib->length_dw);
1617 }
1618
1619 int r600_ib_test(struct radeon_device *rdev)
1620 {
1621         struct radeon_ib *ib;
1622         uint32_t scratch;
1623         uint32_t tmp = 0;
1624         unsigned i;
1625         int r;
1626
1627         r = radeon_scratch_get(rdev, &scratch);
1628         if (r) {
1629                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
1630                 return r;
1631         }
1632         WREG32(scratch, 0xCAFEDEAD);
1633         r = radeon_ib_get(rdev, &ib);
1634         if (r) {
1635                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
1636                 return r;
1637         }
1638         ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
1639         ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
1640         ib->ptr[2] = 0xDEADBEEF;
1641         ib->ptr[3] = PACKET2(0);
1642         ib->ptr[4] = PACKET2(0);
1643         ib->ptr[5] = PACKET2(0);
1644         ib->ptr[6] = PACKET2(0);
1645         ib->ptr[7] = PACKET2(0);
1646         ib->ptr[8] = PACKET2(0);
1647         ib->ptr[9] = PACKET2(0);
1648         ib->ptr[10] = PACKET2(0);
1649         ib->ptr[11] = PACKET2(0);
1650         ib->ptr[12] = PACKET2(0);
1651         ib->ptr[13] = PACKET2(0);
1652         ib->ptr[14] = PACKET2(0);
1653         ib->ptr[15] = PACKET2(0);
1654         ib->length_dw = 16;
1655         r = radeon_ib_schedule(rdev, ib);
1656         if (r) {
1657                 radeon_scratch_free(rdev, scratch);
1658                 radeon_ib_free(rdev, &ib);
1659                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
1660                 return r;
1661         }
1662         r = radeon_fence_wait(ib->fence, false);
1663         if (r) {
1664                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
1665                 return r;
1666         }
1667         for (i = 0; i < rdev->usec_timeout; i++) {
1668                 tmp = RREG32(scratch);
1669                 if (tmp == 0xDEADBEEF)
1670                         break;
1671                 DRM_UDELAY(1);
1672         }
1673         if (i < rdev->usec_timeout) {
1674                 DRM_INFO("ib test succeeded in %u usecs\n", i);
1675         } else {
1676                 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
1677                           scratch, tmp);
1678                 r = -EINVAL;
1679         }
1680         radeon_scratch_free(rdev, scratch);
1681         radeon_ib_free(rdev, &ib);
1682         return r;
1683 }
1684
1685
1686
1687
1688 /*
1689  * Debugfs info
1690  */
1691 #if defined(CONFIG_DEBUG_FS)
1692
1693 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
1694 {
1695         struct drm_info_node *node = (struct drm_info_node *) m->private;
1696         struct drm_device *dev = node->minor->dev;
1697         struct radeon_device *rdev = dev->dev_private;
1698         uint32_t rdp, wdp;
1699         unsigned count, i, j;
1700
1701         radeon_ring_free_size(rdev);
1702         rdp = RREG32(CP_RB_RPTR);
1703         wdp = RREG32(CP_RB_WPTR);
1704         count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
1705         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
1706         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
1707         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
1708         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
1709         seq_printf(m, "%u dwords in ring\n", count);
1710         for (j = 0; j <= count; j++) {
1711                 i = (rdp + j) & rdev->cp.ptr_mask;
1712                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
1713         }
1714         return 0;
1715 }
1716
1717 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
1718 {
1719         struct drm_info_node *node = (struct drm_info_node *) m->private;
1720         struct drm_device *dev = node->minor->dev;
1721         struct radeon_device *rdev = dev->dev_private;
1722
1723         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
1724         DREG32_SYS(m, rdev, VM_L2_STATUS);
1725         return 0;
1726 }
1727
1728 static struct drm_info_list r600_mc_info_list[] = {
1729         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
1730         {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
1731 };
1732 #endif
1733
1734 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
1735 {
1736 #if defined(CONFIG_DEBUG_FS)
1737         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
1738 #else
1739         return 0;
1740 #endif
1741 }