drm/radeon/kms: display watermark fixes
[linux-2.6.git] / drivers / gpu / drm / radeon / r300.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/seq_file.h>
29 #include "drmP.h"
30 #include "drm.h"
31 #include "radeon_reg.h"
32 #include "radeon.h"
33 #include "radeon_asic.h"
34 #include "radeon_drm.h"
35 #include "r100_track.h"
36 #include "r300d.h"
37 #include "rv350d.h"
38 #include "r300_reg_safe.h"
39
40 /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
41  *
42  * GPU Errata:
43  * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
44  *   using MMIO to flush host path read cache, this lead to HARDLOCKUP.
45  *   However, scheduling such write to the ring seems harmless, i suspect
46  *   the CP read collide with the flush somehow, or maybe the MC, hard to
47  *   tell. (Jerome Glisse)
48  */
49
50 /*
51  * rv370,rv380 PCIE GART
52  */
53 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
54
55 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
56 {
57         uint32_t tmp;
58         int i;
59
60         /* Workaround HW bug do flush 2 times */
61         for (i = 0; i < 2; i++) {
62                 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
63                 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
64                 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
65                 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
66         }
67         mb();
68 }
69
70 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
71 {
72         void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
73
74         if (i < 0 || i > rdev->gart.num_gpu_pages) {
75                 return -EINVAL;
76         }
77         addr = (lower_32_bits(addr) >> 8) |
78                ((upper_32_bits(addr) & 0xff) << 24) |
79                0xc;
80         /* on x86 we want this to be CPU endian, on powerpc
81          * on powerpc without HW swappers, it'll get swapped on way
82          * into VRAM - so no need for cpu_to_le32 on VRAM tables */
83         writel(addr, ((void __iomem *)ptr) + (i * 4));
84         return 0;
85 }
86
87 int rv370_pcie_gart_init(struct radeon_device *rdev)
88 {
89         int r;
90
91         if (rdev->gart.table.vram.robj) {
92                 WARN(1, "RV370 PCIE GART already initialized.\n");
93                 return 0;
94         }
95         /* Initialize common gart structure */
96         r = radeon_gart_init(rdev);
97         if (r)
98                 return r;
99         r = rv370_debugfs_pcie_gart_info_init(rdev);
100         if (r)
101                 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
102         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
103         rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
104         rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
105         return radeon_gart_table_vram_alloc(rdev);
106 }
107
108 int rv370_pcie_gart_enable(struct radeon_device *rdev)
109 {
110         uint32_t table_addr;
111         uint32_t tmp;
112         int r;
113
114         if (rdev->gart.table.vram.robj == NULL) {
115                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
116                 return -EINVAL;
117         }
118         r = radeon_gart_table_vram_pin(rdev);
119         if (r)
120                 return r;
121         radeon_gart_restore(rdev);
122         /* discard memory request outside of configured range */
123         tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
124         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
125         WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);
126         tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;
127         WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
128         WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
129         WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
130         table_addr = rdev->gart.table_addr;
131         WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
132         /* FIXME: setup default page */
133         WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);
134         WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
135         /* Clear error */
136         WREG32_PCIE(0x18, 0);
137         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
138         tmp |= RADEON_PCIE_TX_GART_EN;
139         tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
140         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
141         rv370_pcie_gart_tlb_flush(rdev);
142         DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
143                  (unsigned)(rdev->mc.gtt_size >> 20), table_addr);
144         rdev->gart.ready = true;
145         return 0;
146 }
147
148 void rv370_pcie_gart_disable(struct radeon_device *rdev)
149 {
150         u32 tmp;
151         int r;
152
153         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
154         tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
155         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
156         if (rdev->gart.table.vram.robj) {
157                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
158                 if (likely(r == 0)) {
159                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
160                         radeon_bo_unpin(rdev->gart.table.vram.robj);
161                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
162                 }
163         }
164 }
165
166 void rv370_pcie_gart_fini(struct radeon_device *rdev)
167 {
168         rv370_pcie_gart_disable(rdev);
169         radeon_gart_table_vram_free(rdev);
170         radeon_gart_fini(rdev);
171 }
172
173 void r300_fence_ring_emit(struct radeon_device *rdev,
174                           struct radeon_fence *fence)
175 {
176         /* Who ever call radeon_fence_emit should call ring_lock and ask
177          * for enough space (today caller are ib schedule and buffer move) */
178         /* Write SC register so SC & US assert idle */
179         radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_TL, 0));
180         radeon_ring_write(rdev, 0);
181         radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_BR, 0));
182         radeon_ring_write(rdev, 0);
183         /* Flush 3D cache */
184         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
185         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH);
186         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
187         radeon_ring_write(rdev, R300_ZC_FLUSH);
188         /* Wait until IDLE & CLEAN */
189         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
190         radeon_ring_write(rdev, (RADEON_WAIT_3D_IDLECLEAN |
191                                  RADEON_WAIT_2D_IDLECLEAN |
192                                  RADEON_WAIT_DMA_GUI_IDLE));
193         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
194         radeon_ring_write(rdev, rdev->config.r300.hdp_cntl |
195                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
196         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
197         radeon_ring_write(rdev, rdev->config.r300.hdp_cntl);
198         /* Emit fence sequence & fire IRQ */
199         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
200         radeon_ring_write(rdev, fence->seq);
201         radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
202         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
203 }
204
205 void r300_ring_start(struct radeon_device *rdev)
206 {
207         unsigned gb_tile_config;
208         int r;
209
210         /* Sub pixel 1/12 so we can have 4K rendering according to doc */
211         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
212         switch(rdev->num_gb_pipes) {
213         case 2:
214                 gb_tile_config |= R300_PIPE_COUNT_R300;
215                 break;
216         case 3:
217                 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
218                 break;
219         case 4:
220                 gb_tile_config |= R300_PIPE_COUNT_R420;
221                 break;
222         case 1:
223         default:
224                 gb_tile_config |= R300_PIPE_COUNT_RV350;
225                 break;
226         }
227
228         r = radeon_ring_lock(rdev, 64);
229         if (r) {
230                 return;
231         }
232         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
233         radeon_ring_write(rdev,
234                           RADEON_ISYNC_ANY2D_IDLE3D |
235                           RADEON_ISYNC_ANY3D_IDLE2D |
236                           RADEON_ISYNC_WAIT_IDLEGUI |
237                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
238         radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
239         radeon_ring_write(rdev, gb_tile_config);
240         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
241         radeon_ring_write(rdev,
242                           RADEON_WAIT_2D_IDLECLEAN |
243                           RADEON_WAIT_3D_IDLECLEAN);
244         radeon_ring_write(rdev, PACKET0(R300_DST_PIPE_CONFIG, 0));
245         radeon_ring_write(rdev, R300_PIPE_AUTO_CONFIG);
246         radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
247         radeon_ring_write(rdev, 0);
248         radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
249         radeon_ring_write(rdev, 0);
250         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
251         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
252         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
253         radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
254         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
255         radeon_ring_write(rdev,
256                           RADEON_WAIT_2D_IDLECLEAN |
257                           RADEON_WAIT_3D_IDLECLEAN);
258         radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
259         radeon_ring_write(rdev, 0);
260         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
261         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
262         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
263         radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
264         radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
265         radeon_ring_write(rdev,
266                           ((6 << R300_MS_X0_SHIFT) |
267                            (6 << R300_MS_Y0_SHIFT) |
268                            (6 << R300_MS_X1_SHIFT) |
269                            (6 << R300_MS_Y1_SHIFT) |
270                            (6 << R300_MS_X2_SHIFT) |
271                            (6 << R300_MS_Y2_SHIFT) |
272                            (6 << R300_MSBD0_Y_SHIFT) |
273                            (6 << R300_MSBD0_X_SHIFT)));
274         radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
275         radeon_ring_write(rdev,
276                           ((6 << R300_MS_X3_SHIFT) |
277                            (6 << R300_MS_Y3_SHIFT) |
278                            (6 << R300_MS_X4_SHIFT) |
279                            (6 << R300_MS_Y4_SHIFT) |
280                            (6 << R300_MS_X5_SHIFT) |
281                            (6 << R300_MS_Y5_SHIFT) |
282                            (6 << R300_MSBD1_SHIFT)));
283         radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
284         radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
285         radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
286         radeon_ring_write(rdev,
287                           R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
288         radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
289         radeon_ring_write(rdev,
290                           R300_GEOMETRY_ROUND_NEAREST |
291                           R300_COLOR_ROUND_NEAREST);
292         radeon_ring_unlock_commit(rdev);
293 }
294
295 void r300_errata(struct radeon_device *rdev)
296 {
297         rdev->pll_errata = 0;
298
299         if (rdev->family == CHIP_R300 &&
300             (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
301                 rdev->pll_errata |= CHIP_ERRATA_R300_CG;
302         }
303 }
304
305 int r300_mc_wait_for_idle(struct radeon_device *rdev)
306 {
307         unsigned i;
308         uint32_t tmp;
309
310         for (i = 0; i < rdev->usec_timeout; i++) {
311                 /* read MC_STATUS */
312                 tmp = RREG32(RADEON_MC_STATUS);
313                 if (tmp & R300_MC_IDLE) {
314                         return 0;
315                 }
316                 DRM_UDELAY(1);
317         }
318         return -1;
319 }
320
321 void r300_gpu_init(struct radeon_device *rdev)
322 {
323         uint32_t gb_tile_config, tmp;
324
325         r100_hdp_reset(rdev);
326         /* FIXME: rv380 one pipes ? */
327         if ((rdev->family == CHIP_R300) || (rdev->family == CHIP_R350)) {
328                 /* r300,r350 */
329                 rdev->num_gb_pipes = 2;
330         } else {
331                 /* rv350,rv370,rv380 */
332                 rdev->num_gb_pipes = 1;
333         }
334         rdev->num_z_pipes = 1;
335         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
336         switch (rdev->num_gb_pipes) {
337         case 2:
338                 gb_tile_config |= R300_PIPE_COUNT_R300;
339                 break;
340         case 3:
341                 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
342                 break;
343         case 4:
344                 gb_tile_config |= R300_PIPE_COUNT_R420;
345                 break;
346         default:
347         case 1:
348                 gb_tile_config |= R300_PIPE_COUNT_RV350;
349                 break;
350         }
351         WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
352
353         if (r100_gui_wait_for_idle(rdev)) {
354                 printk(KERN_WARNING "Failed to wait GUI idle while "
355                        "programming pipes. Bad things might happen.\n");
356         }
357
358         tmp = RREG32(R300_DST_PIPE_CONFIG);
359         WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
360
361         WREG32(R300_RB2D_DSTCACHE_MODE,
362                R300_DC_AUTOFLUSH_ENABLE |
363                R300_DC_DC_DISABLE_IGNORE_PE);
364
365         if (r100_gui_wait_for_idle(rdev)) {
366                 printk(KERN_WARNING "Failed to wait GUI idle while "
367                        "programming pipes. Bad things might happen.\n");
368         }
369         if (r300_mc_wait_for_idle(rdev)) {
370                 printk(KERN_WARNING "Failed to wait MC idle while "
371                        "programming pipes. Bad things might happen.\n");
372         }
373         DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
374                  rdev->num_gb_pipes, rdev->num_z_pipes);
375 }
376
377 int r300_ga_reset(struct radeon_device *rdev)
378 {
379         uint32_t tmp;
380         bool reinit_cp;
381         int i;
382
383         reinit_cp = rdev->cp.ready;
384         rdev->cp.ready = false;
385         for (i = 0; i < rdev->usec_timeout; i++) {
386                 WREG32(RADEON_CP_CSQ_MODE, 0);
387                 WREG32(RADEON_CP_CSQ_CNTL, 0);
388                 WREG32(RADEON_RBBM_SOFT_RESET, 0x32005);
389                 (void)RREG32(RADEON_RBBM_SOFT_RESET);
390                 udelay(200);
391                 WREG32(RADEON_RBBM_SOFT_RESET, 0);
392                 /* Wait to prevent race in RBBM_STATUS */
393                 mdelay(1);
394                 tmp = RREG32(RADEON_RBBM_STATUS);
395                 if (tmp & ((1 << 20) | (1 << 26))) {
396                         DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp);
397                         /* GA still busy soft reset it */
398                         WREG32(0x429C, 0x200);
399                         WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0);
400                         WREG32(R300_RE_SCISSORS_TL, 0);
401                         WREG32(R300_RE_SCISSORS_BR, 0);
402                         WREG32(0x24AC, 0);
403                 }
404                 /* Wait to prevent race in RBBM_STATUS */
405                 mdelay(1);
406                 tmp = RREG32(RADEON_RBBM_STATUS);
407                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
408                         break;
409                 }
410         }
411         for (i = 0; i < rdev->usec_timeout; i++) {
412                 tmp = RREG32(RADEON_RBBM_STATUS);
413                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
414                         DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
415                                  tmp);
416                         if (reinit_cp) {
417                                 return r100_cp_init(rdev, rdev->cp.ring_size);
418                         }
419                         return 0;
420                 }
421                 DRM_UDELAY(1);
422         }
423         tmp = RREG32(RADEON_RBBM_STATUS);
424         DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
425         return -1;
426 }
427
428 int r300_gpu_reset(struct radeon_device *rdev)
429 {
430         uint32_t status;
431
432         /* reset order likely matter */
433         status = RREG32(RADEON_RBBM_STATUS);
434         /* reset HDP */
435         r100_hdp_reset(rdev);
436         /* reset rb2d */
437         if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
438                 r100_rb2d_reset(rdev);
439         }
440         /* reset GA */
441         if (status & ((1 << 20) | (1 << 26))) {
442                 r300_ga_reset(rdev);
443         }
444         /* reset CP */
445         status = RREG32(RADEON_RBBM_STATUS);
446         if (status & (1 << 16)) {
447                 r100_cp_reset(rdev);
448         }
449         /* Check if GPU is idle */
450         status = RREG32(RADEON_RBBM_STATUS);
451         if (status & RADEON_RBBM_ACTIVE) {
452                 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
453                 return -1;
454         }
455         DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
456         return 0;
457 }
458
459
460 /*
461  * r300,r350,rv350,rv380 VRAM info
462  */
463 void r300_mc_init(struct radeon_device *rdev)
464 {
465         u64 base;
466         u32 tmp;
467
468         /* DDR for all card after R300 & IGP */
469         rdev->mc.vram_is_ddr = true;
470         tmp = RREG32(RADEON_MEM_CNTL);
471         tmp &= R300_MEM_NUM_CHANNELS_MASK;
472         switch (tmp) {
473         case 0: rdev->mc.vram_width = 64; break;
474         case 1: rdev->mc.vram_width = 128; break;
475         case 2: rdev->mc.vram_width = 256; break;
476         default:  rdev->mc.vram_width = 128; break;
477         }
478         r100_vram_init_sizes(rdev);
479         base = rdev->mc.aper_base;
480         if (rdev->flags & RADEON_IS_IGP)
481                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
482         radeon_vram_location(rdev, &rdev->mc, base);
483         if (!(rdev->flags & RADEON_IS_AGP))
484                 radeon_gtt_location(rdev, &rdev->mc);
485         radeon_update_bandwidth_info(rdev);
486 }
487
488 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
489 {
490         uint32_t link_width_cntl, mask;
491
492         if (rdev->flags & RADEON_IS_IGP)
493                 return;
494
495         if (!(rdev->flags & RADEON_IS_PCIE))
496                 return;
497
498         /* FIXME wait for idle */
499
500         switch (lanes) {
501         case 0:
502                 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
503                 break;
504         case 1:
505                 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
506                 break;
507         case 2:
508                 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
509                 break;
510         case 4:
511                 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
512                 break;
513         case 8:
514                 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
515                 break;
516         case 12:
517                 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
518                 break;
519         case 16:
520         default:
521                 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
522                 break;
523         }
524
525         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
526
527         if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
528             (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
529                 return;
530
531         link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
532                              RADEON_PCIE_LC_RECONFIG_NOW |
533                              RADEON_PCIE_LC_RECONFIG_LATER |
534                              RADEON_PCIE_LC_SHORT_RECONFIG_EN);
535         link_width_cntl |= mask;
536         WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
537         WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
538                                                      RADEON_PCIE_LC_RECONFIG_NOW));
539
540         /* wait for lane set to complete */
541         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
542         while (link_width_cntl == 0xffffffff)
543                 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
544
545 }
546
547 int rv370_get_pcie_lanes(struct radeon_device *rdev)
548 {
549         u32 link_width_cntl;
550
551         if (rdev->flags & RADEON_IS_IGP)
552                 return 0;
553
554         if (!(rdev->flags & RADEON_IS_PCIE))
555                 return 0;
556
557         /* FIXME wait for idle */
558
559         if (rdev->family < CHIP_R600)
560                 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
561         else
562                 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
563
564         switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
565         case RADEON_PCIE_LC_LINK_WIDTH_X0:
566                 return 0;
567         case RADEON_PCIE_LC_LINK_WIDTH_X1:
568                 return 1;
569         case RADEON_PCIE_LC_LINK_WIDTH_X2:
570                 return 2;
571         case RADEON_PCIE_LC_LINK_WIDTH_X4:
572                 return 4;
573         case RADEON_PCIE_LC_LINK_WIDTH_X8:
574                 return 8;
575         case RADEON_PCIE_LC_LINK_WIDTH_X16:
576         default:
577                 return 16;
578         }
579 }
580
581 #if defined(CONFIG_DEBUG_FS)
582 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data)
583 {
584         struct drm_info_node *node = (struct drm_info_node *) m->private;
585         struct drm_device *dev = node->minor->dev;
586         struct radeon_device *rdev = dev->dev_private;
587         uint32_t tmp;
588
589         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
590         seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
591         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
592         seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
593         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
594         seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
595         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
596         seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
597         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
598         seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
599         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
600         seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
601         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
602         seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
603         return 0;
604 }
605
606 static struct drm_info_list rv370_pcie_gart_info_list[] = {
607         {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
608 };
609 #endif
610
611 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
612 {
613 #if defined(CONFIG_DEBUG_FS)
614         return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
615 #else
616         return 0;
617 #endif
618 }
619
620 static int r300_packet0_check(struct radeon_cs_parser *p,
621                 struct radeon_cs_packet *pkt,
622                 unsigned idx, unsigned reg)
623 {
624         struct radeon_cs_reloc *reloc;
625         struct r100_cs_track *track;
626         volatile uint32_t *ib;
627         uint32_t tmp, tile_flags = 0;
628         unsigned i;
629         int r;
630         u32 idx_value;
631
632         ib = p->ib->ptr;
633         track = (struct r100_cs_track *)p->track;
634         idx_value = radeon_get_ib_value(p, idx);
635
636         switch(reg) {
637         case AVIVO_D1MODE_VLINE_START_END:
638         case RADEON_CRTC_GUI_TRIG_VLINE:
639                 r = r100_cs_packet_parse_vline(p);
640                 if (r) {
641                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
642                                         idx, reg);
643                         r100_cs_dump_packet(p, pkt);
644                         return r;
645                 }
646                 break;
647         case RADEON_DST_PITCH_OFFSET:
648         case RADEON_SRC_PITCH_OFFSET:
649                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
650                 if (r)
651                         return r;
652                 break;
653         case R300_RB3D_COLOROFFSET0:
654         case R300_RB3D_COLOROFFSET1:
655         case R300_RB3D_COLOROFFSET2:
656         case R300_RB3D_COLOROFFSET3:
657                 i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
658                 r = r100_cs_packet_next_reloc(p, &reloc);
659                 if (r) {
660                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
661                                         idx, reg);
662                         r100_cs_dump_packet(p, pkt);
663                         return r;
664                 }
665                 track->cb[i].robj = reloc->robj;
666                 track->cb[i].offset = idx_value;
667                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
668                 break;
669         case R300_ZB_DEPTHOFFSET:
670                 r = r100_cs_packet_next_reloc(p, &reloc);
671                 if (r) {
672                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
673                                         idx, reg);
674                         r100_cs_dump_packet(p, pkt);
675                         return r;
676                 }
677                 track->zb.robj = reloc->robj;
678                 track->zb.offset = idx_value;
679                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
680                 break;
681         case R300_TX_OFFSET_0:
682         case R300_TX_OFFSET_0+4:
683         case R300_TX_OFFSET_0+8:
684         case R300_TX_OFFSET_0+12:
685         case R300_TX_OFFSET_0+16:
686         case R300_TX_OFFSET_0+20:
687         case R300_TX_OFFSET_0+24:
688         case R300_TX_OFFSET_0+28:
689         case R300_TX_OFFSET_0+32:
690         case R300_TX_OFFSET_0+36:
691         case R300_TX_OFFSET_0+40:
692         case R300_TX_OFFSET_0+44:
693         case R300_TX_OFFSET_0+48:
694         case R300_TX_OFFSET_0+52:
695         case R300_TX_OFFSET_0+56:
696         case R300_TX_OFFSET_0+60:
697                 i = (reg - R300_TX_OFFSET_0) >> 2;
698                 r = r100_cs_packet_next_reloc(p, &reloc);
699                 if (r) {
700                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
701                                         idx, reg);
702                         r100_cs_dump_packet(p, pkt);
703                         return r;
704                 }
705
706                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
707                         tile_flags |= R300_TXO_MACRO_TILE;
708                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
709                         tile_flags |= R300_TXO_MICRO_TILE;
710                 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
711                         tile_flags |= R300_TXO_MICRO_TILE_SQUARE;
712
713                 tmp = idx_value + ((u32)reloc->lobj.gpu_offset);
714                 tmp |= tile_flags;
715                 ib[idx] = tmp;
716                 track->textures[i].robj = reloc->robj;
717                 break;
718         /* Tracked registers */
719         case 0x2084:
720                 /* VAP_VF_CNTL */
721                 track->vap_vf_cntl = idx_value;
722                 break;
723         case 0x20B4:
724                 /* VAP_VTX_SIZE */
725                 track->vtx_size = idx_value & 0x7F;
726                 break;
727         case 0x2134:
728                 /* VAP_VF_MAX_VTX_INDX */
729                 track->max_indx = idx_value & 0x00FFFFFFUL;
730                 break;
731         case 0x43E4:
732                 /* SC_SCISSOR1 */
733                 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
734                 if (p->rdev->family < CHIP_RV515) {
735                         track->maxy -= 1440;
736                 }
737                 break;
738         case 0x4E00:
739                 /* RB3D_CCTL */
740                 track->num_cb = ((idx_value >> 5) & 0x3) + 1;
741                 break;
742         case 0x4E38:
743         case 0x4E3C:
744         case 0x4E40:
745         case 0x4E44:
746                 /* RB3D_COLORPITCH0 */
747                 /* RB3D_COLORPITCH1 */
748                 /* RB3D_COLORPITCH2 */
749                 /* RB3D_COLORPITCH3 */
750                 r = r100_cs_packet_next_reloc(p, &reloc);
751                 if (r) {
752                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
753                                   idx, reg);
754                         r100_cs_dump_packet(p, pkt);
755                         return r;
756                 }
757
758                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
759                         tile_flags |= R300_COLOR_TILE_ENABLE;
760                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
761                         tile_flags |= R300_COLOR_MICROTILE_ENABLE;
762                 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
763                         tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE;
764
765                 tmp = idx_value & ~(0x7 << 16);
766                 tmp |= tile_flags;
767                 ib[idx] = tmp;
768
769                 i = (reg - 0x4E38) >> 2;
770                 track->cb[i].pitch = idx_value & 0x3FFE;
771                 switch (((idx_value >> 21) & 0xF)) {
772                 case 9:
773                 case 11:
774                 case 12:
775                         track->cb[i].cpp = 1;
776                         break;
777                 case 3:
778                 case 4:
779                 case 13:
780                 case 15:
781                         track->cb[i].cpp = 2;
782                         break;
783                 case 6:
784                         track->cb[i].cpp = 4;
785                         break;
786                 case 10:
787                         track->cb[i].cpp = 8;
788                         break;
789                 case 7:
790                         track->cb[i].cpp = 16;
791                         break;
792                 default:
793                         DRM_ERROR("Invalid color buffer format (%d) !\n",
794                                   ((idx_value >> 21) & 0xF));
795                         return -EINVAL;
796                 }
797                 break;
798         case 0x4F00:
799                 /* ZB_CNTL */
800                 if (idx_value & 2) {
801                         track->z_enabled = true;
802                 } else {
803                         track->z_enabled = false;
804                 }
805                 break;
806         case 0x4F10:
807                 /* ZB_FORMAT */
808                 switch ((idx_value & 0xF)) {
809                 case 0:
810                 case 1:
811                         track->zb.cpp = 2;
812                         break;
813                 case 2:
814                         track->zb.cpp = 4;
815                         break;
816                 default:
817                         DRM_ERROR("Invalid z buffer format (%d) !\n",
818                                   (idx_value & 0xF));
819                         return -EINVAL;
820                 }
821                 break;
822         case 0x4F24:
823                 /* ZB_DEPTHPITCH */
824                 r = r100_cs_packet_next_reloc(p, &reloc);
825                 if (r) {
826                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
827                                   idx, reg);
828                         r100_cs_dump_packet(p, pkt);
829                         return r;
830                 }
831
832                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
833                         tile_flags |= R300_DEPTHMACROTILE_ENABLE;
834                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
835                         tile_flags |= R300_DEPTHMICROTILE_TILED;
836                 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
837                         tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE;
838
839                 tmp = idx_value & ~(0x7 << 16);
840                 tmp |= tile_flags;
841                 ib[idx] = tmp;
842
843                 track->zb.pitch = idx_value & 0x3FFC;
844                 break;
845         case 0x4104:
846                 for (i = 0; i < 16; i++) {
847                         bool enabled;
848
849                         enabled = !!(idx_value & (1 << i));
850                         track->textures[i].enabled = enabled;
851                 }
852                 break;
853         case 0x44C0:
854         case 0x44C4:
855         case 0x44C8:
856         case 0x44CC:
857         case 0x44D0:
858         case 0x44D4:
859         case 0x44D8:
860         case 0x44DC:
861         case 0x44E0:
862         case 0x44E4:
863         case 0x44E8:
864         case 0x44EC:
865         case 0x44F0:
866         case 0x44F4:
867         case 0x44F8:
868         case 0x44FC:
869                 /* TX_FORMAT1_[0-15] */
870                 i = (reg - 0x44C0) >> 2;
871                 tmp = (idx_value >> 25) & 0x3;
872                 track->textures[i].tex_coord_type = tmp;
873                 switch ((idx_value & 0x1F)) {
874                 case R300_TX_FORMAT_X8:
875                 case R300_TX_FORMAT_Y4X4:
876                 case R300_TX_FORMAT_Z3Y3X2:
877                         track->textures[i].cpp = 1;
878                         break;
879                 case R300_TX_FORMAT_X16:
880                 case R300_TX_FORMAT_Y8X8:
881                 case R300_TX_FORMAT_Z5Y6X5:
882                 case R300_TX_FORMAT_Z6Y5X5:
883                 case R300_TX_FORMAT_W4Z4Y4X4:
884                 case R300_TX_FORMAT_W1Z5Y5X5:
885                 case R300_TX_FORMAT_D3DMFT_CxV8U8:
886                 case R300_TX_FORMAT_B8G8_B8G8:
887                 case R300_TX_FORMAT_G8R8_G8B8:
888                         track->textures[i].cpp = 2;
889                         break;
890                 case R300_TX_FORMAT_Y16X16:
891                 case R300_TX_FORMAT_Z11Y11X10:
892                 case R300_TX_FORMAT_Z10Y11X11:
893                 case R300_TX_FORMAT_W8Z8Y8X8:
894                 case R300_TX_FORMAT_W2Z10Y10X10:
895                 case 0x17:
896                 case R300_TX_FORMAT_FL_I32:
897                 case 0x1e:
898                         track->textures[i].cpp = 4;
899                         break;
900                 case R300_TX_FORMAT_W16Z16Y16X16:
901                 case R300_TX_FORMAT_FL_R16G16B16A16:
902                 case R300_TX_FORMAT_FL_I32A32:
903                         track->textures[i].cpp = 8;
904                         break;
905                 case R300_TX_FORMAT_FL_R32G32B32A32:
906                         track->textures[i].cpp = 16;
907                         break;
908                 case R300_TX_FORMAT_DXT1:
909                         track->textures[i].cpp = 1;
910                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
911                         break;
912                 case R300_TX_FORMAT_ATI2N:
913                         if (p->rdev->family < CHIP_R420) {
914                                 DRM_ERROR("Invalid texture format %u\n",
915                                           (idx_value & 0x1F));
916                                 return -EINVAL;
917                         }
918                         /* The same rules apply as for DXT3/5. */
919                         /* Pass through. */
920                 case R300_TX_FORMAT_DXT3:
921                 case R300_TX_FORMAT_DXT5:
922                         track->textures[i].cpp = 1;
923                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
924                         break;
925                 default:
926                         DRM_ERROR("Invalid texture format %u\n",
927                                   (idx_value & 0x1F));
928                         return -EINVAL;
929                         break;
930                 }
931                 break;
932         case 0x4400:
933         case 0x4404:
934         case 0x4408:
935         case 0x440C:
936         case 0x4410:
937         case 0x4414:
938         case 0x4418:
939         case 0x441C:
940         case 0x4420:
941         case 0x4424:
942         case 0x4428:
943         case 0x442C:
944         case 0x4430:
945         case 0x4434:
946         case 0x4438:
947         case 0x443C:
948                 /* TX_FILTER0_[0-15] */
949                 i = (reg - 0x4400) >> 2;
950                 tmp = idx_value & 0x7;
951                 if (tmp == 2 || tmp == 4 || tmp == 6) {
952                         track->textures[i].roundup_w = false;
953                 }
954                 tmp = (idx_value >> 3) & 0x7;
955                 if (tmp == 2 || tmp == 4 || tmp == 6) {
956                         track->textures[i].roundup_h = false;
957                 }
958                 break;
959         case 0x4500:
960         case 0x4504:
961         case 0x4508:
962         case 0x450C:
963         case 0x4510:
964         case 0x4514:
965         case 0x4518:
966         case 0x451C:
967         case 0x4520:
968         case 0x4524:
969         case 0x4528:
970         case 0x452C:
971         case 0x4530:
972         case 0x4534:
973         case 0x4538:
974         case 0x453C:
975                 /* TX_FORMAT2_[0-15] */
976                 i = (reg - 0x4500) >> 2;
977                 tmp = idx_value & 0x3FFF;
978                 track->textures[i].pitch = tmp + 1;
979                 if (p->rdev->family >= CHIP_RV515) {
980                         tmp = ((idx_value >> 15) & 1) << 11;
981                         track->textures[i].width_11 = tmp;
982                         tmp = ((idx_value >> 16) & 1) << 11;
983                         track->textures[i].height_11 = tmp;
984
985                         /* ATI1N */
986                         if (idx_value & (1 << 14)) {
987                                 /* The same rules apply as for DXT1. */
988                                 track->textures[i].compress_format =
989                                         R100_TRACK_COMP_DXT1;
990                         }
991                 } else if (idx_value & (1 << 14)) {
992                         DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
993                         return -EINVAL;
994                 }
995                 break;
996         case 0x4480:
997         case 0x4484:
998         case 0x4488:
999         case 0x448C:
1000         case 0x4490:
1001         case 0x4494:
1002         case 0x4498:
1003         case 0x449C:
1004         case 0x44A0:
1005         case 0x44A4:
1006         case 0x44A8:
1007         case 0x44AC:
1008         case 0x44B0:
1009         case 0x44B4:
1010         case 0x44B8:
1011         case 0x44BC:
1012                 /* TX_FORMAT0_[0-15] */
1013                 i = (reg - 0x4480) >> 2;
1014                 tmp = idx_value & 0x7FF;
1015                 track->textures[i].width = tmp + 1;
1016                 tmp = (idx_value >> 11) & 0x7FF;
1017                 track->textures[i].height = tmp + 1;
1018                 tmp = (idx_value >> 26) & 0xF;
1019                 track->textures[i].num_levels = tmp;
1020                 tmp = idx_value & (1 << 31);
1021                 track->textures[i].use_pitch = !!tmp;
1022                 tmp = (idx_value >> 22) & 0xF;
1023                 track->textures[i].txdepth = tmp;
1024                 break;
1025         case R300_ZB_ZPASS_ADDR:
1026                 r = r100_cs_packet_next_reloc(p, &reloc);
1027                 if (r) {
1028                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1029                                         idx, reg);
1030                         r100_cs_dump_packet(p, pkt);
1031                         return r;
1032                 }
1033                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1034                 break;
1035         case 0x4e0c:
1036                 /* RB3D_COLOR_CHANNEL_MASK */
1037                 track->color_channel_mask = idx_value;
1038                 break;
1039         case 0x4d1c:
1040                 /* ZB_BW_CNTL */
1041                 track->fastfill = !!(idx_value & (1 << 2));
1042                 break;
1043         case 0x4e04:
1044                 /* RB3D_BLENDCNTL */
1045                 track->blend_read_enable = !!(idx_value & (1 << 2));
1046                 break;
1047         case 0x4be8:
1048                 /* valid register only on RV530 */
1049                 if (p->rdev->family == CHIP_RV530)
1050                         break;
1051                 /* fallthrough do not move */
1052         default:
1053                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1054                        reg, idx);
1055                 return -EINVAL;
1056         }
1057         return 0;
1058 }
1059
1060 static int r300_packet3_check(struct radeon_cs_parser *p,
1061                               struct radeon_cs_packet *pkt)
1062 {
1063         struct radeon_cs_reloc *reloc;
1064         struct r100_cs_track *track;
1065         volatile uint32_t *ib;
1066         unsigned idx;
1067         int r;
1068
1069         ib = p->ib->ptr;
1070         idx = pkt->idx + 1;
1071         track = (struct r100_cs_track *)p->track;
1072         switch(pkt->opcode) {
1073         case PACKET3_3D_LOAD_VBPNTR:
1074                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1075                 if (r)
1076                         return r;
1077                 break;
1078         case PACKET3_INDX_BUFFER:
1079                 r = r100_cs_packet_next_reloc(p, &reloc);
1080                 if (r) {
1081                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1082                         r100_cs_dump_packet(p, pkt);
1083                         return r;
1084                 }
1085                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1086                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1087                 if (r) {
1088                         return r;
1089                 }
1090                 break;
1091         /* Draw packet */
1092         case PACKET3_3D_DRAW_IMMD:
1093                 /* Number of dwords is vtx_size * (num_vertices - 1)
1094                  * PRIM_WALK must be equal to 3 vertex data in embedded
1095                  * in cmd stream */
1096                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1097                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1098                         return -EINVAL;
1099                 }
1100                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1101                 track->immd_dwords = pkt->count - 1;
1102                 r = r100_cs_track_check(p->rdev, track);
1103                 if (r) {
1104                         return r;
1105                 }
1106                 break;
1107         case PACKET3_3D_DRAW_IMMD_2:
1108                 /* Number of dwords is vtx_size * (num_vertices - 1)
1109                  * PRIM_WALK must be equal to 3 vertex data in embedded
1110                  * in cmd stream */
1111                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1112                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1113                         return -EINVAL;
1114                 }
1115                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1116                 track->immd_dwords = pkt->count;
1117                 r = r100_cs_track_check(p->rdev, track);
1118                 if (r) {
1119                         return r;
1120                 }
1121                 break;
1122         case PACKET3_3D_DRAW_VBUF:
1123                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1124                 r = r100_cs_track_check(p->rdev, track);
1125                 if (r) {
1126                         return r;
1127                 }
1128                 break;
1129         case PACKET3_3D_DRAW_VBUF_2:
1130                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1131                 r = r100_cs_track_check(p->rdev, track);
1132                 if (r) {
1133                         return r;
1134                 }
1135                 break;
1136         case PACKET3_3D_DRAW_INDX:
1137                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1138                 r = r100_cs_track_check(p->rdev, track);
1139                 if (r) {
1140                         return r;
1141                 }
1142                 break;
1143         case PACKET3_3D_DRAW_INDX_2:
1144                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1145                 r = r100_cs_track_check(p->rdev, track);
1146                 if (r) {
1147                         return r;
1148                 }
1149                 break;
1150         case PACKET3_NOP:
1151                 break;
1152         default:
1153                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1154                 return -EINVAL;
1155         }
1156         return 0;
1157 }
1158
1159 int r300_cs_parse(struct radeon_cs_parser *p)
1160 {
1161         struct radeon_cs_packet pkt;
1162         struct r100_cs_track *track;
1163         int r;
1164
1165         track = kzalloc(sizeof(*track), GFP_KERNEL);
1166         r100_cs_track_clear(p->rdev, track);
1167         p->track = track;
1168         do {
1169                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1170                 if (r) {
1171                         return r;
1172                 }
1173                 p->idx += pkt.count + 2;
1174                 switch (pkt.type) {
1175                 case PACKET_TYPE0:
1176                         r = r100_cs_parse_packet0(p, &pkt,
1177                                                   p->rdev->config.r300.reg_safe_bm,
1178                                                   p->rdev->config.r300.reg_safe_bm_size,
1179                                                   &r300_packet0_check);
1180                         break;
1181                 case PACKET_TYPE2:
1182                         break;
1183                 case PACKET_TYPE3:
1184                         r = r300_packet3_check(p, &pkt);
1185                         break;
1186                 default:
1187                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1188                         return -EINVAL;
1189                 }
1190                 if (r) {
1191                         return r;
1192                 }
1193         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1194         return 0;
1195 }
1196
1197 void r300_set_reg_safe(struct radeon_device *rdev)
1198 {
1199         rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
1200         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1201 }
1202
1203 void r300_mc_program(struct radeon_device *rdev)
1204 {
1205         struct r100_mc_save save;
1206         int r;
1207
1208         r = r100_debugfs_mc_info_init(rdev);
1209         if (r) {
1210                 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
1211         }
1212
1213         /* Stops all mc clients */
1214         r100_mc_stop(rdev, &save);
1215         if (rdev->flags & RADEON_IS_AGP) {
1216                 WREG32(R_00014C_MC_AGP_LOCATION,
1217                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
1218                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
1219                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
1220                 WREG32(R_00015C_AGP_BASE_2,
1221                         upper_32_bits(rdev->mc.agp_base) & 0xff);
1222         } else {
1223                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
1224                 WREG32(R_000170_AGP_BASE, 0);
1225                 WREG32(R_00015C_AGP_BASE_2, 0);
1226         }
1227         /* Wait for mc idle */
1228         if (r300_mc_wait_for_idle(rdev))
1229                 DRM_INFO("Failed to wait MC idle before programming MC.\n");
1230         /* Program MC, should be a 32bits limited address space */
1231         WREG32(R_000148_MC_FB_LOCATION,
1232                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
1233                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
1234         r100_mc_resume(rdev, &save);
1235 }
1236
1237 void r300_clock_startup(struct radeon_device *rdev)
1238 {
1239         u32 tmp;
1240
1241         if (radeon_dynclks != -1 && radeon_dynclks)
1242                 radeon_legacy_set_clock_gating(rdev, 1);
1243         /* We need to force on some of the block */
1244         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
1245         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
1246         if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380))
1247                 tmp |= S_00000D_FORCE_VAP(1);
1248         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
1249 }
1250
1251 static int r300_startup(struct radeon_device *rdev)
1252 {
1253         int r;
1254
1255         /* set common regs */
1256         r100_set_common_regs(rdev);
1257         /* program mc */
1258         r300_mc_program(rdev);
1259         /* Resume clock */
1260         r300_clock_startup(rdev);
1261         /* Initialize GPU configuration (# pipes, ...) */
1262         r300_gpu_init(rdev);
1263         /* Initialize GART (initialize after TTM so we can allocate
1264          * memory through TTM but finalize after TTM) */
1265         if (rdev->flags & RADEON_IS_PCIE) {
1266                 r = rv370_pcie_gart_enable(rdev);
1267                 if (r)
1268                         return r;
1269         }
1270
1271         if (rdev->family == CHIP_R300 ||
1272             rdev->family == CHIP_R350 ||
1273             rdev->family == CHIP_RV350)
1274                 r100_enable_bm(rdev);
1275
1276         if (rdev->flags & RADEON_IS_PCI) {
1277                 r = r100_pci_gart_enable(rdev);
1278                 if (r)
1279                         return r;
1280         }
1281         /* Enable IRQ */
1282         r100_irq_set(rdev);
1283         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1284         /* 1M ring buffer */
1285         r = r100_cp_init(rdev, 1024 * 1024);
1286         if (r) {
1287                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
1288                 return r;
1289         }
1290         r = r100_wb_init(rdev);
1291         if (r)
1292                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
1293         r = r100_ib_init(rdev);
1294         if (r) {
1295                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
1296                 return r;
1297         }
1298         return 0;
1299 }
1300
1301 int r300_resume(struct radeon_device *rdev)
1302 {
1303         /* Make sur GART are not working */
1304         if (rdev->flags & RADEON_IS_PCIE)
1305                 rv370_pcie_gart_disable(rdev);
1306         if (rdev->flags & RADEON_IS_PCI)
1307                 r100_pci_gart_disable(rdev);
1308         /* Resume clock before doing reset */
1309         r300_clock_startup(rdev);
1310         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1311         if (radeon_gpu_reset(rdev)) {
1312                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1313                         RREG32(R_000E40_RBBM_STATUS),
1314                         RREG32(R_0007C0_CP_STAT));
1315         }
1316         /* post */
1317         radeon_combios_asic_init(rdev->ddev);
1318         /* Resume clock after posting */
1319         r300_clock_startup(rdev);
1320         /* Initialize surface registers */
1321         radeon_surface_init(rdev);
1322         return r300_startup(rdev);
1323 }
1324
1325 int r300_suspend(struct radeon_device *rdev)
1326 {
1327         r100_cp_disable(rdev);
1328         r100_wb_disable(rdev);
1329         r100_irq_disable(rdev);
1330         if (rdev->flags & RADEON_IS_PCIE)
1331                 rv370_pcie_gart_disable(rdev);
1332         if (rdev->flags & RADEON_IS_PCI)
1333                 r100_pci_gart_disable(rdev);
1334         return 0;
1335 }
1336
1337 void r300_fini(struct radeon_device *rdev)
1338 {
1339         radeon_pm_fini(rdev);
1340         r100_cp_fini(rdev);
1341         r100_wb_fini(rdev);
1342         r100_ib_fini(rdev);
1343         radeon_gem_fini(rdev);
1344         if (rdev->flags & RADEON_IS_PCIE)
1345                 rv370_pcie_gart_fini(rdev);
1346         if (rdev->flags & RADEON_IS_PCI)
1347                 r100_pci_gart_fini(rdev);
1348         radeon_agp_fini(rdev);
1349         radeon_irq_kms_fini(rdev);
1350         radeon_fence_driver_fini(rdev);
1351         radeon_bo_fini(rdev);
1352         radeon_atombios_fini(rdev);
1353         kfree(rdev->bios);
1354         rdev->bios = NULL;
1355 }
1356
1357 int r300_init(struct radeon_device *rdev)
1358 {
1359         int r;
1360
1361         /* Disable VGA */
1362         r100_vga_render_disable(rdev);
1363         /* Initialize scratch registers */
1364         radeon_scratch_init(rdev);
1365         /* Initialize surface registers */
1366         radeon_surface_init(rdev);
1367         /* TODO: disable VGA need to use VGA request */
1368         /* BIOS*/
1369         if (!radeon_get_bios(rdev)) {
1370                 if (ASIC_IS_AVIVO(rdev))
1371                         return -EINVAL;
1372         }
1373         if (rdev->is_atom_bios) {
1374                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
1375                 return -EINVAL;
1376         } else {
1377                 r = radeon_combios_init(rdev);
1378                 if (r)
1379                         return r;
1380         }
1381         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1382         if (radeon_gpu_reset(rdev)) {
1383                 dev_warn(rdev->dev,
1384                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1385                         RREG32(R_000E40_RBBM_STATUS),
1386                         RREG32(R_0007C0_CP_STAT));
1387         }
1388         /* check if cards are posted or not */
1389         if (radeon_boot_test_post_card(rdev) == false)
1390                 return -EINVAL;
1391         /* Set asic errata */
1392         r300_errata(rdev);
1393         /* Initialize clocks */
1394         radeon_get_clock_info(rdev->ddev);
1395         /* Initialize power management */
1396         radeon_pm_init(rdev);
1397         /* initialize AGP */
1398         if (rdev->flags & RADEON_IS_AGP) {
1399                 r = radeon_agp_init(rdev);
1400                 if (r) {
1401                         radeon_agp_disable(rdev);
1402                 }
1403         }
1404         /* initialize memory controller */
1405         r300_mc_init(rdev);
1406         /* Fence driver */
1407         r = radeon_fence_driver_init(rdev);
1408         if (r)
1409                 return r;
1410         r = radeon_irq_kms_init(rdev);
1411         if (r)
1412                 return r;
1413         /* Memory manager */
1414         r = radeon_bo_init(rdev);
1415         if (r)
1416                 return r;
1417         if (rdev->flags & RADEON_IS_PCIE) {
1418                 r = rv370_pcie_gart_init(rdev);
1419                 if (r)
1420                         return r;
1421         }
1422         if (rdev->flags & RADEON_IS_PCI) {
1423                 r = r100_pci_gart_init(rdev);
1424                 if (r)
1425                         return r;
1426         }
1427         r300_set_reg_safe(rdev);
1428         rdev->accel_working = true;
1429         r = r300_startup(rdev);
1430         if (r) {
1431                 /* Somethings want wront with the accel init stop accel */
1432                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1433                 r100_cp_fini(rdev);
1434                 r100_wb_fini(rdev);
1435                 r100_ib_fini(rdev);
1436                 radeon_irq_kms_fini(rdev);
1437                 if (rdev->flags & RADEON_IS_PCIE)
1438                         rv370_pcie_gart_fini(rdev);
1439                 if (rdev->flags & RADEON_IS_PCI)
1440                         r100_pci_gart_fini(rdev);
1441                 radeon_agp_fini(rdev);
1442                 rdev->accel_working = false;
1443         }
1444         return 0;
1445 }