drm/radeon/kms: fix some GART table entry bugs.
[linux-2.6.git] / drivers / gpu / drm / radeon / r300.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/seq_file.h>
29 #include "drmP.h"
30 #include "drm.h"
31 #include "radeon_reg.h"
32 #include "radeon.h"
33
34 /* r300,r350,rv350,rv370,rv380 depends on : */
35 void r100_hdp_reset(struct radeon_device *rdev);
36 int r100_cp_reset(struct radeon_device *rdev);
37 int r100_rb2d_reset(struct radeon_device *rdev);
38 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
39 int r100_pci_gart_enable(struct radeon_device *rdev);
40 void r100_pci_gart_disable(struct radeon_device *rdev);
41 void r100_mc_setup(struct radeon_device *rdev);
42 void r100_mc_disable_clients(struct radeon_device *rdev);
43 int r100_gui_wait_for_idle(struct radeon_device *rdev);
44 int r100_cs_packet_parse(struct radeon_cs_parser *p,
45                          struct radeon_cs_packet *pkt,
46                          unsigned idx);
47 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
48                               struct radeon_cs_reloc **cs_reloc);
49 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
50                           struct radeon_cs_packet *pkt,
51                           const unsigned *auth, unsigned n,
52                           radeon_packet0_check_t check);
53 void r100_cs_dump_packet(struct radeon_cs_parser *p,
54                          struct radeon_cs_packet *pkt);
55 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
56                                          struct radeon_cs_packet *pkt,
57                                          struct radeon_object *robj);
58
59 /* This files gather functions specifics to:
60  * r300,r350,rv350,rv370,rv380
61  *
62  * Some of these functions might be used by newer ASICs.
63  */
64 void r300_gpu_init(struct radeon_device *rdev);
65 int r300_mc_wait_for_idle(struct radeon_device *rdev);
66 int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
67
68
69 /*
70  * rv370,rv380 PCIE GART
71  */
72 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
73 {
74         uint32_t tmp;
75         int i;
76
77         /* Workaround HW bug do flush 2 times */
78         for (i = 0; i < 2; i++) {
79                 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
80                 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
81                 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
82                 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
83                 mb();
84         }
85 }
86
87 int rv370_pcie_gart_enable(struct radeon_device *rdev)
88 {
89         uint32_t table_addr;
90         uint32_t tmp;
91         int r;
92
93         /* Initialize common gart structure */
94         r = radeon_gart_init(rdev);
95         if (r) {
96                 return r;
97         }
98         r = rv370_debugfs_pcie_gart_info_init(rdev);
99         if (r) {
100                 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
101         }
102         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
103         r = radeon_gart_table_vram_alloc(rdev);
104         if (r) {
105                 return r;
106         }
107         /* discard memory request outside of configured range */
108         tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
109         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
110         WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_location);
111         tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 4096;
112         WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
113         WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
114         WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
115         table_addr = rdev->gart.table_addr;
116         WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
117         /* FIXME: setup default page */
118         WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_location);
119         WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
120         /* Clear error */
121         WREG32_PCIE(0x18, 0);
122         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
123         tmp |= RADEON_PCIE_TX_GART_EN;
124         tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
125         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
126         rv370_pcie_gart_tlb_flush(rdev);
127         DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
128                  rdev->mc.gtt_size >> 20, table_addr);
129         rdev->gart.ready = true;
130         return 0;
131 }
132
133 void rv370_pcie_gart_disable(struct radeon_device *rdev)
134 {
135         uint32_t tmp;
136
137         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
138         tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
139         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
140         if (rdev->gart.table.vram.robj) {
141                 radeon_object_kunmap(rdev->gart.table.vram.robj);
142                 radeon_object_unpin(rdev->gart.table.vram.robj);
143         }
144 }
145
146 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
147 {
148         void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
149
150         if (i < 0 || i > rdev->gart.num_gpu_pages) {
151                 return -EINVAL;
152         }
153         addr = (lower_32_bits(addr) >> 8) |
154                ((upper_32_bits(addr) & 0xff) << 24) |
155                0xc;
156         writel(cpu_to_le32(addr), ((void __iomem *)ptr) + (i * 4));
157         return 0;
158 }
159
160 int r300_gart_enable(struct radeon_device *rdev)
161 {
162 #if __OS_HAS_AGP
163         if (rdev->flags & RADEON_IS_AGP) {
164                 if (rdev->family > CHIP_RV350) {
165                         rv370_pcie_gart_disable(rdev);
166                 } else {
167                         r100_pci_gart_disable(rdev);
168                 }
169                 return 0;
170         }
171 #endif
172         if (rdev->flags & RADEON_IS_PCIE) {
173                 rdev->asic->gart_disable = &rv370_pcie_gart_disable;
174                 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
175                 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
176                 return rv370_pcie_gart_enable(rdev);
177         }
178         return r100_pci_gart_enable(rdev);
179 }
180
181
182 /*
183  * MC
184  */
185 int r300_mc_init(struct radeon_device *rdev)
186 {
187         int r;
188
189         if (r100_debugfs_rbbm_init(rdev)) {
190                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
191         }
192
193         r300_gpu_init(rdev);
194         r100_pci_gart_disable(rdev);
195         if (rdev->flags & RADEON_IS_PCIE) {
196                 rv370_pcie_gart_disable(rdev);
197         }
198
199         /* Setup GPU memory space */
200         rdev->mc.vram_location = 0xFFFFFFFFUL;
201         rdev->mc.gtt_location = 0xFFFFFFFFUL;
202         if (rdev->flags & RADEON_IS_AGP) {
203                 r = radeon_agp_init(rdev);
204                 if (r) {
205                         printk(KERN_WARNING "[drm] Disabling AGP\n");
206                         rdev->flags &= ~RADEON_IS_AGP;
207                         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
208                 } else {
209                         rdev->mc.gtt_location = rdev->mc.agp_base;
210                 }
211         }
212         r = radeon_mc_setup(rdev);
213         if (r) {
214                 return r;
215         }
216
217         /* Program GPU memory space */
218         r100_mc_disable_clients(rdev);
219         if (r300_mc_wait_for_idle(rdev)) {
220                 printk(KERN_WARNING "Failed to wait MC idle while "
221                        "programming pipes. Bad things might happen.\n");
222         }
223         r100_mc_setup(rdev);
224         return 0;
225 }
226
227 void r300_mc_fini(struct radeon_device *rdev)
228 {
229         if (rdev->flags & RADEON_IS_PCIE) {
230                 rv370_pcie_gart_disable(rdev);
231                 radeon_gart_table_vram_free(rdev);
232         } else {
233                 r100_pci_gart_disable(rdev);
234                 radeon_gart_table_ram_free(rdev);
235         }
236         radeon_gart_fini(rdev);
237 }
238
239
240 /*
241  * Fence emission
242  */
243 void r300_fence_ring_emit(struct radeon_device *rdev,
244                           struct radeon_fence *fence)
245 {
246         /* Who ever call radeon_fence_emit should call ring_lock and ask
247          * for enough space (today caller are ib schedule and buffer move) */
248         /* Write SC register so SC & US assert idle */
249         radeon_ring_write(rdev, PACKET0(0x43E0, 0));
250         radeon_ring_write(rdev, 0);
251         radeon_ring_write(rdev, PACKET0(0x43E4, 0));
252         radeon_ring_write(rdev, 0);
253         /* Flush 3D cache */
254         radeon_ring_write(rdev, PACKET0(0x4E4C, 0));
255         radeon_ring_write(rdev, (2 << 0));
256         radeon_ring_write(rdev, PACKET0(0x4F18, 0));
257         radeon_ring_write(rdev, (1 << 0));
258         /* Wait until IDLE & CLEAN */
259         radeon_ring_write(rdev, PACKET0(0x1720, 0));
260         radeon_ring_write(rdev, (1 << 17) | (1 << 16)  | (1 << 9));
261         /* Emit fence sequence & fire IRQ */
262         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
263         radeon_ring_write(rdev, fence->seq);
264         radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
265         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
266 }
267
268
269 /*
270  * Global GPU functions
271  */
272 int r300_copy_dma(struct radeon_device *rdev,
273                   uint64_t src_offset,
274                   uint64_t dst_offset,
275                   unsigned num_pages,
276                   struct radeon_fence *fence)
277 {
278         uint32_t size;
279         uint32_t cur_size;
280         int i, num_loops;
281         int r = 0;
282
283         /* radeon pitch is /64 */
284         size = num_pages << PAGE_SHIFT;
285         num_loops = DIV_ROUND_UP(size, 0x1FFFFF);
286         r = radeon_ring_lock(rdev, num_loops * 4 + 64);
287         if (r) {
288                 DRM_ERROR("radeon: moving bo (%d).\n", r);
289                 return r;
290         }
291         /* Must wait for 2D idle & clean before DMA or hangs might happen */
292         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0 ));
293         radeon_ring_write(rdev, (1 << 16));
294         for (i = 0; i < num_loops; i++) {
295                 cur_size = size;
296                 if (cur_size > 0x1FFFFF) {
297                         cur_size = 0x1FFFFF;
298                 }
299                 size -= cur_size;
300                 radeon_ring_write(rdev, PACKET0(0x720, 2));
301                 radeon_ring_write(rdev, src_offset);
302                 radeon_ring_write(rdev, dst_offset);
303                 radeon_ring_write(rdev, cur_size | (1 << 31) | (1 << 30));
304                 src_offset += cur_size;
305                 dst_offset += cur_size;
306         }
307         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
308         radeon_ring_write(rdev, RADEON_WAIT_DMA_GUI_IDLE);
309         if (fence) {
310                 r = radeon_fence_emit(rdev, fence);
311         }
312         radeon_ring_unlock_commit(rdev);
313         return r;
314 }
315
316 void r300_ring_start(struct radeon_device *rdev)
317 {
318         unsigned gb_tile_config;
319         int r;
320
321         /* Sub pixel 1/12 so we can have 4K rendering according to doc */
322         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
323         switch(rdev->num_gb_pipes) {
324         case 2:
325                 gb_tile_config |= R300_PIPE_COUNT_R300;
326                 break;
327         case 3:
328                 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
329                 break;
330         case 4:
331                 gb_tile_config |= R300_PIPE_COUNT_R420;
332                 break;
333         case 1:
334         default:
335                 gb_tile_config |= R300_PIPE_COUNT_RV350;
336                 break;
337         }
338
339         r = radeon_ring_lock(rdev, 64);
340         if (r) {
341                 return;
342         }
343         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
344         radeon_ring_write(rdev,
345                           RADEON_ISYNC_ANY2D_IDLE3D |
346                           RADEON_ISYNC_ANY3D_IDLE2D |
347                           RADEON_ISYNC_WAIT_IDLEGUI |
348                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
349         radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
350         radeon_ring_write(rdev, gb_tile_config);
351         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
352         radeon_ring_write(rdev,
353                           RADEON_WAIT_2D_IDLECLEAN |
354                           RADEON_WAIT_3D_IDLECLEAN);
355         radeon_ring_write(rdev, PACKET0(0x170C, 0));
356         radeon_ring_write(rdev, 1 << 31);
357         radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
358         radeon_ring_write(rdev, 0);
359         radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
360         radeon_ring_write(rdev, 0);
361         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
362         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
363         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
364         radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
365         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
366         radeon_ring_write(rdev,
367                           RADEON_WAIT_2D_IDLECLEAN |
368                           RADEON_WAIT_3D_IDLECLEAN);
369         radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
370         radeon_ring_write(rdev, 0);
371         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
372         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
373         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
374         radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
375         radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
376         radeon_ring_write(rdev,
377                           ((6 << R300_MS_X0_SHIFT) |
378                            (6 << R300_MS_Y0_SHIFT) |
379                            (6 << R300_MS_X1_SHIFT) |
380                            (6 << R300_MS_Y1_SHIFT) |
381                            (6 << R300_MS_X2_SHIFT) |
382                            (6 << R300_MS_Y2_SHIFT) |
383                            (6 << R300_MSBD0_Y_SHIFT) |
384                            (6 << R300_MSBD0_X_SHIFT)));
385         radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
386         radeon_ring_write(rdev,
387                           ((6 << R300_MS_X3_SHIFT) |
388                            (6 << R300_MS_Y3_SHIFT) |
389                            (6 << R300_MS_X4_SHIFT) |
390                            (6 << R300_MS_Y4_SHIFT) |
391                            (6 << R300_MS_X5_SHIFT) |
392                            (6 << R300_MS_Y5_SHIFT) |
393                            (6 << R300_MSBD1_SHIFT)));
394         radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
395         radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
396         radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
397         radeon_ring_write(rdev,
398                           R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
399         radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
400         radeon_ring_write(rdev,
401                           R300_GEOMETRY_ROUND_NEAREST |
402                           R300_COLOR_ROUND_NEAREST);
403         radeon_ring_unlock_commit(rdev);
404 }
405
406 void r300_errata(struct radeon_device *rdev)
407 {
408         rdev->pll_errata = 0;
409
410         if (rdev->family == CHIP_R300 &&
411             (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
412                 rdev->pll_errata |= CHIP_ERRATA_R300_CG;
413         }
414 }
415
416 int r300_mc_wait_for_idle(struct radeon_device *rdev)
417 {
418         unsigned i;
419         uint32_t tmp;
420
421         for (i = 0; i < rdev->usec_timeout; i++) {
422                 /* read MC_STATUS */
423                 tmp = RREG32(0x0150);
424                 if (tmp & (1 << 4)) {
425                         return 0;
426                 }
427                 DRM_UDELAY(1);
428         }
429         return -1;
430 }
431
432 void r300_gpu_init(struct radeon_device *rdev)
433 {
434         uint32_t gb_tile_config, tmp;
435
436         r100_hdp_reset(rdev);
437         /* FIXME: rv380 one pipes ? */
438         if ((rdev->family == CHIP_R300) || (rdev->family == CHIP_R350)) {
439                 /* r300,r350 */
440                 rdev->num_gb_pipes = 2;
441         } else {
442                 /* rv350,rv370,rv380 */
443                 rdev->num_gb_pipes = 1;
444         }
445         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
446         switch (rdev->num_gb_pipes) {
447         case 2:
448                 gb_tile_config |= R300_PIPE_COUNT_R300;
449                 break;
450         case 3:
451                 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
452                 break;
453         case 4:
454                 gb_tile_config |= R300_PIPE_COUNT_R420;
455                 break;
456         default:
457         case 1:
458                 gb_tile_config |= R300_PIPE_COUNT_RV350;
459                 break;
460         }
461         WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
462
463         if (r100_gui_wait_for_idle(rdev)) {
464                 printk(KERN_WARNING "Failed to wait GUI idle while "
465                        "programming pipes. Bad things might happen.\n");
466         }
467
468         tmp = RREG32(0x170C);
469         WREG32(0x170C, tmp | (1 << 31));
470
471         WREG32(R300_RB2D_DSTCACHE_MODE,
472                R300_DC_AUTOFLUSH_ENABLE |
473                R300_DC_DC_DISABLE_IGNORE_PE);
474
475         if (r100_gui_wait_for_idle(rdev)) {
476                 printk(KERN_WARNING "Failed to wait GUI idle while "
477                        "programming pipes. Bad things might happen.\n");
478         }
479         if (r300_mc_wait_for_idle(rdev)) {
480                 printk(KERN_WARNING "Failed to wait MC idle while "
481                        "programming pipes. Bad things might happen.\n");
482         }
483         DRM_INFO("radeon: %d pipes initialized.\n", rdev->num_gb_pipes);
484 }
485
486 int r300_ga_reset(struct radeon_device *rdev)
487 {
488         uint32_t tmp;
489         bool reinit_cp;
490         int i;
491
492         reinit_cp = rdev->cp.ready;
493         rdev->cp.ready = false;
494         for (i = 0; i < rdev->usec_timeout; i++) {
495                 WREG32(RADEON_CP_CSQ_MODE, 0);
496                 WREG32(RADEON_CP_CSQ_CNTL, 0);
497                 WREG32(RADEON_RBBM_SOFT_RESET, 0x32005);
498                 (void)RREG32(RADEON_RBBM_SOFT_RESET);
499                 udelay(200);
500                 WREG32(RADEON_RBBM_SOFT_RESET, 0);
501                 /* Wait to prevent race in RBBM_STATUS */
502                 mdelay(1);
503                 tmp = RREG32(RADEON_RBBM_STATUS);
504                 if (tmp & ((1 << 20) | (1 << 26))) {
505                         DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp);
506                         /* GA still busy soft reset it */
507                         WREG32(0x429C, 0x200);
508                         WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0);
509                         WREG32(0x43E0, 0);
510                         WREG32(0x43E4, 0);
511                         WREG32(0x24AC, 0);
512                 }
513                 /* Wait to prevent race in RBBM_STATUS */
514                 mdelay(1);
515                 tmp = RREG32(RADEON_RBBM_STATUS);
516                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
517                         break;
518                 }
519         }
520         for (i = 0; i < rdev->usec_timeout; i++) {
521                 tmp = RREG32(RADEON_RBBM_STATUS);
522                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
523                         DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
524                                  tmp);
525                         if (reinit_cp) {
526                                 return r100_cp_init(rdev, rdev->cp.ring_size);
527                         }
528                         return 0;
529                 }
530                 DRM_UDELAY(1);
531         }
532         tmp = RREG32(RADEON_RBBM_STATUS);
533         DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
534         return -1;
535 }
536
537 int r300_gpu_reset(struct radeon_device *rdev)
538 {
539         uint32_t status;
540
541         /* reset order likely matter */
542         status = RREG32(RADEON_RBBM_STATUS);
543         /* reset HDP */
544         r100_hdp_reset(rdev);
545         /* reset rb2d */
546         if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
547                 r100_rb2d_reset(rdev);
548         }
549         /* reset GA */
550         if (status & ((1 << 20) | (1 << 26))) {
551                 r300_ga_reset(rdev);
552         }
553         /* reset CP */
554         status = RREG32(RADEON_RBBM_STATUS);
555         if (status & (1 << 16)) {
556                 r100_cp_reset(rdev);
557         }
558         /* Check if GPU is idle */
559         status = RREG32(RADEON_RBBM_STATUS);
560         if (status & (1 << 31)) {
561                 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
562                 return -1;
563         }
564         DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
565         return 0;
566 }
567
568
569 /*
570  * r300,r350,rv350,rv380 VRAM info
571  */
572 void r300_vram_info(struct radeon_device *rdev)
573 {
574         uint32_t tmp;
575
576         /* DDR for all card after R300 & IGP */
577         rdev->mc.vram_is_ddr = true;
578         tmp = RREG32(RADEON_MEM_CNTL);
579         if (tmp & R300_MEM_NUM_CHANNELS_MASK) {
580                 rdev->mc.vram_width = 128;
581         } else {
582                 rdev->mc.vram_width = 64;
583         }
584         rdev->mc.vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
585
586         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
587         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
588 }
589
590
591 /*
592  * Indirect registers accessor
593  */
594 uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
595 {
596         uint32_t r;
597
598         WREG8(RADEON_PCIE_INDEX, ((reg) & 0xff));
599         (void)RREG32(RADEON_PCIE_INDEX);
600         r = RREG32(RADEON_PCIE_DATA);
601         return r;
602 }
603
604 void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
605 {
606         WREG8(RADEON_PCIE_INDEX, ((reg) & 0xff));
607         (void)RREG32(RADEON_PCIE_INDEX);
608         WREG32(RADEON_PCIE_DATA, (v));
609         (void)RREG32(RADEON_PCIE_DATA);
610 }
611
612 /*
613  * PCIE Lanes
614  */
615
616 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
617 {
618         uint32_t link_width_cntl, mask;
619
620         if (rdev->flags & RADEON_IS_IGP)
621                 return;
622
623         if (!(rdev->flags & RADEON_IS_PCIE))
624                 return;
625
626         /* FIXME wait for idle */
627
628         switch (lanes) {
629         case 0:
630                 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
631                 break;
632         case 1:
633                 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
634                 break;
635         case 2:
636                 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
637                 break;
638         case 4:
639                 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
640                 break;
641         case 8:
642                 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
643                 break;
644         case 12:
645                 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
646                 break;
647         case 16:
648         default:
649                 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
650                 break;
651         }
652
653         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
654
655         if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
656             (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
657                 return;
658
659         link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
660                              RADEON_PCIE_LC_RECONFIG_NOW |
661                              RADEON_PCIE_LC_RECONFIG_LATER |
662                              RADEON_PCIE_LC_SHORT_RECONFIG_EN);
663         link_width_cntl |= mask;
664         WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
665         WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
666                                                      RADEON_PCIE_LC_RECONFIG_NOW));
667
668         /* wait for lane set to complete */
669         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
670         while (link_width_cntl == 0xffffffff)
671                 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
672
673 }
674
675
676 /*
677  * Debugfs info
678  */
679 #if defined(CONFIG_DEBUG_FS)
680 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data)
681 {
682         struct drm_info_node *node = (struct drm_info_node *) m->private;
683         struct drm_device *dev = node->minor->dev;
684         struct radeon_device *rdev = dev->dev_private;
685         uint32_t tmp;
686
687         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
688         seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
689         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
690         seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
691         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
692         seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
693         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
694         seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
695         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
696         seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
697         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
698         seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
699         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
700         seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
701         return 0;
702 }
703
704 static struct drm_info_list rv370_pcie_gart_info_list[] = {
705         {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
706 };
707 #endif
708
709 int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
710 {
711 #if defined(CONFIG_DEBUG_FS)
712         return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
713 #else
714         return 0;
715 #endif
716 }
717
718
719 /*
720  * CS functions
721  */
722 struct r300_cs_track_cb {
723         struct radeon_object    *robj;
724         unsigned                pitch;
725         unsigned                cpp;
726         unsigned                offset;
727 };
728
729 struct r300_cs_track_array {
730         struct radeon_object    *robj;
731         unsigned                esize;
732 };
733
734 struct r300_cs_track_texture {
735         struct radeon_object    *robj;
736         unsigned                pitch;
737         unsigned                width;
738         unsigned                height;
739         unsigned                num_levels;
740         unsigned                cpp;
741         unsigned                tex_coord_type;
742         unsigned                txdepth;
743         unsigned                width_11;
744         unsigned                height_11;
745         bool                    use_pitch;
746         bool                    enabled;
747         bool                    roundup_w;
748         bool                    roundup_h;
749 };
750
751 struct r300_cs_track {
752         unsigned                        num_cb;
753         unsigned                        maxy;
754         unsigned                        vtx_size;
755         unsigned                        vap_vf_cntl;
756         unsigned                        immd_dwords;
757         unsigned                        num_arrays;
758         unsigned                        max_indx;
759         struct r300_cs_track_array      arrays[11];
760         struct r300_cs_track_cb         cb[4];
761         struct r300_cs_track_cb         zb;
762         struct r300_cs_track_texture    textures[16];
763         bool                            z_enabled;
764 };
765
766 static inline void r300_cs_track_texture_print(struct r300_cs_track_texture *t)
767 {
768         DRM_ERROR("pitch                      %d\n", t->pitch);
769         DRM_ERROR("width                      %d\n", t->width);
770         DRM_ERROR("height                     %d\n", t->height);
771         DRM_ERROR("num levels                 %d\n", t->num_levels);
772         DRM_ERROR("depth                      %d\n", t->txdepth);
773         DRM_ERROR("bpp                        %d\n", t->cpp);
774         DRM_ERROR("coordinate type            %d\n", t->tex_coord_type);
775         DRM_ERROR("width round to power of 2  %d\n", t->roundup_w);
776         DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
777 }
778
779 static inline int r300_cs_track_texture_check(struct radeon_device *rdev,
780                                               struct r300_cs_track *track)
781 {
782         struct radeon_object *robj;
783         unsigned long size;
784         unsigned u, i, w, h;
785
786         for (u = 0; u < 16; u++) {
787                 if (!track->textures[u].enabled)
788                         continue;
789                 robj = track->textures[u].robj;
790                 if (robj == NULL) {
791                         DRM_ERROR("No texture bound to unit %u\n", u);
792                         return -EINVAL;
793                 }
794                 size = 0;
795                 for (i = 0; i <= track->textures[u].num_levels; i++) {
796                         if (track->textures[u].use_pitch) {
797                                 w = track->textures[u].pitch / (1 << i);
798                         } else {
799                                 w = track->textures[u].width / (1 << i);
800                                 if (rdev->family >= CHIP_RV515)
801                                         w |= track->textures[u].width_11;
802                                 if (track->textures[u].roundup_w)
803                                         w = roundup_pow_of_two(w);
804                         }
805                         h = track->textures[u].height / (1 << i);
806                         if (rdev->family >= CHIP_RV515)
807                                 h |= track->textures[u].height_11;
808                         if (track->textures[u].roundup_h)
809                                 h = roundup_pow_of_two(h);
810                         size += w * h;
811                 }
812                 size *= track->textures[u].cpp;
813                 switch (track->textures[u].tex_coord_type) {
814                 case 0:
815                         break;
816                 case 1:
817                         size *= (1 << track->textures[u].txdepth);
818                         break;
819                 case 2:
820                         size *= 6;
821                         break;
822                 default:
823                         DRM_ERROR("Invalid texture coordinate type %u for unit "
824                                   "%u\n", track->textures[u].tex_coord_type, u);
825                         return -EINVAL;
826                 }
827                 if (size > radeon_object_size(robj)) {
828                         DRM_ERROR("Texture of unit %u needs %lu bytes but is "
829                                   "%lu\n", u, size, radeon_object_size(robj));
830                         r300_cs_track_texture_print(&track->textures[u]);
831                         return -EINVAL;
832                 }
833         }
834         return 0;
835 }
836
837 int r300_cs_track_check(struct radeon_device *rdev, struct r300_cs_track *track)
838 {
839         unsigned i;
840         unsigned long size;
841         unsigned prim_walk;
842         unsigned nverts;
843
844         for (i = 0; i < track->num_cb; i++) {
845                 if (track->cb[i].robj == NULL) {
846                         DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
847                         return -EINVAL;
848                 }
849                 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
850                 size += track->cb[i].offset;
851                 if (size > radeon_object_size(track->cb[i].robj)) {
852                         DRM_ERROR("[drm] Buffer too small for color buffer %d "
853                                   "(need %lu have %lu) !\n", i, size,
854                                   radeon_object_size(track->cb[i].robj));
855                         DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
856                                   i, track->cb[i].pitch, track->cb[i].cpp,
857                                   track->cb[i].offset, track->maxy);
858                         return -EINVAL;
859                 }
860         }
861         if (track->z_enabled) {
862                 if (track->zb.robj == NULL) {
863                         DRM_ERROR("[drm] No buffer for z buffer !\n");
864                         return -EINVAL;
865                 }
866                 size = track->zb.pitch * track->zb.cpp * track->maxy;
867                 size += track->zb.offset;
868                 if (size > radeon_object_size(track->zb.robj)) {
869                         DRM_ERROR("[drm] Buffer too small for z buffer "
870                                   "(need %lu have %lu) !\n", size,
871                                   radeon_object_size(track->zb.robj));
872                         return -EINVAL;
873                 }
874         }
875         prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
876         nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
877         switch (prim_walk) {
878         case 1:
879                 for (i = 0; i < track->num_arrays; i++) {
880                         size = track->arrays[i].esize * track->max_indx * 4;
881                         if (track->arrays[i].robj == NULL) {
882                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
883                                           "bound\n", prim_walk, i);
884                                 return -EINVAL;
885                         }
886                         if (size > radeon_object_size(track->arrays[i].robj)) {
887                                 DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
888                                            "have %lu dwords\n", prim_walk, i,
889                                            size >> 2,
890                                            radeon_object_size(track->arrays[i].robj) >> 2);
891                                 DRM_ERROR("Max indices %u\n", track->max_indx);
892                                 return -EINVAL;
893                         }
894                 }
895                 break;
896         case 2:
897                 for (i = 0; i < track->num_arrays; i++) {
898                         size = track->arrays[i].esize * (nverts - 1) * 4;
899                         if (track->arrays[i].robj == NULL) {
900                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
901                                           "bound\n", prim_walk, i);
902                                 return -EINVAL;
903                         }
904                         if (size > radeon_object_size(track->arrays[i].robj)) {
905                                 DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
906                                            "have %lu dwords\n", prim_walk, i, size >> 2,
907                                            radeon_object_size(track->arrays[i].robj) >> 2);
908                                 return -EINVAL;
909                         }
910                 }
911                 break;
912         case 3:
913                 size = track->vtx_size * nverts;
914                 if (size != track->immd_dwords) {
915                         DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
916                                   track->immd_dwords, size);
917                         DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
918                                   nverts, track->vtx_size);
919                         return -EINVAL;
920                 }
921                 break;
922         default:
923                 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
924                           prim_walk);
925                 return -EINVAL;
926         }
927         return r300_cs_track_texture_check(rdev, track);
928 }
929
930 static inline void r300_cs_track_clear(struct r300_cs_track *track)
931 {
932         unsigned i;
933
934         track->num_cb = 4;
935         track->maxy = 4096;
936         for (i = 0; i < track->num_cb; i++) {
937                 track->cb[i].robj = NULL;
938                 track->cb[i].pitch = 8192;
939                 track->cb[i].cpp = 16;
940                 track->cb[i].offset = 0;
941         }
942         track->z_enabled = true;
943         track->zb.robj = NULL;
944         track->zb.pitch = 8192;
945         track->zb.cpp = 4;
946         track->zb.offset = 0;
947         track->vtx_size = 0x7F;
948         track->immd_dwords = 0xFFFFFFFFUL;
949         track->num_arrays = 11;
950         track->max_indx = 0x00FFFFFFUL;
951         for (i = 0; i < track->num_arrays; i++) {
952                 track->arrays[i].robj = NULL;
953                 track->arrays[i].esize = 0x7F;
954         }
955         for (i = 0; i < 16; i++) {
956                 track->textures[i].pitch = 16536;
957                 track->textures[i].width = 16536;
958                 track->textures[i].height = 16536;
959                 track->textures[i].width_11 = 1 << 11;
960                 track->textures[i].height_11 = 1 << 11;
961                 track->textures[i].num_levels = 12;
962                 track->textures[i].txdepth = 16;
963                 track->textures[i].cpp = 64;
964                 track->textures[i].tex_coord_type = 1;
965                 track->textures[i].robj = NULL;
966                 /* CS IB emission code makes sure texture unit are disabled */
967                 track->textures[i].enabled = false;
968                 track->textures[i].roundup_w = true;
969                 track->textures[i].roundup_h = true;
970         }
971 }
972
973 static const unsigned r300_reg_safe_bm[159] = {
974         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
975         0xFFFFFFBF, 0xFFFFFFFF, 0xFFFFFFBF, 0xFFFFFFFF,
976         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
977         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
978         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
979         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
980         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
981         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
982         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
983         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
984         0x17FF1FFF, 0xFFFFFFFC, 0xFFFFFFFF, 0xFF30FFBF,
985         0xFFFFFFF8, 0xC3E6FFFF, 0xFFFFF6DF, 0xFFFFFFFF,
986         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
987         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
988         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFF03F,
989         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
990         0xFFFFFFFF, 0xFFFFEFCE, 0xF00EBFFF, 0x007C0000,
991         0xF0000078, 0xFF000009, 0xFFFFFFFF, 0xFFFFFFFF,
992         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
993         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
994         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
995         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
996         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
997         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
998         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
999         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
1000         0xFFFFF7FF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
1001         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
1002         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
1003         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
1004         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
1005         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
1006         0xFFFFFC78, 0xFFFFFFFF, 0xFFFFFFFE, 0xFFFFFFFF,
1007         0x38FF8F50, 0xFFF88082, 0xF000000C, 0xFAE009FF,
1008         0x0000FFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000000,
1009         0x00000000, 0x0000C100, 0x00000000, 0x00000000,
1010         0x00000000, 0x00000000, 0x00000000, 0x00000000,
1011         0x00000000, 0xFFFF0000, 0xFFFFFFFF, 0xFF80FFFF,
1012         0x00000000, 0x00000000, 0x00000000, 0x00000000,
1013         0x0003FC01, 0xFFFFFFF8, 0xFE800B19,
1014 };
1015
1016 static int r300_packet0_check(struct radeon_cs_parser *p,
1017                 struct radeon_cs_packet *pkt,
1018                 unsigned idx, unsigned reg)
1019 {
1020         struct radeon_cs_chunk *ib_chunk;
1021         struct radeon_cs_reloc *reloc;
1022         struct r300_cs_track *track;
1023         volatile uint32_t *ib;
1024         uint32_t tmp;
1025         unsigned i;
1026         int r;
1027
1028         ib = p->ib->ptr;
1029         ib_chunk = &p->chunks[p->chunk_ib_idx];
1030         track = (struct r300_cs_track*)p->track;
1031         switch(reg) {
1032         case RADEON_DST_PITCH_OFFSET:
1033         case RADEON_SRC_PITCH_OFFSET:
1034                 r = r100_cs_packet_next_reloc(p, &reloc);
1035                 if (r) {
1036                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1037                                         idx, reg);
1038                         r100_cs_dump_packet(p, pkt);
1039                         return r;
1040                 }
1041                 tmp = ib_chunk->kdata[idx] & 0x003fffff;
1042                 tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
1043                 ib[idx] = (ib_chunk->kdata[idx] & 0xffc00000) | tmp;
1044                 break;
1045         case R300_RB3D_COLOROFFSET0:
1046         case R300_RB3D_COLOROFFSET1:
1047         case R300_RB3D_COLOROFFSET2:
1048         case R300_RB3D_COLOROFFSET3:
1049                 i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
1050                 r = r100_cs_packet_next_reloc(p, &reloc);
1051                 if (r) {
1052                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1053                                         idx, reg);
1054                         r100_cs_dump_packet(p, pkt);
1055                         return r;
1056                 }
1057                 track->cb[i].robj = reloc->robj;
1058                 track->cb[i].offset = ib_chunk->kdata[idx];
1059                 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1060                 break;
1061         case R300_ZB_DEPTHOFFSET:
1062                 r = r100_cs_packet_next_reloc(p, &reloc);
1063                 if (r) {
1064                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1065                                         idx, reg);
1066                         r100_cs_dump_packet(p, pkt);
1067                         return r;
1068                 }
1069                 track->zb.robj = reloc->robj;
1070                 track->zb.offset = ib_chunk->kdata[idx];
1071                 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1072                 break;
1073         case R300_TX_OFFSET_0:
1074         case R300_TX_OFFSET_0+4:
1075         case R300_TX_OFFSET_0+8:
1076         case R300_TX_OFFSET_0+12:
1077         case R300_TX_OFFSET_0+16:
1078         case R300_TX_OFFSET_0+20:
1079         case R300_TX_OFFSET_0+24:
1080         case R300_TX_OFFSET_0+28:
1081         case R300_TX_OFFSET_0+32:
1082         case R300_TX_OFFSET_0+36:
1083         case R300_TX_OFFSET_0+40:
1084         case R300_TX_OFFSET_0+44:
1085         case R300_TX_OFFSET_0+48:
1086         case R300_TX_OFFSET_0+52:
1087         case R300_TX_OFFSET_0+56:
1088         case R300_TX_OFFSET_0+60:
1089                 i = (reg - R300_TX_OFFSET_0) >> 2;
1090                 r = r100_cs_packet_next_reloc(p, &reloc);
1091                 if (r) {
1092                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1093                                         idx, reg);
1094                         r100_cs_dump_packet(p, pkt);
1095                         return r;
1096                 }
1097                 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1098                 track->textures[i].robj = reloc->robj;
1099                 break;
1100         /* Tracked registers */
1101         case 0x2084:
1102                 /* VAP_VF_CNTL */
1103                 track->vap_vf_cntl = ib_chunk->kdata[idx];
1104                 break;
1105         case 0x20B4:
1106                 /* VAP_VTX_SIZE */
1107                 track->vtx_size = ib_chunk->kdata[idx] & 0x7F;
1108                 break;
1109         case 0x2134:
1110                 /* VAP_VF_MAX_VTX_INDX */
1111                 track->max_indx = ib_chunk->kdata[idx] & 0x00FFFFFFUL;
1112                 break;
1113         case 0x43E4:
1114                 /* SC_SCISSOR1 */
1115                 track->maxy = ((ib_chunk->kdata[idx] >> 13) & 0x1FFF) + 1;
1116                 if (p->rdev->family < CHIP_RV515) {
1117                         track->maxy -= 1440;
1118                 }
1119                 break;
1120         case 0x4E00:
1121                 /* RB3D_CCTL */
1122                 track->num_cb = ((ib_chunk->kdata[idx] >> 5) & 0x3) + 1;
1123                 break;
1124         case 0x4E38:
1125         case 0x4E3C:
1126         case 0x4E40:
1127         case 0x4E44:
1128                 /* RB3D_COLORPITCH0 */
1129                 /* RB3D_COLORPITCH1 */
1130                 /* RB3D_COLORPITCH2 */
1131                 /* RB3D_COLORPITCH3 */
1132                 i = (reg - 0x4E38) >> 2;
1133                 track->cb[i].pitch = ib_chunk->kdata[idx] & 0x3FFE;
1134                 switch (((ib_chunk->kdata[idx] >> 21) & 0xF)) {
1135                 case 9:
1136                 case 11:
1137                 case 12:
1138                         track->cb[i].cpp = 1;
1139                         break;
1140                 case 3:
1141                 case 4:
1142                 case 13:
1143                 case 15:
1144                         track->cb[i].cpp = 2;
1145                         break;
1146                 case 6:
1147                         track->cb[i].cpp = 4;
1148                         break;
1149                 case 10:
1150                         track->cb[i].cpp = 8;
1151                         break;
1152                 case 7:
1153                         track->cb[i].cpp = 16;
1154                         break;
1155                 default:
1156                         DRM_ERROR("Invalid color buffer format (%d) !\n",
1157                                   ((ib_chunk->kdata[idx] >> 21) & 0xF));
1158                         return -EINVAL;
1159                 }
1160                 break;
1161         case 0x4F00:
1162                 /* ZB_CNTL */
1163                 if (ib_chunk->kdata[idx] & 2) {
1164                         track->z_enabled = true;
1165                 } else {
1166                         track->z_enabled = false;
1167                 }
1168                 break;
1169         case 0x4F10:
1170                 /* ZB_FORMAT */
1171                 switch ((ib_chunk->kdata[idx] & 0xF)) {
1172                 case 0:
1173                 case 1:
1174                         track->zb.cpp = 2;
1175                         break;
1176                 case 2:
1177                         track->zb.cpp = 4;
1178                         break;
1179                 default:
1180                         DRM_ERROR("Invalid z buffer format (%d) !\n",
1181                                   (ib_chunk->kdata[idx] & 0xF));
1182                         return -EINVAL;
1183                 }
1184                 break;
1185         case 0x4F24:
1186                 /* ZB_DEPTHPITCH */
1187                 track->zb.pitch = ib_chunk->kdata[idx] & 0x3FFC;
1188                 break;
1189         case 0x4104:
1190                 for (i = 0; i < 16; i++) {
1191                         bool enabled;
1192
1193                         enabled = !!(ib_chunk->kdata[idx] & (1 << i));
1194                         track->textures[i].enabled = enabled;
1195                 }
1196                 break;
1197         case 0x44C0:
1198         case 0x44C4:
1199         case 0x44C8:
1200         case 0x44CC:
1201         case 0x44D0:
1202         case 0x44D4:
1203         case 0x44D8:
1204         case 0x44DC:
1205         case 0x44E0:
1206         case 0x44E4:
1207         case 0x44E8:
1208         case 0x44EC:
1209         case 0x44F0:
1210         case 0x44F4:
1211         case 0x44F8:
1212         case 0x44FC:
1213                 /* TX_FORMAT1_[0-15] */
1214                 i = (reg - 0x44C0) >> 2;
1215                 tmp = (ib_chunk->kdata[idx] >> 25) & 0x3;
1216                 track->textures[i].tex_coord_type = tmp;
1217                 switch ((ib_chunk->kdata[idx] & 0x1F)) {
1218                 case 0:
1219                 case 2:
1220                 case 5:
1221                 case 18:
1222                 case 20:
1223                 case 21:
1224                         track->textures[i].cpp = 1;
1225                         break;
1226                 case 1:
1227                 case 3:
1228                 case 6:
1229                 case 7:
1230                 case 10:
1231                 case 11:
1232                 case 19:
1233                 case 22:
1234                 case 24:
1235                         track->textures[i].cpp = 2;
1236                         break;
1237                 case 4:
1238                 case 8:
1239                 case 9:
1240                 case 12:
1241                 case 13:
1242                 case 23:
1243                 case 25:
1244                 case 27:
1245                 case 30:
1246                         track->textures[i].cpp = 4;
1247                         break;
1248                 case 14:
1249                 case 26:
1250                 case 28:
1251                         track->textures[i].cpp = 8;
1252                         break;
1253                 case 29:
1254                         track->textures[i].cpp = 16;
1255                         break;
1256                 default:
1257                         DRM_ERROR("Invalid texture format %u\n",
1258                                   (ib_chunk->kdata[idx] & 0x1F));
1259                         return -EINVAL;
1260                         break;
1261                 }
1262                 break;
1263         case 0x4400:
1264         case 0x4404:
1265         case 0x4408:
1266         case 0x440C:
1267         case 0x4410:
1268         case 0x4414:
1269         case 0x4418:
1270         case 0x441C:
1271         case 0x4420:
1272         case 0x4424:
1273         case 0x4428:
1274         case 0x442C:
1275         case 0x4430:
1276         case 0x4434:
1277         case 0x4438:
1278         case 0x443C:
1279                 /* TX_FILTER0_[0-15] */
1280                 i = (reg - 0x4400) >> 2;
1281                 tmp = ib_chunk->kdata[idx] & 0x7;;
1282                 if (tmp == 2 || tmp == 4 || tmp == 6) {
1283                         track->textures[i].roundup_w = false;
1284                 }
1285                 tmp = (ib_chunk->kdata[idx] >> 3) & 0x7;;
1286                 if (tmp == 2 || tmp == 4 || tmp == 6) {
1287                         track->textures[i].roundup_h = false;
1288                 }
1289                 break;
1290         case 0x4500:
1291         case 0x4504:
1292         case 0x4508:
1293         case 0x450C:
1294         case 0x4510:
1295         case 0x4514:
1296         case 0x4518:
1297         case 0x451C:
1298         case 0x4520:
1299         case 0x4524:
1300         case 0x4528:
1301         case 0x452C:
1302         case 0x4530:
1303         case 0x4534:
1304         case 0x4538:
1305         case 0x453C:
1306                 /* TX_FORMAT2_[0-15] */
1307                 i = (reg - 0x4500) >> 2;
1308                 tmp = ib_chunk->kdata[idx] & 0x3FFF;
1309                 track->textures[i].pitch = tmp + 1;
1310                 if (p->rdev->family >= CHIP_RV515) {
1311                         tmp = ((ib_chunk->kdata[idx] >> 15) & 1) << 11;
1312                         track->textures[i].width_11 = tmp;
1313                         tmp = ((ib_chunk->kdata[idx] >> 16) & 1) << 11;
1314                         track->textures[i].height_11 = tmp;
1315                 }
1316                 break;
1317         case 0x4480:
1318         case 0x4484:
1319         case 0x4488:
1320         case 0x448C:
1321         case 0x4490:
1322         case 0x4494:
1323         case 0x4498:
1324         case 0x449C:
1325         case 0x44A0:
1326         case 0x44A4:
1327         case 0x44A8:
1328         case 0x44AC:
1329         case 0x44B0:
1330         case 0x44B4:
1331         case 0x44B8:
1332         case 0x44BC:
1333                 /* TX_FORMAT0_[0-15] */
1334                 i = (reg - 0x4480) >> 2;
1335                 tmp = ib_chunk->kdata[idx] & 0x7FF;
1336                 track->textures[i].width = tmp + 1;
1337                 tmp = (ib_chunk->kdata[idx] >> 11) & 0x7FF;
1338                 track->textures[i].height = tmp + 1;
1339                 tmp = (ib_chunk->kdata[idx] >> 26) & 0xF;
1340                 track->textures[i].num_levels = tmp;
1341                 tmp = ib_chunk->kdata[idx] & (1 << 31);
1342                 track->textures[i].use_pitch = !!tmp;
1343                 tmp = (ib_chunk->kdata[idx] >> 22) & 0xF;
1344                 track->textures[i].txdepth = tmp;
1345                 break;
1346         default:
1347                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1348                        reg, idx);
1349                 return -EINVAL;
1350         }
1351         return 0;
1352 }
1353
1354 static int r300_packet3_check(struct radeon_cs_parser *p,
1355                               struct radeon_cs_packet *pkt)
1356 {
1357         struct radeon_cs_chunk *ib_chunk;
1358         struct radeon_cs_reloc *reloc;
1359         struct r300_cs_track *track;
1360         volatile uint32_t *ib;
1361         unsigned idx;
1362         unsigned i, c;
1363         int r;
1364
1365         ib = p->ib->ptr;
1366         ib_chunk = &p->chunks[p->chunk_ib_idx];
1367         idx = pkt->idx + 1;
1368         track = (struct r300_cs_track*)p->track;
1369         switch(pkt->opcode) {
1370         case PACKET3_3D_LOAD_VBPNTR:
1371                 c = ib_chunk->kdata[idx++] & 0x1F;
1372                 track->num_arrays = c;
1373                 for (i = 0; i < (c - 1); i+=2, idx+=3) {
1374                         r = r100_cs_packet_next_reloc(p, &reloc);
1375                         if (r) {
1376                                 DRM_ERROR("No reloc for packet3 %d\n",
1377                                           pkt->opcode);
1378                                 r100_cs_dump_packet(p, pkt);
1379                                 return r;
1380                         }
1381                         ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
1382                         track->arrays[i + 0].robj = reloc->robj;
1383                         track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8;
1384                         track->arrays[i + 0].esize &= 0x7F;
1385                         r = r100_cs_packet_next_reloc(p, &reloc);
1386                         if (r) {
1387                                 DRM_ERROR("No reloc for packet3 %d\n",
1388                                           pkt->opcode);
1389                                 r100_cs_dump_packet(p, pkt);
1390                                 return r;
1391                         }
1392                         ib[idx+2] = ib_chunk->kdata[idx+2] + ((u32)reloc->lobj.gpu_offset);
1393                         track->arrays[i + 1].robj = reloc->robj;
1394                         track->arrays[i + 1].esize = ib_chunk->kdata[idx] >> 24;
1395                         track->arrays[i + 1].esize &= 0x7F;
1396                 }
1397                 if (c & 1) {
1398                         r = r100_cs_packet_next_reloc(p, &reloc);
1399                         if (r) {
1400                                 DRM_ERROR("No reloc for packet3 %d\n",
1401                                           pkt->opcode);
1402                                 r100_cs_dump_packet(p, pkt);
1403                                 return r;
1404                         }
1405                         ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
1406                         track->arrays[i + 0].robj = reloc->robj;
1407                         track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8;
1408                         track->arrays[i + 0].esize &= 0x7F;
1409                 }
1410                 break;
1411         case PACKET3_INDX_BUFFER:
1412                 r = r100_cs_packet_next_reloc(p, &reloc);
1413                 if (r) {
1414                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1415                         r100_cs_dump_packet(p, pkt);
1416                         return r;
1417                 }
1418                 ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
1419                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1420                 if (r) {
1421                         return r;
1422                 }
1423                 break;
1424         /* Draw packet */
1425         case PACKET3_3D_DRAW_IMMD:
1426                 /* Number of dwords is vtx_size * (num_vertices - 1)
1427                  * PRIM_WALK must be equal to 3 vertex data in embedded
1428                  * in cmd stream */
1429                 if (((ib_chunk->kdata[idx+1] >> 4) & 0x3) != 3) {
1430                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1431                         return -EINVAL;
1432                 }
1433                 track->vap_vf_cntl = ib_chunk->kdata[idx+1];
1434                 track->immd_dwords = pkt->count - 1;
1435                 r = r300_cs_track_check(p->rdev, track);
1436                 if (r) {
1437                         return r;
1438                 }
1439                 break;
1440         case PACKET3_3D_DRAW_IMMD_2:
1441                 /* Number of dwords is vtx_size * (num_vertices - 1)
1442                  * PRIM_WALK must be equal to 3 vertex data in embedded
1443                  * in cmd stream */
1444                 if (((ib_chunk->kdata[idx] >> 4) & 0x3) != 3) {
1445                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1446                         return -EINVAL;
1447                 }
1448                 track->vap_vf_cntl = ib_chunk->kdata[idx];
1449                 track->immd_dwords = pkt->count;
1450                 r = r300_cs_track_check(p->rdev, track);
1451                 if (r) {
1452                         return r;
1453                 }
1454                 break;
1455         case PACKET3_3D_DRAW_VBUF:
1456                 track->vap_vf_cntl = ib_chunk->kdata[idx + 1];
1457                 r = r300_cs_track_check(p->rdev, track);
1458                 if (r) {
1459                         return r;
1460                 }
1461                 break;
1462         case PACKET3_3D_DRAW_VBUF_2:
1463                 track->vap_vf_cntl = ib_chunk->kdata[idx];
1464                 r = r300_cs_track_check(p->rdev, track);
1465                 if (r) {
1466                         return r;
1467                 }
1468                 break;
1469         case PACKET3_3D_DRAW_INDX:
1470                 track->vap_vf_cntl = ib_chunk->kdata[idx + 1];
1471                 r = r300_cs_track_check(p->rdev, track);
1472                 if (r) {
1473                         return r;
1474                 }
1475                 break;
1476         case PACKET3_3D_DRAW_INDX_2:
1477                 track->vap_vf_cntl = ib_chunk->kdata[idx];
1478                 r = r300_cs_track_check(p->rdev, track);
1479                 if (r) {
1480                         return r;
1481                 }
1482                 break;
1483         case PACKET3_NOP:
1484                 break;
1485         default:
1486                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1487                 return -EINVAL;
1488         }
1489         return 0;
1490 }
1491
1492 int r300_cs_parse(struct radeon_cs_parser *p)
1493 {
1494         struct radeon_cs_packet pkt;
1495         struct r300_cs_track track;
1496         int r;
1497
1498         r300_cs_track_clear(&track);
1499         p->track = &track;
1500         do {
1501                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1502                 if (r) {
1503                         return r;
1504                 }
1505                 p->idx += pkt.count + 2;
1506                 switch (pkt.type) {
1507                 case PACKET_TYPE0:
1508                         r = r100_cs_parse_packet0(p, &pkt,
1509                                                   p->rdev->config.r300.reg_safe_bm,
1510                                                   p->rdev->config.r300.reg_safe_bm_size,
1511                                                   &r300_packet0_check);
1512                         break;
1513                 case PACKET_TYPE2:
1514                         break;
1515                 case PACKET_TYPE3:
1516                         r = r300_packet3_check(p, &pkt);
1517                         break;
1518                 default:
1519                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1520                         return -EINVAL;
1521                 }
1522                 if (r) {
1523                         return r;
1524                 }
1525         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1526         return 0;
1527 }
1528
1529 int r300_init(struct radeon_device *rdev)
1530 {
1531         rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
1532         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1533         return 0;
1534 }