drm/radeon: include radeon_asic.h in the asic specific files
[linux-2.6.git] / drivers / gpu / drm / radeon / r300.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/seq_file.h>
29 #include "drmP.h"
30 #include "drm.h"
31 #include "radeon_reg.h"
32 #include "radeon.h"
33 #include "radeon_asic.h"
34 #include "radeon_drm.h"
35 #include "r100_track.h"
36 #include "r300d.h"
37 #include "rv350d.h"
38 #include "r300_reg_safe.h"
39
40 /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
41  *
42  * GPU Errata:
43  * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
44  *   using MMIO to flush host path read cache, this lead to HARDLOCKUP.
45  *   However, scheduling such write to the ring seems harmless, i suspect
46  *   the CP read collide with the flush somehow, or maybe the MC, hard to
47  *   tell. (Jerome Glisse)
48  */
49
50 /*
51  * rv370,rv380 PCIE GART
52  */
53 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
54
55 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
56 {
57         uint32_t tmp;
58         int i;
59
60         /* Workaround HW bug do flush 2 times */
61         for (i = 0; i < 2; i++) {
62                 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
63                 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
64                 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
65                 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
66         }
67         mb();
68 }
69
70 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
71 {
72         void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
73
74         if (i < 0 || i > rdev->gart.num_gpu_pages) {
75                 return -EINVAL;
76         }
77         addr = (lower_32_bits(addr) >> 8) |
78                ((upper_32_bits(addr) & 0xff) << 24) |
79                0xc;
80         /* on x86 we want this to be CPU endian, on powerpc
81          * on powerpc without HW swappers, it'll get swapped on way
82          * into VRAM - so no need for cpu_to_le32 on VRAM tables */
83         writel(addr, ((void __iomem *)ptr) + (i * 4));
84         return 0;
85 }
86
87 int rv370_pcie_gart_init(struct radeon_device *rdev)
88 {
89         int r;
90
91         if (rdev->gart.table.vram.robj) {
92                 WARN(1, "RV370 PCIE GART already initialized.\n");
93                 return 0;
94         }
95         /* Initialize common gart structure */
96         r = radeon_gart_init(rdev);
97         if (r)
98                 return r;
99         r = rv370_debugfs_pcie_gart_info_init(rdev);
100         if (r)
101                 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
102         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
103         rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
104         rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
105         return radeon_gart_table_vram_alloc(rdev);
106 }
107
108 int rv370_pcie_gart_enable(struct radeon_device *rdev)
109 {
110         uint32_t table_addr;
111         uint32_t tmp;
112         int r;
113
114         if (rdev->gart.table.vram.robj == NULL) {
115                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
116                 return -EINVAL;
117         }
118         r = radeon_gart_table_vram_pin(rdev);
119         if (r)
120                 return r;
121         radeon_gart_restore(rdev);
122         /* discard memory request outside of configured range */
123         tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
124         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
125         WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_start);
126         tmp = rdev->mc.gtt_end & ~RADEON_GPU_PAGE_MASK;
127         WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
128         WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
129         WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
130         table_addr = rdev->gart.table_addr;
131         WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
132         /* FIXME: setup default page */
133         WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_start);
134         WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
135         /* Clear error */
136         WREG32_PCIE(0x18, 0);
137         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
138         tmp |= RADEON_PCIE_TX_GART_EN;
139         tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
140         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
141         rv370_pcie_gart_tlb_flush(rdev);
142         DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
143                  (unsigned)(rdev->mc.gtt_size >> 20), table_addr);
144         rdev->gart.ready = true;
145         return 0;
146 }
147
148 void rv370_pcie_gart_disable(struct radeon_device *rdev)
149 {
150         u32 tmp;
151         int r;
152
153         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
154         tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
155         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
156         if (rdev->gart.table.vram.robj) {
157                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
158                 if (likely(r == 0)) {
159                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
160                         radeon_bo_unpin(rdev->gart.table.vram.robj);
161                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
162                 }
163         }
164 }
165
166 void rv370_pcie_gart_fini(struct radeon_device *rdev)
167 {
168         rv370_pcie_gart_disable(rdev);
169         radeon_gart_table_vram_free(rdev);
170         radeon_gart_fini(rdev);
171 }
172
173 void r300_fence_ring_emit(struct radeon_device *rdev,
174                           struct radeon_fence *fence)
175 {
176         /* Who ever call radeon_fence_emit should call ring_lock and ask
177          * for enough space (today caller are ib schedule and buffer move) */
178         /* Write SC register so SC & US assert idle */
179         radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_TL, 0));
180         radeon_ring_write(rdev, 0);
181         radeon_ring_write(rdev, PACKET0(R300_RE_SCISSORS_BR, 0));
182         radeon_ring_write(rdev, 0);
183         /* Flush 3D cache */
184         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
185         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH);
186         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
187         radeon_ring_write(rdev, R300_ZC_FLUSH);
188         /* Wait until IDLE & CLEAN */
189         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
190         radeon_ring_write(rdev, (RADEON_WAIT_3D_IDLECLEAN |
191                                  RADEON_WAIT_2D_IDLECLEAN |
192                                  RADEON_WAIT_DMA_GUI_IDLE));
193         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
194         radeon_ring_write(rdev, rdev->config.r300.hdp_cntl |
195                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
196         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
197         radeon_ring_write(rdev, rdev->config.r300.hdp_cntl);
198         /* Emit fence sequence & fire IRQ */
199         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
200         radeon_ring_write(rdev, fence->seq);
201         radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
202         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
203 }
204
205 void r300_ring_start(struct radeon_device *rdev)
206 {
207         unsigned gb_tile_config;
208         int r;
209
210         /* Sub pixel 1/12 so we can have 4K rendering according to doc */
211         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
212         switch(rdev->num_gb_pipes) {
213         case 2:
214                 gb_tile_config |= R300_PIPE_COUNT_R300;
215                 break;
216         case 3:
217                 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
218                 break;
219         case 4:
220                 gb_tile_config |= R300_PIPE_COUNT_R420;
221                 break;
222         case 1:
223         default:
224                 gb_tile_config |= R300_PIPE_COUNT_RV350;
225                 break;
226         }
227
228         r = radeon_ring_lock(rdev, 64);
229         if (r) {
230                 return;
231         }
232         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
233         radeon_ring_write(rdev,
234                           RADEON_ISYNC_ANY2D_IDLE3D |
235                           RADEON_ISYNC_ANY3D_IDLE2D |
236                           RADEON_ISYNC_WAIT_IDLEGUI |
237                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
238         radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
239         radeon_ring_write(rdev, gb_tile_config);
240         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
241         radeon_ring_write(rdev,
242                           RADEON_WAIT_2D_IDLECLEAN |
243                           RADEON_WAIT_3D_IDLECLEAN);
244         radeon_ring_write(rdev, PACKET0(R300_DST_PIPE_CONFIG, 0));
245         radeon_ring_write(rdev, R300_PIPE_AUTO_CONFIG);
246         radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
247         radeon_ring_write(rdev, 0);
248         radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
249         radeon_ring_write(rdev, 0);
250         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
251         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
252         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
253         radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
254         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
255         radeon_ring_write(rdev,
256                           RADEON_WAIT_2D_IDLECLEAN |
257                           RADEON_WAIT_3D_IDLECLEAN);
258         radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
259         radeon_ring_write(rdev, 0);
260         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
261         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
262         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
263         radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
264         radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
265         radeon_ring_write(rdev,
266                           ((6 << R300_MS_X0_SHIFT) |
267                            (6 << R300_MS_Y0_SHIFT) |
268                            (6 << R300_MS_X1_SHIFT) |
269                            (6 << R300_MS_Y1_SHIFT) |
270                            (6 << R300_MS_X2_SHIFT) |
271                            (6 << R300_MS_Y2_SHIFT) |
272                            (6 << R300_MSBD0_Y_SHIFT) |
273                            (6 << R300_MSBD0_X_SHIFT)));
274         radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
275         radeon_ring_write(rdev,
276                           ((6 << R300_MS_X3_SHIFT) |
277                            (6 << R300_MS_Y3_SHIFT) |
278                            (6 << R300_MS_X4_SHIFT) |
279                            (6 << R300_MS_Y4_SHIFT) |
280                            (6 << R300_MS_X5_SHIFT) |
281                            (6 << R300_MS_Y5_SHIFT) |
282                            (6 << R300_MSBD1_SHIFT)));
283         radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
284         radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
285         radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
286         radeon_ring_write(rdev,
287                           R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
288         radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
289         radeon_ring_write(rdev,
290                           R300_GEOMETRY_ROUND_NEAREST |
291                           R300_COLOR_ROUND_NEAREST);
292         radeon_ring_unlock_commit(rdev);
293 }
294
295 void r300_errata(struct radeon_device *rdev)
296 {
297         rdev->pll_errata = 0;
298
299         if (rdev->family == CHIP_R300 &&
300             (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
301                 rdev->pll_errata |= CHIP_ERRATA_R300_CG;
302         }
303 }
304
305 int r300_mc_wait_for_idle(struct radeon_device *rdev)
306 {
307         unsigned i;
308         uint32_t tmp;
309
310         for (i = 0; i < rdev->usec_timeout; i++) {
311                 /* read MC_STATUS */
312                 tmp = RREG32(RADEON_MC_STATUS);
313                 if (tmp & R300_MC_IDLE) {
314                         return 0;
315                 }
316                 DRM_UDELAY(1);
317         }
318         return -1;
319 }
320
321 void r300_gpu_init(struct radeon_device *rdev)
322 {
323         uint32_t gb_tile_config, tmp;
324
325         r100_hdp_reset(rdev);
326         /* FIXME: rv380 one pipes ? */
327         if ((rdev->family == CHIP_R300) || (rdev->family == CHIP_R350)) {
328                 /* r300,r350 */
329                 rdev->num_gb_pipes = 2;
330         } else {
331                 /* rv350,rv370,rv380 */
332                 rdev->num_gb_pipes = 1;
333         }
334         rdev->num_z_pipes = 1;
335         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
336         switch (rdev->num_gb_pipes) {
337         case 2:
338                 gb_tile_config |= R300_PIPE_COUNT_R300;
339                 break;
340         case 3:
341                 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
342                 break;
343         case 4:
344                 gb_tile_config |= R300_PIPE_COUNT_R420;
345                 break;
346         default:
347         case 1:
348                 gb_tile_config |= R300_PIPE_COUNT_RV350;
349                 break;
350         }
351         WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
352
353         if (r100_gui_wait_for_idle(rdev)) {
354                 printk(KERN_WARNING "Failed to wait GUI idle while "
355                        "programming pipes. Bad things might happen.\n");
356         }
357
358         tmp = RREG32(R300_DST_PIPE_CONFIG);
359         WREG32(R300_DST_PIPE_CONFIG, tmp | R300_PIPE_AUTO_CONFIG);
360
361         WREG32(R300_RB2D_DSTCACHE_MODE,
362                R300_DC_AUTOFLUSH_ENABLE |
363                R300_DC_DC_DISABLE_IGNORE_PE);
364
365         if (r100_gui_wait_for_idle(rdev)) {
366                 printk(KERN_WARNING "Failed to wait GUI idle while "
367                        "programming pipes. Bad things might happen.\n");
368         }
369         if (r300_mc_wait_for_idle(rdev)) {
370                 printk(KERN_WARNING "Failed to wait MC idle while "
371                        "programming pipes. Bad things might happen.\n");
372         }
373         DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
374                  rdev->num_gb_pipes, rdev->num_z_pipes);
375 }
376
377 int r300_ga_reset(struct radeon_device *rdev)
378 {
379         uint32_t tmp;
380         bool reinit_cp;
381         int i;
382
383         reinit_cp = rdev->cp.ready;
384         rdev->cp.ready = false;
385         for (i = 0; i < rdev->usec_timeout; i++) {
386                 WREG32(RADEON_CP_CSQ_MODE, 0);
387                 WREG32(RADEON_CP_CSQ_CNTL, 0);
388                 WREG32(RADEON_RBBM_SOFT_RESET, 0x32005);
389                 (void)RREG32(RADEON_RBBM_SOFT_RESET);
390                 udelay(200);
391                 WREG32(RADEON_RBBM_SOFT_RESET, 0);
392                 /* Wait to prevent race in RBBM_STATUS */
393                 mdelay(1);
394                 tmp = RREG32(RADEON_RBBM_STATUS);
395                 if (tmp & ((1 << 20) | (1 << 26))) {
396                         DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp);
397                         /* GA still busy soft reset it */
398                         WREG32(0x429C, 0x200);
399                         WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0);
400                         WREG32(R300_RE_SCISSORS_TL, 0);
401                         WREG32(R300_RE_SCISSORS_BR, 0);
402                         WREG32(0x24AC, 0);
403                 }
404                 /* Wait to prevent race in RBBM_STATUS */
405                 mdelay(1);
406                 tmp = RREG32(RADEON_RBBM_STATUS);
407                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
408                         break;
409                 }
410         }
411         for (i = 0; i < rdev->usec_timeout; i++) {
412                 tmp = RREG32(RADEON_RBBM_STATUS);
413                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
414                         DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
415                                  tmp);
416                         if (reinit_cp) {
417                                 return r100_cp_init(rdev, rdev->cp.ring_size);
418                         }
419                         return 0;
420                 }
421                 DRM_UDELAY(1);
422         }
423         tmp = RREG32(RADEON_RBBM_STATUS);
424         DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
425         return -1;
426 }
427
428 int r300_gpu_reset(struct radeon_device *rdev)
429 {
430         uint32_t status;
431
432         /* reset order likely matter */
433         status = RREG32(RADEON_RBBM_STATUS);
434         /* reset HDP */
435         r100_hdp_reset(rdev);
436         /* reset rb2d */
437         if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
438                 r100_rb2d_reset(rdev);
439         }
440         /* reset GA */
441         if (status & ((1 << 20) | (1 << 26))) {
442                 r300_ga_reset(rdev);
443         }
444         /* reset CP */
445         status = RREG32(RADEON_RBBM_STATUS);
446         if (status & (1 << 16)) {
447                 r100_cp_reset(rdev);
448         }
449         /* Check if GPU is idle */
450         status = RREG32(RADEON_RBBM_STATUS);
451         if (status & RADEON_RBBM_ACTIVE) {
452                 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
453                 return -1;
454         }
455         DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
456         return 0;
457 }
458
459
460 /*
461  * r300,r350,rv350,rv380 VRAM info
462  */
463 void r300_mc_init(struct radeon_device *rdev)
464 {
465         u64 base;
466         u32 tmp;
467
468         /* DDR for all card after R300 & IGP */
469         rdev->mc.vram_is_ddr = true;
470         tmp = RREG32(RADEON_MEM_CNTL);
471         tmp &= R300_MEM_NUM_CHANNELS_MASK;
472         switch (tmp) {
473         case 0: rdev->mc.vram_width = 64; break;
474         case 1: rdev->mc.vram_width = 128; break;
475         case 2: rdev->mc.vram_width = 256; break;
476         default:  rdev->mc.vram_width = 128; break;
477         }
478         r100_vram_init_sizes(rdev);
479         base = rdev->mc.aper_base;
480         if (rdev->flags & RADEON_IS_IGP)
481                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
482         radeon_vram_location(rdev, &rdev->mc, base);
483         if (!(rdev->flags & RADEON_IS_AGP))
484                 radeon_gtt_location(rdev, &rdev->mc);
485 }
486
487 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
488 {
489         uint32_t link_width_cntl, mask;
490
491         if (rdev->flags & RADEON_IS_IGP)
492                 return;
493
494         if (!(rdev->flags & RADEON_IS_PCIE))
495                 return;
496
497         /* FIXME wait for idle */
498
499         switch (lanes) {
500         case 0:
501                 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
502                 break;
503         case 1:
504                 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
505                 break;
506         case 2:
507                 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
508                 break;
509         case 4:
510                 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
511                 break;
512         case 8:
513                 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
514                 break;
515         case 12:
516                 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
517                 break;
518         case 16:
519         default:
520                 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
521                 break;
522         }
523
524         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
525
526         if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
527             (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
528                 return;
529
530         link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
531                              RADEON_PCIE_LC_RECONFIG_NOW |
532                              RADEON_PCIE_LC_RECONFIG_LATER |
533                              RADEON_PCIE_LC_SHORT_RECONFIG_EN);
534         link_width_cntl |= mask;
535         WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
536         WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
537                                                      RADEON_PCIE_LC_RECONFIG_NOW));
538
539         /* wait for lane set to complete */
540         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
541         while (link_width_cntl == 0xffffffff)
542                 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
543
544 }
545
546 int rv370_get_pcie_lanes(struct radeon_device *rdev)
547 {
548         u32 link_width_cntl;
549
550         if (rdev->flags & RADEON_IS_IGP)
551                 return 0;
552
553         if (!(rdev->flags & RADEON_IS_PCIE))
554                 return 0;
555
556         /* FIXME wait for idle */
557
558         if (rdev->family < CHIP_R600)
559                 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
560         else
561                 link_width_cntl = RREG32_PCIE_P(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
562
563         switch ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) >> RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT) {
564         case RADEON_PCIE_LC_LINK_WIDTH_X0:
565                 return 0;
566         case RADEON_PCIE_LC_LINK_WIDTH_X1:
567                 return 1;
568         case RADEON_PCIE_LC_LINK_WIDTH_X2:
569                 return 2;
570         case RADEON_PCIE_LC_LINK_WIDTH_X4:
571                 return 4;
572         case RADEON_PCIE_LC_LINK_WIDTH_X8:
573                 return 8;
574         case RADEON_PCIE_LC_LINK_WIDTH_X16:
575         default:
576                 return 16;
577         }
578 }
579
580 #if defined(CONFIG_DEBUG_FS)
581 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data)
582 {
583         struct drm_info_node *node = (struct drm_info_node *) m->private;
584         struct drm_device *dev = node->minor->dev;
585         struct radeon_device *rdev = dev->dev_private;
586         uint32_t tmp;
587
588         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
589         seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
590         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
591         seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
592         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
593         seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
594         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
595         seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
596         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
597         seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
598         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
599         seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
600         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
601         seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
602         return 0;
603 }
604
605 static struct drm_info_list rv370_pcie_gart_info_list[] = {
606         {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
607 };
608 #endif
609
610 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
611 {
612 #if defined(CONFIG_DEBUG_FS)
613         return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
614 #else
615         return 0;
616 #endif
617 }
618
619 static int r300_packet0_check(struct radeon_cs_parser *p,
620                 struct radeon_cs_packet *pkt,
621                 unsigned idx, unsigned reg)
622 {
623         struct radeon_cs_reloc *reloc;
624         struct r100_cs_track *track;
625         volatile uint32_t *ib;
626         uint32_t tmp, tile_flags = 0;
627         unsigned i;
628         int r;
629         u32 idx_value;
630
631         ib = p->ib->ptr;
632         track = (struct r100_cs_track *)p->track;
633         idx_value = radeon_get_ib_value(p, idx);
634
635         switch(reg) {
636         case AVIVO_D1MODE_VLINE_START_END:
637         case RADEON_CRTC_GUI_TRIG_VLINE:
638                 r = r100_cs_packet_parse_vline(p);
639                 if (r) {
640                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
641                                         idx, reg);
642                         r100_cs_dump_packet(p, pkt);
643                         return r;
644                 }
645                 break;
646         case RADEON_DST_PITCH_OFFSET:
647         case RADEON_SRC_PITCH_OFFSET:
648                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
649                 if (r)
650                         return r;
651                 break;
652         case R300_RB3D_COLOROFFSET0:
653         case R300_RB3D_COLOROFFSET1:
654         case R300_RB3D_COLOROFFSET2:
655         case R300_RB3D_COLOROFFSET3:
656                 i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
657                 r = r100_cs_packet_next_reloc(p, &reloc);
658                 if (r) {
659                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
660                                         idx, reg);
661                         r100_cs_dump_packet(p, pkt);
662                         return r;
663                 }
664                 track->cb[i].robj = reloc->robj;
665                 track->cb[i].offset = idx_value;
666                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
667                 break;
668         case R300_ZB_DEPTHOFFSET:
669                 r = r100_cs_packet_next_reloc(p, &reloc);
670                 if (r) {
671                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
672                                         idx, reg);
673                         r100_cs_dump_packet(p, pkt);
674                         return r;
675                 }
676                 track->zb.robj = reloc->robj;
677                 track->zb.offset = idx_value;
678                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
679                 break;
680         case R300_TX_OFFSET_0:
681         case R300_TX_OFFSET_0+4:
682         case R300_TX_OFFSET_0+8:
683         case R300_TX_OFFSET_0+12:
684         case R300_TX_OFFSET_0+16:
685         case R300_TX_OFFSET_0+20:
686         case R300_TX_OFFSET_0+24:
687         case R300_TX_OFFSET_0+28:
688         case R300_TX_OFFSET_0+32:
689         case R300_TX_OFFSET_0+36:
690         case R300_TX_OFFSET_0+40:
691         case R300_TX_OFFSET_0+44:
692         case R300_TX_OFFSET_0+48:
693         case R300_TX_OFFSET_0+52:
694         case R300_TX_OFFSET_0+56:
695         case R300_TX_OFFSET_0+60:
696                 i = (reg - R300_TX_OFFSET_0) >> 2;
697                 r = r100_cs_packet_next_reloc(p, &reloc);
698                 if (r) {
699                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
700                                         idx, reg);
701                         r100_cs_dump_packet(p, pkt);
702                         return r;
703                 }
704
705                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
706                         tile_flags |= R300_TXO_MACRO_TILE;
707                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
708                         tile_flags |= R300_TXO_MICRO_TILE;
709                 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
710                         tile_flags |= R300_TXO_MICRO_TILE_SQUARE;
711
712                 tmp = idx_value + ((u32)reloc->lobj.gpu_offset);
713                 tmp |= tile_flags;
714                 ib[idx] = tmp;
715                 track->textures[i].robj = reloc->robj;
716                 break;
717         /* Tracked registers */
718         case 0x2084:
719                 /* VAP_VF_CNTL */
720                 track->vap_vf_cntl = idx_value;
721                 break;
722         case 0x20B4:
723                 /* VAP_VTX_SIZE */
724                 track->vtx_size = idx_value & 0x7F;
725                 break;
726         case 0x2134:
727                 /* VAP_VF_MAX_VTX_INDX */
728                 track->max_indx = idx_value & 0x00FFFFFFUL;
729                 break;
730         case 0x43E4:
731                 /* SC_SCISSOR1 */
732                 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
733                 if (p->rdev->family < CHIP_RV515) {
734                         track->maxy -= 1440;
735                 }
736                 break;
737         case 0x4E00:
738                 /* RB3D_CCTL */
739                 track->num_cb = ((idx_value >> 5) & 0x3) + 1;
740                 break;
741         case 0x4E38:
742         case 0x4E3C:
743         case 0x4E40:
744         case 0x4E44:
745                 /* RB3D_COLORPITCH0 */
746                 /* RB3D_COLORPITCH1 */
747                 /* RB3D_COLORPITCH2 */
748                 /* RB3D_COLORPITCH3 */
749                 r = r100_cs_packet_next_reloc(p, &reloc);
750                 if (r) {
751                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
752                                   idx, reg);
753                         r100_cs_dump_packet(p, pkt);
754                         return r;
755                 }
756
757                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
758                         tile_flags |= R300_COLOR_TILE_ENABLE;
759                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
760                         tile_flags |= R300_COLOR_MICROTILE_ENABLE;
761                 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
762                         tile_flags |= R300_COLOR_MICROTILE_SQUARE_ENABLE;
763
764                 tmp = idx_value & ~(0x7 << 16);
765                 tmp |= tile_flags;
766                 ib[idx] = tmp;
767
768                 i = (reg - 0x4E38) >> 2;
769                 track->cb[i].pitch = idx_value & 0x3FFE;
770                 switch (((idx_value >> 21) & 0xF)) {
771                 case 9:
772                 case 11:
773                 case 12:
774                         track->cb[i].cpp = 1;
775                         break;
776                 case 3:
777                 case 4:
778                 case 13:
779                 case 15:
780                         track->cb[i].cpp = 2;
781                         break;
782                 case 6:
783                         track->cb[i].cpp = 4;
784                         break;
785                 case 10:
786                         track->cb[i].cpp = 8;
787                         break;
788                 case 7:
789                         track->cb[i].cpp = 16;
790                         break;
791                 default:
792                         DRM_ERROR("Invalid color buffer format (%d) !\n",
793                                   ((idx_value >> 21) & 0xF));
794                         return -EINVAL;
795                 }
796                 break;
797         case 0x4F00:
798                 /* ZB_CNTL */
799                 if (idx_value & 2) {
800                         track->z_enabled = true;
801                 } else {
802                         track->z_enabled = false;
803                 }
804                 break;
805         case 0x4F10:
806                 /* ZB_FORMAT */
807                 switch ((idx_value & 0xF)) {
808                 case 0:
809                 case 1:
810                         track->zb.cpp = 2;
811                         break;
812                 case 2:
813                         track->zb.cpp = 4;
814                         break;
815                 default:
816                         DRM_ERROR("Invalid z buffer format (%d) !\n",
817                                   (idx_value & 0xF));
818                         return -EINVAL;
819                 }
820                 break;
821         case 0x4F24:
822                 /* ZB_DEPTHPITCH */
823                 r = r100_cs_packet_next_reloc(p, &reloc);
824                 if (r) {
825                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
826                                   idx, reg);
827                         r100_cs_dump_packet(p, pkt);
828                         return r;
829                 }
830
831                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
832                         tile_flags |= R300_DEPTHMACROTILE_ENABLE;
833                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
834                         tile_flags |= R300_DEPTHMICROTILE_TILED;
835                 else if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO_SQUARE)
836                         tile_flags |= R300_DEPTHMICROTILE_TILED_SQUARE;
837
838                 tmp = idx_value & ~(0x7 << 16);
839                 tmp |= tile_flags;
840                 ib[idx] = tmp;
841
842                 track->zb.pitch = idx_value & 0x3FFC;
843                 break;
844         case 0x4104:
845                 for (i = 0; i < 16; i++) {
846                         bool enabled;
847
848                         enabled = !!(idx_value & (1 << i));
849                         track->textures[i].enabled = enabled;
850                 }
851                 break;
852         case 0x44C0:
853         case 0x44C4:
854         case 0x44C8:
855         case 0x44CC:
856         case 0x44D0:
857         case 0x44D4:
858         case 0x44D8:
859         case 0x44DC:
860         case 0x44E0:
861         case 0x44E4:
862         case 0x44E8:
863         case 0x44EC:
864         case 0x44F0:
865         case 0x44F4:
866         case 0x44F8:
867         case 0x44FC:
868                 /* TX_FORMAT1_[0-15] */
869                 i = (reg - 0x44C0) >> 2;
870                 tmp = (idx_value >> 25) & 0x3;
871                 track->textures[i].tex_coord_type = tmp;
872                 switch ((idx_value & 0x1F)) {
873                 case R300_TX_FORMAT_X8:
874                 case R300_TX_FORMAT_Y4X4:
875                 case R300_TX_FORMAT_Z3Y3X2:
876                         track->textures[i].cpp = 1;
877                         break;
878                 case R300_TX_FORMAT_X16:
879                 case R300_TX_FORMAT_Y8X8:
880                 case R300_TX_FORMAT_Z5Y6X5:
881                 case R300_TX_FORMAT_Z6Y5X5:
882                 case R300_TX_FORMAT_W4Z4Y4X4:
883                 case R300_TX_FORMAT_W1Z5Y5X5:
884                 case R300_TX_FORMAT_D3DMFT_CxV8U8:
885                 case R300_TX_FORMAT_B8G8_B8G8:
886                 case R300_TX_FORMAT_G8R8_G8B8:
887                         track->textures[i].cpp = 2;
888                         break;
889                 case R300_TX_FORMAT_Y16X16:
890                 case R300_TX_FORMAT_Z11Y11X10:
891                 case R300_TX_FORMAT_Z10Y11X11:
892                 case R300_TX_FORMAT_W8Z8Y8X8:
893                 case R300_TX_FORMAT_W2Z10Y10X10:
894                 case 0x17:
895                 case R300_TX_FORMAT_FL_I32:
896                 case 0x1e:
897                         track->textures[i].cpp = 4;
898                         break;
899                 case R300_TX_FORMAT_W16Z16Y16X16:
900                 case R300_TX_FORMAT_FL_R16G16B16A16:
901                 case R300_TX_FORMAT_FL_I32A32:
902                         track->textures[i].cpp = 8;
903                         break;
904                 case R300_TX_FORMAT_FL_R32G32B32A32:
905                         track->textures[i].cpp = 16;
906                         break;
907                 case R300_TX_FORMAT_DXT1:
908                         track->textures[i].cpp = 1;
909                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
910                         break;
911                 case R300_TX_FORMAT_ATI2N:
912                         if (p->rdev->family < CHIP_R420) {
913                                 DRM_ERROR("Invalid texture format %u\n",
914                                           (idx_value & 0x1F));
915                                 return -EINVAL;
916                         }
917                         /* The same rules apply as for DXT3/5. */
918                         /* Pass through. */
919                 case R300_TX_FORMAT_DXT3:
920                 case R300_TX_FORMAT_DXT5:
921                         track->textures[i].cpp = 1;
922                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
923                         break;
924                 default:
925                         DRM_ERROR("Invalid texture format %u\n",
926                                   (idx_value & 0x1F));
927                         return -EINVAL;
928                         break;
929                 }
930                 break;
931         case 0x4400:
932         case 0x4404:
933         case 0x4408:
934         case 0x440C:
935         case 0x4410:
936         case 0x4414:
937         case 0x4418:
938         case 0x441C:
939         case 0x4420:
940         case 0x4424:
941         case 0x4428:
942         case 0x442C:
943         case 0x4430:
944         case 0x4434:
945         case 0x4438:
946         case 0x443C:
947                 /* TX_FILTER0_[0-15] */
948                 i = (reg - 0x4400) >> 2;
949                 tmp = idx_value & 0x7;
950                 if (tmp == 2 || tmp == 4 || tmp == 6) {
951                         track->textures[i].roundup_w = false;
952                 }
953                 tmp = (idx_value >> 3) & 0x7;
954                 if (tmp == 2 || tmp == 4 || tmp == 6) {
955                         track->textures[i].roundup_h = false;
956                 }
957                 break;
958         case 0x4500:
959         case 0x4504:
960         case 0x4508:
961         case 0x450C:
962         case 0x4510:
963         case 0x4514:
964         case 0x4518:
965         case 0x451C:
966         case 0x4520:
967         case 0x4524:
968         case 0x4528:
969         case 0x452C:
970         case 0x4530:
971         case 0x4534:
972         case 0x4538:
973         case 0x453C:
974                 /* TX_FORMAT2_[0-15] */
975                 i = (reg - 0x4500) >> 2;
976                 tmp = idx_value & 0x3FFF;
977                 track->textures[i].pitch = tmp + 1;
978                 if (p->rdev->family >= CHIP_RV515) {
979                         tmp = ((idx_value >> 15) & 1) << 11;
980                         track->textures[i].width_11 = tmp;
981                         tmp = ((idx_value >> 16) & 1) << 11;
982                         track->textures[i].height_11 = tmp;
983
984                         /* ATI1N */
985                         if (idx_value & (1 << 14)) {
986                                 /* The same rules apply as for DXT1. */
987                                 track->textures[i].compress_format =
988                                         R100_TRACK_COMP_DXT1;
989                         }
990                 } else if (idx_value & (1 << 14)) {
991                         DRM_ERROR("Forbidden bit TXFORMAT_MSB\n");
992                         return -EINVAL;
993                 }
994                 break;
995         case 0x4480:
996         case 0x4484:
997         case 0x4488:
998         case 0x448C:
999         case 0x4490:
1000         case 0x4494:
1001         case 0x4498:
1002         case 0x449C:
1003         case 0x44A0:
1004         case 0x44A4:
1005         case 0x44A8:
1006         case 0x44AC:
1007         case 0x44B0:
1008         case 0x44B4:
1009         case 0x44B8:
1010         case 0x44BC:
1011                 /* TX_FORMAT0_[0-15] */
1012                 i = (reg - 0x4480) >> 2;
1013                 tmp = idx_value & 0x7FF;
1014                 track->textures[i].width = tmp + 1;
1015                 tmp = (idx_value >> 11) & 0x7FF;
1016                 track->textures[i].height = tmp + 1;
1017                 tmp = (idx_value >> 26) & 0xF;
1018                 track->textures[i].num_levels = tmp;
1019                 tmp = idx_value & (1 << 31);
1020                 track->textures[i].use_pitch = !!tmp;
1021                 tmp = (idx_value >> 22) & 0xF;
1022                 track->textures[i].txdepth = tmp;
1023                 break;
1024         case R300_ZB_ZPASS_ADDR:
1025                 r = r100_cs_packet_next_reloc(p, &reloc);
1026                 if (r) {
1027                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1028                                         idx, reg);
1029                         r100_cs_dump_packet(p, pkt);
1030                         return r;
1031                 }
1032                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1033                 break;
1034         case 0x4e0c:
1035                 /* RB3D_COLOR_CHANNEL_MASK */
1036                 track->color_channel_mask = idx_value;
1037                 break;
1038         case 0x4d1c:
1039                 /* ZB_BW_CNTL */
1040                 track->fastfill = !!(idx_value & (1 << 2));
1041                 break;
1042         case 0x4e04:
1043                 /* RB3D_BLENDCNTL */
1044                 track->blend_read_enable = !!(idx_value & (1 << 2));
1045                 break;
1046         case 0x4be8:
1047                 /* valid register only on RV530 */
1048                 if (p->rdev->family == CHIP_RV530)
1049                         break;
1050                 /* fallthrough do not move */
1051         default:
1052                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1053                        reg, idx);
1054                 return -EINVAL;
1055         }
1056         return 0;
1057 }
1058
1059 static int r300_packet3_check(struct radeon_cs_parser *p,
1060                               struct radeon_cs_packet *pkt)
1061 {
1062         struct radeon_cs_reloc *reloc;
1063         struct r100_cs_track *track;
1064         volatile uint32_t *ib;
1065         unsigned idx;
1066         int r;
1067
1068         ib = p->ib->ptr;
1069         idx = pkt->idx + 1;
1070         track = (struct r100_cs_track *)p->track;
1071         switch(pkt->opcode) {
1072         case PACKET3_3D_LOAD_VBPNTR:
1073                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1074                 if (r)
1075                         return r;
1076                 break;
1077         case PACKET3_INDX_BUFFER:
1078                 r = r100_cs_packet_next_reloc(p, &reloc);
1079                 if (r) {
1080                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1081                         r100_cs_dump_packet(p, pkt);
1082                         return r;
1083                 }
1084                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1085                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1086                 if (r) {
1087                         return r;
1088                 }
1089                 break;
1090         /* Draw packet */
1091         case PACKET3_3D_DRAW_IMMD:
1092                 /* Number of dwords is vtx_size * (num_vertices - 1)
1093                  * PRIM_WALK must be equal to 3 vertex data in embedded
1094                  * in cmd stream */
1095                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1096                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1097                         return -EINVAL;
1098                 }
1099                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1100                 track->immd_dwords = pkt->count - 1;
1101                 r = r100_cs_track_check(p->rdev, track);
1102                 if (r) {
1103                         return r;
1104                 }
1105                 break;
1106         case PACKET3_3D_DRAW_IMMD_2:
1107                 /* Number of dwords is vtx_size * (num_vertices - 1)
1108                  * PRIM_WALK must be equal to 3 vertex data in embedded
1109                  * in cmd stream */
1110                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1111                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1112                         return -EINVAL;
1113                 }
1114                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1115                 track->immd_dwords = pkt->count;
1116                 r = r100_cs_track_check(p->rdev, track);
1117                 if (r) {
1118                         return r;
1119                 }
1120                 break;
1121         case PACKET3_3D_DRAW_VBUF:
1122                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1123                 r = r100_cs_track_check(p->rdev, track);
1124                 if (r) {
1125                         return r;
1126                 }
1127                 break;
1128         case PACKET3_3D_DRAW_VBUF_2:
1129                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1130                 r = r100_cs_track_check(p->rdev, track);
1131                 if (r) {
1132                         return r;
1133                 }
1134                 break;
1135         case PACKET3_3D_DRAW_INDX:
1136                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1137                 r = r100_cs_track_check(p->rdev, track);
1138                 if (r) {
1139                         return r;
1140                 }
1141                 break;
1142         case PACKET3_3D_DRAW_INDX_2:
1143                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1144                 r = r100_cs_track_check(p->rdev, track);
1145                 if (r) {
1146                         return r;
1147                 }
1148                 break;
1149         case PACKET3_NOP:
1150                 break;
1151         default:
1152                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1153                 return -EINVAL;
1154         }
1155         return 0;
1156 }
1157
1158 int r300_cs_parse(struct radeon_cs_parser *p)
1159 {
1160         struct radeon_cs_packet pkt;
1161         struct r100_cs_track *track;
1162         int r;
1163
1164         track = kzalloc(sizeof(*track), GFP_KERNEL);
1165         r100_cs_track_clear(p->rdev, track);
1166         p->track = track;
1167         do {
1168                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1169                 if (r) {
1170                         return r;
1171                 }
1172                 p->idx += pkt.count + 2;
1173                 switch (pkt.type) {
1174                 case PACKET_TYPE0:
1175                         r = r100_cs_parse_packet0(p, &pkt,
1176                                                   p->rdev->config.r300.reg_safe_bm,
1177                                                   p->rdev->config.r300.reg_safe_bm_size,
1178                                                   &r300_packet0_check);
1179                         break;
1180                 case PACKET_TYPE2:
1181                         break;
1182                 case PACKET_TYPE3:
1183                         r = r300_packet3_check(p, &pkt);
1184                         break;
1185                 default:
1186                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1187                         return -EINVAL;
1188                 }
1189                 if (r) {
1190                         return r;
1191                 }
1192         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1193         return 0;
1194 }
1195
1196 void r300_set_reg_safe(struct radeon_device *rdev)
1197 {
1198         rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
1199         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1200 }
1201
1202 void r300_mc_program(struct radeon_device *rdev)
1203 {
1204         struct r100_mc_save save;
1205         int r;
1206
1207         r = r100_debugfs_mc_info_init(rdev);
1208         if (r) {
1209                 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
1210         }
1211
1212         /* Stops all mc clients */
1213         r100_mc_stop(rdev, &save);
1214         if (rdev->flags & RADEON_IS_AGP) {
1215                 WREG32(R_00014C_MC_AGP_LOCATION,
1216                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
1217                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
1218                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
1219                 WREG32(R_00015C_AGP_BASE_2,
1220                         upper_32_bits(rdev->mc.agp_base) & 0xff);
1221         } else {
1222                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
1223                 WREG32(R_000170_AGP_BASE, 0);
1224                 WREG32(R_00015C_AGP_BASE_2, 0);
1225         }
1226         /* Wait for mc idle */
1227         if (r300_mc_wait_for_idle(rdev))
1228                 DRM_INFO("Failed to wait MC idle before programming MC.\n");
1229         /* Program MC, should be a 32bits limited address space */
1230         WREG32(R_000148_MC_FB_LOCATION,
1231                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
1232                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
1233         r100_mc_resume(rdev, &save);
1234 }
1235
1236 void r300_clock_startup(struct radeon_device *rdev)
1237 {
1238         u32 tmp;
1239
1240         if (radeon_dynclks != -1 && radeon_dynclks)
1241                 radeon_legacy_set_clock_gating(rdev, 1);
1242         /* We need to force on some of the block */
1243         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
1244         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
1245         if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380))
1246                 tmp |= S_00000D_FORCE_VAP(1);
1247         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
1248 }
1249
1250 static int r300_startup(struct radeon_device *rdev)
1251 {
1252         int r;
1253
1254         /* set common regs */
1255         r100_set_common_regs(rdev);
1256         /* program mc */
1257         r300_mc_program(rdev);
1258         /* Resume clock */
1259         r300_clock_startup(rdev);
1260         /* Initialize GPU configuration (# pipes, ...) */
1261         r300_gpu_init(rdev);
1262         /* Initialize GART (initialize after TTM so we can allocate
1263          * memory through TTM but finalize after TTM) */
1264         if (rdev->flags & RADEON_IS_PCIE) {
1265                 r = rv370_pcie_gart_enable(rdev);
1266                 if (r)
1267                         return r;
1268         }
1269
1270         if (rdev->family == CHIP_R300 ||
1271             rdev->family == CHIP_R350 ||
1272             rdev->family == CHIP_RV350)
1273                 r100_enable_bm(rdev);
1274
1275         if (rdev->flags & RADEON_IS_PCI) {
1276                 r = r100_pci_gart_enable(rdev);
1277                 if (r)
1278                         return r;
1279         }
1280         /* Enable IRQ */
1281         r100_irq_set(rdev);
1282         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
1283         /* 1M ring buffer */
1284         r = r100_cp_init(rdev, 1024 * 1024);
1285         if (r) {
1286                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
1287                 return r;
1288         }
1289         r = r100_wb_init(rdev);
1290         if (r)
1291                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
1292         r = r100_ib_init(rdev);
1293         if (r) {
1294                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
1295                 return r;
1296         }
1297         return 0;
1298 }
1299
1300 int r300_resume(struct radeon_device *rdev)
1301 {
1302         /* Make sur GART are not working */
1303         if (rdev->flags & RADEON_IS_PCIE)
1304                 rv370_pcie_gart_disable(rdev);
1305         if (rdev->flags & RADEON_IS_PCI)
1306                 r100_pci_gart_disable(rdev);
1307         /* Resume clock before doing reset */
1308         r300_clock_startup(rdev);
1309         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1310         if (radeon_gpu_reset(rdev)) {
1311                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1312                         RREG32(R_000E40_RBBM_STATUS),
1313                         RREG32(R_0007C0_CP_STAT));
1314         }
1315         /* post */
1316         radeon_combios_asic_init(rdev->ddev);
1317         /* Resume clock after posting */
1318         r300_clock_startup(rdev);
1319         /* Initialize surface registers */
1320         radeon_surface_init(rdev);
1321         return r300_startup(rdev);
1322 }
1323
1324 int r300_suspend(struct radeon_device *rdev)
1325 {
1326         r100_cp_disable(rdev);
1327         r100_wb_disable(rdev);
1328         r100_irq_disable(rdev);
1329         if (rdev->flags & RADEON_IS_PCIE)
1330                 rv370_pcie_gart_disable(rdev);
1331         if (rdev->flags & RADEON_IS_PCI)
1332                 r100_pci_gart_disable(rdev);
1333         return 0;
1334 }
1335
1336 void r300_fini(struct radeon_device *rdev)
1337 {
1338         r100_cp_fini(rdev);
1339         r100_wb_fini(rdev);
1340         r100_ib_fini(rdev);
1341         radeon_gem_fini(rdev);
1342         if (rdev->flags & RADEON_IS_PCIE)
1343                 rv370_pcie_gart_fini(rdev);
1344         if (rdev->flags & RADEON_IS_PCI)
1345                 r100_pci_gart_fini(rdev);
1346         radeon_agp_fini(rdev);
1347         radeon_irq_kms_fini(rdev);
1348         radeon_fence_driver_fini(rdev);
1349         radeon_bo_fini(rdev);
1350         radeon_atombios_fini(rdev);
1351         kfree(rdev->bios);
1352         rdev->bios = NULL;
1353 }
1354
1355 int r300_init(struct radeon_device *rdev)
1356 {
1357         int r;
1358
1359         /* Disable VGA */
1360         r100_vga_render_disable(rdev);
1361         /* Initialize scratch registers */
1362         radeon_scratch_init(rdev);
1363         /* Initialize surface registers */
1364         radeon_surface_init(rdev);
1365         /* TODO: disable VGA need to use VGA request */
1366         /* BIOS*/
1367         if (!radeon_get_bios(rdev)) {
1368                 if (ASIC_IS_AVIVO(rdev))
1369                         return -EINVAL;
1370         }
1371         if (rdev->is_atom_bios) {
1372                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
1373                 return -EINVAL;
1374         } else {
1375                 r = radeon_combios_init(rdev);
1376                 if (r)
1377                         return r;
1378         }
1379         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1380         if (radeon_gpu_reset(rdev)) {
1381                 dev_warn(rdev->dev,
1382                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1383                         RREG32(R_000E40_RBBM_STATUS),
1384                         RREG32(R_0007C0_CP_STAT));
1385         }
1386         /* check if cards are posted or not */
1387         if (radeon_boot_test_post_card(rdev) == false)
1388                 return -EINVAL;
1389         /* Set asic errata */
1390         r300_errata(rdev);
1391         /* Initialize clocks */
1392         radeon_get_clock_info(rdev->ddev);
1393         /* Initialize power management */
1394         radeon_pm_init(rdev);
1395         /* initialize AGP */
1396         if (rdev->flags & RADEON_IS_AGP) {
1397                 r = radeon_agp_init(rdev);
1398                 if (r) {
1399                         radeon_agp_disable(rdev);
1400                 }
1401         }
1402         /* initialize memory controller */
1403         r300_mc_init(rdev);
1404         /* Fence driver */
1405         r = radeon_fence_driver_init(rdev);
1406         if (r)
1407                 return r;
1408         r = radeon_irq_kms_init(rdev);
1409         if (r)
1410                 return r;
1411         /* Memory manager */
1412         r = radeon_bo_init(rdev);
1413         if (r)
1414                 return r;
1415         if (rdev->flags & RADEON_IS_PCIE) {
1416                 r = rv370_pcie_gart_init(rdev);
1417                 if (r)
1418                         return r;
1419         }
1420         if (rdev->flags & RADEON_IS_PCI) {
1421                 r = r100_pci_gart_init(rdev);
1422                 if (r)
1423                         return r;
1424         }
1425         r300_set_reg_safe(rdev);
1426         rdev->accel_working = true;
1427         r = r300_startup(rdev);
1428         if (r) {
1429                 /* Somethings want wront with the accel init stop accel */
1430                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1431                 r100_cp_fini(rdev);
1432                 r100_wb_fini(rdev);
1433                 r100_ib_fini(rdev);
1434                 radeon_irq_kms_fini(rdev);
1435                 if (rdev->flags & RADEON_IS_PCIE)
1436                         rv370_pcie_gart_fini(rdev);
1437                 if (rdev->flags & RADEON_IS_PCI)
1438                         r100_pci_gart_fini(rdev);
1439                 radeon_agp_fini(rdev);
1440                 rdev->accel_working = false;
1441         }
1442         return 0;
1443 }