drm/radeon/kms: generate the safe register tables.
[linux-2.6.git] / drivers / gpu / drm / radeon / r300.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/seq_file.h>
29 #include "drmP.h"
30 #include "drm.h"
31 #include "radeon_reg.h"
32 #include "radeon.h"
33 #include "radeon_drm.h"
34 #include "radeon_share.h"
35
36 #include "r300_reg_safe.h"
37
38 /* r300,r350,rv350,rv370,rv380 depends on : */
39 void r100_hdp_reset(struct radeon_device *rdev);
40 int r100_cp_reset(struct radeon_device *rdev);
41 int r100_rb2d_reset(struct radeon_device *rdev);
42 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
43 int r100_pci_gart_enable(struct radeon_device *rdev);
44 void r100_pci_gart_disable(struct radeon_device *rdev);
45 void r100_mc_setup(struct radeon_device *rdev);
46 void r100_mc_disable_clients(struct radeon_device *rdev);
47 int r100_gui_wait_for_idle(struct radeon_device *rdev);
48 int r100_cs_packet_parse(struct radeon_cs_parser *p,
49                          struct radeon_cs_packet *pkt,
50                          unsigned idx);
51 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p);
52 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
53                               struct radeon_cs_reloc **cs_reloc);
54 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
55                           struct radeon_cs_packet *pkt,
56                           const unsigned *auth, unsigned n,
57                           radeon_packet0_check_t check);
58 void r100_cs_dump_packet(struct radeon_cs_parser *p,
59                          struct radeon_cs_packet *pkt);
60 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
61                                          struct radeon_cs_packet *pkt,
62                                          struct radeon_object *robj);
63
64 /* This files gather functions specifics to:
65  * r300,r350,rv350,rv370,rv380
66  *
67  * Some of these functions might be used by newer ASICs.
68  */
69 void r300_gpu_init(struct radeon_device *rdev);
70 int r300_mc_wait_for_idle(struct radeon_device *rdev);
71 int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
72
73
74 /*
75  * rv370,rv380 PCIE GART
76  */
77 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
78 {
79         uint32_t tmp;
80         int i;
81
82         /* Workaround HW bug do flush 2 times */
83         for (i = 0; i < 2; i++) {
84                 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
85                 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
86                 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
87                 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
88         }
89         mb();
90 }
91
92 int rv370_pcie_gart_enable(struct radeon_device *rdev)
93 {
94         uint32_t table_addr;
95         uint32_t tmp;
96         int r;
97
98         /* Initialize common gart structure */
99         r = radeon_gart_init(rdev);
100         if (r) {
101                 return r;
102         }
103         r = rv370_debugfs_pcie_gart_info_init(rdev);
104         if (r) {
105                 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
106         }
107         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
108         r = radeon_gart_table_vram_alloc(rdev);
109         if (r) {
110                 return r;
111         }
112         /* discard memory request outside of configured range */
113         tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
114         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
115         WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_location);
116         tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 4096;
117         WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
118         WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
119         WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
120         table_addr = rdev->gart.table_addr;
121         WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
122         /* FIXME: setup default page */
123         WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_location);
124         WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
125         /* Clear error */
126         WREG32_PCIE(0x18, 0);
127         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
128         tmp |= RADEON_PCIE_TX_GART_EN;
129         tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
130         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
131         rv370_pcie_gart_tlb_flush(rdev);
132         DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
133                  rdev->mc.gtt_size >> 20, table_addr);
134         rdev->gart.ready = true;
135         return 0;
136 }
137
138 void rv370_pcie_gart_disable(struct radeon_device *rdev)
139 {
140         uint32_t tmp;
141
142         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
143         tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
144         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
145         if (rdev->gart.table.vram.robj) {
146                 radeon_object_kunmap(rdev->gart.table.vram.robj);
147                 radeon_object_unpin(rdev->gart.table.vram.robj);
148         }
149 }
150
151 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
152 {
153         void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
154
155         if (i < 0 || i > rdev->gart.num_gpu_pages) {
156                 return -EINVAL;
157         }
158         addr = (lower_32_bits(addr) >> 8) |
159                ((upper_32_bits(addr) & 0xff) << 24) |
160                0xc;
161         /* on x86 we want this to be CPU endian, on powerpc
162          * on powerpc without HW swappers, it'll get swapped on way
163          * into VRAM - so no need for cpu_to_le32 on VRAM tables */
164         writel(addr, ((void __iomem *)ptr) + (i * 4));
165         return 0;
166 }
167
168 int r300_gart_enable(struct radeon_device *rdev)
169 {
170 #if __OS_HAS_AGP
171         if (rdev->flags & RADEON_IS_AGP) {
172                 if (rdev->family > CHIP_RV350) {
173                         rv370_pcie_gart_disable(rdev);
174                 } else {
175                         r100_pci_gart_disable(rdev);
176                 }
177                 return 0;
178         }
179 #endif
180         if (rdev->flags & RADEON_IS_PCIE) {
181                 rdev->asic->gart_disable = &rv370_pcie_gart_disable;
182                 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
183                 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
184                 return rv370_pcie_gart_enable(rdev);
185         }
186         return r100_pci_gart_enable(rdev);
187 }
188
189
190 /*
191  * MC
192  */
193 int r300_mc_init(struct radeon_device *rdev)
194 {
195         int r;
196
197         if (r100_debugfs_rbbm_init(rdev)) {
198                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
199         }
200
201         r300_gpu_init(rdev);
202         r100_pci_gart_disable(rdev);
203         if (rdev->flags & RADEON_IS_PCIE) {
204                 rv370_pcie_gart_disable(rdev);
205         }
206
207         /* Setup GPU memory space */
208         rdev->mc.vram_location = 0xFFFFFFFFUL;
209         rdev->mc.gtt_location = 0xFFFFFFFFUL;
210         if (rdev->flags & RADEON_IS_AGP) {
211                 r = radeon_agp_init(rdev);
212                 if (r) {
213                         printk(KERN_WARNING "[drm] Disabling AGP\n");
214                         rdev->flags &= ~RADEON_IS_AGP;
215                         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
216                 } else {
217                         rdev->mc.gtt_location = rdev->mc.agp_base;
218                 }
219         }
220         r = radeon_mc_setup(rdev);
221         if (r) {
222                 return r;
223         }
224
225         /* Program GPU memory space */
226         r100_mc_disable_clients(rdev);
227         if (r300_mc_wait_for_idle(rdev)) {
228                 printk(KERN_WARNING "Failed to wait MC idle while "
229                        "programming pipes. Bad things might happen.\n");
230         }
231         r100_mc_setup(rdev);
232         return 0;
233 }
234
235 void r300_mc_fini(struct radeon_device *rdev)
236 {
237         if (rdev->flags & RADEON_IS_PCIE) {
238                 rv370_pcie_gart_disable(rdev);
239                 radeon_gart_table_vram_free(rdev);
240         } else {
241                 r100_pci_gart_disable(rdev);
242                 radeon_gart_table_ram_free(rdev);
243         }
244         radeon_gart_fini(rdev);
245 }
246
247
248 /*
249  * Fence emission
250  */
251 void r300_fence_ring_emit(struct radeon_device *rdev,
252                           struct radeon_fence *fence)
253 {
254         /* Who ever call radeon_fence_emit should call ring_lock and ask
255          * for enough space (today caller are ib schedule and buffer move) */
256         /* Write SC register so SC & US assert idle */
257         radeon_ring_write(rdev, PACKET0(0x43E0, 0));
258         radeon_ring_write(rdev, 0);
259         radeon_ring_write(rdev, PACKET0(0x43E4, 0));
260         radeon_ring_write(rdev, 0);
261         /* Flush 3D cache */
262         radeon_ring_write(rdev, PACKET0(0x4E4C, 0));
263         radeon_ring_write(rdev, (2 << 0));
264         radeon_ring_write(rdev, PACKET0(0x4F18, 0));
265         radeon_ring_write(rdev, (1 << 0));
266         /* Wait until IDLE & CLEAN */
267         radeon_ring_write(rdev, PACKET0(0x1720, 0));
268         radeon_ring_write(rdev, (1 << 17) | (1 << 16)  | (1 << 9));
269         /* Emit fence sequence & fire IRQ */
270         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
271         radeon_ring_write(rdev, fence->seq);
272         radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
273         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
274 }
275
276
277 /*
278  * Global GPU functions
279  */
280 int r300_copy_dma(struct radeon_device *rdev,
281                   uint64_t src_offset,
282                   uint64_t dst_offset,
283                   unsigned num_pages,
284                   struct radeon_fence *fence)
285 {
286         uint32_t size;
287         uint32_t cur_size;
288         int i, num_loops;
289         int r = 0;
290
291         /* radeon pitch is /64 */
292         size = num_pages << PAGE_SHIFT;
293         num_loops = DIV_ROUND_UP(size, 0x1FFFFF);
294         r = radeon_ring_lock(rdev, num_loops * 4 + 64);
295         if (r) {
296                 DRM_ERROR("radeon: moving bo (%d).\n", r);
297                 return r;
298         }
299         /* Must wait for 2D idle & clean before DMA or hangs might happen */
300         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0 ));
301         radeon_ring_write(rdev, (1 << 16));
302         for (i = 0; i < num_loops; i++) {
303                 cur_size = size;
304                 if (cur_size > 0x1FFFFF) {
305                         cur_size = 0x1FFFFF;
306                 }
307                 size -= cur_size;
308                 radeon_ring_write(rdev, PACKET0(0x720, 2));
309                 radeon_ring_write(rdev, src_offset);
310                 radeon_ring_write(rdev, dst_offset);
311                 radeon_ring_write(rdev, cur_size | (1 << 31) | (1 << 30));
312                 src_offset += cur_size;
313                 dst_offset += cur_size;
314         }
315         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
316         radeon_ring_write(rdev, RADEON_WAIT_DMA_GUI_IDLE);
317         if (fence) {
318                 r = radeon_fence_emit(rdev, fence);
319         }
320         radeon_ring_unlock_commit(rdev);
321         return r;
322 }
323
324 void r300_ring_start(struct radeon_device *rdev)
325 {
326         unsigned gb_tile_config;
327         int r;
328
329         /* Sub pixel 1/12 so we can have 4K rendering according to doc */
330         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
331         switch(rdev->num_gb_pipes) {
332         case 2:
333                 gb_tile_config |= R300_PIPE_COUNT_R300;
334                 break;
335         case 3:
336                 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
337                 break;
338         case 4:
339                 gb_tile_config |= R300_PIPE_COUNT_R420;
340                 break;
341         case 1:
342         default:
343                 gb_tile_config |= R300_PIPE_COUNT_RV350;
344                 break;
345         }
346
347         r = radeon_ring_lock(rdev, 64);
348         if (r) {
349                 return;
350         }
351         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
352         radeon_ring_write(rdev,
353                           RADEON_ISYNC_ANY2D_IDLE3D |
354                           RADEON_ISYNC_ANY3D_IDLE2D |
355                           RADEON_ISYNC_WAIT_IDLEGUI |
356                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
357         radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
358         radeon_ring_write(rdev, gb_tile_config);
359         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
360         radeon_ring_write(rdev,
361                           RADEON_WAIT_2D_IDLECLEAN |
362                           RADEON_WAIT_3D_IDLECLEAN);
363         radeon_ring_write(rdev, PACKET0(0x170C, 0));
364         radeon_ring_write(rdev, 1 << 31);
365         radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
366         radeon_ring_write(rdev, 0);
367         radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
368         radeon_ring_write(rdev, 0);
369         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
370         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
371         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
372         radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
373         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
374         radeon_ring_write(rdev,
375                           RADEON_WAIT_2D_IDLECLEAN |
376                           RADEON_WAIT_3D_IDLECLEAN);
377         radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
378         radeon_ring_write(rdev, 0);
379         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
380         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
381         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
382         radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
383         radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
384         radeon_ring_write(rdev,
385                           ((6 << R300_MS_X0_SHIFT) |
386                            (6 << R300_MS_Y0_SHIFT) |
387                            (6 << R300_MS_X1_SHIFT) |
388                            (6 << R300_MS_Y1_SHIFT) |
389                            (6 << R300_MS_X2_SHIFT) |
390                            (6 << R300_MS_Y2_SHIFT) |
391                            (6 << R300_MSBD0_Y_SHIFT) |
392                            (6 << R300_MSBD0_X_SHIFT)));
393         radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
394         radeon_ring_write(rdev,
395                           ((6 << R300_MS_X3_SHIFT) |
396                            (6 << R300_MS_Y3_SHIFT) |
397                            (6 << R300_MS_X4_SHIFT) |
398                            (6 << R300_MS_Y4_SHIFT) |
399                            (6 << R300_MS_X5_SHIFT) |
400                            (6 << R300_MS_Y5_SHIFT) |
401                            (6 << R300_MSBD1_SHIFT)));
402         radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
403         radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
404         radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
405         radeon_ring_write(rdev,
406                           R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
407         radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
408         radeon_ring_write(rdev,
409                           R300_GEOMETRY_ROUND_NEAREST |
410                           R300_COLOR_ROUND_NEAREST);
411         radeon_ring_unlock_commit(rdev);
412 }
413
414 void r300_errata(struct radeon_device *rdev)
415 {
416         rdev->pll_errata = 0;
417
418         if (rdev->family == CHIP_R300 &&
419             (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
420                 rdev->pll_errata |= CHIP_ERRATA_R300_CG;
421         }
422 }
423
424 int r300_mc_wait_for_idle(struct radeon_device *rdev)
425 {
426         unsigned i;
427         uint32_t tmp;
428
429         for (i = 0; i < rdev->usec_timeout; i++) {
430                 /* read MC_STATUS */
431                 tmp = RREG32(0x0150);
432                 if (tmp & (1 << 4)) {
433                         return 0;
434                 }
435                 DRM_UDELAY(1);
436         }
437         return -1;
438 }
439
440 void r300_gpu_init(struct radeon_device *rdev)
441 {
442         uint32_t gb_tile_config, tmp;
443
444         r100_hdp_reset(rdev);
445         /* FIXME: rv380 one pipes ? */
446         if ((rdev->family == CHIP_R300) || (rdev->family == CHIP_R350)) {
447                 /* r300,r350 */
448                 rdev->num_gb_pipes = 2;
449         } else {
450                 /* rv350,rv370,rv380 */
451                 rdev->num_gb_pipes = 1;
452         }
453         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
454         switch (rdev->num_gb_pipes) {
455         case 2:
456                 gb_tile_config |= R300_PIPE_COUNT_R300;
457                 break;
458         case 3:
459                 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
460                 break;
461         case 4:
462                 gb_tile_config |= R300_PIPE_COUNT_R420;
463                 break;
464         default:
465         case 1:
466                 gb_tile_config |= R300_PIPE_COUNT_RV350;
467                 break;
468         }
469         WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
470
471         if (r100_gui_wait_for_idle(rdev)) {
472                 printk(KERN_WARNING "Failed to wait GUI idle while "
473                        "programming pipes. Bad things might happen.\n");
474         }
475
476         tmp = RREG32(0x170C);
477         WREG32(0x170C, tmp | (1 << 31));
478
479         WREG32(R300_RB2D_DSTCACHE_MODE,
480                R300_DC_AUTOFLUSH_ENABLE |
481                R300_DC_DC_DISABLE_IGNORE_PE);
482
483         if (r100_gui_wait_for_idle(rdev)) {
484                 printk(KERN_WARNING "Failed to wait GUI idle while "
485                        "programming pipes. Bad things might happen.\n");
486         }
487         if (r300_mc_wait_for_idle(rdev)) {
488                 printk(KERN_WARNING "Failed to wait MC idle while "
489                        "programming pipes. Bad things might happen.\n");
490         }
491         DRM_INFO("radeon: %d pipes initialized.\n", rdev->num_gb_pipes);
492 }
493
494 int r300_ga_reset(struct radeon_device *rdev)
495 {
496         uint32_t tmp;
497         bool reinit_cp;
498         int i;
499
500         reinit_cp = rdev->cp.ready;
501         rdev->cp.ready = false;
502         for (i = 0; i < rdev->usec_timeout; i++) {
503                 WREG32(RADEON_CP_CSQ_MODE, 0);
504                 WREG32(RADEON_CP_CSQ_CNTL, 0);
505                 WREG32(RADEON_RBBM_SOFT_RESET, 0x32005);
506                 (void)RREG32(RADEON_RBBM_SOFT_RESET);
507                 udelay(200);
508                 WREG32(RADEON_RBBM_SOFT_RESET, 0);
509                 /* Wait to prevent race in RBBM_STATUS */
510                 mdelay(1);
511                 tmp = RREG32(RADEON_RBBM_STATUS);
512                 if (tmp & ((1 << 20) | (1 << 26))) {
513                         DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp);
514                         /* GA still busy soft reset it */
515                         WREG32(0x429C, 0x200);
516                         WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0);
517                         WREG32(0x43E0, 0);
518                         WREG32(0x43E4, 0);
519                         WREG32(0x24AC, 0);
520                 }
521                 /* Wait to prevent race in RBBM_STATUS */
522                 mdelay(1);
523                 tmp = RREG32(RADEON_RBBM_STATUS);
524                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
525                         break;
526                 }
527         }
528         for (i = 0; i < rdev->usec_timeout; i++) {
529                 tmp = RREG32(RADEON_RBBM_STATUS);
530                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
531                         DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
532                                  tmp);
533                         if (reinit_cp) {
534                                 return r100_cp_init(rdev, rdev->cp.ring_size);
535                         }
536                         return 0;
537                 }
538                 DRM_UDELAY(1);
539         }
540         tmp = RREG32(RADEON_RBBM_STATUS);
541         DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
542         return -1;
543 }
544
545 int r300_gpu_reset(struct radeon_device *rdev)
546 {
547         uint32_t status;
548
549         /* reset order likely matter */
550         status = RREG32(RADEON_RBBM_STATUS);
551         /* reset HDP */
552         r100_hdp_reset(rdev);
553         /* reset rb2d */
554         if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
555                 r100_rb2d_reset(rdev);
556         }
557         /* reset GA */
558         if (status & ((1 << 20) | (1 << 26))) {
559                 r300_ga_reset(rdev);
560         }
561         /* reset CP */
562         status = RREG32(RADEON_RBBM_STATUS);
563         if (status & (1 << 16)) {
564                 r100_cp_reset(rdev);
565         }
566         /* Check if GPU is idle */
567         status = RREG32(RADEON_RBBM_STATUS);
568         if (status & (1 << 31)) {
569                 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
570                 return -1;
571         }
572         DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
573         return 0;
574 }
575
576
577 /*
578  * r300,r350,rv350,rv380 VRAM info
579  */
580 void r300_vram_info(struct radeon_device *rdev)
581 {
582         uint32_t tmp;
583
584         /* DDR for all card after R300 & IGP */
585         rdev->mc.vram_is_ddr = true;
586         tmp = RREG32(RADEON_MEM_CNTL);
587         if (tmp & R300_MEM_NUM_CHANNELS_MASK) {
588                 rdev->mc.vram_width = 128;
589         } else {
590                 rdev->mc.vram_width = 64;
591         }
592
593         r100_vram_init_sizes(rdev);
594 }
595
596
597 /*
598  * PCIE Lanes
599  */
600
601 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
602 {
603         uint32_t link_width_cntl, mask;
604
605         if (rdev->flags & RADEON_IS_IGP)
606                 return;
607
608         if (!(rdev->flags & RADEON_IS_PCIE))
609                 return;
610
611         /* FIXME wait for idle */
612
613         switch (lanes) {
614         case 0:
615                 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
616                 break;
617         case 1:
618                 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
619                 break;
620         case 2:
621                 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
622                 break;
623         case 4:
624                 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
625                 break;
626         case 8:
627                 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
628                 break;
629         case 12:
630                 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
631                 break;
632         case 16:
633         default:
634                 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
635                 break;
636         }
637
638         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
639
640         if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
641             (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
642                 return;
643
644         link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
645                              RADEON_PCIE_LC_RECONFIG_NOW |
646                              RADEON_PCIE_LC_RECONFIG_LATER |
647                              RADEON_PCIE_LC_SHORT_RECONFIG_EN);
648         link_width_cntl |= mask;
649         WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
650         WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
651                                                      RADEON_PCIE_LC_RECONFIG_NOW));
652
653         /* wait for lane set to complete */
654         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
655         while (link_width_cntl == 0xffffffff)
656                 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
657
658 }
659
660
661 /*
662  * Debugfs info
663  */
664 #if defined(CONFIG_DEBUG_FS)
665 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data)
666 {
667         struct drm_info_node *node = (struct drm_info_node *) m->private;
668         struct drm_device *dev = node->minor->dev;
669         struct radeon_device *rdev = dev->dev_private;
670         uint32_t tmp;
671
672         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
673         seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
674         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
675         seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
676         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
677         seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
678         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
679         seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
680         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
681         seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
682         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
683         seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
684         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
685         seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
686         return 0;
687 }
688
689 static struct drm_info_list rv370_pcie_gart_info_list[] = {
690         {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
691 };
692 #endif
693
694 int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
695 {
696 #if defined(CONFIG_DEBUG_FS)
697         return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
698 #else
699         return 0;
700 #endif
701 }
702
703
704 /*
705  * CS functions
706  */
707 struct r300_cs_track_cb {
708         struct radeon_object    *robj;
709         unsigned                pitch;
710         unsigned                cpp;
711         unsigned                offset;
712 };
713
714 struct r300_cs_track_array {
715         struct radeon_object    *robj;
716         unsigned                esize;
717 };
718
719 struct r300_cs_track_texture {
720         struct radeon_object    *robj;
721         unsigned                pitch;
722         unsigned                width;
723         unsigned                height;
724         unsigned                num_levels;
725         unsigned                cpp;
726         unsigned                tex_coord_type;
727         unsigned                txdepth;
728         unsigned                width_11;
729         unsigned                height_11;
730         bool                    use_pitch;
731         bool                    enabled;
732         bool                    roundup_w;
733         bool                    roundup_h;
734 };
735
736 struct r300_cs_track {
737         unsigned                        num_cb;
738         unsigned                        maxy;
739         unsigned                        vtx_size;
740         unsigned                        vap_vf_cntl;
741         unsigned                        immd_dwords;
742         unsigned                        num_arrays;
743         unsigned                        max_indx;
744         struct r300_cs_track_array      arrays[11];
745         struct r300_cs_track_cb         cb[4];
746         struct r300_cs_track_cb         zb;
747         struct r300_cs_track_texture    textures[16];
748         bool                            z_enabled;
749 };
750
751 static inline void r300_cs_track_texture_print(struct r300_cs_track_texture *t)
752 {
753         DRM_ERROR("pitch                      %d\n", t->pitch);
754         DRM_ERROR("width                      %d\n", t->width);
755         DRM_ERROR("height                     %d\n", t->height);
756         DRM_ERROR("num levels                 %d\n", t->num_levels);
757         DRM_ERROR("depth                      %d\n", t->txdepth);
758         DRM_ERROR("bpp                        %d\n", t->cpp);
759         DRM_ERROR("coordinate type            %d\n", t->tex_coord_type);
760         DRM_ERROR("width round to power of 2  %d\n", t->roundup_w);
761         DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
762 }
763
764 static inline int r300_cs_track_texture_check(struct radeon_device *rdev,
765                                               struct r300_cs_track *track)
766 {
767         struct radeon_object *robj;
768         unsigned long size;
769         unsigned u, i, w, h;
770
771         for (u = 0; u < 16; u++) {
772                 if (!track->textures[u].enabled)
773                         continue;
774                 robj = track->textures[u].robj;
775                 if (robj == NULL) {
776                         DRM_ERROR("No texture bound to unit %u\n", u);
777                         return -EINVAL;
778                 }
779                 size = 0;
780                 for (i = 0; i <= track->textures[u].num_levels; i++) {
781                         if (track->textures[u].use_pitch) {
782                                 w = track->textures[u].pitch / (1 << i);
783                         } else {
784                                 w = track->textures[u].width / (1 << i);
785                                 if (rdev->family >= CHIP_RV515)
786                                         w |= track->textures[u].width_11;
787                                 if (track->textures[u].roundup_w)
788                                         w = roundup_pow_of_two(w);
789                         }
790                         h = track->textures[u].height / (1 << i);
791                         if (rdev->family >= CHIP_RV515)
792                                 h |= track->textures[u].height_11;
793                         if (track->textures[u].roundup_h)
794                                 h = roundup_pow_of_two(h);
795                         size += w * h;
796                 }
797                 size *= track->textures[u].cpp;
798                 switch (track->textures[u].tex_coord_type) {
799                 case 0:
800                         break;
801                 case 1:
802                         size *= (1 << track->textures[u].txdepth);
803                         break;
804                 case 2:
805                         size *= 6;
806                         break;
807                 default:
808                         DRM_ERROR("Invalid texture coordinate type %u for unit "
809                                   "%u\n", track->textures[u].tex_coord_type, u);
810                         return -EINVAL;
811                 }
812                 if (size > radeon_object_size(robj)) {
813                         DRM_ERROR("Texture of unit %u needs %lu bytes but is "
814                                   "%lu\n", u, size, radeon_object_size(robj));
815                         r300_cs_track_texture_print(&track->textures[u]);
816                         return -EINVAL;
817                 }
818         }
819         return 0;
820 }
821
822 int r300_cs_track_check(struct radeon_device *rdev, struct r300_cs_track *track)
823 {
824         unsigned i;
825         unsigned long size;
826         unsigned prim_walk;
827         unsigned nverts;
828
829         for (i = 0; i < track->num_cb; i++) {
830                 if (track->cb[i].robj == NULL) {
831                         DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
832                         return -EINVAL;
833                 }
834                 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
835                 size += track->cb[i].offset;
836                 if (size > radeon_object_size(track->cb[i].robj)) {
837                         DRM_ERROR("[drm] Buffer too small for color buffer %d "
838                                   "(need %lu have %lu) !\n", i, size,
839                                   radeon_object_size(track->cb[i].robj));
840                         DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
841                                   i, track->cb[i].pitch, track->cb[i].cpp,
842                                   track->cb[i].offset, track->maxy);
843                         return -EINVAL;
844                 }
845         }
846         if (track->z_enabled) {
847                 if (track->zb.robj == NULL) {
848                         DRM_ERROR("[drm] No buffer for z buffer !\n");
849                         return -EINVAL;
850                 }
851                 size = track->zb.pitch * track->zb.cpp * track->maxy;
852                 size += track->zb.offset;
853                 if (size > radeon_object_size(track->zb.robj)) {
854                         DRM_ERROR("[drm] Buffer too small for z buffer "
855                                   "(need %lu have %lu) !\n", size,
856                                   radeon_object_size(track->zb.robj));
857                         return -EINVAL;
858                 }
859         }
860         prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
861         nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
862         switch (prim_walk) {
863         case 1:
864                 for (i = 0; i < track->num_arrays; i++) {
865                         size = track->arrays[i].esize * track->max_indx * 4;
866                         if (track->arrays[i].robj == NULL) {
867                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
868                                           "bound\n", prim_walk, i);
869                                 return -EINVAL;
870                         }
871                         if (size > radeon_object_size(track->arrays[i].robj)) {
872                                 DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
873                                            "have %lu dwords\n", prim_walk, i,
874                                            size >> 2,
875                                            radeon_object_size(track->arrays[i].robj) >> 2);
876                                 DRM_ERROR("Max indices %u\n", track->max_indx);
877                                 return -EINVAL;
878                         }
879                 }
880                 break;
881         case 2:
882                 for (i = 0; i < track->num_arrays; i++) {
883                         size = track->arrays[i].esize * (nverts - 1) * 4;
884                         if (track->arrays[i].robj == NULL) {
885                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
886                                           "bound\n", prim_walk, i);
887                                 return -EINVAL;
888                         }
889                         if (size > radeon_object_size(track->arrays[i].robj)) {
890                                 DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
891                                            "have %lu dwords\n", prim_walk, i, size >> 2,
892                                            radeon_object_size(track->arrays[i].robj) >> 2);
893                                 return -EINVAL;
894                         }
895                 }
896                 break;
897         case 3:
898                 size = track->vtx_size * nverts;
899                 if (size != track->immd_dwords) {
900                         DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
901                                   track->immd_dwords, size);
902                         DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
903                                   nverts, track->vtx_size);
904                         return -EINVAL;
905                 }
906                 break;
907         default:
908                 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
909                           prim_walk);
910                 return -EINVAL;
911         }
912         return r300_cs_track_texture_check(rdev, track);
913 }
914
915 static inline void r300_cs_track_clear(struct r300_cs_track *track)
916 {
917         unsigned i;
918
919         track->num_cb = 4;
920         track->maxy = 4096;
921         for (i = 0; i < track->num_cb; i++) {
922                 track->cb[i].robj = NULL;
923                 track->cb[i].pitch = 8192;
924                 track->cb[i].cpp = 16;
925                 track->cb[i].offset = 0;
926         }
927         track->z_enabled = true;
928         track->zb.robj = NULL;
929         track->zb.pitch = 8192;
930         track->zb.cpp = 4;
931         track->zb.offset = 0;
932         track->vtx_size = 0x7F;
933         track->immd_dwords = 0xFFFFFFFFUL;
934         track->num_arrays = 11;
935         track->max_indx = 0x00FFFFFFUL;
936         for (i = 0; i < track->num_arrays; i++) {
937                 track->arrays[i].robj = NULL;
938                 track->arrays[i].esize = 0x7F;
939         }
940         for (i = 0; i < 16; i++) {
941                 track->textures[i].pitch = 16536;
942                 track->textures[i].width = 16536;
943                 track->textures[i].height = 16536;
944                 track->textures[i].width_11 = 1 << 11;
945                 track->textures[i].height_11 = 1 << 11;
946                 track->textures[i].num_levels = 12;
947                 track->textures[i].txdepth = 16;
948                 track->textures[i].cpp = 64;
949                 track->textures[i].tex_coord_type = 1;
950                 track->textures[i].robj = NULL;
951                 /* CS IB emission code makes sure texture unit are disabled */
952                 track->textures[i].enabled = false;
953                 track->textures[i].roundup_w = true;
954                 track->textures[i].roundup_h = true;
955         }
956 }
957
958 static int r300_packet0_check(struct radeon_cs_parser *p,
959                 struct radeon_cs_packet *pkt,
960                 unsigned idx, unsigned reg)
961 {
962         struct radeon_cs_chunk *ib_chunk;
963         struct radeon_cs_reloc *reloc;
964         struct r300_cs_track *track;
965         volatile uint32_t *ib;
966         uint32_t tmp, tile_flags = 0;
967         unsigned i;
968         int r;
969
970         ib = p->ib->ptr;
971         ib_chunk = &p->chunks[p->chunk_ib_idx];
972         track = (struct r300_cs_track*)p->track;
973         switch(reg) {
974         case AVIVO_D1MODE_VLINE_START_END:
975         case RADEON_CRTC_GUI_TRIG_VLINE:
976                 r = r100_cs_packet_parse_vline(p);
977                 if (r) {
978                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
979                                         idx, reg);
980                         r100_cs_dump_packet(p, pkt);
981                         return r;
982                 }
983                 break;
984         case RADEON_DST_PITCH_OFFSET:
985         case RADEON_SRC_PITCH_OFFSET:
986                 r = r100_cs_packet_next_reloc(p, &reloc);
987                 if (r) {
988                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
989                                         idx, reg);
990                         r100_cs_dump_packet(p, pkt);
991                         return r;
992                 }
993                 tmp = ib_chunk->kdata[idx] & 0x003fffff;
994                 tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
995
996                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
997                         tile_flags |= RADEON_DST_TILE_MACRO;
998                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
999                         if (reg == RADEON_SRC_PITCH_OFFSET) {
1000                                 DRM_ERROR("Cannot src blit from microtiled surface\n");
1001                                 r100_cs_dump_packet(p, pkt);
1002                                 return -EINVAL;
1003                         }
1004                         tile_flags |= RADEON_DST_TILE_MICRO;
1005                 }
1006                 tmp |= tile_flags;
1007                 ib[idx] = (ib_chunk->kdata[idx] & 0x3fc00000) | tmp;
1008                 break;
1009         case R300_RB3D_COLOROFFSET0:
1010         case R300_RB3D_COLOROFFSET1:
1011         case R300_RB3D_COLOROFFSET2:
1012         case R300_RB3D_COLOROFFSET3:
1013                 i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
1014                 r = r100_cs_packet_next_reloc(p, &reloc);
1015                 if (r) {
1016                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1017                                         idx, reg);
1018                         r100_cs_dump_packet(p, pkt);
1019                         return r;
1020                 }
1021                 track->cb[i].robj = reloc->robj;
1022                 track->cb[i].offset = ib_chunk->kdata[idx];
1023                 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1024                 break;
1025         case R300_ZB_DEPTHOFFSET:
1026                 r = r100_cs_packet_next_reloc(p, &reloc);
1027                 if (r) {
1028                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1029                                         idx, reg);
1030                         r100_cs_dump_packet(p, pkt);
1031                         return r;
1032                 }
1033                 track->zb.robj = reloc->robj;
1034                 track->zb.offset = ib_chunk->kdata[idx];
1035                 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1036                 break;
1037         case R300_TX_OFFSET_0:
1038         case R300_TX_OFFSET_0+4:
1039         case R300_TX_OFFSET_0+8:
1040         case R300_TX_OFFSET_0+12:
1041         case R300_TX_OFFSET_0+16:
1042         case R300_TX_OFFSET_0+20:
1043         case R300_TX_OFFSET_0+24:
1044         case R300_TX_OFFSET_0+28:
1045         case R300_TX_OFFSET_0+32:
1046         case R300_TX_OFFSET_0+36:
1047         case R300_TX_OFFSET_0+40:
1048         case R300_TX_OFFSET_0+44:
1049         case R300_TX_OFFSET_0+48:
1050         case R300_TX_OFFSET_0+52:
1051         case R300_TX_OFFSET_0+56:
1052         case R300_TX_OFFSET_0+60:
1053                 i = (reg - R300_TX_OFFSET_0) >> 2;
1054                 r = r100_cs_packet_next_reloc(p, &reloc);
1055                 if (r) {
1056                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1057                                         idx, reg);
1058                         r100_cs_dump_packet(p, pkt);
1059                         return r;
1060                 }
1061                 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1062                 track->textures[i].robj = reloc->robj;
1063                 break;
1064         /* Tracked registers */
1065         case 0x2084:
1066                 /* VAP_VF_CNTL */
1067                 track->vap_vf_cntl = ib_chunk->kdata[idx];
1068                 break;
1069         case 0x20B4:
1070                 /* VAP_VTX_SIZE */
1071                 track->vtx_size = ib_chunk->kdata[idx] & 0x7F;
1072                 break;
1073         case 0x2134:
1074                 /* VAP_VF_MAX_VTX_INDX */
1075                 track->max_indx = ib_chunk->kdata[idx] & 0x00FFFFFFUL;
1076                 break;
1077         case 0x43E4:
1078                 /* SC_SCISSOR1 */
1079                 track->maxy = ((ib_chunk->kdata[idx] >> 13) & 0x1FFF) + 1;
1080                 if (p->rdev->family < CHIP_RV515) {
1081                         track->maxy -= 1440;
1082                 }
1083                 break;
1084         case 0x4E00:
1085                 /* RB3D_CCTL */
1086                 track->num_cb = ((ib_chunk->kdata[idx] >> 5) & 0x3) + 1;
1087                 break;
1088         case 0x4E38:
1089         case 0x4E3C:
1090         case 0x4E40:
1091         case 0x4E44:
1092                 /* RB3D_COLORPITCH0 */
1093                 /* RB3D_COLORPITCH1 */
1094                 /* RB3D_COLORPITCH2 */
1095                 /* RB3D_COLORPITCH3 */
1096                 r = r100_cs_packet_next_reloc(p, &reloc);
1097                 if (r) {
1098                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1099                                   idx, reg);
1100                         r100_cs_dump_packet(p, pkt);
1101                         return r;
1102                 }
1103
1104                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1105                         tile_flags |= R300_COLOR_TILE_ENABLE;
1106                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1107                         tile_flags |= R300_COLOR_MICROTILE_ENABLE;
1108
1109                 tmp = ib_chunk->kdata[idx] & ~(0x7 << 16);
1110                 tmp |= tile_flags;
1111                 ib[idx] = tmp;
1112
1113                 i = (reg - 0x4E38) >> 2;
1114                 track->cb[i].pitch = ib_chunk->kdata[idx] & 0x3FFE;
1115                 switch (((ib_chunk->kdata[idx] >> 21) & 0xF)) {
1116                 case 9:
1117                 case 11:
1118                 case 12:
1119                         track->cb[i].cpp = 1;
1120                         break;
1121                 case 3:
1122                 case 4:
1123                 case 13:
1124                 case 15:
1125                         track->cb[i].cpp = 2;
1126                         break;
1127                 case 6:
1128                         track->cb[i].cpp = 4;
1129                         break;
1130                 case 10:
1131                         track->cb[i].cpp = 8;
1132                         break;
1133                 case 7:
1134                         track->cb[i].cpp = 16;
1135                         break;
1136                 default:
1137                         DRM_ERROR("Invalid color buffer format (%d) !\n",
1138                                   ((ib_chunk->kdata[idx] >> 21) & 0xF));
1139                         return -EINVAL;
1140                 }
1141                 break;
1142         case 0x4F00:
1143                 /* ZB_CNTL */
1144                 if (ib_chunk->kdata[idx] & 2) {
1145                         track->z_enabled = true;
1146                 } else {
1147                         track->z_enabled = false;
1148                 }
1149                 break;
1150         case 0x4F10:
1151                 /* ZB_FORMAT */
1152                 switch ((ib_chunk->kdata[idx] & 0xF)) {
1153                 case 0:
1154                 case 1:
1155                         track->zb.cpp = 2;
1156                         break;
1157                 case 2:
1158                         track->zb.cpp = 4;
1159                         break;
1160                 default:
1161                         DRM_ERROR("Invalid z buffer format (%d) !\n",
1162                                   (ib_chunk->kdata[idx] & 0xF));
1163                         return -EINVAL;
1164                 }
1165                 break;
1166         case 0x4F24:
1167                 /* ZB_DEPTHPITCH */
1168                 r = r100_cs_packet_next_reloc(p, &reloc);
1169                 if (r) {
1170                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1171                                   idx, reg);
1172                         r100_cs_dump_packet(p, pkt);
1173                         return r;
1174                 }
1175
1176                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1177                         tile_flags |= R300_DEPTHMACROTILE_ENABLE;
1178                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1179                         tile_flags |= R300_DEPTHMICROTILE_TILED;;
1180
1181                 tmp = ib_chunk->kdata[idx] & ~(0x7 << 16);
1182                 tmp |= tile_flags;
1183                 ib[idx] = tmp;
1184
1185                 track->zb.pitch = ib_chunk->kdata[idx] & 0x3FFC;
1186                 break;
1187         case 0x4104:
1188                 for (i = 0; i < 16; i++) {
1189                         bool enabled;
1190
1191                         enabled = !!(ib_chunk->kdata[idx] & (1 << i));
1192                         track->textures[i].enabled = enabled;
1193                 }
1194                 break;
1195         case 0x44C0:
1196         case 0x44C4:
1197         case 0x44C8:
1198         case 0x44CC:
1199         case 0x44D0:
1200         case 0x44D4:
1201         case 0x44D8:
1202         case 0x44DC:
1203         case 0x44E0:
1204         case 0x44E4:
1205         case 0x44E8:
1206         case 0x44EC:
1207         case 0x44F0:
1208         case 0x44F4:
1209         case 0x44F8:
1210         case 0x44FC:
1211                 /* TX_FORMAT1_[0-15] */
1212                 i = (reg - 0x44C0) >> 2;
1213                 tmp = (ib_chunk->kdata[idx] >> 25) & 0x3;
1214                 track->textures[i].tex_coord_type = tmp;
1215                 switch ((ib_chunk->kdata[idx] & 0x1F)) {
1216                 case 0:
1217                 case 2:
1218                 case 5:
1219                 case 18:
1220                 case 20:
1221                 case 21:
1222                         track->textures[i].cpp = 1;
1223                         break;
1224                 case 1:
1225                 case 3:
1226                 case 6:
1227                 case 7:
1228                 case 10:
1229                 case 11:
1230                 case 19:
1231                 case 22:
1232                 case 24:
1233                         track->textures[i].cpp = 2;
1234                         break;
1235                 case 4:
1236                 case 8:
1237                 case 9:
1238                 case 12:
1239                 case 13:
1240                 case 23:
1241                 case 25:
1242                 case 27:
1243                 case 30:
1244                         track->textures[i].cpp = 4;
1245                         break;
1246                 case 14:
1247                 case 26:
1248                 case 28:
1249                         track->textures[i].cpp = 8;
1250                         break;
1251                 case 29:
1252                         track->textures[i].cpp = 16;
1253                         break;
1254                 default:
1255                         DRM_ERROR("Invalid texture format %u\n",
1256                                   (ib_chunk->kdata[idx] & 0x1F));
1257                         return -EINVAL;
1258                         break;
1259                 }
1260                 break;
1261         case 0x4400:
1262         case 0x4404:
1263         case 0x4408:
1264         case 0x440C:
1265         case 0x4410:
1266         case 0x4414:
1267         case 0x4418:
1268         case 0x441C:
1269         case 0x4420:
1270         case 0x4424:
1271         case 0x4428:
1272         case 0x442C:
1273         case 0x4430:
1274         case 0x4434:
1275         case 0x4438:
1276         case 0x443C:
1277                 /* TX_FILTER0_[0-15] */
1278                 i = (reg - 0x4400) >> 2;
1279                 tmp = ib_chunk->kdata[idx] & 0x7;;
1280                 if (tmp == 2 || tmp == 4 || tmp == 6) {
1281                         track->textures[i].roundup_w = false;
1282                 }
1283                 tmp = (ib_chunk->kdata[idx] >> 3) & 0x7;;
1284                 if (tmp == 2 || tmp == 4 || tmp == 6) {
1285                         track->textures[i].roundup_h = false;
1286                 }
1287                 break;
1288         case 0x4500:
1289         case 0x4504:
1290         case 0x4508:
1291         case 0x450C:
1292         case 0x4510:
1293         case 0x4514:
1294         case 0x4518:
1295         case 0x451C:
1296         case 0x4520:
1297         case 0x4524:
1298         case 0x4528:
1299         case 0x452C:
1300         case 0x4530:
1301         case 0x4534:
1302         case 0x4538:
1303         case 0x453C:
1304                 /* TX_FORMAT2_[0-15] */
1305                 i = (reg - 0x4500) >> 2;
1306                 tmp = ib_chunk->kdata[idx] & 0x3FFF;
1307                 track->textures[i].pitch = tmp + 1;
1308                 if (p->rdev->family >= CHIP_RV515) {
1309                         tmp = ((ib_chunk->kdata[idx] >> 15) & 1) << 11;
1310                         track->textures[i].width_11 = tmp;
1311                         tmp = ((ib_chunk->kdata[idx] >> 16) & 1) << 11;
1312                         track->textures[i].height_11 = tmp;
1313                 }
1314                 break;
1315         case 0x4480:
1316         case 0x4484:
1317         case 0x4488:
1318         case 0x448C:
1319         case 0x4490:
1320         case 0x4494:
1321         case 0x4498:
1322         case 0x449C:
1323         case 0x44A0:
1324         case 0x44A4:
1325         case 0x44A8:
1326         case 0x44AC:
1327         case 0x44B0:
1328         case 0x44B4:
1329         case 0x44B8:
1330         case 0x44BC:
1331                 /* TX_FORMAT0_[0-15] */
1332                 i = (reg - 0x4480) >> 2;
1333                 tmp = ib_chunk->kdata[idx] & 0x7FF;
1334                 track->textures[i].width = tmp + 1;
1335                 tmp = (ib_chunk->kdata[idx] >> 11) & 0x7FF;
1336                 track->textures[i].height = tmp + 1;
1337                 tmp = (ib_chunk->kdata[idx] >> 26) & 0xF;
1338                 track->textures[i].num_levels = tmp;
1339                 tmp = ib_chunk->kdata[idx] & (1 << 31);
1340                 track->textures[i].use_pitch = !!tmp;
1341                 tmp = (ib_chunk->kdata[idx] >> 22) & 0xF;
1342                 track->textures[i].txdepth = tmp;
1343                 break;
1344         case R300_ZB_ZPASS_ADDR:
1345                 r = r100_cs_packet_next_reloc(p, &reloc);
1346                 if (r) {
1347                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1348                                         idx, reg);
1349                         r100_cs_dump_packet(p, pkt);
1350                         return r;
1351                 }
1352                 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1353                 break;
1354         case 0x4be8:
1355                 /* valid register only on RV530 */
1356                 if (p->rdev->family == CHIP_RV530)
1357                         break;
1358                 /* fallthrough do not move */
1359         default:
1360                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1361                        reg, idx);
1362                 return -EINVAL;
1363         }
1364         return 0;
1365 }
1366
1367 static int r300_packet3_check(struct radeon_cs_parser *p,
1368                               struct radeon_cs_packet *pkt)
1369 {
1370         struct radeon_cs_chunk *ib_chunk;
1371         struct radeon_cs_reloc *reloc;
1372         struct r300_cs_track *track;
1373         volatile uint32_t *ib;
1374         unsigned idx;
1375         unsigned i, c;
1376         int r;
1377
1378         ib = p->ib->ptr;
1379         ib_chunk = &p->chunks[p->chunk_ib_idx];
1380         idx = pkt->idx + 1;
1381         track = (struct r300_cs_track*)p->track;
1382         switch(pkt->opcode) {
1383         case PACKET3_3D_LOAD_VBPNTR:
1384                 c = ib_chunk->kdata[idx++] & 0x1F;
1385                 track->num_arrays = c;
1386                 for (i = 0; i < (c - 1); i+=2, idx+=3) {
1387                         r = r100_cs_packet_next_reloc(p, &reloc);
1388                         if (r) {
1389                                 DRM_ERROR("No reloc for packet3 %d\n",
1390                                           pkt->opcode);
1391                                 r100_cs_dump_packet(p, pkt);
1392                                 return r;
1393                         }
1394                         ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
1395                         track->arrays[i + 0].robj = reloc->robj;
1396                         track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8;
1397                         track->arrays[i + 0].esize &= 0x7F;
1398                         r = r100_cs_packet_next_reloc(p, &reloc);
1399                         if (r) {
1400                                 DRM_ERROR("No reloc for packet3 %d\n",
1401                                           pkt->opcode);
1402                                 r100_cs_dump_packet(p, pkt);
1403                                 return r;
1404                         }
1405                         ib[idx+2] = ib_chunk->kdata[idx+2] + ((u32)reloc->lobj.gpu_offset);
1406                         track->arrays[i + 1].robj = reloc->robj;
1407                         track->arrays[i + 1].esize = ib_chunk->kdata[idx] >> 24;
1408                         track->arrays[i + 1].esize &= 0x7F;
1409                 }
1410                 if (c & 1) {
1411                         r = r100_cs_packet_next_reloc(p, &reloc);
1412                         if (r) {
1413                                 DRM_ERROR("No reloc for packet3 %d\n",
1414                                           pkt->opcode);
1415                                 r100_cs_dump_packet(p, pkt);
1416                                 return r;
1417                         }
1418                         ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
1419                         track->arrays[i + 0].robj = reloc->robj;
1420                         track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8;
1421                         track->arrays[i + 0].esize &= 0x7F;
1422                 }
1423                 break;
1424         case PACKET3_INDX_BUFFER:
1425                 r = r100_cs_packet_next_reloc(p, &reloc);
1426                 if (r) {
1427                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1428                         r100_cs_dump_packet(p, pkt);
1429                         return r;
1430                 }
1431                 ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
1432                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1433                 if (r) {
1434                         return r;
1435                 }
1436                 break;
1437         /* Draw packet */
1438         case PACKET3_3D_DRAW_IMMD:
1439                 /* Number of dwords is vtx_size * (num_vertices - 1)
1440                  * PRIM_WALK must be equal to 3 vertex data in embedded
1441                  * in cmd stream */
1442                 if (((ib_chunk->kdata[idx+1] >> 4) & 0x3) != 3) {
1443                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1444                         return -EINVAL;
1445                 }
1446                 track->vap_vf_cntl = ib_chunk->kdata[idx+1];
1447                 track->immd_dwords = pkt->count - 1;
1448                 r = r300_cs_track_check(p->rdev, track);
1449                 if (r) {
1450                         return r;
1451                 }
1452                 break;
1453         case PACKET3_3D_DRAW_IMMD_2:
1454                 /* Number of dwords is vtx_size * (num_vertices - 1)
1455                  * PRIM_WALK must be equal to 3 vertex data in embedded
1456                  * in cmd stream */
1457                 if (((ib_chunk->kdata[idx] >> 4) & 0x3) != 3) {
1458                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1459                         return -EINVAL;
1460                 }
1461                 track->vap_vf_cntl = ib_chunk->kdata[idx];
1462                 track->immd_dwords = pkt->count;
1463                 r = r300_cs_track_check(p->rdev, track);
1464                 if (r) {
1465                         return r;
1466                 }
1467                 break;
1468         case PACKET3_3D_DRAW_VBUF:
1469                 track->vap_vf_cntl = ib_chunk->kdata[idx + 1];
1470                 r = r300_cs_track_check(p->rdev, track);
1471                 if (r) {
1472                         return r;
1473                 }
1474                 break;
1475         case PACKET3_3D_DRAW_VBUF_2:
1476                 track->vap_vf_cntl = ib_chunk->kdata[idx];
1477                 r = r300_cs_track_check(p->rdev, track);
1478                 if (r) {
1479                         return r;
1480                 }
1481                 break;
1482         case PACKET3_3D_DRAW_INDX:
1483                 track->vap_vf_cntl = ib_chunk->kdata[idx + 1];
1484                 r = r300_cs_track_check(p->rdev, track);
1485                 if (r) {
1486                         return r;
1487                 }
1488                 break;
1489         case PACKET3_3D_DRAW_INDX_2:
1490                 track->vap_vf_cntl = ib_chunk->kdata[idx];
1491                 r = r300_cs_track_check(p->rdev, track);
1492                 if (r) {
1493                         return r;
1494                 }
1495                 break;
1496         case PACKET3_NOP:
1497                 break;
1498         default:
1499                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1500                 return -EINVAL;
1501         }
1502         return 0;
1503 }
1504
1505 int r300_cs_parse(struct radeon_cs_parser *p)
1506 {
1507         struct radeon_cs_packet pkt;
1508         struct r300_cs_track track;
1509         int r;
1510
1511         r300_cs_track_clear(&track);
1512         p->track = &track;
1513         do {
1514                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1515                 if (r) {
1516                         return r;
1517                 }
1518                 p->idx += pkt.count + 2;
1519                 switch (pkt.type) {
1520                 case PACKET_TYPE0:
1521                         r = r100_cs_parse_packet0(p, &pkt,
1522                                                   p->rdev->config.r300.reg_safe_bm,
1523                                                   p->rdev->config.r300.reg_safe_bm_size,
1524                                                   &r300_packet0_check);
1525                         break;
1526                 case PACKET_TYPE2:
1527                         break;
1528                 case PACKET_TYPE3:
1529                         r = r300_packet3_check(p, &pkt);
1530                         break;
1531                 default:
1532                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1533                         return -EINVAL;
1534                 }
1535                 if (r) {
1536                         return r;
1537                 }
1538         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1539         return 0;
1540 }
1541
1542 int r300_init(struct radeon_device *rdev)
1543 {
1544         rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
1545         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1546         return 0;
1547 }