drm/radeon/kms: Convert R300 to new init path
[linux-2.6.git] / drivers / gpu / drm / radeon / r300.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/seq_file.h>
29 #include "drmP.h"
30 #include "drm.h"
31 #include "radeon_reg.h"
32 #include "radeon.h"
33 #include "radeon_drm.h"
34 #include "r100_track.h"
35 #include "r300d.h"
36 #include "rv350d.h"
37 #include "r300_reg_safe.h"
38
39 /* This files gather functions specifics to: r300,r350,rv350,rv370,rv380 */
40
41 /*
42  * rv370,rv380 PCIE GART
43  */
44 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
45
46 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
47 {
48         uint32_t tmp;
49         int i;
50
51         /* Workaround HW bug do flush 2 times */
52         for (i = 0; i < 2; i++) {
53                 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
54                 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
55                 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
56                 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
57         }
58         mb();
59 }
60
61 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
62 {
63         void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
64
65         if (i < 0 || i > rdev->gart.num_gpu_pages) {
66                 return -EINVAL;
67         }
68         addr = (lower_32_bits(addr) >> 8) |
69                ((upper_32_bits(addr) & 0xff) << 24) |
70                0xc;
71         /* on x86 we want this to be CPU endian, on powerpc
72          * on powerpc without HW swappers, it'll get swapped on way
73          * into VRAM - so no need for cpu_to_le32 on VRAM tables */
74         writel(addr, ((void __iomem *)ptr) + (i * 4));
75         return 0;
76 }
77
78 int rv370_pcie_gart_init(struct radeon_device *rdev)
79 {
80         int r;
81
82         if (rdev->gart.table.vram.robj) {
83                 WARN(1, "RV370 PCIE GART already initialized.\n");
84                 return 0;
85         }
86         /* Initialize common gart structure */
87         r = radeon_gart_init(rdev);
88         if (r)
89                 return r;
90         r = rv370_debugfs_pcie_gart_info_init(rdev);
91         if (r)
92                 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
93         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
94         rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
95         rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
96         return radeon_gart_table_vram_alloc(rdev);
97 }
98
99 int rv370_pcie_gart_enable(struct radeon_device *rdev)
100 {
101         uint32_t table_addr;
102         uint32_t tmp;
103         int r;
104
105         if (rdev->gart.table.vram.robj == NULL) {
106                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
107                 return -EINVAL;
108         }
109         r = radeon_gart_table_vram_pin(rdev);
110         if (r)
111                 return r;
112         /* discard memory request outside of configured range */
113         tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
114         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
115         WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_location);
116         tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 4096;
117         WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
118         WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
119         WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
120         table_addr = rdev->gart.table_addr;
121         WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
122         /* FIXME: setup default page */
123         WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_location);
124         WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
125         /* Clear error */
126         WREG32_PCIE(0x18, 0);
127         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
128         tmp |= RADEON_PCIE_TX_GART_EN;
129         tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
130         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
131         rv370_pcie_gart_tlb_flush(rdev);
132         DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
133                  (unsigned)(rdev->mc.gtt_size >> 20), table_addr);
134         rdev->gart.ready = true;
135         return 0;
136 }
137
138 void rv370_pcie_gart_disable(struct radeon_device *rdev)
139 {
140         uint32_t tmp;
141
142         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
143         tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
144         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
145         if (rdev->gart.table.vram.robj) {
146                 radeon_object_kunmap(rdev->gart.table.vram.robj);
147                 radeon_object_unpin(rdev->gart.table.vram.robj);
148         }
149 }
150
151 void rv370_pcie_gart_fini(struct radeon_device *rdev)
152 {
153         rv370_pcie_gart_disable(rdev);
154         radeon_gart_table_vram_free(rdev);
155         radeon_gart_fini(rdev);
156 }
157
158 void r300_fence_ring_emit(struct radeon_device *rdev,
159                           struct radeon_fence *fence)
160 {
161         /* Who ever call radeon_fence_emit should call ring_lock and ask
162          * for enough space (today caller are ib schedule and buffer move) */
163         /* Write SC register so SC & US assert idle */
164         radeon_ring_write(rdev, PACKET0(0x43E0, 0));
165         radeon_ring_write(rdev, 0);
166         radeon_ring_write(rdev, PACKET0(0x43E4, 0));
167         radeon_ring_write(rdev, 0);
168         /* Flush 3D cache */
169         radeon_ring_write(rdev, PACKET0(0x4E4C, 0));
170         radeon_ring_write(rdev, (2 << 0));
171         radeon_ring_write(rdev, PACKET0(0x4F18, 0));
172         radeon_ring_write(rdev, (1 << 0));
173         /* Wait until IDLE & CLEAN */
174         radeon_ring_write(rdev, PACKET0(0x1720, 0));
175         radeon_ring_write(rdev, (1 << 17) | (1 << 16)  | (1 << 9));
176         /* Emit fence sequence & fire IRQ */
177         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
178         radeon_ring_write(rdev, fence->seq);
179         radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
180         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
181 }
182
183 int r300_copy_dma(struct radeon_device *rdev,
184                   uint64_t src_offset,
185                   uint64_t dst_offset,
186                   unsigned num_pages,
187                   struct radeon_fence *fence)
188 {
189         uint32_t size;
190         uint32_t cur_size;
191         int i, num_loops;
192         int r = 0;
193
194         /* radeon pitch is /64 */
195         size = num_pages << PAGE_SHIFT;
196         num_loops = DIV_ROUND_UP(size, 0x1FFFFF);
197         r = radeon_ring_lock(rdev, num_loops * 4 + 64);
198         if (r) {
199                 DRM_ERROR("radeon: moving bo (%d).\n", r);
200                 return r;
201         }
202         /* Must wait for 2D idle & clean before DMA or hangs might happen */
203         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0 ));
204         radeon_ring_write(rdev, (1 << 16));
205         for (i = 0; i < num_loops; i++) {
206                 cur_size = size;
207                 if (cur_size > 0x1FFFFF) {
208                         cur_size = 0x1FFFFF;
209                 }
210                 size -= cur_size;
211                 radeon_ring_write(rdev, PACKET0(0x720, 2));
212                 radeon_ring_write(rdev, src_offset);
213                 radeon_ring_write(rdev, dst_offset);
214                 radeon_ring_write(rdev, cur_size | (1 << 31) | (1 << 30));
215                 src_offset += cur_size;
216                 dst_offset += cur_size;
217         }
218         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
219         radeon_ring_write(rdev, RADEON_WAIT_DMA_GUI_IDLE);
220         if (fence) {
221                 r = radeon_fence_emit(rdev, fence);
222         }
223         radeon_ring_unlock_commit(rdev);
224         return r;
225 }
226
227 void r300_ring_start(struct radeon_device *rdev)
228 {
229         unsigned gb_tile_config;
230         int r;
231
232         /* Sub pixel 1/12 so we can have 4K rendering according to doc */
233         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
234         switch(rdev->num_gb_pipes) {
235         case 2:
236                 gb_tile_config |= R300_PIPE_COUNT_R300;
237                 break;
238         case 3:
239                 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
240                 break;
241         case 4:
242                 gb_tile_config |= R300_PIPE_COUNT_R420;
243                 break;
244         case 1:
245         default:
246                 gb_tile_config |= R300_PIPE_COUNT_RV350;
247                 break;
248         }
249
250         r = radeon_ring_lock(rdev, 64);
251         if (r) {
252                 return;
253         }
254         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
255         radeon_ring_write(rdev,
256                           RADEON_ISYNC_ANY2D_IDLE3D |
257                           RADEON_ISYNC_ANY3D_IDLE2D |
258                           RADEON_ISYNC_WAIT_IDLEGUI |
259                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
260         radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
261         radeon_ring_write(rdev, gb_tile_config);
262         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
263         radeon_ring_write(rdev,
264                           RADEON_WAIT_2D_IDLECLEAN |
265                           RADEON_WAIT_3D_IDLECLEAN);
266         radeon_ring_write(rdev, PACKET0(0x170C, 0));
267         radeon_ring_write(rdev, 1 << 31);
268         radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
269         radeon_ring_write(rdev, 0);
270         radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
271         radeon_ring_write(rdev, 0);
272         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
273         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
274         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
275         radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
276         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
277         radeon_ring_write(rdev,
278                           RADEON_WAIT_2D_IDLECLEAN |
279                           RADEON_WAIT_3D_IDLECLEAN);
280         radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
281         radeon_ring_write(rdev, 0);
282         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
283         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
284         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
285         radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
286         radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
287         radeon_ring_write(rdev,
288                           ((6 << R300_MS_X0_SHIFT) |
289                            (6 << R300_MS_Y0_SHIFT) |
290                            (6 << R300_MS_X1_SHIFT) |
291                            (6 << R300_MS_Y1_SHIFT) |
292                            (6 << R300_MS_X2_SHIFT) |
293                            (6 << R300_MS_Y2_SHIFT) |
294                            (6 << R300_MSBD0_Y_SHIFT) |
295                            (6 << R300_MSBD0_X_SHIFT)));
296         radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
297         radeon_ring_write(rdev,
298                           ((6 << R300_MS_X3_SHIFT) |
299                            (6 << R300_MS_Y3_SHIFT) |
300                            (6 << R300_MS_X4_SHIFT) |
301                            (6 << R300_MS_Y4_SHIFT) |
302                            (6 << R300_MS_X5_SHIFT) |
303                            (6 << R300_MS_Y5_SHIFT) |
304                            (6 << R300_MSBD1_SHIFT)));
305         radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
306         radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
307         radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
308         radeon_ring_write(rdev,
309                           R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
310         radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
311         radeon_ring_write(rdev,
312                           R300_GEOMETRY_ROUND_NEAREST |
313                           R300_COLOR_ROUND_NEAREST);
314         radeon_ring_unlock_commit(rdev);
315 }
316
317 void r300_errata(struct radeon_device *rdev)
318 {
319         rdev->pll_errata = 0;
320
321         if (rdev->family == CHIP_R300 &&
322             (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
323                 rdev->pll_errata |= CHIP_ERRATA_R300_CG;
324         }
325 }
326
327 int r300_mc_wait_for_idle(struct radeon_device *rdev)
328 {
329         unsigned i;
330         uint32_t tmp;
331
332         for (i = 0; i < rdev->usec_timeout; i++) {
333                 /* read MC_STATUS */
334                 tmp = RREG32(0x0150);
335                 if (tmp & (1 << 4)) {
336                         return 0;
337                 }
338                 DRM_UDELAY(1);
339         }
340         return -1;
341 }
342
343 void r300_gpu_init(struct radeon_device *rdev)
344 {
345         uint32_t gb_tile_config, tmp;
346
347         r100_hdp_reset(rdev);
348         /* FIXME: rv380 one pipes ? */
349         if ((rdev->family == CHIP_R300) || (rdev->family == CHIP_R350)) {
350                 /* r300,r350 */
351                 rdev->num_gb_pipes = 2;
352         } else {
353                 /* rv350,rv370,rv380 */
354                 rdev->num_gb_pipes = 1;
355         }
356         rdev->num_z_pipes = 1;
357         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
358         switch (rdev->num_gb_pipes) {
359         case 2:
360                 gb_tile_config |= R300_PIPE_COUNT_R300;
361                 break;
362         case 3:
363                 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
364                 break;
365         case 4:
366                 gb_tile_config |= R300_PIPE_COUNT_R420;
367                 break;
368         default:
369         case 1:
370                 gb_tile_config |= R300_PIPE_COUNT_RV350;
371                 break;
372         }
373         WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
374
375         if (r100_gui_wait_for_idle(rdev)) {
376                 printk(KERN_WARNING "Failed to wait GUI idle while "
377                        "programming pipes. Bad things might happen.\n");
378         }
379
380         tmp = RREG32(0x170C);
381         WREG32(0x170C, tmp | (1 << 31));
382
383         WREG32(R300_RB2D_DSTCACHE_MODE,
384                R300_DC_AUTOFLUSH_ENABLE |
385                R300_DC_DC_DISABLE_IGNORE_PE);
386
387         if (r100_gui_wait_for_idle(rdev)) {
388                 printk(KERN_WARNING "Failed to wait GUI idle while "
389                        "programming pipes. Bad things might happen.\n");
390         }
391         if (r300_mc_wait_for_idle(rdev)) {
392                 printk(KERN_WARNING "Failed to wait MC idle while "
393                        "programming pipes. Bad things might happen.\n");
394         }
395         DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
396                  rdev->num_gb_pipes, rdev->num_z_pipes);
397 }
398
399 int r300_ga_reset(struct radeon_device *rdev)
400 {
401         uint32_t tmp;
402         bool reinit_cp;
403         int i;
404
405         reinit_cp = rdev->cp.ready;
406         rdev->cp.ready = false;
407         for (i = 0; i < rdev->usec_timeout; i++) {
408                 WREG32(RADEON_CP_CSQ_MODE, 0);
409                 WREG32(RADEON_CP_CSQ_CNTL, 0);
410                 WREG32(RADEON_RBBM_SOFT_RESET, 0x32005);
411                 (void)RREG32(RADEON_RBBM_SOFT_RESET);
412                 udelay(200);
413                 WREG32(RADEON_RBBM_SOFT_RESET, 0);
414                 /* Wait to prevent race in RBBM_STATUS */
415                 mdelay(1);
416                 tmp = RREG32(RADEON_RBBM_STATUS);
417                 if (tmp & ((1 << 20) | (1 << 26))) {
418                         DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp);
419                         /* GA still busy soft reset it */
420                         WREG32(0x429C, 0x200);
421                         WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0);
422                         WREG32(0x43E0, 0);
423                         WREG32(0x43E4, 0);
424                         WREG32(0x24AC, 0);
425                 }
426                 /* Wait to prevent race in RBBM_STATUS */
427                 mdelay(1);
428                 tmp = RREG32(RADEON_RBBM_STATUS);
429                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
430                         break;
431                 }
432         }
433         for (i = 0; i < rdev->usec_timeout; i++) {
434                 tmp = RREG32(RADEON_RBBM_STATUS);
435                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
436                         DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
437                                  tmp);
438                         if (reinit_cp) {
439                                 return r100_cp_init(rdev, rdev->cp.ring_size);
440                         }
441                         return 0;
442                 }
443                 DRM_UDELAY(1);
444         }
445         tmp = RREG32(RADEON_RBBM_STATUS);
446         DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
447         return -1;
448 }
449
450 int r300_gpu_reset(struct radeon_device *rdev)
451 {
452         uint32_t status;
453
454         /* reset order likely matter */
455         status = RREG32(RADEON_RBBM_STATUS);
456         /* reset HDP */
457         r100_hdp_reset(rdev);
458         /* reset rb2d */
459         if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
460                 r100_rb2d_reset(rdev);
461         }
462         /* reset GA */
463         if (status & ((1 << 20) | (1 << 26))) {
464                 r300_ga_reset(rdev);
465         }
466         /* reset CP */
467         status = RREG32(RADEON_RBBM_STATUS);
468         if (status & (1 << 16)) {
469                 r100_cp_reset(rdev);
470         }
471         /* Check if GPU is idle */
472         status = RREG32(RADEON_RBBM_STATUS);
473         if (status & (1 << 31)) {
474                 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
475                 return -1;
476         }
477         DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
478         return 0;
479 }
480
481
482 /*
483  * r300,r350,rv350,rv380 VRAM info
484  */
485 void r300_vram_info(struct radeon_device *rdev)
486 {
487         uint32_t tmp;
488
489         /* DDR for all card after R300 & IGP */
490         rdev->mc.vram_is_ddr = true;
491         tmp = RREG32(RADEON_MEM_CNTL);
492         if (tmp & R300_MEM_NUM_CHANNELS_MASK) {
493                 rdev->mc.vram_width = 128;
494         } else {
495                 rdev->mc.vram_width = 64;
496         }
497
498         r100_vram_init_sizes(rdev);
499 }
500
501 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
502 {
503         uint32_t link_width_cntl, mask;
504
505         if (rdev->flags & RADEON_IS_IGP)
506                 return;
507
508         if (!(rdev->flags & RADEON_IS_PCIE))
509                 return;
510
511         /* FIXME wait for idle */
512
513         switch (lanes) {
514         case 0:
515                 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
516                 break;
517         case 1:
518                 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
519                 break;
520         case 2:
521                 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
522                 break;
523         case 4:
524                 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
525                 break;
526         case 8:
527                 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
528                 break;
529         case 12:
530                 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
531                 break;
532         case 16:
533         default:
534                 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
535                 break;
536         }
537
538         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
539
540         if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
541             (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
542                 return;
543
544         link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
545                              RADEON_PCIE_LC_RECONFIG_NOW |
546                              RADEON_PCIE_LC_RECONFIG_LATER |
547                              RADEON_PCIE_LC_SHORT_RECONFIG_EN);
548         link_width_cntl |= mask;
549         WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
550         WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
551                                                      RADEON_PCIE_LC_RECONFIG_NOW));
552
553         /* wait for lane set to complete */
554         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
555         while (link_width_cntl == 0xffffffff)
556                 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
557
558 }
559
560 #if defined(CONFIG_DEBUG_FS)
561 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data)
562 {
563         struct drm_info_node *node = (struct drm_info_node *) m->private;
564         struct drm_device *dev = node->minor->dev;
565         struct radeon_device *rdev = dev->dev_private;
566         uint32_t tmp;
567
568         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
569         seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
570         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
571         seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
572         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
573         seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
574         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
575         seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
576         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
577         seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
578         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
579         seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
580         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
581         seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
582         return 0;
583 }
584
585 static struct drm_info_list rv370_pcie_gart_info_list[] = {
586         {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
587 };
588 #endif
589
590 static int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
591 {
592 #if defined(CONFIG_DEBUG_FS)
593         return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
594 #else
595         return 0;
596 #endif
597 }
598
599 static int r300_packet0_check(struct radeon_cs_parser *p,
600                 struct radeon_cs_packet *pkt,
601                 unsigned idx, unsigned reg)
602 {
603         struct radeon_cs_reloc *reloc;
604         struct r100_cs_track *track;
605         volatile uint32_t *ib;
606         uint32_t tmp, tile_flags = 0;
607         unsigned i;
608         int r;
609         u32 idx_value;
610
611         ib = p->ib->ptr;
612         track = (struct r100_cs_track *)p->track;
613         idx_value = radeon_get_ib_value(p, idx);
614
615         switch(reg) {
616         case AVIVO_D1MODE_VLINE_START_END:
617         case RADEON_CRTC_GUI_TRIG_VLINE:
618                 r = r100_cs_packet_parse_vline(p);
619                 if (r) {
620                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
621                                         idx, reg);
622                         r100_cs_dump_packet(p, pkt);
623                         return r;
624                 }
625                 break;
626         case RADEON_DST_PITCH_OFFSET:
627         case RADEON_SRC_PITCH_OFFSET:
628                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
629                 if (r)
630                         return r;
631                 break;
632         case R300_RB3D_COLOROFFSET0:
633         case R300_RB3D_COLOROFFSET1:
634         case R300_RB3D_COLOROFFSET2:
635         case R300_RB3D_COLOROFFSET3:
636                 i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
637                 r = r100_cs_packet_next_reloc(p, &reloc);
638                 if (r) {
639                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
640                                         idx, reg);
641                         r100_cs_dump_packet(p, pkt);
642                         return r;
643                 }
644                 track->cb[i].robj = reloc->robj;
645                 track->cb[i].offset = idx_value;
646                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
647                 break;
648         case R300_ZB_DEPTHOFFSET:
649                 r = r100_cs_packet_next_reloc(p, &reloc);
650                 if (r) {
651                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
652                                         idx, reg);
653                         r100_cs_dump_packet(p, pkt);
654                         return r;
655                 }
656                 track->zb.robj = reloc->robj;
657                 track->zb.offset = idx_value;
658                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
659                 break;
660         case R300_TX_OFFSET_0:
661         case R300_TX_OFFSET_0+4:
662         case R300_TX_OFFSET_0+8:
663         case R300_TX_OFFSET_0+12:
664         case R300_TX_OFFSET_0+16:
665         case R300_TX_OFFSET_0+20:
666         case R300_TX_OFFSET_0+24:
667         case R300_TX_OFFSET_0+28:
668         case R300_TX_OFFSET_0+32:
669         case R300_TX_OFFSET_0+36:
670         case R300_TX_OFFSET_0+40:
671         case R300_TX_OFFSET_0+44:
672         case R300_TX_OFFSET_0+48:
673         case R300_TX_OFFSET_0+52:
674         case R300_TX_OFFSET_0+56:
675         case R300_TX_OFFSET_0+60:
676                 i = (reg - R300_TX_OFFSET_0) >> 2;
677                 r = r100_cs_packet_next_reloc(p, &reloc);
678                 if (r) {
679                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
680                                         idx, reg);
681                         r100_cs_dump_packet(p, pkt);
682                         return r;
683                 }
684                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
685                 track->textures[i].robj = reloc->robj;
686                 break;
687         /* Tracked registers */
688         case 0x2084:
689                 /* VAP_VF_CNTL */
690                 track->vap_vf_cntl = idx_value;
691                 break;
692         case 0x20B4:
693                 /* VAP_VTX_SIZE */
694                 track->vtx_size = idx_value & 0x7F;
695                 break;
696         case 0x2134:
697                 /* VAP_VF_MAX_VTX_INDX */
698                 track->max_indx = idx_value & 0x00FFFFFFUL;
699                 break;
700         case 0x43E4:
701                 /* SC_SCISSOR1 */
702                 track->maxy = ((idx_value >> 13) & 0x1FFF) + 1;
703                 if (p->rdev->family < CHIP_RV515) {
704                         track->maxy -= 1440;
705                 }
706                 break;
707         case 0x4E00:
708                 /* RB3D_CCTL */
709                 track->num_cb = ((idx_value >> 5) & 0x3) + 1;
710                 break;
711         case 0x4E38:
712         case 0x4E3C:
713         case 0x4E40:
714         case 0x4E44:
715                 /* RB3D_COLORPITCH0 */
716                 /* RB3D_COLORPITCH1 */
717                 /* RB3D_COLORPITCH2 */
718                 /* RB3D_COLORPITCH3 */
719                 r = r100_cs_packet_next_reloc(p, &reloc);
720                 if (r) {
721                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
722                                   idx, reg);
723                         r100_cs_dump_packet(p, pkt);
724                         return r;
725                 }
726
727                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
728                         tile_flags |= R300_COLOR_TILE_ENABLE;
729                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
730                         tile_flags |= R300_COLOR_MICROTILE_ENABLE;
731
732                 tmp = idx_value & ~(0x7 << 16);
733                 tmp |= tile_flags;
734                 ib[idx] = tmp;
735
736                 i = (reg - 0x4E38) >> 2;
737                 track->cb[i].pitch = idx_value & 0x3FFE;
738                 switch (((idx_value >> 21) & 0xF)) {
739                 case 9:
740                 case 11:
741                 case 12:
742                         track->cb[i].cpp = 1;
743                         break;
744                 case 3:
745                 case 4:
746                 case 13:
747                 case 15:
748                         track->cb[i].cpp = 2;
749                         break;
750                 case 6:
751                         track->cb[i].cpp = 4;
752                         break;
753                 case 10:
754                         track->cb[i].cpp = 8;
755                         break;
756                 case 7:
757                         track->cb[i].cpp = 16;
758                         break;
759                 default:
760                         DRM_ERROR("Invalid color buffer format (%d) !\n",
761                                   ((idx_value >> 21) & 0xF));
762                         return -EINVAL;
763                 }
764                 break;
765         case 0x4F00:
766                 /* ZB_CNTL */
767                 if (idx_value & 2) {
768                         track->z_enabled = true;
769                 } else {
770                         track->z_enabled = false;
771                 }
772                 break;
773         case 0x4F10:
774                 /* ZB_FORMAT */
775                 switch ((idx_value & 0xF)) {
776                 case 0:
777                 case 1:
778                         track->zb.cpp = 2;
779                         break;
780                 case 2:
781                         track->zb.cpp = 4;
782                         break;
783                 default:
784                         DRM_ERROR("Invalid z buffer format (%d) !\n",
785                                   (idx_value & 0xF));
786                         return -EINVAL;
787                 }
788                 break;
789         case 0x4F24:
790                 /* ZB_DEPTHPITCH */
791                 r = r100_cs_packet_next_reloc(p, &reloc);
792                 if (r) {
793                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
794                                   idx, reg);
795                         r100_cs_dump_packet(p, pkt);
796                         return r;
797                 }
798
799                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
800                         tile_flags |= R300_DEPTHMACROTILE_ENABLE;
801                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
802                         tile_flags |= R300_DEPTHMICROTILE_TILED;;
803
804                 tmp = idx_value & ~(0x7 << 16);
805                 tmp |= tile_flags;
806                 ib[idx] = tmp;
807
808                 track->zb.pitch = idx_value & 0x3FFC;
809                 break;
810         case 0x4104:
811                 for (i = 0; i < 16; i++) {
812                         bool enabled;
813
814                         enabled = !!(idx_value & (1 << i));
815                         track->textures[i].enabled = enabled;
816                 }
817                 break;
818         case 0x44C0:
819         case 0x44C4:
820         case 0x44C8:
821         case 0x44CC:
822         case 0x44D0:
823         case 0x44D4:
824         case 0x44D8:
825         case 0x44DC:
826         case 0x44E0:
827         case 0x44E4:
828         case 0x44E8:
829         case 0x44EC:
830         case 0x44F0:
831         case 0x44F4:
832         case 0x44F8:
833         case 0x44FC:
834                 /* TX_FORMAT1_[0-15] */
835                 i = (reg - 0x44C0) >> 2;
836                 tmp = (idx_value >> 25) & 0x3;
837                 track->textures[i].tex_coord_type = tmp;
838                 switch ((idx_value & 0x1F)) {
839                 case R300_TX_FORMAT_X8:
840                 case R300_TX_FORMAT_Y4X4:
841                 case R300_TX_FORMAT_Z3Y3X2:
842                         track->textures[i].cpp = 1;
843                         break;
844                 case R300_TX_FORMAT_X16:
845                 case R300_TX_FORMAT_Y8X8:
846                 case R300_TX_FORMAT_Z5Y6X5:
847                 case R300_TX_FORMAT_Z6Y5X5:
848                 case R300_TX_FORMAT_W4Z4Y4X4:
849                 case R300_TX_FORMAT_W1Z5Y5X5:
850                 case R300_TX_FORMAT_DXT1:
851                 case R300_TX_FORMAT_D3DMFT_CxV8U8:
852                 case R300_TX_FORMAT_B8G8_B8G8:
853                 case R300_TX_FORMAT_G8R8_G8B8:
854                         track->textures[i].cpp = 2;
855                         break;
856                 case R300_TX_FORMAT_Y16X16:
857                 case R300_TX_FORMAT_Z11Y11X10:
858                 case R300_TX_FORMAT_Z10Y11X11:
859                 case R300_TX_FORMAT_W8Z8Y8X8:
860                 case R300_TX_FORMAT_W2Z10Y10X10:
861                 case 0x17:
862                 case R300_TX_FORMAT_FL_I32:
863                 case 0x1e:
864                 case R300_TX_FORMAT_DXT3:
865                 case R300_TX_FORMAT_DXT5:
866                         track->textures[i].cpp = 4;
867                         break;
868                 case R300_TX_FORMAT_W16Z16Y16X16:
869                 case R300_TX_FORMAT_FL_R16G16B16A16:
870                 case R300_TX_FORMAT_FL_I32A32:
871                         track->textures[i].cpp = 8;
872                         break;
873                 case R300_TX_FORMAT_FL_R32G32B32A32:
874                         track->textures[i].cpp = 16;
875                         break;
876                 default:
877                         DRM_ERROR("Invalid texture format %u\n",
878                                   (idx_value & 0x1F));
879                         return -EINVAL;
880                         break;
881                 }
882                 break;
883         case 0x4400:
884         case 0x4404:
885         case 0x4408:
886         case 0x440C:
887         case 0x4410:
888         case 0x4414:
889         case 0x4418:
890         case 0x441C:
891         case 0x4420:
892         case 0x4424:
893         case 0x4428:
894         case 0x442C:
895         case 0x4430:
896         case 0x4434:
897         case 0x4438:
898         case 0x443C:
899                 /* TX_FILTER0_[0-15] */
900                 i = (reg - 0x4400) >> 2;
901                 tmp = idx_value & 0x7;
902                 if (tmp == 2 || tmp == 4 || tmp == 6) {
903                         track->textures[i].roundup_w = false;
904                 }
905                 tmp = (idx_value >> 3) & 0x7;
906                 if (tmp == 2 || tmp == 4 || tmp == 6) {
907                         track->textures[i].roundup_h = false;
908                 }
909                 break;
910         case 0x4500:
911         case 0x4504:
912         case 0x4508:
913         case 0x450C:
914         case 0x4510:
915         case 0x4514:
916         case 0x4518:
917         case 0x451C:
918         case 0x4520:
919         case 0x4524:
920         case 0x4528:
921         case 0x452C:
922         case 0x4530:
923         case 0x4534:
924         case 0x4538:
925         case 0x453C:
926                 /* TX_FORMAT2_[0-15] */
927                 i = (reg - 0x4500) >> 2;
928                 tmp = idx_value & 0x3FFF;
929                 track->textures[i].pitch = tmp + 1;
930                 if (p->rdev->family >= CHIP_RV515) {
931                         tmp = ((idx_value >> 15) & 1) << 11;
932                         track->textures[i].width_11 = tmp;
933                         tmp = ((idx_value >> 16) & 1) << 11;
934                         track->textures[i].height_11 = tmp;
935                 }
936                 break;
937         case 0x4480:
938         case 0x4484:
939         case 0x4488:
940         case 0x448C:
941         case 0x4490:
942         case 0x4494:
943         case 0x4498:
944         case 0x449C:
945         case 0x44A0:
946         case 0x44A4:
947         case 0x44A8:
948         case 0x44AC:
949         case 0x44B0:
950         case 0x44B4:
951         case 0x44B8:
952         case 0x44BC:
953                 /* TX_FORMAT0_[0-15] */
954                 i = (reg - 0x4480) >> 2;
955                 tmp = idx_value & 0x7FF;
956                 track->textures[i].width = tmp + 1;
957                 tmp = (idx_value >> 11) & 0x7FF;
958                 track->textures[i].height = tmp + 1;
959                 tmp = (idx_value >> 26) & 0xF;
960                 track->textures[i].num_levels = tmp;
961                 tmp = idx_value & (1 << 31);
962                 track->textures[i].use_pitch = !!tmp;
963                 tmp = (idx_value >> 22) & 0xF;
964                 track->textures[i].txdepth = tmp;
965                 break;
966         case R300_ZB_ZPASS_ADDR:
967                 r = r100_cs_packet_next_reloc(p, &reloc);
968                 if (r) {
969                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
970                                         idx, reg);
971                         r100_cs_dump_packet(p, pkt);
972                         return r;
973                 }
974                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
975                 break;
976         case 0x4be8:
977                 /* valid register only on RV530 */
978                 if (p->rdev->family == CHIP_RV530)
979                         break;
980                 /* fallthrough do not move */
981         default:
982                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
983                        reg, idx);
984                 return -EINVAL;
985         }
986         return 0;
987 }
988
989 static int r300_packet3_check(struct radeon_cs_parser *p,
990                               struct radeon_cs_packet *pkt)
991 {
992         struct radeon_cs_reloc *reloc;
993         struct r100_cs_track *track;
994         volatile uint32_t *ib;
995         unsigned idx;
996         int r;
997
998         ib = p->ib->ptr;
999         idx = pkt->idx + 1;
1000         track = (struct r100_cs_track *)p->track;
1001         switch(pkt->opcode) {
1002         case PACKET3_3D_LOAD_VBPNTR:
1003                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1004                 if (r)
1005                         return r;
1006                 break;
1007         case PACKET3_INDX_BUFFER:
1008                 r = r100_cs_packet_next_reloc(p, &reloc);
1009                 if (r) {
1010                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1011                         r100_cs_dump_packet(p, pkt);
1012                         return r;
1013                 }
1014                 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset);
1015                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1016                 if (r) {
1017                         return r;
1018                 }
1019                 break;
1020         /* Draw packet */
1021         case PACKET3_3D_DRAW_IMMD:
1022                 /* Number of dwords is vtx_size * (num_vertices - 1)
1023                  * PRIM_WALK must be equal to 3 vertex data in embedded
1024                  * in cmd stream */
1025                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1026                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1027                         return -EINVAL;
1028                 }
1029                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1030                 track->immd_dwords = pkt->count - 1;
1031                 r = r100_cs_track_check(p->rdev, track);
1032                 if (r) {
1033                         return r;
1034                 }
1035                 break;
1036         case PACKET3_3D_DRAW_IMMD_2:
1037                 /* Number of dwords is vtx_size * (num_vertices - 1)
1038                  * PRIM_WALK must be equal to 3 vertex data in embedded
1039                  * in cmd stream */
1040                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1041                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1042                         return -EINVAL;
1043                 }
1044                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1045                 track->immd_dwords = pkt->count;
1046                 r = r100_cs_track_check(p->rdev, track);
1047                 if (r) {
1048                         return r;
1049                 }
1050                 break;
1051         case PACKET3_3D_DRAW_VBUF:
1052                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1053                 r = r100_cs_track_check(p->rdev, track);
1054                 if (r) {
1055                         return r;
1056                 }
1057                 break;
1058         case PACKET3_3D_DRAW_VBUF_2:
1059                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1060                 r = r100_cs_track_check(p->rdev, track);
1061                 if (r) {
1062                         return r;
1063                 }
1064                 break;
1065         case PACKET3_3D_DRAW_INDX:
1066                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1067                 r = r100_cs_track_check(p->rdev, track);
1068                 if (r) {
1069                         return r;
1070                 }
1071                 break;
1072         case PACKET3_3D_DRAW_INDX_2:
1073                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1074                 r = r100_cs_track_check(p->rdev, track);
1075                 if (r) {
1076                         return r;
1077                 }
1078                 break;
1079         case PACKET3_NOP:
1080                 break;
1081         default:
1082                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1083                 return -EINVAL;
1084         }
1085         return 0;
1086 }
1087
1088 int r300_cs_parse(struct radeon_cs_parser *p)
1089 {
1090         struct radeon_cs_packet pkt;
1091         struct r100_cs_track *track;
1092         int r;
1093
1094         track = kzalloc(sizeof(*track), GFP_KERNEL);
1095         r100_cs_track_clear(p->rdev, track);
1096         p->track = track;
1097         do {
1098                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1099                 if (r) {
1100                         return r;
1101                 }
1102                 p->idx += pkt.count + 2;
1103                 switch (pkt.type) {
1104                 case PACKET_TYPE0:
1105                         r = r100_cs_parse_packet0(p, &pkt,
1106                                                   p->rdev->config.r300.reg_safe_bm,
1107                                                   p->rdev->config.r300.reg_safe_bm_size,
1108                                                   &r300_packet0_check);
1109                         break;
1110                 case PACKET_TYPE2:
1111                         break;
1112                 case PACKET_TYPE3:
1113                         r = r300_packet3_check(p, &pkt);
1114                         break;
1115                 default:
1116                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1117                         return -EINVAL;
1118                 }
1119                 if (r) {
1120                         return r;
1121                 }
1122         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1123         return 0;
1124 }
1125
1126 void r300_set_reg_safe(struct radeon_device *rdev)
1127 {
1128         rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
1129         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1130 }
1131
1132 void r300_mc_program(struct radeon_device *rdev)
1133 {
1134         struct r100_mc_save save;
1135         int r;
1136
1137         r = r100_debugfs_mc_info_init(rdev);
1138         if (r) {
1139                 dev_err(rdev->dev, "Failed to create r100_mc debugfs file.\n");
1140         }
1141
1142         /* Stops all mc clients */
1143         r100_mc_stop(rdev, &save);
1144         if (rdev->flags & RADEON_IS_AGP) {
1145                 WREG32(R_00014C_MC_AGP_LOCATION,
1146                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
1147                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
1148                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
1149                 WREG32(R_00015C_AGP_BASE_2,
1150                         upper_32_bits(rdev->mc.agp_base) & 0xff);
1151         } else {
1152                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
1153                 WREG32(R_000170_AGP_BASE, 0);
1154                 WREG32(R_00015C_AGP_BASE_2, 0);
1155         }
1156         /* Wait for mc idle */
1157         if (r300_mc_wait_for_idle(rdev))
1158                 DRM_INFO("Failed to wait MC idle before programming MC.\n");
1159         /* Program MC, should be a 32bits limited address space */
1160         WREG32(R_000148_MC_FB_LOCATION,
1161                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
1162                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
1163         r100_mc_resume(rdev, &save);
1164 }
1165
1166 void r300_clock_startup(struct radeon_device *rdev)
1167 {
1168         u32 tmp;
1169
1170         if (radeon_dynclks != -1 && radeon_dynclks)
1171                 radeon_legacy_set_clock_gating(rdev, 1);
1172         /* We need to force on some of the block */
1173         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
1174         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
1175         if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380))
1176                 tmp |= S_00000D_FORCE_VAP(1);
1177         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
1178 }
1179
1180 static int r300_startup(struct radeon_device *rdev)
1181 {
1182         int r;
1183
1184         r300_mc_program(rdev);
1185         /* Resume clock */
1186         r300_clock_startup(rdev);
1187         /* Initialize GPU configuration (# pipes, ...) */
1188         r300_gpu_init(rdev);
1189         /* Initialize GART (initialize after TTM so we can allocate
1190          * memory through TTM but finalize after TTM) */
1191         if (rdev->flags & RADEON_IS_PCIE) {
1192                 r = rv370_pcie_gart_enable(rdev);
1193                 if (r)
1194                         return r;
1195         }
1196         if (rdev->flags & RADEON_IS_PCI) {
1197                 r = r100_pci_gart_enable(rdev);
1198                 if (r)
1199                         return r;
1200         }
1201         /* Enable IRQ */
1202         rdev->irq.sw_int = true;
1203         r100_irq_set(rdev);
1204         /* 1M ring buffer */
1205         r = r100_cp_init(rdev, 1024 * 1024);
1206         if (r) {
1207                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
1208                 return r;
1209         }
1210         r = r100_wb_init(rdev);
1211         if (r)
1212                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
1213         r = r100_ib_init(rdev);
1214         if (r) {
1215                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
1216                 return r;
1217         }
1218         return 0;
1219 }
1220
1221 int r300_resume(struct radeon_device *rdev)
1222 {
1223         /* Make sur GART are not working */
1224         if (rdev->flags & RADEON_IS_PCIE)
1225                 rv370_pcie_gart_disable(rdev);
1226         if (rdev->flags & RADEON_IS_PCI)
1227                 r100_pci_gart_disable(rdev);
1228         /* Resume clock before doing reset */
1229         r300_clock_startup(rdev);
1230         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1231         if (radeon_gpu_reset(rdev)) {
1232                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1233                         RREG32(R_000E40_RBBM_STATUS),
1234                         RREG32(R_0007C0_CP_STAT));
1235         }
1236         /* post */
1237         radeon_combios_asic_init(rdev->ddev);
1238         /* Resume clock after posting */
1239         r300_clock_startup(rdev);
1240         return r300_startup(rdev);
1241 }
1242
1243 int r300_suspend(struct radeon_device *rdev)
1244 {
1245         r100_cp_disable(rdev);
1246         r100_wb_disable(rdev);
1247         r100_irq_disable(rdev);
1248         if (rdev->flags & RADEON_IS_PCIE)
1249                 rv370_pcie_gart_disable(rdev);
1250         if (rdev->flags & RADEON_IS_PCI)
1251                 r100_pci_gart_disable(rdev);
1252         return 0;
1253 }
1254
1255 void r300_fini(struct radeon_device *rdev)
1256 {
1257         r300_suspend(rdev);
1258         r100_cp_fini(rdev);
1259         r100_wb_fini(rdev);
1260         r100_ib_fini(rdev);
1261         radeon_gem_fini(rdev);
1262         if (rdev->flags & RADEON_IS_PCIE)
1263                 rv370_pcie_gart_fini(rdev);
1264         if (rdev->flags & RADEON_IS_PCI)
1265                 r100_pci_gart_fini(rdev);
1266         radeon_irq_kms_fini(rdev);
1267         radeon_fence_driver_fini(rdev);
1268         radeon_object_fini(rdev);
1269         radeon_atombios_fini(rdev);
1270         kfree(rdev->bios);
1271         rdev->bios = NULL;
1272 }
1273
1274 int r300_init(struct radeon_device *rdev)
1275 {
1276         int r;
1277
1278         rdev->new_init_path = true;
1279         /* Disable VGA */
1280         r100_vga_render_disable(rdev);
1281         /* Initialize scratch registers */
1282         radeon_scratch_init(rdev);
1283         /* Initialize surface registers */
1284         radeon_surface_init(rdev);
1285         /* TODO: disable VGA need to use VGA request */
1286         /* BIOS*/
1287         if (!radeon_get_bios(rdev)) {
1288                 if (ASIC_IS_AVIVO(rdev))
1289                         return -EINVAL;
1290         }
1291         if (rdev->is_atom_bios) {
1292                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
1293                 return -EINVAL;
1294         } else {
1295                 r = radeon_combios_init(rdev);
1296                 if (r)
1297                         return r;
1298         }
1299         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
1300         if (radeon_gpu_reset(rdev)) {
1301                 dev_warn(rdev->dev,
1302                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
1303                         RREG32(R_000E40_RBBM_STATUS),
1304                         RREG32(R_0007C0_CP_STAT));
1305         }
1306         /* check if cards are posted or not */
1307         if (!radeon_card_posted(rdev) && rdev->bios) {
1308                 DRM_INFO("GPU not posted. posting now...\n");
1309                 radeon_combios_asic_init(rdev->ddev);
1310         }
1311         /* Set asic errata */
1312         r300_errata(rdev);
1313         /* Initialize clocks */
1314         radeon_get_clock_info(rdev->ddev);
1315         /* Get vram informations */
1316         r300_vram_info(rdev);
1317         /* Initialize memory controller (also test AGP) */
1318         r = r420_mc_init(rdev);
1319         if (r)
1320                 return r;
1321         /* Fence driver */
1322         r = radeon_fence_driver_init(rdev);
1323         if (r)
1324                 return r;
1325         r = radeon_irq_kms_init(rdev);
1326         if (r)
1327                 return r;
1328         /* Memory manager */
1329         r = radeon_object_init(rdev);
1330         if (r)
1331                 return r;
1332         if (rdev->flags & RADEON_IS_PCIE) {
1333                 r = rv370_pcie_gart_init(rdev);
1334                 if (r)
1335                         return r;
1336         }
1337         if (rdev->flags & RADEON_IS_PCI) {
1338                 r = r100_pci_gart_init(rdev);
1339                 if (r)
1340                         return r;
1341         }
1342         r300_set_reg_safe(rdev);
1343         rdev->accel_working = true;
1344         r = r300_startup(rdev);
1345         if (r) {
1346                 /* Somethings want wront with the accel init stop accel */
1347                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
1348                 r300_suspend(rdev);
1349                 r100_cp_fini(rdev);
1350                 r100_wb_fini(rdev);
1351                 r100_ib_fini(rdev);
1352                 if (rdev->flags & RADEON_IS_PCIE)
1353                         rv370_pcie_gart_fini(rdev);
1354                 if (rdev->flags & RADEON_IS_PCI)
1355                         r100_pci_gart_fini(rdev);
1356                 radeon_irq_kms_fini(rdev);
1357                 rdev->accel_working = false;
1358         }
1359         return 0;
1360 }