Merge intel drm-intel-next branch
[linux-2.6.git] / drivers / gpu / drm / radeon / r300.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/seq_file.h>
29 #include "drmP.h"
30 #include "drm.h"
31 #include "radeon_reg.h"
32 #include "radeon.h"
33 #include "radeon_drm.h"
34 #include "radeon_share.h"
35
36 #include "r300_reg_safe.h"
37
38 /* r300,r350,rv350,rv370,rv380 depends on : */
39 void r100_hdp_reset(struct radeon_device *rdev);
40 int r100_cp_reset(struct radeon_device *rdev);
41 int r100_rb2d_reset(struct radeon_device *rdev);
42 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
43 int r100_pci_gart_enable(struct radeon_device *rdev);
44 void r100_pci_gart_disable(struct radeon_device *rdev);
45 void r100_mc_setup(struct radeon_device *rdev);
46 void r100_mc_disable_clients(struct radeon_device *rdev);
47 int r100_gui_wait_for_idle(struct radeon_device *rdev);
48 int r100_cs_packet_parse(struct radeon_cs_parser *p,
49                          struct radeon_cs_packet *pkt,
50                          unsigned idx);
51 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p);
52 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
53                               struct radeon_cs_reloc **cs_reloc);
54 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
55                           struct radeon_cs_packet *pkt,
56                           const unsigned *auth, unsigned n,
57                           radeon_packet0_check_t check);
58 void r100_cs_dump_packet(struct radeon_cs_parser *p,
59                          struct radeon_cs_packet *pkt);
60 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
61                                          struct radeon_cs_packet *pkt,
62                                          struct radeon_object *robj);
63
64 /* This files gather functions specifics to:
65  * r300,r350,rv350,rv370,rv380
66  *
67  * Some of these functions might be used by newer ASICs.
68  */
69 void r300_gpu_init(struct radeon_device *rdev);
70 int r300_mc_wait_for_idle(struct radeon_device *rdev);
71 int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev);
72
73
74 /*
75  * rv370,rv380 PCIE GART
76  */
77 void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev)
78 {
79         uint32_t tmp;
80         int i;
81
82         /* Workaround HW bug do flush 2 times */
83         for (i = 0; i < 2; i++) {
84                 tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
85                 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp | RADEON_PCIE_TX_GART_INVALIDATE_TLB);
86                 (void)RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
87                 WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
88         }
89         mb();
90 }
91
92 int rv370_pcie_gart_enable(struct radeon_device *rdev)
93 {
94         uint32_t table_addr;
95         uint32_t tmp;
96         int r;
97
98         /* Initialize common gart structure */
99         r = radeon_gart_init(rdev);
100         if (r) {
101                 return r;
102         }
103         r = rv370_debugfs_pcie_gart_info_init(rdev);
104         if (r) {
105                 DRM_ERROR("Failed to register debugfs file for PCIE gart !\n");
106         }
107         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
108         r = radeon_gart_table_vram_alloc(rdev);
109         if (r) {
110                 return r;
111         }
112         /* discard memory request outside of configured range */
113         tmp = RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
114         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
115         WREG32_PCIE(RADEON_PCIE_TX_GART_START_LO, rdev->mc.gtt_location);
116         tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 4096;
117         WREG32_PCIE(RADEON_PCIE_TX_GART_END_LO, tmp);
118         WREG32_PCIE(RADEON_PCIE_TX_GART_START_HI, 0);
119         WREG32_PCIE(RADEON_PCIE_TX_GART_END_HI, 0);
120         table_addr = rdev->gart.table_addr;
121         WREG32_PCIE(RADEON_PCIE_TX_GART_BASE, table_addr);
122         /* FIXME: setup default page */
123         WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, rdev->mc.vram_location);
124         WREG32_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_HI, 0);
125         /* Clear error */
126         WREG32_PCIE(0x18, 0);
127         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
128         tmp |= RADEON_PCIE_TX_GART_EN;
129         tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
130         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp);
131         rv370_pcie_gart_tlb_flush(rdev);
132         DRM_INFO("PCIE GART of %uM enabled (table at 0x%08X).\n",
133                  rdev->mc.gtt_size >> 20, table_addr);
134         rdev->gart.ready = true;
135         return 0;
136 }
137
138 void rv370_pcie_gart_disable(struct radeon_device *rdev)
139 {
140         uint32_t tmp;
141
142         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
143         tmp |= RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD;
144         WREG32_PCIE(RADEON_PCIE_TX_GART_CNTL, tmp & ~RADEON_PCIE_TX_GART_EN);
145         if (rdev->gart.table.vram.robj) {
146                 radeon_object_kunmap(rdev->gart.table.vram.robj);
147                 radeon_object_unpin(rdev->gart.table.vram.robj);
148         }
149 }
150
151 int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
152 {
153         void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
154
155         if (i < 0 || i > rdev->gart.num_gpu_pages) {
156                 return -EINVAL;
157         }
158         addr = (lower_32_bits(addr) >> 8) |
159                ((upper_32_bits(addr) & 0xff) << 24) |
160                0xc;
161         /* on x86 we want this to be CPU endian, on powerpc
162          * on powerpc without HW swappers, it'll get swapped on way
163          * into VRAM - so no need for cpu_to_le32 on VRAM tables */
164         writel(addr, ((void __iomem *)ptr) + (i * 4));
165         return 0;
166 }
167
168 int r300_gart_enable(struct radeon_device *rdev)
169 {
170 #if __OS_HAS_AGP
171         if (rdev->flags & RADEON_IS_AGP) {
172                 if (rdev->family > CHIP_RV350) {
173                         rv370_pcie_gart_disable(rdev);
174                 } else {
175                         r100_pci_gart_disable(rdev);
176                 }
177                 return 0;
178         }
179 #endif
180         if (rdev->flags & RADEON_IS_PCIE) {
181                 rdev->asic->gart_disable = &rv370_pcie_gart_disable;
182                 rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush;
183                 rdev->asic->gart_set_page = &rv370_pcie_gart_set_page;
184                 return rv370_pcie_gart_enable(rdev);
185         }
186         return r100_pci_gart_enable(rdev);
187 }
188
189
190 /*
191  * MC
192  */
193 int r300_mc_init(struct radeon_device *rdev)
194 {
195         int r;
196
197         if (r100_debugfs_rbbm_init(rdev)) {
198                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
199         }
200
201         r300_gpu_init(rdev);
202         r100_pci_gart_disable(rdev);
203         if (rdev->flags & RADEON_IS_PCIE) {
204                 rv370_pcie_gart_disable(rdev);
205         }
206
207         /* Setup GPU memory space */
208         rdev->mc.vram_location = 0xFFFFFFFFUL;
209         rdev->mc.gtt_location = 0xFFFFFFFFUL;
210         if (rdev->flags & RADEON_IS_AGP) {
211                 r = radeon_agp_init(rdev);
212                 if (r) {
213                         printk(KERN_WARNING "[drm] Disabling AGP\n");
214                         rdev->flags &= ~RADEON_IS_AGP;
215                         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
216                 } else {
217                         rdev->mc.gtt_location = rdev->mc.agp_base;
218                 }
219         }
220         r = radeon_mc_setup(rdev);
221         if (r) {
222                 return r;
223         }
224
225         /* Program GPU memory space */
226         r100_mc_disable_clients(rdev);
227         if (r300_mc_wait_for_idle(rdev)) {
228                 printk(KERN_WARNING "Failed to wait MC idle while "
229                        "programming pipes. Bad things might happen.\n");
230         }
231         r100_mc_setup(rdev);
232         return 0;
233 }
234
235 void r300_mc_fini(struct radeon_device *rdev)
236 {
237         if (rdev->flags & RADEON_IS_PCIE) {
238                 rv370_pcie_gart_disable(rdev);
239                 radeon_gart_table_vram_free(rdev);
240         } else {
241                 r100_pci_gart_disable(rdev);
242                 radeon_gart_table_ram_free(rdev);
243         }
244         radeon_gart_fini(rdev);
245 }
246
247
248 /*
249  * Fence emission
250  */
251 void r300_fence_ring_emit(struct radeon_device *rdev,
252                           struct radeon_fence *fence)
253 {
254         /* Who ever call radeon_fence_emit should call ring_lock and ask
255          * for enough space (today caller are ib schedule and buffer move) */
256         /* Write SC register so SC & US assert idle */
257         radeon_ring_write(rdev, PACKET0(0x43E0, 0));
258         radeon_ring_write(rdev, 0);
259         radeon_ring_write(rdev, PACKET0(0x43E4, 0));
260         radeon_ring_write(rdev, 0);
261         /* Flush 3D cache */
262         radeon_ring_write(rdev, PACKET0(0x4E4C, 0));
263         radeon_ring_write(rdev, (2 << 0));
264         radeon_ring_write(rdev, PACKET0(0x4F18, 0));
265         radeon_ring_write(rdev, (1 << 0));
266         /* Wait until IDLE & CLEAN */
267         radeon_ring_write(rdev, PACKET0(0x1720, 0));
268         radeon_ring_write(rdev, (1 << 17) | (1 << 16)  | (1 << 9));
269         /* Emit fence sequence & fire IRQ */
270         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
271         radeon_ring_write(rdev, fence->seq);
272         radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
273         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
274 }
275
276
277 /*
278  * Global GPU functions
279  */
280 int r300_copy_dma(struct radeon_device *rdev,
281                   uint64_t src_offset,
282                   uint64_t dst_offset,
283                   unsigned num_pages,
284                   struct radeon_fence *fence)
285 {
286         uint32_t size;
287         uint32_t cur_size;
288         int i, num_loops;
289         int r = 0;
290
291         /* radeon pitch is /64 */
292         size = num_pages << PAGE_SHIFT;
293         num_loops = DIV_ROUND_UP(size, 0x1FFFFF);
294         r = radeon_ring_lock(rdev, num_loops * 4 + 64);
295         if (r) {
296                 DRM_ERROR("radeon: moving bo (%d).\n", r);
297                 return r;
298         }
299         /* Must wait for 2D idle & clean before DMA or hangs might happen */
300         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0 ));
301         radeon_ring_write(rdev, (1 << 16));
302         for (i = 0; i < num_loops; i++) {
303                 cur_size = size;
304                 if (cur_size > 0x1FFFFF) {
305                         cur_size = 0x1FFFFF;
306                 }
307                 size -= cur_size;
308                 radeon_ring_write(rdev, PACKET0(0x720, 2));
309                 radeon_ring_write(rdev, src_offset);
310                 radeon_ring_write(rdev, dst_offset);
311                 radeon_ring_write(rdev, cur_size | (1 << 31) | (1 << 30));
312                 src_offset += cur_size;
313                 dst_offset += cur_size;
314         }
315         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
316         radeon_ring_write(rdev, RADEON_WAIT_DMA_GUI_IDLE);
317         if (fence) {
318                 r = radeon_fence_emit(rdev, fence);
319         }
320         radeon_ring_unlock_commit(rdev);
321         return r;
322 }
323
324 void r300_ring_start(struct radeon_device *rdev)
325 {
326         unsigned gb_tile_config;
327         int r;
328
329         /* Sub pixel 1/12 so we can have 4K rendering according to doc */
330         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
331         switch(rdev->num_gb_pipes) {
332         case 2:
333                 gb_tile_config |= R300_PIPE_COUNT_R300;
334                 break;
335         case 3:
336                 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
337                 break;
338         case 4:
339                 gb_tile_config |= R300_PIPE_COUNT_R420;
340                 break;
341         case 1:
342         default:
343                 gb_tile_config |= R300_PIPE_COUNT_RV350;
344                 break;
345         }
346
347         r = radeon_ring_lock(rdev, 64);
348         if (r) {
349                 return;
350         }
351         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
352         radeon_ring_write(rdev,
353                           RADEON_ISYNC_ANY2D_IDLE3D |
354                           RADEON_ISYNC_ANY3D_IDLE2D |
355                           RADEON_ISYNC_WAIT_IDLEGUI |
356                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
357         radeon_ring_write(rdev, PACKET0(R300_GB_TILE_CONFIG, 0));
358         radeon_ring_write(rdev, gb_tile_config);
359         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
360         radeon_ring_write(rdev,
361                           RADEON_WAIT_2D_IDLECLEAN |
362                           RADEON_WAIT_3D_IDLECLEAN);
363         radeon_ring_write(rdev, PACKET0(0x170C, 0));
364         radeon_ring_write(rdev, 1 << 31);
365         radeon_ring_write(rdev, PACKET0(R300_GB_SELECT, 0));
366         radeon_ring_write(rdev, 0);
367         radeon_ring_write(rdev, PACKET0(R300_GB_ENABLE, 0));
368         radeon_ring_write(rdev, 0);
369         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
370         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
371         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
372         radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
373         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
374         radeon_ring_write(rdev,
375                           RADEON_WAIT_2D_IDLECLEAN |
376                           RADEON_WAIT_3D_IDLECLEAN);
377         radeon_ring_write(rdev, PACKET0(R300_GB_AA_CONFIG, 0));
378         radeon_ring_write(rdev, 0);
379         radeon_ring_write(rdev, PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
380         radeon_ring_write(rdev, R300_RB3D_DC_FLUSH | R300_RB3D_DC_FREE);
381         radeon_ring_write(rdev, PACKET0(R300_RB3D_ZCACHE_CTLSTAT, 0));
382         radeon_ring_write(rdev, R300_ZC_FLUSH | R300_ZC_FREE);
383         radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS0, 0));
384         radeon_ring_write(rdev,
385                           ((6 << R300_MS_X0_SHIFT) |
386                            (6 << R300_MS_Y0_SHIFT) |
387                            (6 << R300_MS_X1_SHIFT) |
388                            (6 << R300_MS_Y1_SHIFT) |
389                            (6 << R300_MS_X2_SHIFT) |
390                            (6 << R300_MS_Y2_SHIFT) |
391                            (6 << R300_MSBD0_Y_SHIFT) |
392                            (6 << R300_MSBD0_X_SHIFT)));
393         radeon_ring_write(rdev, PACKET0(R300_GB_MSPOS1, 0));
394         radeon_ring_write(rdev,
395                           ((6 << R300_MS_X3_SHIFT) |
396                            (6 << R300_MS_Y3_SHIFT) |
397                            (6 << R300_MS_X4_SHIFT) |
398                            (6 << R300_MS_Y4_SHIFT) |
399                            (6 << R300_MS_X5_SHIFT) |
400                            (6 << R300_MS_Y5_SHIFT) |
401                            (6 << R300_MSBD1_SHIFT)));
402         radeon_ring_write(rdev, PACKET0(R300_GA_ENHANCE, 0));
403         radeon_ring_write(rdev, R300_GA_DEADLOCK_CNTL | R300_GA_FASTSYNC_CNTL);
404         radeon_ring_write(rdev, PACKET0(R300_GA_POLY_MODE, 0));
405         radeon_ring_write(rdev,
406                           R300_FRONT_PTYPE_TRIANGE | R300_BACK_PTYPE_TRIANGE);
407         radeon_ring_write(rdev, PACKET0(R300_GA_ROUND_MODE, 0));
408         radeon_ring_write(rdev,
409                           R300_GEOMETRY_ROUND_NEAREST |
410                           R300_COLOR_ROUND_NEAREST);
411         radeon_ring_unlock_commit(rdev);
412 }
413
414 void r300_errata(struct radeon_device *rdev)
415 {
416         rdev->pll_errata = 0;
417
418         if (rdev->family == CHIP_R300 &&
419             (RREG32(RADEON_CONFIG_CNTL) & RADEON_CFG_ATI_REV_ID_MASK) == RADEON_CFG_ATI_REV_A11) {
420                 rdev->pll_errata |= CHIP_ERRATA_R300_CG;
421         }
422 }
423
424 int r300_mc_wait_for_idle(struct radeon_device *rdev)
425 {
426         unsigned i;
427         uint32_t tmp;
428
429         for (i = 0; i < rdev->usec_timeout; i++) {
430                 /* read MC_STATUS */
431                 tmp = RREG32(0x0150);
432                 if (tmp & (1 << 4)) {
433                         return 0;
434                 }
435                 DRM_UDELAY(1);
436         }
437         return -1;
438 }
439
440 void r300_gpu_init(struct radeon_device *rdev)
441 {
442         uint32_t gb_tile_config, tmp;
443
444         r100_hdp_reset(rdev);
445         /* FIXME: rv380 one pipes ? */
446         if ((rdev->family == CHIP_R300) || (rdev->family == CHIP_R350)) {
447                 /* r300,r350 */
448                 rdev->num_gb_pipes = 2;
449         } else {
450                 /* rv350,rv370,rv380 */
451                 rdev->num_gb_pipes = 1;
452         }
453         rdev->num_z_pipes = 1;
454         gb_tile_config = (R300_ENABLE_TILING | R300_TILE_SIZE_16);
455         switch (rdev->num_gb_pipes) {
456         case 2:
457                 gb_tile_config |= R300_PIPE_COUNT_R300;
458                 break;
459         case 3:
460                 gb_tile_config |= R300_PIPE_COUNT_R420_3P;
461                 break;
462         case 4:
463                 gb_tile_config |= R300_PIPE_COUNT_R420;
464                 break;
465         default:
466         case 1:
467                 gb_tile_config |= R300_PIPE_COUNT_RV350;
468                 break;
469         }
470         WREG32(R300_GB_TILE_CONFIG, gb_tile_config);
471
472         if (r100_gui_wait_for_idle(rdev)) {
473                 printk(KERN_WARNING "Failed to wait GUI idle while "
474                        "programming pipes. Bad things might happen.\n");
475         }
476
477         tmp = RREG32(0x170C);
478         WREG32(0x170C, tmp | (1 << 31));
479
480         WREG32(R300_RB2D_DSTCACHE_MODE,
481                R300_DC_AUTOFLUSH_ENABLE |
482                R300_DC_DC_DISABLE_IGNORE_PE);
483
484         if (r100_gui_wait_for_idle(rdev)) {
485                 printk(KERN_WARNING "Failed to wait GUI idle while "
486                        "programming pipes. Bad things might happen.\n");
487         }
488         if (r300_mc_wait_for_idle(rdev)) {
489                 printk(KERN_WARNING "Failed to wait MC idle while "
490                        "programming pipes. Bad things might happen.\n");
491         }
492         DRM_INFO("radeon: %d quad pipes, %d Z pipes initialized.\n",
493                  rdev->num_gb_pipes, rdev->num_z_pipes);
494 }
495
496 int r300_ga_reset(struct radeon_device *rdev)
497 {
498         uint32_t tmp;
499         bool reinit_cp;
500         int i;
501
502         reinit_cp = rdev->cp.ready;
503         rdev->cp.ready = false;
504         for (i = 0; i < rdev->usec_timeout; i++) {
505                 WREG32(RADEON_CP_CSQ_MODE, 0);
506                 WREG32(RADEON_CP_CSQ_CNTL, 0);
507                 WREG32(RADEON_RBBM_SOFT_RESET, 0x32005);
508                 (void)RREG32(RADEON_RBBM_SOFT_RESET);
509                 udelay(200);
510                 WREG32(RADEON_RBBM_SOFT_RESET, 0);
511                 /* Wait to prevent race in RBBM_STATUS */
512                 mdelay(1);
513                 tmp = RREG32(RADEON_RBBM_STATUS);
514                 if (tmp & ((1 << 20) | (1 << 26))) {
515                         DRM_ERROR("VAP & CP still busy (RBBM_STATUS=0x%08X)", tmp);
516                         /* GA still busy soft reset it */
517                         WREG32(0x429C, 0x200);
518                         WREG32(R300_VAP_PVS_STATE_FLUSH_REG, 0);
519                         WREG32(0x43E0, 0);
520                         WREG32(0x43E4, 0);
521                         WREG32(0x24AC, 0);
522                 }
523                 /* Wait to prevent race in RBBM_STATUS */
524                 mdelay(1);
525                 tmp = RREG32(RADEON_RBBM_STATUS);
526                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
527                         break;
528                 }
529         }
530         for (i = 0; i < rdev->usec_timeout; i++) {
531                 tmp = RREG32(RADEON_RBBM_STATUS);
532                 if (!(tmp & ((1 << 20) | (1 << 26)))) {
533                         DRM_INFO("GA reset succeed (RBBM_STATUS=0x%08X)\n",
534                                  tmp);
535                         if (reinit_cp) {
536                                 return r100_cp_init(rdev, rdev->cp.ring_size);
537                         }
538                         return 0;
539                 }
540                 DRM_UDELAY(1);
541         }
542         tmp = RREG32(RADEON_RBBM_STATUS);
543         DRM_ERROR("Failed to reset GA ! (RBBM_STATUS=0x%08X)\n", tmp);
544         return -1;
545 }
546
547 int r300_gpu_reset(struct radeon_device *rdev)
548 {
549         uint32_t status;
550
551         /* reset order likely matter */
552         status = RREG32(RADEON_RBBM_STATUS);
553         /* reset HDP */
554         r100_hdp_reset(rdev);
555         /* reset rb2d */
556         if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
557                 r100_rb2d_reset(rdev);
558         }
559         /* reset GA */
560         if (status & ((1 << 20) | (1 << 26))) {
561                 r300_ga_reset(rdev);
562         }
563         /* reset CP */
564         status = RREG32(RADEON_RBBM_STATUS);
565         if (status & (1 << 16)) {
566                 r100_cp_reset(rdev);
567         }
568         /* Check if GPU is idle */
569         status = RREG32(RADEON_RBBM_STATUS);
570         if (status & (1 << 31)) {
571                 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
572                 return -1;
573         }
574         DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
575         return 0;
576 }
577
578
579 /*
580  * r300,r350,rv350,rv380 VRAM info
581  */
582 void r300_vram_info(struct radeon_device *rdev)
583 {
584         uint32_t tmp;
585
586         /* DDR for all card after R300 & IGP */
587         rdev->mc.vram_is_ddr = true;
588         tmp = RREG32(RADEON_MEM_CNTL);
589         if (tmp & R300_MEM_NUM_CHANNELS_MASK) {
590                 rdev->mc.vram_width = 128;
591         } else {
592                 rdev->mc.vram_width = 64;
593         }
594
595         r100_vram_init_sizes(rdev);
596 }
597
598
599 /*
600  * PCIE Lanes
601  */
602
603 void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes)
604 {
605         uint32_t link_width_cntl, mask;
606
607         if (rdev->flags & RADEON_IS_IGP)
608                 return;
609
610         if (!(rdev->flags & RADEON_IS_PCIE))
611                 return;
612
613         /* FIXME wait for idle */
614
615         switch (lanes) {
616         case 0:
617                 mask = RADEON_PCIE_LC_LINK_WIDTH_X0;
618                 break;
619         case 1:
620                 mask = RADEON_PCIE_LC_LINK_WIDTH_X1;
621                 break;
622         case 2:
623                 mask = RADEON_PCIE_LC_LINK_WIDTH_X2;
624                 break;
625         case 4:
626                 mask = RADEON_PCIE_LC_LINK_WIDTH_X4;
627                 break;
628         case 8:
629                 mask = RADEON_PCIE_LC_LINK_WIDTH_X8;
630                 break;
631         case 12:
632                 mask = RADEON_PCIE_LC_LINK_WIDTH_X12;
633                 break;
634         case 16:
635         default:
636                 mask = RADEON_PCIE_LC_LINK_WIDTH_X16;
637                 break;
638         }
639
640         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
641
642         if ((link_width_cntl & RADEON_PCIE_LC_LINK_WIDTH_RD_MASK) ==
643             (mask << RADEON_PCIE_LC_LINK_WIDTH_RD_SHIFT))
644                 return;
645
646         link_width_cntl &= ~(RADEON_PCIE_LC_LINK_WIDTH_MASK |
647                              RADEON_PCIE_LC_RECONFIG_NOW |
648                              RADEON_PCIE_LC_RECONFIG_LATER |
649                              RADEON_PCIE_LC_SHORT_RECONFIG_EN);
650         link_width_cntl |= mask;
651         WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
652         WREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL, (link_width_cntl |
653                                                      RADEON_PCIE_LC_RECONFIG_NOW));
654
655         /* wait for lane set to complete */
656         link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
657         while (link_width_cntl == 0xffffffff)
658                 link_width_cntl = RREG32_PCIE(RADEON_PCIE_LC_LINK_WIDTH_CNTL);
659
660 }
661
662
663 /*
664  * Debugfs info
665  */
666 #if defined(CONFIG_DEBUG_FS)
667 static int rv370_debugfs_pcie_gart_info(struct seq_file *m, void *data)
668 {
669         struct drm_info_node *node = (struct drm_info_node *) m->private;
670         struct drm_device *dev = node->minor->dev;
671         struct radeon_device *rdev = dev->dev_private;
672         uint32_t tmp;
673
674         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_CNTL);
675         seq_printf(m, "PCIE_TX_GART_CNTL 0x%08x\n", tmp);
676         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_BASE);
677         seq_printf(m, "PCIE_TX_GART_BASE 0x%08x\n", tmp);
678         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_LO);
679         seq_printf(m, "PCIE_TX_GART_START_LO 0x%08x\n", tmp);
680         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_START_HI);
681         seq_printf(m, "PCIE_TX_GART_START_HI 0x%08x\n", tmp);
682         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_LO);
683         seq_printf(m, "PCIE_TX_GART_END_LO 0x%08x\n", tmp);
684         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_END_HI);
685         seq_printf(m, "PCIE_TX_GART_END_HI 0x%08x\n", tmp);
686         tmp = RREG32_PCIE(RADEON_PCIE_TX_GART_ERROR);
687         seq_printf(m, "PCIE_TX_GART_ERROR 0x%08x\n", tmp);
688         return 0;
689 }
690
691 static struct drm_info_list rv370_pcie_gart_info_list[] = {
692         {"rv370_pcie_gart_info", rv370_debugfs_pcie_gart_info, 0, NULL},
693 };
694 #endif
695
696 int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev)
697 {
698 #if defined(CONFIG_DEBUG_FS)
699         return radeon_debugfs_add_files(rdev, rv370_pcie_gart_info_list, 1);
700 #else
701         return 0;
702 #endif
703 }
704
705
706 /*
707  * CS functions
708  */
709 struct r300_cs_track_cb {
710         struct radeon_object    *robj;
711         unsigned                pitch;
712         unsigned                cpp;
713         unsigned                offset;
714 };
715
716 struct r300_cs_track_array {
717         struct radeon_object    *robj;
718         unsigned                esize;
719 };
720
721 struct r300_cs_track_texture {
722         struct radeon_object    *robj;
723         unsigned                pitch;
724         unsigned                width;
725         unsigned                height;
726         unsigned                num_levels;
727         unsigned                cpp;
728         unsigned                tex_coord_type;
729         unsigned                txdepth;
730         unsigned                width_11;
731         unsigned                height_11;
732         bool                    use_pitch;
733         bool                    enabled;
734         bool                    roundup_w;
735         bool                    roundup_h;
736 };
737
738 struct r300_cs_track {
739         unsigned                        num_cb;
740         unsigned                        maxy;
741         unsigned                        vtx_size;
742         unsigned                        vap_vf_cntl;
743         unsigned                        immd_dwords;
744         unsigned                        num_arrays;
745         unsigned                        max_indx;
746         struct r300_cs_track_array      arrays[11];
747         struct r300_cs_track_cb         cb[4];
748         struct r300_cs_track_cb         zb;
749         struct r300_cs_track_texture    textures[16];
750         bool                            z_enabled;
751 };
752
753 static inline void r300_cs_track_texture_print(struct r300_cs_track_texture *t)
754 {
755         DRM_ERROR("pitch                      %d\n", t->pitch);
756         DRM_ERROR("width                      %d\n", t->width);
757         DRM_ERROR("height                     %d\n", t->height);
758         DRM_ERROR("num levels                 %d\n", t->num_levels);
759         DRM_ERROR("depth                      %d\n", t->txdepth);
760         DRM_ERROR("bpp                        %d\n", t->cpp);
761         DRM_ERROR("coordinate type            %d\n", t->tex_coord_type);
762         DRM_ERROR("width round to power of 2  %d\n", t->roundup_w);
763         DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
764 }
765
766 static inline int r300_cs_track_texture_check(struct radeon_device *rdev,
767                                               struct r300_cs_track *track)
768 {
769         struct radeon_object *robj;
770         unsigned long size;
771         unsigned u, i, w, h;
772
773         for (u = 0; u < 16; u++) {
774                 if (!track->textures[u].enabled)
775                         continue;
776                 robj = track->textures[u].robj;
777                 if (robj == NULL) {
778                         DRM_ERROR("No texture bound to unit %u\n", u);
779                         return -EINVAL;
780                 }
781                 size = 0;
782                 for (i = 0; i <= track->textures[u].num_levels; i++) {
783                         if (track->textures[u].use_pitch) {
784                                 w = track->textures[u].pitch / (1 << i);
785                         } else {
786                                 w = track->textures[u].width / (1 << i);
787                                 if (rdev->family >= CHIP_RV515)
788                                         w |= track->textures[u].width_11;
789                                 if (track->textures[u].roundup_w)
790                                         w = roundup_pow_of_two(w);
791                         }
792                         h = track->textures[u].height / (1 << i);
793                         if (rdev->family >= CHIP_RV515)
794                                 h |= track->textures[u].height_11;
795                         if (track->textures[u].roundup_h)
796                                 h = roundup_pow_of_two(h);
797                         size += w * h;
798                 }
799                 size *= track->textures[u].cpp;
800                 switch (track->textures[u].tex_coord_type) {
801                 case 0:
802                         break;
803                 case 1:
804                         size *= (1 << track->textures[u].txdepth);
805                         break;
806                 case 2:
807                         size *= 6;
808                         break;
809                 default:
810                         DRM_ERROR("Invalid texture coordinate type %u for unit "
811                                   "%u\n", track->textures[u].tex_coord_type, u);
812                         return -EINVAL;
813                 }
814                 if (size > radeon_object_size(robj)) {
815                         DRM_ERROR("Texture of unit %u needs %lu bytes but is "
816                                   "%lu\n", u, size, radeon_object_size(robj));
817                         r300_cs_track_texture_print(&track->textures[u]);
818                         return -EINVAL;
819                 }
820         }
821         return 0;
822 }
823
824 int r300_cs_track_check(struct radeon_device *rdev, struct r300_cs_track *track)
825 {
826         unsigned i;
827         unsigned long size;
828         unsigned prim_walk;
829         unsigned nverts;
830
831         for (i = 0; i < track->num_cb; i++) {
832                 if (track->cb[i].robj == NULL) {
833                         DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
834                         return -EINVAL;
835                 }
836                 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
837                 size += track->cb[i].offset;
838                 if (size > radeon_object_size(track->cb[i].robj)) {
839                         DRM_ERROR("[drm] Buffer too small for color buffer %d "
840                                   "(need %lu have %lu) !\n", i, size,
841                                   radeon_object_size(track->cb[i].robj));
842                         DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
843                                   i, track->cb[i].pitch, track->cb[i].cpp,
844                                   track->cb[i].offset, track->maxy);
845                         return -EINVAL;
846                 }
847         }
848         if (track->z_enabled) {
849                 if (track->zb.robj == NULL) {
850                         DRM_ERROR("[drm] No buffer for z buffer !\n");
851                         return -EINVAL;
852                 }
853                 size = track->zb.pitch * track->zb.cpp * track->maxy;
854                 size += track->zb.offset;
855                 if (size > radeon_object_size(track->zb.robj)) {
856                         DRM_ERROR("[drm] Buffer too small for z buffer "
857                                   "(need %lu have %lu) !\n", size,
858                                   radeon_object_size(track->zb.robj));
859                         return -EINVAL;
860                 }
861         }
862         prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
863         nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
864         switch (prim_walk) {
865         case 1:
866                 for (i = 0; i < track->num_arrays; i++) {
867                         size = track->arrays[i].esize * track->max_indx * 4;
868                         if (track->arrays[i].robj == NULL) {
869                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
870                                           "bound\n", prim_walk, i);
871                                 return -EINVAL;
872                         }
873                         if (size > radeon_object_size(track->arrays[i].robj)) {
874                                 DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
875                                            "have %lu dwords\n", prim_walk, i,
876                                            size >> 2,
877                                            radeon_object_size(track->arrays[i].robj) >> 2);
878                                 DRM_ERROR("Max indices %u\n", track->max_indx);
879                                 return -EINVAL;
880                         }
881                 }
882                 break;
883         case 2:
884                 for (i = 0; i < track->num_arrays; i++) {
885                         size = track->arrays[i].esize * (nverts - 1) * 4;
886                         if (track->arrays[i].robj == NULL) {
887                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
888                                           "bound\n", prim_walk, i);
889                                 return -EINVAL;
890                         }
891                         if (size > radeon_object_size(track->arrays[i].robj)) {
892                                 DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
893                                            "have %lu dwords\n", prim_walk, i, size >> 2,
894                                            radeon_object_size(track->arrays[i].robj) >> 2);
895                                 return -EINVAL;
896                         }
897                 }
898                 break;
899         case 3:
900                 size = track->vtx_size * nverts;
901                 if (size != track->immd_dwords) {
902                         DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
903                                   track->immd_dwords, size);
904                         DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
905                                   nverts, track->vtx_size);
906                         return -EINVAL;
907                 }
908                 break;
909         default:
910                 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
911                           prim_walk);
912                 return -EINVAL;
913         }
914         return r300_cs_track_texture_check(rdev, track);
915 }
916
917 static inline void r300_cs_track_clear(struct r300_cs_track *track)
918 {
919         unsigned i;
920
921         track->num_cb = 4;
922         track->maxy = 4096;
923         for (i = 0; i < track->num_cb; i++) {
924                 track->cb[i].robj = NULL;
925                 track->cb[i].pitch = 8192;
926                 track->cb[i].cpp = 16;
927                 track->cb[i].offset = 0;
928         }
929         track->z_enabled = true;
930         track->zb.robj = NULL;
931         track->zb.pitch = 8192;
932         track->zb.cpp = 4;
933         track->zb.offset = 0;
934         track->vtx_size = 0x7F;
935         track->immd_dwords = 0xFFFFFFFFUL;
936         track->num_arrays = 11;
937         track->max_indx = 0x00FFFFFFUL;
938         for (i = 0; i < track->num_arrays; i++) {
939                 track->arrays[i].robj = NULL;
940                 track->arrays[i].esize = 0x7F;
941         }
942         for (i = 0; i < 16; i++) {
943                 track->textures[i].pitch = 16536;
944                 track->textures[i].width = 16536;
945                 track->textures[i].height = 16536;
946                 track->textures[i].width_11 = 1 << 11;
947                 track->textures[i].height_11 = 1 << 11;
948                 track->textures[i].num_levels = 12;
949                 track->textures[i].txdepth = 16;
950                 track->textures[i].cpp = 64;
951                 track->textures[i].tex_coord_type = 1;
952                 track->textures[i].robj = NULL;
953                 /* CS IB emission code makes sure texture unit are disabled */
954                 track->textures[i].enabled = false;
955                 track->textures[i].roundup_w = true;
956                 track->textures[i].roundup_h = true;
957         }
958 }
959
960 static int r300_packet0_check(struct radeon_cs_parser *p,
961                 struct radeon_cs_packet *pkt,
962                 unsigned idx, unsigned reg)
963 {
964         struct radeon_cs_chunk *ib_chunk;
965         struct radeon_cs_reloc *reloc;
966         struct r300_cs_track *track;
967         volatile uint32_t *ib;
968         uint32_t tmp, tile_flags = 0;
969         unsigned i;
970         int r;
971
972         ib = p->ib->ptr;
973         ib_chunk = &p->chunks[p->chunk_ib_idx];
974         track = (struct r300_cs_track*)p->track;
975         switch(reg) {
976         case AVIVO_D1MODE_VLINE_START_END:
977         case RADEON_CRTC_GUI_TRIG_VLINE:
978                 r = r100_cs_packet_parse_vline(p);
979                 if (r) {
980                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
981                                         idx, reg);
982                         r100_cs_dump_packet(p, pkt);
983                         return r;
984                 }
985                 break;
986         case RADEON_DST_PITCH_OFFSET:
987         case RADEON_SRC_PITCH_OFFSET:
988                 r = r100_cs_packet_next_reloc(p, &reloc);
989                 if (r) {
990                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
991                                         idx, reg);
992                         r100_cs_dump_packet(p, pkt);
993                         return r;
994                 }
995                 tmp = ib_chunk->kdata[idx] & 0x003fffff;
996                 tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
997
998                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
999                         tile_flags |= RADEON_DST_TILE_MACRO;
1000                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) {
1001                         if (reg == RADEON_SRC_PITCH_OFFSET) {
1002                                 DRM_ERROR("Cannot src blit from microtiled surface\n");
1003                                 r100_cs_dump_packet(p, pkt);
1004                                 return -EINVAL;
1005                         }
1006                         tile_flags |= RADEON_DST_TILE_MICRO;
1007                 }
1008                 tmp |= tile_flags;
1009                 ib[idx] = (ib_chunk->kdata[idx] & 0x3fc00000) | tmp;
1010                 break;
1011         case R300_RB3D_COLOROFFSET0:
1012         case R300_RB3D_COLOROFFSET1:
1013         case R300_RB3D_COLOROFFSET2:
1014         case R300_RB3D_COLOROFFSET3:
1015                 i = (reg - R300_RB3D_COLOROFFSET0) >> 2;
1016                 r = r100_cs_packet_next_reloc(p, &reloc);
1017                 if (r) {
1018                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1019                                         idx, reg);
1020                         r100_cs_dump_packet(p, pkt);
1021                         return r;
1022                 }
1023                 track->cb[i].robj = reloc->robj;
1024                 track->cb[i].offset = ib_chunk->kdata[idx];
1025                 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1026                 break;
1027         case R300_ZB_DEPTHOFFSET:
1028                 r = r100_cs_packet_next_reloc(p, &reloc);
1029                 if (r) {
1030                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1031                                         idx, reg);
1032                         r100_cs_dump_packet(p, pkt);
1033                         return r;
1034                 }
1035                 track->zb.robj = reloc->robj;
1036                 track->zb.offset = ib_chunk->kdata[idx];
1037                 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1038                 break;
1039         case R300_TX_OFFSET_0:
1040         case R300_TX_OFFSET_0+4:
1041         case R300_TX_OFFSET_0+8:
1042         case R300_TX_OFFSET_0+12:
1043         case R300_TX_OFFSET_0+16:
1044         case R300_TX_OFFSET_0+20:
1045         case R300_TX_OFFSET_0+24:
1046         case R300_TX_OFFSET_0+28:
1047         case R300_TX_OFFSET_0+32:
1048         case R300_TX_OFFSET_0+36:
1049         case R300_TX_OFFSET_0+40:
1050         case R300_TX_OFFSET_0+44:
1051         case R300_TX_OFFSET_0+48:
1052         case R300_TX_OFFSET_0+52:
1053         case R300_TX_OFFSET_0+56:
1054         case R300_TX_OFFSET_0+60:
1055                 i = (reg - R300_TX_OFFSET_0) >> 2;
1056                 r = r100_cs_packet_next_reloc(p, &reloc);
1057                 if (r) {
1058                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1059                                         idx, reg);
1060                         r100_cs_dump_packet(p, pkt);
1061                         return r;
1062                 }
1063                 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1064                 track->textures[i].robj = reloc->robj;
1065                 break;
1066         /* Tracked registers */
1067         case 0x2084:
1068                 /* VAP_VF_CNTL */
1069                 track->vap_vf_cntl = ib_chunk->kdata[idx];
1070                 break;
1071         case 0x20B4:
1072                 /* VAP_VTX_SIZE */
1073                 track->vtx_size = ib_chunk->kdata[idx] & 0x7F;
1074                 break;
1075         case 0x2134:
1076                 /* VAP_VF_MAX_VTX_INDX */
1077                 track->max_indx = ib_chunk->kdata[idx] & 0x00FFFFFFUL;
1078                 break;
1079         case 0x43E4:
1080                 /* SC_SCISSOR1 */
1081                 track->maxy = ((ib_chunk->kdata[idx] >> 13) & 0x1FFF) + 1;
1082                 if (p->rdev->family < CHIP_RV515) {
1083                         track->maxy -= 1440;
1084                 }
1085                 break;
1086         case 0x4E00:
1087                 /* RB3D_CCTL */
1088                 track->num_cb = ((ib_chunk->kdata[idx] >> 5) & 0x3) + 1;
1089                 break;
1090         case 0x4E38:
1091         case 0x4E3C:
1092         case 0x4E40:
1093         case 0x4E44:
1094                 /* RB3D_COLORPITCH0 */
1095                 /* RB3D_COLORPITCH1 */
1096                 /* RB3D_COLORPITCH2 */
1097                 /* RB3D_COLORPITCH3 */
1098                 r = r100_cs_packet_next_reloc(p, &reloc);
1099                 if (r) {
1100                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1101                                   idx, reg);
1102                         r100_cs_dump_packet(p, pkt);
1103                         return r;
1104                 }
1105
1106                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1107                         tile_flags |= R300_COLOR_TILE_ENABLE;
1108                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1109                         tile_flags |= R300_COLOR_MICROTILE_ENABLE;
1110
1111                 tmp = ib_chunk->kdata[idx] & ~(0x7 << 16);
1112                 tmp |= tile_flags;
1113                 ib[idx] = tmp;
1114
1115                 i = (reg - 0x4E38) >> 2;
1116                 track->cb[i].pitch = ib_chunk->kdata[idx] & 0x3FFE;
1117                 switch (((ib_chunk->kdata[idx] >> 21) & 0xF)) {
1118                 case 9:
1119                 case 11:
1120                 case 12:
1121                         track->cb[i].cpp = 1;
1122                         break;
1123                 case 3:
1124                 case 4:
1125                 case 13:
1126                 case 15:
1127                         track->cb[i].cpp = 2;
1128                         break;
1129                 case 6:
1130                         track->cb[i].cpp = 4;
1131                         break;
1132                 case 10:
1133                         track->cb[i].cpp = 8;
1134                         break;
1135                 case 7:
1136                         track->cb[i].cpp = 16;
1137                         break;
1138                 default:
1139                         DRM_ERROR("Invalid color buffer format (%d) !\n",
1140                                   ((ib_chunk->kdata[idx] >> 21) & 0xF));
1141                         return -EINVAL;
1142                 }
1143                 break;
1144         case 0x4F00:
1145                 /* ZB_CNTL */
1146                 if (ib_chunk->kdata[idx] & 2) {
1147                         track->z_enabled = true;
1148                 } else {
1149                         track->z_enabled = false;
1150                 }
1151                 break;
1152         case 0x4F10:
1153                 /* ZB_FORMAT */
1154                 switch ((ib_chunk->kdata[idx] & 0xF)) {
1155                 case 0:
1156                 case 1:
1157                         track->zb.cpp = 2;
1158                         break;
1159                 case 2:
1160                         track->zb.cpp = 4;
1161                         break;
1162                 default:
1163                         DRM_ERROR("Invalid z buffer format (%d) !\n",
1164                                   (ib_chunk->kdata[idx] & 0xF));
1165                         return -EINVAL;
1166                 }
1167                 break;
1168         case 0x4F24:
1169                 /* ZB_DEPTHPITCH */
1170                 r = r100_cs_packet_next_reloc(p, &reloc);
1171                 if (r) {
1172                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1173                                   idx, reg);
1174                         r100_cs_dump_packet(p, pkt);
1175                         return r;
1176                 }
1177
1178                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1179                         tile_flags |= R300_DEPTHMACROTILE_ENABLE;
1180                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1181                         tile_flags |= R300_DEPTHMICROTILE_TILED;;
1182
1183                 tmp = ib_chunk->kdata[idx] & ~(0x7 << 16);
1184                 tmp |= tile_flags;
1185                 ib[idx] = tmp;
1186
1187                 track->zb.pitch = ib_chunk->kdata[idx] & 0x3FFC;
1188                 break;
1189         case 0x4104:
1190                 for (i = 0; i < 16; i++) {
1191                         bool enabled;
1192
1193                         enabled = !!(ib_chunk->kdata[idx] & (1 << i));
1194                         track->textures[i].enabled = enabled;
1195                 }
1196                 break;
1197         case 0x44C0:
1198         case 0x44C4:
1199         case 0x44C8:
1200         case 0x44CC:
1201         case 0x44D0:
1202         case 0x44D4:
1203         case 0x44D8:
1204         case 0x44DC:
1205         case 0x44E0:
1206         case 0x44E4:
1207         case 0x44E8:
1208         case 0x44EC:
1209         case 0x44F0:
1210         case 0x44F4:
1211         case 0x44F8:
1212         case 0x44FC:
1213                 /* TX_FORMAT1_[0-15] */
1214                 i = (reg - 0x44C0) >> 2;
1215                 tmp = (ib_chunk->kdata[idx] >> 25) & 0x3;
1216                 track->textures[i].tex_coord_type = tmp;
1217                 switch ((ib_chunk->kdata[idx] & 0x1F)) {
1218                 case 0:
1219                 case 2:
1220                 case 5:
1221                 case 18:
1222                 case 20:
1223                 case 21:
1224                         track->textures[i].cpp = 1;
1225                         break;
1226                 case 1:
1227                 case 3:
1228                 case 6:
1229                 case 7:
1230                 case 10:
1231                 case 11:
1232                 case 19:
1233                 case 22:
1234                 case 24:
1235                         track->textures[i].cpp = 2;
1236                         break;
1237                 case 4:
1238                 case 8:
1239                 case 9:
1240                 case 12:
1241                 case 13:
1242                 case 23:
1243                 case 25:
1244                 case 27:
1245                 case 30:
1246                         track->textures[i].cpp = 4;
1247                         break;
1248                 case 14:
1249                 case 26:
1250                 case 28:
1251                         track->textures[i].cpp = 8;
1252                         break;
1253                 case 29:
1254                         track->textures[i].cpp = 16;
1255                         break;
1256                 default:
1257                         DRM_ERROR("Invalid texture format %u\n",
1258                                   (ib_chunk->kdata[idx] & 0x1F));
1259                         return -EINVAL;
1260                         break;
1261                 }
1262                 break;
1263         case 0x4400:
1264         case 0x4404:
1265         case 0x4408:
1266         case 0x440C:
1267         case 0x4410:
1268         case 0x4414:
1269         case 0x4418:
1270         case 0x441C:
1271         case 0x4420:
1272         case 0x4424:
1273         case 0x4428:
1274         case 0x442C:
1275         case 0x4430:
1276         case 0x4434:
1277         case 0x4438:
1278         case 0x443C:
1279                 /* TX_FILTER0_[0-15] */
1280                 i = (reg - 0x4400) >> 2;
1281                 tmp = ib_chunk->kdata[idx] & 0x7;;
1282                 if (tmp == 2 || tmp == 4 || tmp == 6) {
1283                         track->textures[i].roundup_w = false;
1284                 }
1285                 tmp = (ib_chunk->kdata[idx] >> 3) & 0x7;;
1286                 if (tmp == 2 || tmp == 4 || tmp == 6) {
1287                         track->textures[i].roundup_h = false;
1288                 }
1289                 break;
1290         case 0x4500:
1291         case 0x4504:
1292         case 0x4508:
1293         case 0x450C:
1294         case 0x4510:
1295         case 0x4514:
1296         case 0x4518:
1297         case 0x451C:
1298         case 0x4520:
1299         case 0x4524:
1300         case 0x4528:
1301         case 0x452C:
1302         case 0x4530:
1303         case 0x4534:
1304         case 0x4538:
1305         case 0x453C:
1306                 /* TX_FORMAT2_[0-15] */
1307                 i = (reg - 0x4500) >> 2;
1308                 tmp = ib_chunk->kdata[idx] & 0x3FFF;
1309                 track->textures[i].pitch = tmp + 1;
1310                 if (p->rdev->family >= CHIP_RV515) {
1311                         tmp = ((ib_chunk->kdata[idx] >> 15) & 1) << 11;
1312                         track->textures[i].width_11 = tmp;
1313                         tmp = ((ib_chunk->kdata[idx] >> 16) & 1) << 11;
1314                         track->textures[i].height_11 = tmp;
1315                 }
1316                 break;
1317         case 0x4480:
1318         case 0x4484:
1319         case 0x4488:
1320         case 0x448C:
1321         case 0x4490:
1322         case 0x4494:
1323         case 0x4498:
1324         case 0x449C:
1325         case 0x44A0:
1326         case 0x44A4:
1327         case 0x44A8:
1328         case 0x44AC:
1329         case 0x44B0:
1330         case 0x44B4:
1331         case 0x44B8:
1332         case 0x44BC:
1333                 /* TX_FORMAT0_[0-15] */
1334                 i = (reg - 0x4480) >> 2;
1335                 tmp = ib_chunk->kdata[idx] & 0x7FF;
1336                 track->textures[i].width = tmp + 1;
1337                 tmp = (ib_chunk->kdata[idx] >> 11) & 0x7FF;
1338                 track->textures[i].height = tmp + 1;
1339                 tmp = (ib_chunk->kdata[idx] >> 26) & 0xF;
1340                 track->textures[i].num_levels = tmp;
1341                 tmp = ib_chunk->kdata[idx] & (1 << 31);
1342                 track->textures[i].use_pitch = !!tmp;
1343                 tmp = (ib_chunk->kdata[idx] >> 22) & 0xF;
1344                 track->textures[i].txdepth = tmp;
1345                 break;
1346         case R300_ZB_ZPASS_ADDR:
1347                 r = r100_cs_packet_next_reloc(p, &reloc);
1348                 if (r) {
1349                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1350                                         idx, reg);
1351                         r100_cs_dump_packet(p, pkt);
1352                         return r;
1353                 }
1354                 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
1355                 break;
1356         case 0x4be8:
1357                 /* valid register only on RV530 */
1358                 if (p->rdev->family == CHIP_RV530)
1359                         break;
1360                 /* fallthrough do not move */
1361         default:
1362                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1363                        reg, idx);
1364                 return -EINVAL;
1365         }
1366         return 0;
1367 }
1368
1369 static int r300_packet3_check(struct radeon_cs_parser *p,
1370                               struct radeon_cs_packet *pkt)
1371 {
1372         struct radeon_cs_chunk *ib_chunk;
1373         struct radeon_cs_reloc *reloc;
1374         struct r300_cs_track *track;
1375         volatile uint32_t *ib;
1376         unsigned idx;
1377         unsigned i, c;
1378         int r;
1379
1380         ib = p->ib->ptr;
1381         ib_chunk = &p->chunks[p->chunk_ib_idx];
1382         idx = pkt->idx + 1;
1383         track = (struct r300_cs_track*)p->track;
1384         switch(pkt->opcode) {
1385         case PACKET3_3D_LOAD_VBPNTR:
1386                 c = ib_chunk->kdata[idx++] & 0x1F;
1387                 track->num_arrays = c;
1388                 for (i = 0; i < (c - 1); i+=2, idx+=3) {
1389                         r = r100_cs_packet_next_reloc(p, &reloc);
1390                         if (r) {
1391                                 DRM_ERROR("No reloc for packet3 %d\n",
1392                                           pkt->opcode);
1393                                 r100_cs_dump_packet(p, pkt);
1394                                 return r;
1395                         }
1396                         ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
1397                         track->arrays[i + 0].robj = reloc->robj;
1398                         track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8;
1399                         track->arrays[i + 0].esize &= 0x7F;
1400                         r = r100_cs_packet_next_reloc(p, &reloc);
1401                         if (r) {
1402                                 DRM_ERROR("No reloc for packet3 %d\n",
1403                                           pkt->opcode);
1404                                 r100_cs_dump_packet(p, pkt);
1405                                 return r;
1406                         }
1407                         ib[idx+2] = ib_chunk->kdata[idx+2] + ((u32)reloc->lobj.gpu_offset);
1408                         track->arrays[i + 1].robj = reloc->robj;
1409                         track->arrays[i + 1].esize = ib_chunk->kdata[idx] >> 24;
1410                         track->arrays[i + 1].esize &= 0x7F;
1411                 }
1412                 if (c & 1) {
1413                         r = r100_cs_packet_next_reloc(p, &reloc);
1414                         if (r) {
1415                                 DRM_ERROR("No reloc for packet3 %d\n",
1416                                           pkt->opcode);
1417                                 r100_cs_dump_packet(p, pkt);
1418                                 return r;
1419                         }
1420                         ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
1421                         track->arrays[i + 0].robj = reloc->robj;
1422                         track->arrays[i + 0].esize = ib_chunk->kdata[idx] >> 8;
1423                         track->arrays[i + 0].esize &= 0x7F;
1424                 }
1425                 break;
1426         case PACKET3_INDX_BUFFER:
1427                 r = r100_cs_packet_next_reloc(p, &reloc);
1428                 if (r) {
1429                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1430                         r100_cs_dump_packet(p, pkt);
1431                         return r;
1432                 }
1433                 ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
1434                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1435                 if (r) {
1436                         return r;
1437                 }
1438                 break;
1439         /* Draw packet */
1440         case PACKET3_3D_DRAW_IMMD:
1441                 /* Number of dwords is vtx_size * (num_vertices - 1)
1442                  * PRIM_WALK must be equal to 3 vertex data in embedded
1443                  * in cmd stream */
1444                 if (((ib_chunk->kdata[idx+1] >> 4) & 0x3) != 3) {
1445                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1446                         return -EINVAL;
1447                 }
1448                 track->vap_vf_cntl = ib_chunk->kdata[idx+1];
1449                 track->immd_dwords = pkt->count - 1;
1450                 r = r300_cs_track_check(p->rdev, track);
1451                 if (r) {
1452                         return r;
1453                 }
1454                 break;
1455         case PACKET3_3D_DRAW_IMMD_2:
1456                 /* Number of dwords is vtx_size * (num_vertices - 1)
1457                  * PRIM_WALK must be equal to 3 vertex data in embedded
1458                  * in cmd stream */
1459                 if (((ib_chunk->kdata[idx] >> 4) & 0x3) != 3) {
1460                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1461                         return -EINVAL;
1462                 }
1463                 track->vap_vf_cntl = ib_chunk->kdata[idx];
1464                 track->immd_dwords = pkt->count;
1465                 r = r300_cs_track_check(p->rdev, track);
1466                 if (r) {
1467                         return r;
1468                 }
1469                 break;
1470         case PACKET3_3D_DRAW_VBUF:
1471                 track->vap_vf_cntl = ib_chunk->kdata[idx + 1];
1472                 r = r300_cs_track_check(p->rdev, track);
1473                 if (r) {
1474                         return r;
1475                 }
1476                 break;
1477         case PACKET3_3D_DRAW_VBUF_2:
1478                 track->vap_vf_cntl = ib_chunk->kdata[idx];
1479                 r = r300_cs_track_check(p->rdev, track);
1480                 if (r) {
1481                         return r;
1482                 }
1483                 break;
1484         case PACKET3_3D_DRAW_INDX:
1485                 track->vap_vf_cntl = ib_chunk->kdata[idx + 1];
1486                 r = r300_cs_track_check(p->rdev, track);
1487                 if (r) {
1488                         return r;
1489                 }
1490                 break;
1491         case PACKET3_3D_DRAW_INDX_2:
1492                 track->vap_vf_cntl = ib_chunk->kdata[idx];
1493                 r = r300_cs_track_check(p->rdev, track);
1494                 if (r) {
1495                         return r;
1496                 }
1497                 break;
1498         case PACKET3_NOP:
1499                 break;
1500         default:
1501                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1502                 return -EINVAL;
1503         }
1504         return 0;
1505 }
1506
1507 int r300_cs_parse(struct radeon_cs_parser *p)
1508 {
1509         struct radeon_cs_packet pkt;
1510         struct r300_cs_track track;
1511         int r;
1512
1513         r300_cs_track_clear(&track);
1514         p->track = &track;
1515         do {
1516                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1517                 if (r) {
1518                         return r;
1519                 }
1520                 p->idx += pkt.count + 2;
1521                 switch (pkt.type) {
1522                 case PACKET_TYPE0:
1523                         r = r100_cs_parse_packet0(p, &pkt,
1524                                                   p->rdev->config.r300.reg_safe_bm,
1525                                                   p->rdev->config.r300.reg_safe_bm_size,
1526                                                   &r300_packet0_check);
1527                         break;
1528                 case PACKET_TYPE2:
1529                         break;
1530                 case PACKET_TYPE3:
1531                         r = r300_packet3_check(p, &pkt);
1532                         break;
1533                 default:
1534                         DRM_ERROR("Unknown packet type %d !\n", pkt.type);
1535                         return -EINVAL;
1536                 }
1537                 if (r) {
1538                         return r;
1539                 }
1540         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1541         return 0;
1542 }
1543
1544 int r300_init(struct radeon_device *rdev)
1545 {
1546         rdev->config.r300.reg_safe_bm = r300_reg_safe_bm;
1547         rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(r300_reg_safe_bm);
1548         return 0;
1549 }