drm/radeon/kms: respect TOM on rs100->rs480 IGP variants.
[linux-2.6.git] / drivers / gpu / drm / radeon / r100.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/seq_file.h>
29 #include "drmP.h"
30 #include "drm.h"
31 #include "radeon_drm.h"
32 #include "radeon_microcode.h"
33 #include "radeon_reg.h"
34 #include "radeon.h"
35
36 /* This files gather functions specifics to:
37  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
38  *
39  * Some of these functions might be used by newer ASICs.
40  */
41 void r100_hdp_reset(struct radeon_device *rdev);
42 void r100_gpu_init(struct radeon_device *rdev);
43 int r100_gui_wait_for_idle(struct radeon_device *rdev);
44 int r100_mc_wait_for_idle(struct radeon_device *rdev);
45 void r100_gpu_wait_for_vsync(struct radeon_device *rdev);
46 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev);
47 int r100_debugfs_mc_info_init(struct radeon_device *rdev);
48
49
50 /*
51  * PCI GART
52  */
53 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
54 {
55         /* TODO: can we do somethings here ? */
56         /* It seems hw only cache one entry so we should discard this
57          * entry otherwise if first GPU GART read hit this entry it
58          * could end up in wrong address. */
59 }
60
61 int r100_pci_gart_enable(struct radeon_device *rdev)
62 {
63         uint32_t tmp;
64         int r;
65
66         /* Initialize common gart structure */
67         r = radeon_gart_init(rdev);
68         if (r) {
69                 return r;
70         }
71         if (rdev->gart.table.ram.ptr == NULL) {
72                 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
73                 r = radeon_gart_table_ram_alloc(rdev);
74                 if (r) {
75                         return r;
76                 }
77         }
78         /* discard memory request outside of configured range */
79         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
80         WREG32(RADEON_AIC_CNTL, tmp);
81         /* set address range for PCI address translate */
82         WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location);
83         tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
84         WREG32(RADEON_AIC_HI_ADDR, tmp);
85         /* Enable bus mastering */
86         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
87         WREG32(RADEON_BUS_CNTL, tmp);
88         /* set PCI GART page-table base address */
89         WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
90         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
91         WREG32(RADEON_AIC_CNTL, tmp);
92         r100_pci_gart_tlb_flush(rdev);
93         rdev->gart.ready = true;
94         return 0;
95 }
96
97 void r100_pci_gart_disable(struct radeon_device *rdev)
98 {
99         uint32_t tmp;
100
101         /* discard memory request outside of configured range */
102         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
103         WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
104         WREG32(RADEON_AIC_LO_ADDR, 0);
105         WREG32(RADEON_AIC_HI_ADDR, 0);
106 }
107
108 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
109 {
110         if (i < 0 || i > rdev->gart.num_gpu_pages) {
111                 return -EINVAL;
112         }
113         rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
114         return 0;
115 }
116
117 int r100_gart_enable(struct radeon_device *rdev)
118 {
119         if (rdev->flags & RADEON_IS_AGP) {
120                 r100_pci_gart_disable(rdev);
121                 return 0;
122         }
123         return r100_pci_gart_enable(rdev);
124 }
125
126
127 /*
128  * MC
129  */
130 void r100_mc_disable_clients(struct radeon_device *rdev)
131 {
132         uint32_t ov0_scale_cntl, crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl;
133
134         /* FIXME: is this function correct for rs100,rs200,rs300 ? */
135         if (r100_gui_wait_for_idle(rdev)) {
136                 printk(KERN_WARNING "Failed to wait GUI idle while "
137                        "programming pipes. Bad things might happen.\n");
138         }
139
140         /* stop display and memory access */
141         ov0_scale_cntl = RREG32(RADEON_OV0_SCALE_CNTL);
142         WREG32(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl & ~RADEON_SCALER_ENABLE);
143         crtc_ext_cntl = RREG32(RADEON_CRTC_EXT_CNTL);
144         WREG32(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl | RADEON_CRTC_DISPLAY_DIS);
145         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
146
147         r100_gpu_wait_for_vsync(rdev);
148
149         WREG32(RADEON_CRTC_GEN_CNTL,
150                (crtc_gen_cntl & ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_ICON_EN)) |
151                RADEON_CRTC_DISP_REQ_EN_B | RADEON_CRTC_EXT_DISP_EN);
152
153         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
154                 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
155
156                 r100_gpu_wait_for_vsync2(rdev);
157                 WREG32(RADEON_CRTC2_GEN_CNTL,
158                        (crtc2_gen_cntl &
159                         ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_ICON_EN)) |
160                        RADEON_CRTC2_DISP_REQ_EN_B);
161         }
162
163         udelay(500);
164 }
165
166 void r100_mc_setup(struct radeon_device *rdev)
167 {
168         uint32_t tmp;
169         int r;
170
171         r = r100_debugfs_mc_info_init(rdev);
172         if (r) {
173                 DRM_ERROR("Failed to register debugfs file for R100 MC !\n");
174         }
175         /* Write VRAM size in case we are limiting it */
176         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
177         tmp = rdev->mc.vram_location + rdev->mc.vram_size - 1;
178         tmp = REG_SET(RADEON_MC_FB_TOP, tmp >> 16);
179         tmp |= REG_SET(RADEON_MC_FB_START, rdev->mc.vram_location >> 16);
180         WREG32(RADEON_MC_FB_LOCATION, tmp);
181
182         /* Enable bus mastering */
183         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
184         WREG32(RADEON_BUS_CNTL, tmp);
185
186         if (rdev->flags & RADEON_IS_AGP) {
187                 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
188                 tmp = REG_SET(RADEON_MC_AGP_TOP, tmp >> 16);
189                 tmp |= REG_SET(RADEON_MC_AGP_START, rdev->mc.gtt_location >> 16);
190                 WREG32(RADEON_MC_AGP_LOCATION, tmp);
191                 WREG32(RADEON_AGP_BASE, rdev->mc.agp_base);
192         } else {
193                 WREG32(RADEON_MC_AGP_LOCATION, 0x0FFFFFFF);
194                 WREG32(RADEON_AGP_BASE, 0);
195         }
196
197         tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
198         tmp |= (7 << 28);
199         WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
200         (void)RREG32(RADEON_HOST_PATH_CNTL);
201         WREG32(RADEON_HOST_PATH_CNTL, tmp);
202         (void)RREG32(RADEON_HOST_PATH_CNTL);
203 }
204
205 int r100_mc_init(struct radeon_device *rdev)
206 {
207         int r;
208
209         if (r100_debugfs_rbbm_init(rdev)) {
210                 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
211         }
212
213         r100_gpu_init(rdev);
214         /* Disable gart which also disable out of gart access */
215         r100_pci_gart_disable(rdev);
216
217         /* Setup GPU memory space */
218         rdev->mc.gtt_location = 0xFFFFFFFFUL;
219         if (rdev->flags & RADEON_IS_AGP) {
220                 r = radeon_agp_init(rdev);
221                 if (r) {
222                         printk(KERN_WARNING "[drm] Disabling AGP\n");
223                         rdev->flags &= ~RADEON_IS_AGP;
224                         rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
225                 } else {
226                         rdev->mc.gtt_location = rdev->mc.agp_base;
227                 }
228         }
229         r = radeon_mc_setup(rdev);
230         if (r) {
231                 return r;
232         }
233
234         r100_mc_disable_clients(rdev);
235         if (r100_mc_wait_for_idle(rdev)) {
236                 printk(KERN_WARNING "Failed to wait MC idle while "
237                        "programming pipes. Bad things might happen.\n");
238         }
239
240         r100_mc_setup(rdev);
241         return 0;
242 }
243
244 void r100_mc_fini(struct radeon_device *rdev)
245 {
246         r100_pci_gart_disable(rdev);
247         radeon_gart_table_ram_free(rdev);
248         radeon_gart_fini(rdev);
249 }
250
251
252 /*
253  * Fence emission
254  */
255 void r100_fence_ring_emit(struct radeon_device *rdev,
256                           struct radeon_fence *fence)
257 {
258         /* Who ever call radeon_fence_emit should call ring_lock and ask
259          * for enough space (today caller are ib schedule and buffer move) */
260         /* Wait until IDLE & CLEAN */
261         radeon_ring_write(rdev, PACKET0(0x1720, 0));
262         radeon_ring_write(rdev, (1 << 16) | (1 << 17));
263         /* Emit fence sequence & fire IRQ */
264         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
265         radeon_ring_write(rdev, fence->seq);
266         radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
267         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
268 }
269
270
271 /*
272  * Writeback
273  */
274 int r100_wb_init(struct radeon_device *rdev)
275 {
276         int r;
277
278         if (rdev->wb.wb_obj == NULL) {
279                 r = radeon_object_create(rdev, NULL, 4096,
280                                          true,
281                                          RADEON_GEM_DOMAIN_GTT,
282                                          false, &rdev->wb.wb_obj);
283                 if (r) {
284                         DRM_ERROR("radeon: failed to create WB buffer (%d).\n", r);
285                         return r;
286                 }
287                 r = radeon_object_pin(rdev->wb.wb_obj,
288                                       RADEON_GEM_DOMAIN_GTT,
289                                       &rdev->wb.gpu_addr);
290                 if (r) {
291                         DRM_ERROR("radeon: failed to pin WB buffer (%d).\n", r);
292                         return r;
293                 }
294                 r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
295                 if (r) {
296                         DRM_ERROR("radeon: failed to map WB buffer (%d).\n", r);
297                         return r;
298                 }
299         }
300         WREG32(0x774, rdev->wb.gpu_addr);
301         WREG32(0x70C, rdev->wb.gpu_addr + 1024);
302         WREG32(0x770, 0xff);
303         return 0;
304 }
305
306 void r100_wb_fini(struct radeon_device *rdev)
307 {
308         if (rdev->wb.wb_obj) {
309                 radeon_object_kunmap(rdev->wb.wb_obj);
310                 radeon_object_unpin(rdev->wb.wb_obj);
311                 radeon_object_unref(&rdev->wb.wb_obj);
312                 rdev->wb.wb = NULL;
313                 rdev->wb.wb_obj = NULL;
314         }
315 }
316
317 int r100_copy_blit(struct radeon_device *rdev,
318                    uint64_t src_offset,
319                    uint64_t dst_offset,
320                    unsigned num_pages,
321                    struct radeon_fence *fence)
322 {
323         uint32_t cur_pages;
324         uint32_t stride_bytes = PAGE_SIZE;
325         uint32_t pitch;
326         uint32_t stride_pixels;
327         unsigned ndw;
328         int num_loops;
329         int r = 0;
330
331         /* radeon limited to 16k stride */
332         stride_bytes &= 0x3fff;
333         /* radeon pitch is /64 */
334         pitch = stride_bytes / 64;
335         stride_pixels = stride_bytes / 4;
336         num_loops = DIV_ROUND_UP(num_pages, 8191);
337
338         /* Ask for enough room for blit + flush + fence */
339         ndw = 64 + (10 * num_loops);
340         r = radeon_ring_lock(rdev, ndw);
341         if (r) {
342                 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
343                 return -EINVAL;
344         }
345         while (num_pages > 0) {
346                 cur_pages = num_pages;
347                 if (cur_pages > 8191) {
348                         cur_pages = 8191;
349                 }
350                 num_pages -= cur_pages;
351
352                 /* pages are in Y direction - height
353                    page width in X direction - width */
354                 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
355                 radeon_ring_write(rdev,
356                                   RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
357                                   RADEON_GMC_DST_PITCH_OFFSET_CNTL |
358                                   RADEON_GMC_SRC_CLIPPING |
359                                   RADEON_GMC_DST_CLIPPING |
360                                   RADEON_GMC_BRUSH_NONE |
361                                   (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
362                                   RADEON_GMC_SRC_DATATYPE_COLOR |
363                                   RADEON_ROP3_S |
364                                   RADEON_DP_SRC_SOURCE_MEMORY |
365                                   RADEON_GMC_CLR_CMP_CNTL_DIS |
366                                   RADEON_GMC_WR_MSK_DIS);
367                 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
368                 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
369                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
370                 radeon_ring_write(rdev, 0);
371                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
372                 radeon_ring_write(rdev, num_pages);
373                 radeon_ring_write(rdev, num_pages);
374                 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
375         }
376         radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
377         radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
378         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
379         radeon_ring_write(rdev,
380                           RADEON_WAIT_2D_IDLECLEAN |
381                           RADEON_WAIT_HOST_IDLECLEAN |
382                           RADEON_WAIT_DMA_GUI_IDLE);
383         if (fence) {
384                 r = radeon_fence_emit(rdev, fence);
385         }
386         radeon_ring_unlock_commit(rdev);
387         return r;
388 }
389
390
391 /*
392  * CP
393  */
394 void r100_ring_start(struct radeon_device *rdev)
395 {
396         int r;
397
398         r = radeon_ring_lock(rdev, 2);
399         if (r) {
400                 return;
401         }
402         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
403         radeon_ring_write(rdev,
404                           RADEON_ISYNC_ANY2D_IDLE3D |
405                           RADEON_ISYNC_ANY3D_IDLE2D |
406                           RADEON_ISYNC_WAIT_IDLEGUI |
407                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
408         radeon_ring_unlock_commit(rdev);
409 }
410
411 static void r100_cp_load_microcode(struct radeon_device *rdev)
412 {
413         int i;
414
415         if (r100_gui_wait_for_idle(rdev)) {
416                 printk(KERN_WARNING "Failed to wait GUI idle while "
417                        "programming pipes. Bad things might happen.\n");
418         }
419
420         WREG32(RADEON_CP_ME_RAM_ADDR, 0);
421         if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
422             (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
423             (rdev->family == CHIP_RS200)) {
424                 DRM_INFO("Loading R100 Microcode\n");
425                 for (i = 0; i < 256; i++) {
426                         WREG32(RADEON_CP_ME_RAM_DATAH, R100_cp_microcode[i][1]);
427                         WREG32(RADEON_CP_ME_RAM_DATAL, R100_cp_microcode[i][0]);
428                 }
429         } else if ((rdev->family == CHIP_R200) ||
430                    (rdev->family == CHIP_RV250) ||
431                    (rdev->family == CHIP_RV280) ||
432                    (rdev->family == CHIP_RS300)) {
433                 DRM_INFO("Loading R200 Microcode\n");
434                 for (i = 0; i < 256; i++) {
435                         WREG32(RADEON_CP_ME_RAM_DATAH, R200_cp_microcode[i][1]);
436                         WREG32(RADEON_CP_ME_RAM_DATAL, R200_cp_microcode[i][0]);
437                 }
438         } else if ((rdev->family == CHIP_R300) ||
439                    (rdev->family == CHIP_R350) ||
440                    (rdev->family == CHIP_RV350) ||
441                    (rdev->family == CHIP_RV380) ||
442                    (rdev->family == CHIP_RS400) ||
443                    (rdev->family == CHIP_RS480)) {
444                 DRM_INFO("Loading R300 Microcode\n");
445                 for (i = 0; i < 256; i++) {
446                         WREG32(RADEON_CP_ME_RAM_DATAH, R300_cp_microcode[i][1]);
447                         WREG32(RADEON_CP_ME_RAM_DATAL, R300_cp_microcode[i][0]);
448                 }
449         } else if ((rdev->family == CHIP_R420) ||
450                    (rdev->family == CHIP_R423) ||
451                    (rdev->family == CHIP_RV410)) {
452                 DRM_INFO("Loading R400 Microcode\n");
453                 for (i = 0; i < 256; i++) {
454                         WREG32(RADEON_CP_ME_RAM_DATAH, R420_cp_microcode[i][1]);
455                         WREG32(RADEON_CP_ME_RAM_DATAL, R420_cp_microcode[i][0]);
456                 }
457         } else if ((rdev->family == CHIP_RS690) ||
458                    (rdev->family == CHIP_RS740)) {
459                 DRM_INFO("Loading RS690/RS740 Microcode\n");
460                 for (i = 0; i < 256; i++) {
461                         WREG32(RADEON_CP_ME_RAM_DATAH, RS690_cp_microcode[i][1]);
462                         WREG32(RADEON_CP_ME_RAM_DATAL, RS690_cp_microcode[i][0]);
463                 }
464         } else if (rdev->family == CHIP_RS600) {
465                 DRM_INFO("Loading RS600 Microcode\n");
466                 for (i = 0; i < 256; i++) {
467                         WREG32(RADEON_CP_ME_RAM_DATAH, RS600_cp_microcode[i][1]);
468                         WREG32(RADEON_CP_ME_RAM_DATAL, RS600_cp_microcode[i][0]);
469                 }
470         } else if ((rdev->family == CHIP_RV515) ||
471                    (rdev->family == CHIP_R520) ||
472                    (rdev->family == CHIP_RV530) ||
473                    (rdev->family == CHIP_R580) ||
474                    (rdev->family == CHIP_RV560) ||
475                    (rdev->family == CHIP_RV570)) {
476                 DRM_INFO("Loading R500 Microcode\n");
477                 for (i = 0; i < 256; i++) {
478                         WREG32(RADEON_CP_ME_RAM_DATAH, R520_cp_microcode[i][1]);
479                         WREG32(RADEON_CP_ME_RAM_DATAL, R520_cp_microcode[i][0]);
480                 }
481         }
482 }
483
484 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
485 {
486         unsigned rb_bufsz;
487         unsigned rb_blksz;
488         unsigned max_fetch;
489         unsigned pre_write_timer;
490         unsigned pre_write_limit;
491         unsigned indirect2_start;
492         unsigned indirect1_start;
493         uint32_t tmp;
494         int r;
495
496         if (r100_debugfs_cp_init(rdev)) {
497                 DRM_ERROR("Failed to register debugfs file for CP !\n");
498         }
499         /* Reset CP */
500         tmp = RREG32(RADEON_CP_CSQ_STAT);
501         if ((tmp & (1 << 31))) {
502                 DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
503                 WREG32(RADEON_CP_CSQ_MODE, 0);
504                 WREG32(RADEON_CP_CSQ_CNTL, 0);
505                 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
506                 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
507                 mdelay(2);
508                 WREG32(RADEON_RBBM_SOFT_RESET, 0);
509                 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
510                 mdelay(2);
511                 tmp = RREG32(RADEON_CP_CSQ_STAT);
512                 if ((tmp & (1 << 31))) {
513                         DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp);
514                 }
515         } else {
516                 DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
517         }
518         /* Align ring size */
519         rb_bufsz = drm_order(ring_size / 8);
520         ring_size = (1 << (rb_bufsz + 1)) * 4;
521         r100_cp_load_microcode(rdev);
522         r = radeon_ring_init(rdev, ring_size);
523         if (r) {
524                 return r;
525         }
526         /* Each time the cp read 1024 bytes (16 dword/quadword) update
527          * the rptr copy in system ram */
528         rb_blksz = 9;
529         /* cp will read 128bytes at a time (4 dwords) */
530         max_fetch = 1;
531         rdev->cp.align_mask = 16 - 1;
532         /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
533         pre_write_timer = 64;
534         /* Force CP_RB_WPTR write if written more than one time before the
535          * delay expire
536          */
537         pre_write_limit = 0;
538         /* Setup the cp cache like this (cache size is 96 dwords) :
539          *      RING            0  to 15
540          *      INDIRECT1       16 to 79
541          *      INDIRECT2       80 to 95
542          * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
543          *    indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
544          *    indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
545          * Idea being that most of the gpu cmd will be through indirect1 buffer
546          * so it gets the bigger cache.
547          */
548         indirect2_start = 80;
549         indirect1_start = 16;
550         /* cp setup */
551         WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
552         WREG32(RADEON_CP_RB_CNTL,
553 #ifdef __BIG_ENDIAN
554                RADEON_BUF_SWAP_32BIT |
555 #endif
556                REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
557                REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
558                REG_SET(RADEON_MAX_FETCH, max_fetch) |
559                RADEON_RB_NO_UPDATE);
560         /* Set ring address */
561         DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
562         WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
563         /* Force read & write ptr to 0 */
564         tmp = RREG32(RADEON_CP_RB_CNTL);
565         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
566         WREG32(RADEON_CP_RB_RPTR_WR, 0);
567         WREG32(RADEON_CP_RB_WPTR, 0);
568         WREG32(RADEON_CP_RB_CNTL, tmp);
569         udelay(10);
570         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
571         rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
572         /* Set cp mode to bus mastering & enable cp*/
573         WREG32(RADEON_CP_CSQ_MODE,
574                REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
575                REG_SET(RADEON_INDIRECT1_START, indirect1_start));
576         WREG32(0x718, 0);
577         WREG32(0x744, 0x00004D4D);
578         WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
579         radeon_ring_start(rdev);
580         r = radeon_ring_test(rdev);
581         if (r) {
582                 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
583                 return r;
584         }
585         rdev->cp.ready = true;
586         return 0;
587 }
588
589 void r100_cp_fini(struct radeon_device *rdev)
590 {
591         /* Disable ring */
592         rdev->cp.ready = false;
593         WREG32(RADEON_CP_CSQ_CNTL, 0);
594         radeon_ring_fini(rdev);
595         DRM_INFO("radeon: cp finalized\n");
596 }
597
598 void r100_cp_disable(struct radeon_device *rdev)
599 {
600         /* Disable ring */
601         rdev->cp.ready = false;
602         WREG32(RADEON_CP_CSQ_MODE, 0);
603         WREG32(RADEON_CP_CSQ_CNTL, 0);
604         if (r100_gui_wait_for_idle(rdev)) {
605                 printk(KERN_WARNING "Failed to wait GUI idle while "
606                        "programming pipes. Bad things might happen.\n");
607         }
608 }
609
610 int r100_cp_reset(struct radeon_device *rdev)
611 {
612         uint32_t tmp;
613         bool reinit_cp;
614         int i;
615
616         reinit_cp = rdev->cp.ready;
617         rdev->cp.ready = false;
618         WREG32(RADEON_CP_CSQ_MODE, 0);
619         WREG32(RADEON_CP_CSQ_CNTL, 0);
620         WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
621         (void)RREG32(RADEON_RBBM_SOFT_RESET);
622         udelay(200);
623         WREG32(RADEON_RBBM_SOFT_RESET, 0);
624         /* Wait to prevent race in RBBM_STATUS */
625         mdelay(1);
626         for (i = 0; i < rdev->usec_timeout; i++) {
627                 tmp = RREG32(RADEON_RBBM_STATUS);
628                 if (!(tmp & (1 << 16))) {
629                         DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
630                                  tmp);
631                         if (reinit_cp) {
632                                 return r100_cp_init(rdev, rdev->cp.ring_size);
633                         }
634                         return 0;
635                 }
636                 DRM_UDELAY(1);
637         }
638         tmp = RREG32(RADEON_RBBM_STATUS);
639         DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp);
640         return -1;
641 }
642
643
644 /*
645  * CS functions
646  */
647 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
648                           struct radeon_cs_packet *pkt,
649                           const unsigned *auth, unsigned n,
650                           radeon_packet0_check_t check)
651 {
652         unsigned reg;
653         unsigned i, j, m;
654         unsigned idx;
655         int r;
656
657         idx = pkt->idx + 1;
658         reg = pkt->reg;
659         /* Check that register fall into register range
660          * determined by the number of entry (n) in the
661          * safe register bitmap.
662          */
663         if (pkt->one_reg_wr) {
664                 if ((reg >> 7) > n) {
665                         return -EINVAL;
666                 }
667         } else {
668                 if (((reg + (pkt->count << 2)) >> 7) > n) {
669                         return -EINVAL;
670                 }
671         }
672         for (i = 0; i <= pkt->count; i++, idx++) {
673                 j = (reg >> 7);
674                 m = 1 << ((reg >> 2) & 31);
675                 if (auth[j] & m) {
676                         r = check(p, pkt, idx, reg);
677                         if (r) {
678                                 return r;
679                         }
680                 }
681                 if (pkt->one_reg_wr) {
682                         if (!(auth[j] & m)) {
683                                 break;
684                         }
685                 } else {
686                         reg += 4;
687                 }
688         }
689         return 0;
690 }
691
692 void r100_cs_dump_packet(struct radeon_cs_parser *p,
693                          struct radeon_cs_packet *pkt)
694 {
695         struct radeon_cs_chunk *ib_chunk;
696         volatile uint32_t *ib;
697         unsigned i;
698         unsigned idx;
699
700         ib = p->ib->ptr;
701         ib_chunk = &p->chunks[p->chunk_ib_idx];
702         idx = pkt->idx;
703         for (i = 0; i <= (pkt->count + 1); i++, idx++) {
704                 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
705         }
706 }
707
708 /**
709  * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
710  * @parser:     parser structure holding parsing context.
711  * @pkt:        where to store packet informations
712  *
713  * Assume that chunk_ib_index is properly set. Will return -EINVAL
714  * if packet is bigger than remaining ib size. or if packets is unknown.
715  **/
716 int r100_cs_packet_parse(struct radeon_cs_parser *p,
717                          struct radeon_cs_packet *pkt,
718                          unsigned idx)
719 {
720         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
721         uint32_t header = ib_chunk->kdata[idx];
722
723         if (idx >= ib_chunk->length_dw) {
724                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
725                           idx, ib_chunk->length_dw);
726                 return -EINVAL;
727         }
728         pkt->idx = idx;
729         pkt->type = CP_PACKET_GET_TYPE(header);
730         pkt->count = CP_PACKET_GET_COUNT(header);
731         switch (pkt->type) {
732         case PACKET_TYPE0:
733                 pkt->reg = CP_PACKET0_GET_REG(header);
734                 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
735                 break;
736         case PACKET_TYPE3:
737                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
738                 break;
739         case PACKET_TYPE2:
740                 pkt->count = -1;
741                 break;
742         default:
743                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
744                 return -EINVAL;
745         }
746         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
747                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
748                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
749                 return -EINVAL;
750         }
751         return 0;
752 }
753
754 /**
755  * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
756  * @parser:             parser structure holding parsing context.
757  * @data:               pointer to relocation data
758  * @offset_start:       starting offset
759  * @offset_mask:        offset mask (to align start offset on)
760  * @reloc:              reloc informations
761  *
762  * Check next packet is relocation packet3, do bo validation and compute
763  * GPU offset using the provided start.
764  **/
765 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
766                               struct radeon_cs_reloc **cs_reloc)
767 {
768         struct radeon_cs_chunk *ib_chunk;
769         struct radeon_cs_chunk *relocs_chunk;
770         struct radeon_cs_packet p3reloc;
771         unsigned idx;
772         int r;
773
774         if (p->chunk_relocs_idx == -1) {
775                 DRM_ERROR("No relocation chunk !\n");
776                 return -EINVAL;
777         }
778         *cs_reloc = NULL;
779         ib_chunk = &p->chunks[p->chunk_ib_idx];
780         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
781         r = r100_cs_packet_parse(p, &p3reloc, p->idx);
782         if (r) {
783                 return r;
784         }
785         p->idx += p3reloc.count + 2;
786         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
787                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
788                           p3reloc.idx);
789                 r100_cs_dump_packet(p, &p3reloc);
790                 return -EINVAL;
791         }
792         idx = ib_chunk->kdata[p3reloc.idx + 1];
793         if (idx >= relocs_chunk->length_dw) {
794                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
795                           idx, relocs_chunk->length_dw);
796                 r100_cs_dump_packet(p, &p3reloc);
797                 return -EINVAL;
798         }
799         /* FIXME: we assume reloc size is 4 dwords */
800         *cs_reloc = p->relocs_ptr[(idx / 4)];
801         return 0;
802 }
803
804 static int r100_packet0_check(struct radeon_cs_parser *p,
805                               struct radeon_cs_packet *pkt)
806 {
807         struct radeon_cs_chunk *ib_chunk;
808         struct radeon_cs_reloc *reloc;
809         volatile uint32_t *ib;
810         uint32_t tmp;
811         unsigned reg;
812         unsigned i;
813         unsigned idx;
814         bool onereg;
815         int r;
816
817         ib = p->ib->ptr;
818         ib_chunk = &p->chunks[p->chunk_ib_idx];
819         idx = pkt->idx + 1;
820         reg = pkt->reg;
821         onereg = false;
822         if (CP_PACKET0_GET_ONE_REG_WR(ib_chunk->kdata[pkt->idx])) {
823                 onereg = true;
824         }
825         for (i = 0; i <= pkt->count; i++, idx++, reg += 4) {
826                 switch (reg) {
827                 /* FIXME: only allow PACKET3 blit? easier to check for out of
828                  * range access */
829                 case RADEON_DST_PITCH_OFFSET:
830                 case RADEON_SRC_PITCH_OFFSET:
831                         r = r100_cs_packet_next_reloc(p, &reloc);
832                         if (r) {
833                                 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
834                                           idx, reg);
835                                 r100_cs_dump_packet(p, pkt);
836                                 return r;
837                         }
838                         tmp = ib_chunk->kdata[idx] & 0x003fffff;
839                         tmp += (((u32)reloc->lobj.gpu_offset) >> 10);
840                         ib[idx] = (ib_chunk->kdata[idx] & 0xffc00000) | tmp;
841                         break;
842                 case RADEON_RB3D_DEPTHOFFSET:
843                 case RADEON_RB3D_COLOROFFSET:
844                 case R300_RB3D_COLOROFFSET0:
845                 case R300_ZB_DEPTHOFFSET:
846                 case R200_PP_TXOFFSET_0:
847                 case R200_PP_TXOFFSET_1:
848                 case R200_PP_TXOFFSET_2:
849                 case R200_PP_TXOFFSET_3:
850                 case R200_PP_TXOFFSET_4:
851                 case R200_PP_TXOFFSET_5:
852                 case RADEON_PP_TXOFFSET_0:
853                 case RADEON_PP_TXOFFSET_1:
854                 case RADEON_PP_TXOFFSET_2:
855                 case R300_TX_OFFSET_0:
856                 case R300_TX_OFFSET_0+4:
857                 case R300_TX_OFFSET_0+8:
858                 case R300_TX_OFFSET_0+12:
859                 case R300_TX_OFFSET_0+16:
860                 case R300_TX_OFFSET_0+20:
861                 case R300_TX_OFFSET_0+24:
862                 case R300_TX_OFFSET_0+28:
863                 case R300_TX_OFFSET_0+32:
864                 case R300_TX_OFFSET_0+36:
865                 case R300_TX_OFFSET_0+40:
866                 case R300_TX_OFFSET_0+44:
867                 case R300_TX_OFFSET_0+48:
868                 case R300_TX_OFFSET_0+52:
869                 case R300_TX_OFFSET_0+56:
870                 case R300_TX_OFFSET_0+60:
871                         r = r100_cs_packet_next_reloc(p, &reloc);
872                         if (r) {
873                                 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
874                                           idx, reg);
875                                 r100_cs_dump_packet(p, pkt);
876                                 return r;
877                         }
878                         ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
879                         break;
880                 default:
881                         /* FIXME: we don't want to allow anyothers packet */
882                         break;
883                 }
884                 if (onereg) {
885                         /* FIXME: forbid onereg write to register on relocate */
886                         break;
887                 }
888         }
889         return 0;
890 }
891
892 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
893                                          struct radeon_cs_packet *pkt,
894                                          struct radeon_object *robj)
895 {
896         struct radeon_cs_chunk *ib_chunk;
897         unsigned idx;
898
899         ib_chunk = &p->chunks[p->chunk_ib_idx];
900         idx = pkt->idx + 1;
901         if ((ib_chunk->kdata[idx+2] + 1) > radeon_object_size(robj)) {
902                 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
903                           "(need %u have %lu) !\n",
904                           ib_chunk->kdata[idx+2] + 1,
905                           radeon_object_size(robj));
906                 return -EINVAL;
907         }
908         return 0;
909 }
910
911 static int r100_packet3_check(struct radeon_cs_parser *p,
912                               struct radeon_cs_packet *pkt)
913 {
914         struct radeon_cs_chunk *ib_chunk;
915         struct radeon_cs_reloc *reloc;
916         unsigned idx;
917         unsigned i, c;
918         volatile uint32_t *ib;
919         int r;
920
921         ib = p->ib->ptr;
922         ib_chunk = &p->chunks[p->chunk_ib_idx];
923         idx = pkt->idx + 1;
924         switch (pkt->opcode) {
925         case PACKET3_3D_LOAD_VBPNTR:
926                 c = ib_chunk->kdata[idx++];
927                 for (i = 0; i < (c - 1); i += 2, idx += 3) {
928                         r = r100_cs_packet_next_reloc(p, &reloc);
929                         if (r) {
930                                 DRM_ERROR("No reloc for packet3 %d\n",
931                                           pkt->opcode);
932                                 r100_cs_dump_packet(p, pkt);
933                                 return r;
934                         }
935                         ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
936                         r = r100_cs_packet_next_reloc(p, &reloc);
937                         if (r) {
938                                 DRM_ERROR("No reloc for packet3 %d\n",
939                                           pkt->opcode);
940                                 r100_cs_dump_packet(p, pkt);
941                                 return r;
942                         }
943                         ib[idx+2] = ib_chunk->kdata[idx+2] + ((u32)reloc->lobj.gpu_offset);
944                 }
945                 if (c & 1) {
946                         r = r100_cs_packet_next_reloc(p, &reloc);
947                         if (r) {
948                                 DRM_ERROR("No reloc for packet3 %d\n",
949                                           pkt->opcode);
950                                 r100_cs_dump_packet(p, pkt);
951                                 return r;
952                         }
953                         ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
954                 }
955                 break;
956         case PACKET3_INDX_BUFFER:
957                 r = r100_cs_packet_next_reloc(p, &reloc);
958                 if (r) {
959                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
960                         r100_cs_dump_packet(p, pkt);
961                         return r;
962                 }
963                 ib[idx+1] = ib_chunk->kdata[idx+1] + ((u32)reloc->lobj.gpu_offset);
964                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
965                 if (r) {
966                         return r;
967                 }
968                 break;
969         case 0x23:
970                 /* FIXME: cleanup */
971                 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
972                 r = r100_cs_packet_next_reloc(p, &reloc);
973                 if (r) {
974                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
975                         r100_cs_dump_packet(p, pkt);
976                         return r;
977                 }
978                 ib[idx] = ib_chunk->kdata[idx] + ((u32)reloc->lobj.gpu_offset);
979                 break;
980         case PACKET3_3D_DRAW_IMMD:
981                 /* triggers drawing using in-packet vertex data */
982         case PACKET3_3D_DRAW_IMMD_2:
983                 /* triggers drawing using in-packet vertex data */
984         case PACKET3_3D_DRAW_VBUF_2:
985                 /* triggers drawing of vertex buffers setup elsewhere */
986         case PACKET3_3D_DRAW_INDX_2:
987                 /* triggers drawing using indices to vertex buffer */
988         case PACKET3_3D_DRAW_VBUF:
989                 /* triggers drawing of vertex buffers setup elsewhere */
990         case PACKET3_3D_DRAW_INDX:
991                 /* triggers drawing using indices to vertex buffer */
992         case PACKET3_NOP:
993                 break;
994         default:
995                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
996                 return -EINVAL;
997         }
998         return 0;
999 }
1000
1001 int r100_cs_parse(struct radeon_cs_parser *p)
1002 {
1003         struct radeon_cs_packet pkt;
1004         int r;
1005
1006         do {
1007                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1008                 if (r) {
1009                         return r;
1010                 }
1011                 p->idx += pkt.count + 2;
1012                 switch (pkt.type) {
1013                         case PACKET_TYPE0:
1014                                 r = r100_packet0_check(p, &pkt);
1015                                 break;
1016                         case PACKET_TYPE2:
1017                                 break;
1018                         case PACKET_TYPE3:
1019                                 r = r100_packet3_check(p, &pkt);
1020                                 break;
1021                         default:
1022                                 DRM_ERROR("Unknown packet type %d !\n",
1023                                           pkt.type);
1024                                 return -EINVAL;
1025                 }
1026                 if (r) {
1027                         return r;
1028                 }
1029         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1030         return 0;
1031 }
1032
1033
1034 /*
1035  * Global GPU functions
1036  */
1037 void r100_errata(struct radeon_device *rdev)
1038 {
1039         rdev->pll_errata = 0;
1040
1041         if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1042                 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1043         }
1044
1045         if (rdev->family == CHIP_RV100 ||
1046             rdev->family == CHIP_RS100 ||
1047             rdev->family == CHIP_RS200) {
1048                 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1049         }
1050 }
1051
1052 /* Wait for vertical sync on primary CRTC */
1053 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1054 {
1055         uint32_t crtc_gen_cntl, tmp;
1056         int i;
1057
1058         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1059         if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1060             !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1061                 return;
1062         }
1063         /* Clear the CRTC_VBLANK_SAVE bit */
1064         WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1065         for (i = 0; i < rdev->usec_timeout; i++) {
1066                 tmp = RREG32(RADEON_CRTC_STATUS);
1067                 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1068                         return;
1069                 }
1070                 DRM_UDELAY(1);
1071         }
1072 }
1073
1074 /* Wait for vertical sync on secondary CRTC */
1075 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1076 {
1077         uint32_t crtc2_gen_cntl, tmp;
1078         int i;
1079
1080         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1081         if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1082             !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1083                 return;
1084
1085         /* Clear the CRTC_VBLANK_SAVE bit */
1086         WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1087         for (i = 0; i < rdev->usec_timeout; i++) {
1088                 tmp = RREG32(RADEON_CRTC2_STATUS);
1089                 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1090                         return;
1091                 }
1092                 DRM_UDELAY(1);
1093         }
1094 }
1095
1096 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1097 {
1098         unsigned i;
1099         uint32_t tmp;
1100
1101         for (i = 0; i < rdev->usec_timeout; i++) {
1102                 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1103                 if (tmp >= n) {
1104                         return 0;
1105                 }
1106                 DRM_UDELAY(1);
1107         }
1108         return -1;
1109 }
1110
1111 int r100_gui_wait_for_idle(struct radeon_device *rdev)
1112 {
1113         unsigned i;
1114         uint32_t tmp;
1115
1116         if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1117                 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1118                        " Bad things might happen.\n");
1119         }
1120         for (i = 0; i < rdev->usec_timeout; i++) {
1121                 tmp = RREG32(RADEON_RBBM_STATUS);
1122                 if (!(tmp & (1 << 31))) {
1123                         return 0;
1124                 }
1125                 DRM_UDELAY(1);
1126         }
1127         return -1;
1128 }
1129
1130 int r100_mc_wait_for_idle(struct radeon_device *rdev)
1131 {
1132         unsigned i;
1133         uint32_t tmp;
1134
1135         for (i = 0; i < rdev->usec_timeout; i++) {
1136                 /* read MC_STATUS */
1137                 tmp = RREG32(0x0150);
1138                 if (tmp & (1 << 2)) {
1139                         return 0;
1140                 }
1141                 DRM_UDELAY(1);
1142         }
1143         return -1;
1144 }
1145
1146 void r100_gpu_init(struct radeon_device *rdev)
1147 {
1148         /* TODO: anythings to do here ? pipes ? */
1149         r100_hdp_reset(rdev);
1150 }
1151
1152 void r100_hdp_reset(struct radeon_device *rdev)
1153 {
1154         uint32_t tmp;
1155
1156         tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
1157         tmp |= (7 << 28);
1158         WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
1159         (void)RREG32(RADEON_HOST_PATH_CNTL);
1160         udelay(200);
1161         WREG32(RADEON_RBBM_SOFT_RESET, 0);
1162         WREG32(RADEON_HOST_PATH_CNTL, tmp);
1163         (void)RREG32(RADEON_HOST_PATH_CNTL);
1164 }
1165
1166 int r100_rb2d_reset(struct radeon_device *rdev)
1167 {
1168         uint32_t tmp;
1169         int i;
1170
1171         WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2);
1172         (void)RREG32(RADEON_RBBM_SOFT_RESET);
1173         udelay(200);
1174         WREG32(RADEON_RBBM_SOFT_RESET, 0);
1175         /* Wait to prevent race in RBBM_STATUS */
1176         mdelay(1);
1177         for (i = 0; i < rdev->usec_timeout; i++) {
1178                 tmp = RREG32(RADEON_RBBM_STATUS);
1179                 if (!(tmp & (1 << 26))) {
1180                         DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
1181                                  tmp);
1182                         return 0;
1183                 }
1184                 DRM_UDELAY(1);
1185         }
1186         tmp = RREG32(RADEON_RBBM_STATUS);
1187         DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);
1188         return -1;
1189 }
1190
1191 int r100_gpu_reset(struct radeon_device *rdev)
1192 {
1193         uint32_t status;
1194
1195         /* reset order likely matter */
1196         status = RREG32(RADEON_RBBM_STATUS);
1197         /* reset HDP */
1198         r100_hdp_reset(rdev);
1199         /* reset rb2d */
1200         if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
1201                 r100_rb2d_reset(rdev);
1202         }
1203         /* TODO: reset 3D engine */
1204         /* reset CP */
1205         status = RREG32(RADEON_RBBM_STATUS);
1206         if (status & (1 << 16)) {
1207                 r100_cp_reset(rdev);
1208         }
1209         /* Check if GPU is idle */
1210         status = RREG32(RADEON_RBBM_STATUS);
1211         if (status & (1 << 31)) {
1212                 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
1213                 return -1;
1214         }
1215         DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
1216         return 0;
1217 }
1218
1219
1220 /*
1221  * VRAM info
1222  */
1223 static void r100_vram_get_type(struct radeon_device *rdev)
1224 {
1225         uint32_t tmp;
1226
1227         rdev->mc.vram_is_ddr = false;
1228         if (rdev->flags & RADEON_IS_IGP)
1229                 rdev->mc.vram_is_ddr = true;
1230         else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
1231                 rdev->mc.vram_is_ddr = true;
1232         if ((rdev->family == CHIP_RV100) ||
1233             (rdev->family == CHIP_RS100) ||
1234             (rdev->family == CHIP_RS200)) {
1235                 tmp = RREG32(RADEON_MEM_CNTL);
1236                 if (tmp & RV100_HALF_MODE) {
1237                         rdev->mc.vram_width = 32;
1238                 } else {
1239                         rdev->mc.vram_width = 64;
1240                 }
1241                 if (rdev->flags & RADEON_SINGLE_CRTC) {
1242                         rdev->mc.vram_width /= 4;
1243                         rdev->mc.vram_is_ddr = true;
1244                 }
1245         } else if (rdev->family <= CHIP_RV280) {
1246                 tmp = RREG32(RADEON_MEM_CNTL);
1247                 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
1248                         rdev->mc.vram_width = 128;
1249                 } else {
1250                         rdev->mc.vram_width = 64;
1251                 }
1252         } else {
1253                 /* newer IGPs */
1254                 rdev->mc.vram_width = 128;
1255         }
1256 }
1257
1258 void r100_vram_info(struct radeon_device *rdev)
1259 {
1260         r100_vram_get_type(rdev);
1261
1262         if (rdev->flags & RADEON_IS_IGP) {
1263                 uint32_t tom;
1264                 /* read NB_TOM to get the amount of ram stolen for the GPU */
1265                 tom = RREG32(RADEON_NB_TOM);
1266                 rdev->mc.vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
1267                 /* for IGPs we need to keep VRAM where it was put by the BIOS */
1268                 rdev->mc.vram_location = (tom & 0xffff) << 16;
1269                 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
1270         } else {
1271                 rdev->mc.vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
1272                 /* Some production boards of m6 will report 0
1273                  * if it's 8 MB
1274                  */
1275                 if (rdev->mc.vram_size == 0) {
1276                         rdev->mc.vram_size = 8192 * 1024;
1277                         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.vram_size);
1278                 }
1279                 /* let driver place VRAM */
1280                 rdev->mc.vram_location = 0xFFFFFFFFUL;
1281         }
1282
1283         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1284         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1285 }
1286
1287
1288 /*
1289  * Indirect registers accessor
1290  */
1291 void r100_pll_errata_after_index(struct radeon_device *rdev)
1292 {
1293         if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
1294                 return;
1295         }
1296         (void)RREG32(RADEON_CLOCK_CNTL_DATA);
1297         (void)RREG32(RADEON_CRTC_GEN_CNTL);
1298 }
1299
1300 static void r100_pll_errata_after_data(struct radeon_device *rdev)
1301 {
1302         /* This workarounds is necessary on RV100, RS100 and RS200 chips
1303          * or the chip could hang on a subsequent access
1304          */
1305         if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
1306                 udelay(5000);
1307         }
1308
1309         /* This function is required to workaround a hardware bug in some (all?)
1310          * revisions of the R300.  This workaround should be called after every
1311          * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
1312          * may not be correct.
1313          */
1314         if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
1315                 uint32_t save, tmp;
1316
1317                 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
1318                 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
1319                 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
1320                 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
1321                 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
1322         }
1323 }
1324
1325 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
1326 {
1327         uint32_t data;
1328
1329         WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
1330         r100_pll_errata_after_index(rdev);
1331         data = RREG32(RADEON_CLOCK_CNTL_DATA);
1332         r100_pll_errata_after_data(rdev);
1333         return data;
1334 }
1335
1336 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1337 {
1338         WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
1339         r100_pll_errata_after_index(rdev);
1340         WREG32(RADEON_CLOCK_CNTL_DATA, v);
1341         r100_pll_errata_after_data(rdev);
1342 }
1343
1344 uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
1345 {
1346         if (reg < 0x10000)
1347                 return readl(((void __iomem *)rdev->rmmio) + reg);
1348         else {
1349                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1350                 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1351         }
1352 }
1353
1354 void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1355 {
1356         if (reg < 0x10000)
1357                 writel(v, ((void __iomem *)rdev->rmmio) + reg);
1358         else {
1359                 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1360                 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1361         }
1362 }
1363
1364 int r100_init(struct radeon_device *rdev)
1365 {
1366         return 0;
1367 }
1368
1369 /*
1370  * Debugfs info
1371  */
1372 #if defined(CONFIG_DEBUG_FS)
1373 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
1374 {
1375         struct drm_info_node *node = (struct drm_info_node *) m->private;
1376         struct drm_device *dev = node->minor->dev;
1377         struct radeon_device *rdev = dev->dev_private;
1378         uint32_t reg, value;
1379         unsigned i;
1380
1381         seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
1382         seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
1383         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
1384         for (i = 0; i < 64; i++) {
1385                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
1386                 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
1387                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
1388                 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
1389                 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
1390         }
1391         return 0;
1392 }
1393
1394 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
1395 {
1396         struct drm_info_node *node = (struct drm_info_node *) m->private;
1397         struct drm_device *dev = node->minor->dev;
1398         struct radeon_device *rdev = dev->dev_private;
1399         uint32_t rdp, wdp;
1400         unsigned count, i, j;
1401
1402         radeon_ring_free_size(rdev);
1403         rdp = RREG32(RADEON_CP_RB_RPTR);
1404         wdp = RREG32(RADEON_CP_RB_WPTR);
1405         count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
1406         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
1407         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
1408         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
1409         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
1410         seq_printf(m, "%u dwords in ring\n", count);
1411         for (j = 0; j <= count; j++) {
1412                 i = (rdp + j) & rdev->cp.ptr_mask;
1413                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
1414         }
1415         return 0;
1416 }
1417
1418
1419 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
1420 {
1421         struct drm_info_node *node = (struct drm_info_node *) m->private;
1422         struct drm_device *dev = node->minor->dev;
1423         struct radeon_device *rdev = dev->dev_private;
1424         uint32_t csq_stat, csq2_stat, tmp;
1425         unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
1426         unsigned i;
1427
1428         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
1429         seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
1430         csq_stat = RREG32(RADEON_CP_CSQ_STAT);
1431         csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
1432         r_rptr = (csq_stat >> 0) & 0x3ff;
1433         r_wptr = (csq_stat >> 10) & 0x3ff;
1434         ib1_rptr = (csq_stat >> 20) & 0x3ff;
1435         ib1_wptr = (csq2_stat >> 0) & 0x3ff;
1436         ib2_rptr = (csq2_stat >> 10) & 0x3ff;
1437         ib2_wptr = (csq2_stat >> 20) & 0x3ff;
1438         seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
1439         seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
1440         seq_printf(m, "Ring rptr %u\n", r_rptr);
1441         seq_printf(m, "Ring wptr %u\n", r_wptr);
1442         seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
1443         seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
1444         seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
1445         seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
1446         /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
1447          * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
1448         seq_printf(m, "Ring fifo:\n");
1449         for (i = 0; i < 256; i++) {
1450                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
1451                 tmp = RREG32(RADEON_CP_CSQ_DATA);
1452                 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
1453         }
1454         seq_printf(m, "Indirect1 fifo:\n");
1455         for (i = 256; i <= 512; i++) {
1456                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
1457                 tmp = RREG32(RADEON_CP_CSQ_DATA);
1458                 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
1459         }
1460         seq_printf(m, "Indirect2 fifo:\n");
1461         for (i = 640; i < ib1_wptr; i++) {
1462                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
1463                 tmp = RREG32(RADEON_CP_CSQ_DATA);
1464                 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
1465         }
1466         return 0;
1467 }
1468
1469 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
1470 {
1471         struct drm_info_node *node = (struct drm_info_node *) m->private;
1472         struct drm_device *dev = node->minor->dev;
1473         struct radeon_device *rdev = dev->dev_private;
1474         uint32_t tmp;
1475
1476         tmp = RREG32(RADEON_CONFIG_MEMSIZE);
1477         seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
1478         tmp = RREG32(RADEON_MC_FB_LOCATION);
1479         seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
1480         tmp = RREG32(RADEON_BUS_CNTL);
1481         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
1482         tmp = RREG32(RADEON_MC_AGP_LOCATION);
1483         seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
1484         tmp = RREG32(RADEON_AGP_BASE);
1485         seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
1486         tmp = RREG32(RADEON_HOST_PATH_CNTL);
1487         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
1488         tmp = RREG32(0x01D0);
1489         seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
1490         tmp = RREG32(RADEON_AIC_LO_ADDR);
1491         seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
1492         tmp = RREG32(RADEON_AIC_HI_ADDR);
1493         seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
1494         tmp = RREG32(0x01E4);
1495         seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
1496         return 0;
1497 }
1498
1499 static struct drm_info_list r100_debugfs_rbbm_list[] = {
1500         {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
1501 };
1502
1503 static struct drm_info_list r100_debugfs_cp_list[] = {
1504         {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
1505         {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
1506 };
1507
1508 static struct drm_info_list r100_debugfs_mc_info_list[] = {
1509         {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
1510 };
1511 #endif
1512
1513 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
1514 {
1515 #if defined(CONFIG_DEBUG_FS)
1516         return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
1517 #else
1518         return 0;
1519 #endif
1520 }
1521
1522 int r100_debugfs_cp_init(struct radeon_device *rdev)
1523 {
1524 #if defined(CONFIG_DEBUG_FS)
1525         return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
1526 #else
1527         return 0;
1528 #endif
1529 }
1530
1531 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
1532 {
1533 #if defined(CONFIG_DEBUG_FS)
1534         return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
1535 #else
1536         return 0;
1537 #endif
1538 }