e35cf1932829252859f1037cff9e0feed8b68e3f
[linux-2.6.git] / drivers / gpu / drm / radeon / r100.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/seq_file.h>
29 #include "drmP.h"
30 #include "drm.h"
31 #include "radeon_drm.h"
32 #include "radeon_reg.h"
33 #include "radeon.h"
34 #include "radeon_asic.h"
35 #include "r100d.h"
36 #include "rs100d.h"
37 #include "rv200d.h"
38 #include "rv250d.h"
39
40 #include <linux/firmware.h>
41 #include <linux/platform_device.h>
42
43 #include "r100_reg_safe.h"
44 #include "rn50_reg_safe.h"
45
46 /* Firmware Names */
47 #define FIRMWARE_R100           "radeon/R100_cp.bin"
48 #define FIRMWARE_R200           "radeon/R200_cp.bin"
49 #define FIRMWARE_R300           "radeon/R300_cp.bin"
50 #define FIRMWARE_R420           "radeon/R420_cp.bin"
51 #define FIRMWARE_RS690          "radeon/RS690_cp.bin"
52 #define FIRMWARE_RS600          "radeon/RS600_cp.bin"
53 #define FIRMWARE_R520           "radeon/R520_cp.bin"
54
55 MODULE_FIRMWARE(FIRMWARE_R100);
56 MODULE_FIRMWARE(FIRMWARE_R200);
57 MODULE_FIRMWARE(FIRMWARE_R300);
58 MODULE_FIRMWARE(FIRMWARE_R420);
59 MODULE_FIRMWARE(FIRMWARE_RS690);
60 MODULE_FIRMWARE(FIRMWARE_RS600);
61 MODULE_FIRMWARE(FIRMWARE_R520);
62
63 #include "r100_track.h"
64
65 /* This files gather functions specifics to:
66  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
67  */
68
69 /* hpd for digital panel detect/disconnect */
70 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
71 {
72         bool connected = false;
73
74         switch (hpd) {
75         case RADEON_HPD_1:
76                 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
77                         connected = true;
78                 break;
79         case RADEON_HPD_2:
80                 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
81                         connected = true;
82                 break;
83         default:
84                 break;
85         }
86         return connected;
87 }
88
89 void r100_hpd_set_polarity(struct radeon_device *rdev,
90                            enum radeon_hpd_id hpd)
91 {
92         u32 tmp;
93         bool connected = r100_hpd_sense(rdev, hpd);
94
95         switch (hpd) {
96         case RADEON_HPD_1:
97                 tmp = RREG32(RADEON_FP_GEN_CNTL);
98                 if (connected)
99                         tmp &= ~RADEON_FP_DETECT_INT_POL;
100                 else
101                         tmp |= RADEON_FP_DETECT_INT_POL;
102                 WREG32(RADEON_FP_GEN_CNTL, tmp);
103                 break;
104         case RADEON_HPD_2:
105                 tmp = RREG32(RADEON_FP2_GEN_CNTL);
106                 if (connected)
107                         tmp &= ~RADEON_FP2_DETECT_INT_POL;
108                 else
109                         tmp |= RADEON_FP2_DETECT_INT_POL;
110                 WREG32(RADEON_FP2_GEN_CNTL, tmp);
111                 break;
112         default:
113                 break;
114         }
115 }
116
117 void r100_hpd_init(struct radeon_device *rdev)
118 {
119         struct drm_device *dev = rdev->ddev;
120         struct drm_connector *connector;
121
122         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
123                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
124                 switch (radeon_connector->hpd.hpd) {
125                 case RADEON_HPD_1:
126                         rdev->irq.hpd[0] = true;
127                         break;
128                 case RADEON_HPD_2:
129                         rdev->irq.hpd[1] = true;
130                         break;
131                 default:
132                         break;
133                 }
134         }
135         if (rdev->irq.installed)
136                 r100_irq_set(rdev);
137 }
138
139 void r100_hpd_fini(struct radeon_device *rdev)
140 {
141         struct drm_device *dev = rdev->ddev;
142         struct drm_connector *connector;
143
144         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
145                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
146                 switch (radeon_connector->hpd.hpd) {
147                 case RADEON_HPD_1:
148                         rdev->irq.hpd[0] = false;
149                         break;
150                 case RADEON_HPD_2:
151                         rdev->irq.hpd[1] = false;
152                         break;
153                 default:
154                         break;
155                 }
156         }
157 }
158
159 /*
160  * PCI GART
161  */
162 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
163 {
164         /* TODO: can we do somethings here ? */
165         /* It seems hw only cache one entry so we should discard this
166          * entry otherwise if first GPU GART read hit this entry it
167          * could end up in wrong address. */
168 }
169
170 int r100_pci_gart_init(struct radeon_device *rdev)
171 {
172         int r;
173
174         if (rdev->gart.table.ram.ptr) {
175                 WARN(1, "R100 PCI GART already initialized.\n");
176                 return 0;
177         }
178         /* Initialize common gart structure */
179         r = radeon_gart_init(rdev);
180         if (r)
181                 return r;
182         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
183         rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
184         rdev->asic->gart_set_page = &r100_pci_gart_set_page;
185         return radeon_gart_table_ram_alloc(rdev);
186 }
187
188 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
189 void r100_enable_bm(struct radeon_device *rdev)
190 {
191         uint32_t tmp;
192         /* Enable bus mastering */
193         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
194         WREG32(RADEON_BUS_CNTL, tmp);
195 }
196
197 int r100_pci_gart_enable(struct radeon_device *rdev)
198 {
199         uint32_t tmp;
200
201         radeon_gart_restore(rdev);
202         /* discard memory request outside of configured range */
203         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
204         WREG32(RADEON_AIC_CNTL, tmp);
205         /* set address range for PCI address translate */
206         WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
207         WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
208         /* set PCI GART page-table base address */
209         WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
210         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
211         WREG32(RADEON_AIC_CNTL, tmp);
212         r100_pci_gart_tlb_flush(rdev);
213         rdev->gart.ready = true;
214         return 0;
215 }
216
217 void r100_pci_gart_disable(struct radeon_device *rdev)
218 {
219         uint32_t tmp;
220
221         /* discard memory request outside of configured range */
222         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
223         WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
224         WREG32(RADEON_AIC_LO_ADDR, 0);
225         WREG32(RADEON_AIC_HI_ADDR, 0);
226 }
227
228 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
229 {
230         if (i < 0 || i > rdev->gart.num_gpu_pages) {
231                 return -EINVAL;
232         }
233         rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
234         return 0;
235 }
236
237 void r100_pci_gart_fini(struct radeon_device *rdev)
238 {
239         r100_pci_gart_disable(rdev);
240         radeon_gart_table_ram_free(rdev);
241         radeon_gart_fini(rdev);
242 }
243
244 int r100_irq_set(struct radeon_device *rdev)
245 {
246         uint32_t tmp = 0;
247
248         if (!rdev->irq.installed) {
249                 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
250                 WREG32(R_000040_GEN_INT_CNTL, 0);
251                 return -EINVAL;
252         }
253         if (rdev->irq.sw_int) {
254                 tmp |= RADEON_SW_INT_ENABLE;
255         }
256         if (rdev->irq.crtc_vblank_int[0]) {
257                 tmp |= RADEON_CRTC_VBLANK_MASK;
258         }
259         if (rdev->irq.crtc_vblank_int[1]) {
260                 tmp |= RADEON_CRTC2_VBLANK_MASK;
261         }
262         if (rdev->irq.hpd[0]) {
263                 tmp |= RADEON_FP_DETECT_MASK;
264         }
265         if (rdev->irq.hpd[1]) {
266                 tmp |= RADEON_FP2_DETECT_MASK;
267         }
268         WREG32(RADEON_GEN_INT_CNTL, tmp);
269         return 0;
270 }
271
272 void r100_irq_disable(struct radeon_device *rdev)
273 {
274         u32 tmp;
275
276         WREG32(R_000040_GEN_INT_CNTL, 0);
277         /* Wait and acknowledge irq */
278         mdelay(1);
279         tmp = RREG32(R_000044_GEN_INT_STATUS);
280         WREG32(R_000044_GEN_INT_STATUS, tmp);
281 }
282
283 static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
284 {
285         uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
286         uint32_t irq_mask = RADEON_SW_INT_TEST |
287                 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
288                 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
289
290         if (irqs) {
291                 WREG32(RADEON_GEN_INT_STATUS, irqs);
292         }
293         return irqs & irq_mask;
294 }
295
296 int r100_irq_process(struct radeon_device *rdev)
297 {
298         uint32_t status, msi_rearm;
299         bool queue_hotplug = false;
300
301         status = r100_irq_ack(rdev);
302         if (!status) {
303                 return IRQ_NONE;
304         }
305         if (rdev->shutdown) {
306                 return IRQ_NONE;
307         }
308         while (status) {
309                 /* SW interrupt */
310                 if (status & RADEON_SW_INT_TEST) {
311                         radeon_fence_process(rdev);
312                 }
313                 /* Vertical blank interrupts */
314                 if (status & RADEON_CRTC_VBLANK_STAT) {
315                         drm_handle_vblank(rdev->ddev, 0);
316                         rdev->pm.vblank_sync = true;
317                         wake_up(&rdev->irq.vblank_queue);
318                 }
319                 if (status & RADEON_CRTC2_VBLANK_STAT) {
320                         drm_handle_vblank(rdev->ddev, 1);
321                         rdev->pm.vblank_sync = true;
322                         wake_up(&rdev->irq.vblank_queue);
323                 }
324                 if (status & RADEON_FP_DETECT_STAT) {
325                         queue_hotplug = true;
326                         DRM_DEBUG("HPD1\n");
327                 }
328                 if (status & RADEON_FP2_DETECT_STAT) {
329                         queue_hotplug = true;
330                         DRM_DEBUG("HPD2\n");
331                 }
332                 status = r100_irq_ack(rdev);
333         }
334         if (queue_hotplug)
335                 queue_work(rdev->wq, &rdev->hotplug_work);
336         if (rdev->msi_enabled) {
337                 switch (rdev->family) {
338                 case CHIP_RS400:
339                 case CHIP_RS480:
340                         msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
341                         WREG32(RADEON_AIC_CNTL, msi_rearm);
342                         WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
343                         break;
344                 default:
345                         msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
346                         WREG32(RADEON_MSI_REARM_EN, msi_rearm);
347                         WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
348                         break;
349                 }
350         }
351         return IRQ_HANDLED;
352 }
353
354 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
355 {
356         if (crtc == 0)
357                 return RREG32(RADEON_CRTC_CRNT_FRAME);
358         else
359                 return RREG32(RADEON_CRTC2_CRNT_FRAME);
360 }
361
362 /* Who ever call radeon_fence_emit should call ring_lock and ask
363  * for enough space (today caller are ib schedule and buffer move) */
364 void r100_fence_ring_emit(struct radeon_device *rdev,
365                           struct radeon_fence *fence)
366 {
367         /* We have to make sure that caches are flushed before
368          * CPU might read something from VRAM. */
369         radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
370         radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
371         radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
372         radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
373         /* Wait until IDLE & CLEAN */
374         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
375         radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
376         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
377         radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
378                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
379         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
380         radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
381         /* Emit fence sequence & fire IRQ */
382         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
383         radeon_ring_write(rdev, fence->seq);
384         radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
385         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
386 }
387
388 int r100_wb_init(struct radeon_device *rdev)
389 {
390         int r;
391
392         if (rdev->wb.wb_obj == NULL) {
393                 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
394                                         RADEON_GEM_DOMAIN_GTT,
395                                         &rdev->wb.wb_obj);
396                 if (r) {
397                         dev_err(rdev->dev, "(%d) create WB buffer failed\n", r);
398                         return r;
399                 }
400                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
401                 if (unlikely(r != 0))
402                         return r;
403                 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
404                                         &rdev->wb.gpu_addr);
405                 if (r) {
406                         dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r);
407                         radeon_bo_unreserve(rdev->wb.wb_obj);
408                         return r;
409                 }
410                 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
411                 radeon_bo_unreserve(rdev->wb.wb_obj);
412                 if (r) {
413                         dev_err(rdev->dev, "(%d) map WB buffer failed\n", r);
414                         return r;
415                 }
416         }
417         WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
418         WREG32(R_00070C_CP_RB_RPTR_ADDR,
419                 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
420         WREG32(R_000770_SCRATCH_UMSK, 0xff);
421         return 0;
422 }
423
424 void r100_wb_disable(struct radeon_device *rdev)
425 {
426         WREG32(R_000770_SCRATCH_UMSK, 0);
427 }
428
429 void r100_wb_fini(struct radeon_device *rdev)
430 {
431         int r;
432
433         r100_wb_disable(rdev);
434         if (rdev->wb.wb_obj) {
435                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
436                 if (unlikely(r != 0)) {
437                         dev_err(rdev->dev, "(%d) can't finish WB\n", r);
438                         return;
439                 }
440                 radeon_bo_kunmap(rdev->wb.wb_obj);
441                 radeon_bo_unpin(rdev->wb.wb_obj);
442                 radeon_bo_unreserve(rdev->wb.wb_obj);
443                 radeon_bo_unref(&rdev->wb.wb_obj);
444                 rdev->wb.wb = NULL;
445                 rdev->wb.wb_obj = NULL;
446         }
447 }
448
449 int r100_copy_blit(struct radeon_device *rdev,
450                    uint64_t src_offset,
451                    uint64_t dst_offset,
452                    unsigned num_pages,
453                    struct radeon_fence *fence)
454 {
455         uint32_t cur_pages;
456         uint32_t stride_bytes = PAGE_SIZE;
457         uint32_t pitch;
458         uint32_t stride_pixels;
459         unsigned ndw;
460         int num_loops;
461         int r = 0;
462
463         /* radeon limited to 16k stride */
464         stride_bytes &= 0x3fff;
465         /* radeon pitch is /64 */
466         pitch = stride_bytes / 64;
467         stride_pixels = stride_bytes / 4;
468         num_loops = DIV_ROUND_UP(num_pages, 8191);
469
470         /* Ask for enough room for blit + flush + fence */
471         ndw = 64 + (10 * num_loops);
472         r = radeon_ring_lock(rdev, ndw);
473         if (r) {
474                 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
475                 return -EINVAL;
476         }
477         while (num_pages > 0) {
478                 cur_pages = num_pages;
479                 if (cur_pages > 8191) {
480                         cur_pages = 8191;
481                 }
482                 num_pages -= cur_pages;
483
484                 /* pages are in Y direction - height
485                    page width in X direction - width */
486                 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
487                 radeon_ring_write(rdev,
488                                   RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
489                                   RADEON_GMC_DST_PITCH_OFFSET_CNTL |
490                                   RADEON_GMC_SRC_CLIPPING |
491                                   RADEON_GMC_DST_CLIPPING |
492                                   RADEON_GMC_BRUSH_NONE |
493                                   (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
494                                   RADEON_GMC_SRC_DATATYPE_COLOR |
495                                   RADEON_ROP3_S |
496                                   RADEON_DP_SRC_SOURCE_MEMORY |
497                                   RADEON_GMC_CLR_CMP_CNTL_DIS |
498                                   RADEON_GMC_WR_MSK_DIS);
499                 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
500                 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
501                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
502                 radeon_ring_write(rdev, 0);
503                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
504                 radeon_ring_write(rdev, num_pages);
505                 radeon_ring_write(rdev, num_pages);
506                 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
507         }
508         radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
509         radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
510         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
511         radeon_ring_write(rdev,
512                           RADEON_WAIT_2D_IDLECLEAN |
513                           RADEON_WAIT_HOST_IDLECLEAN |
514                           RADEON_WAIT_DMA_GUI_IDLE);
515         if (fence) {
516                 r = radeon_fence_emit(rdev, fence);
517         }
518         radeon_ring_unlock_commit(rdev);
519         return r;
520 }
521
522 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
523 {
524         unsigned i;
525         u32 tmp;
526
527         for (i = 0; i < rdev->usec_timeout; i++) {
528                 tmp = RREG32(R_000E40_RBBM_STATUS);
529                 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
530                         return 0;
531                 }
532                 udelay(1);
533         }
534         return -1;
535 }
536
537 void r100_ring_start(struct radeon_device *rdev)
538 {
539         int r;
540
541         r = radeon_ring_lock(rdev, 2);
542         if (r) {
543                 return;
544         }
545         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
546         radeon_ring_write(rdev,
547                           RADEON_ISYNC_ANY2D_IDLE3D |
548                           RADEON_ISYNC_ANY3D_IDLE2D |
549                           RADEON_ISYNC_WAIT_IDLEGUI |
550                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
551         radeon_ring_unlock_commit(rdev);
552 }
553
554
555 /* Load the microcode for the CP */
556 static int r100_cp_init_microcode(struct radeon_device *rdev)
557 {
558         struct platform_device *pdev;
559         const char *fw_name = NULL;
560         int err;
561
562         DRM_DEBUG("\n");
563
564         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
565         err = IS_ERR(pdev);
566         if (err) {
567                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
568                 return -EINVAL;
569         }
570         if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
571             (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
572             (rdev->family == CHIP_RS200)) {
573                 DRM_INFO("Loading R100 Microcode\n");
574                 fw_name = FIRMWARE_R100;
575         } else if ((rdev->family == CHIP_R200) ||
576                    (rdev->family == CHIP_RV250) ||
577                    (rdev->family == CHIP_RV280) ||
578                    (rdev->family == CHIP_RS300)) {
579                 DRM_INFO("Loading R200 Microcode\n");
580                 fw_name = FIRMWARE_R200;
581         } else if ((rdev->family == CHIP_R300) ||
582                    (rdev->family == CHIP_R350) ||
583                    (rdev->family == CHIP_RV350) ||
584                    (rdev->family == CHIP_RV380) ||
585                    (rdev->family == CHIP_RS400) ||
586                    (rdev->family == CHIP_RS480)) {
587                 DRM_INFO("Loading R300 Microcode\n");
588                 fw_name = FIRMWARE_R300;
589         } else if ((rdev->family == CHIP_R420) ||
590                    (rdev->family == CHIP_R423) ||
591                    (rdev->family == CHIP_RV410)) {
592                 DRM_INFO("Loading R400 Microcode\n");
593                 fw_name = FIRMWARE_R420;
594         } else if ((rdev->family == CHIP_RS690) ||
595                    (rdev->family == CHIP_RS740)) {
596                 DRM_INFO("Loading RS690/RS740 Microcode\n");
597                 fw_name = FIRMWARE_RS690;
598         } else if (rdev->family == CHIP_RS600) {
599                 DRM_INFO("Loading RS600 Microcode\n");
600                 fw_name = FIRMWARE_RS600;
601         } else if ((rdev->family == CHIP_RV515) ||
602                    (rdev->family == CHIP_R520) ||
603                    (rdev->family == CHIP_RV530) ||
604                    (rdev->family == CHIP_R580) ||
605                    (rdev->family == CHIP_RV560) ||
606                    (rdev->family == CHIP_RV570)) {
607                 DRM_INFO("Loading R500 Microcode\n");
608                 fw_name = FIRMWARE_R520;
609         }
610
611         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
612         platform_device_unregister(pdev);
613         if (err) {
614                 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
615                        fw_name);
616         } else if (rdev->me_fw->size % 8) {
617                 printk(KERN_ERR
618                        "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
619                        rdev->me_fw->size, fw_name);
620                 err = -EINVAL;
621                 release_firmware(rdev->me_fw);
622                 rdev->me_fw = NULL;
623         }
624         return err;
625 }
626
627 static void r100_cp_load_microcode(struct radeon_device *rdev)
628 {
629         const __be32 *fw_data;
630         int i, size;
631
632         if (r100_gui_wait_for_idle(rdev)) {
633                 printk(KERN_WARNING "Failed to wait GUI idle while "
634                        "programming pipes. Bad things might happen.\n");
635         }
636
637         if (rdev->me_fw) {
638                 size = rdev->me_fw->size / 4;
639                 fw_data = (const __be32 *)&rdev->me_fw->data[0];
640                 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
641                 for (i = 0; i < size; i += 2) {
642                         WREG32(RADEON_CP_ME_RAM_DATAH,
643                                be32_to_cpup(&fw_data[i]));
644                         WREG32(RADEON_CP_ME_RAM_DATAL,
645                                be32_to_cpup(&fw_data[i + 1]));
646                 }
647         }
648 }
649
650 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
651 {
652         unsigned rb_bufsz;
653         unsigned rb_blksz;
654         unsigned max_fetch;
655         unsigned pre_write_timer;
656         unsigned pre_write_limit;
657         unsigned indirect2_start;
658         unsigned indirect1_start;
659         uint32_t tmp;
660         int r;
661
662         if (r100_debugfs_cp_init(rdev)) {
663                 DRM_ERROR("Failed to register debugfs file for CP !\n");
664         }
665         /* Reset CP */
666         tmp = RREG32(RADEON_CP_CSQ_STAT);
667         if ((tmp & (1 << 31))) {
668                 DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
669                 WREG32(RADEON_CP_CSQ_MODE, 0);
670                 WREG32(RADEON_CP_CSQ_CNTL, 0);
671                 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
672                 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
673                 mdelay(2);
674                 WREG32(RADEON_RBBM_SOFT_RESET, 0);
675                 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
676                 mdelay(2);
677                 tmp = RREG32(RADEON_CP_CSQ_STAT);
678                 if ((tmp & (1 << 31))) {
679                         DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp);
680                 }
681         } else {
682                 DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
683         }
684
685         if (!rdev->me_fw) {
686                 r = r100_cp_init_microcode(rdev);
687                 if (r) {
688                         DRM_ERROR("Failed to load firmware!\n");
689                         return r;
690                 }
691         }
692
693         /* Align ring size */
694         rb_bufsz = drm_order(ring_size / 8);
695         ring_size = (1 << (rb_bufsz + 1)) * 4;
696         r100_cp_load_microcode(rdev);
697         r = radeon_ring_init(rdev, ring_size);
698         if (r) {
699                 return r;
700         }
701         /* Each time the cp read 1024 bytes (16 dword/quadword) update
702          * the rptr copy in system ram */
703         rb_blksz = 9;
704         /* cp will read 128bytes at a time (4 dwords) */
705         max_fetch = 1;
706         rdev->cp.align_mask = 16 - 1;
707         /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
708         pre_write_timer = 64;
709         /* Force CP_RB_WPTR write if written more than one time before the
710          * delay expire
711          */
712         pre_write_limit = 0;
713         /* Setup the cp cache like this (cache size is 96 dwords) :
714          *      RING            0  to 15
715          *      INDIRECT1       16 to 79
716          *      INDIRECT2       80 to 95
717          * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
718          *    indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
719          *    indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
720          * Idea being that most of the gpu cmd will be through indirect1 buffer
721          * so it gets the bigger cache.
722          */
723         indirect2_start = 80;
724         indirect1_start = 16;
725         /* cp setup */
726         WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
727         tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
728                REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
729                REG_SET(RADEON_MAX_FETCH, max_fetch) |
730                RADEON_RB_NO_UPDATE);
731 #ifdef __BIG_ENDIAN
732         tmp |= RADEON_BUF_SWAP_32BIT;
733 #endif
734         WREG32(RADEON_CP_RB_CNTL, tmp);
735
736         /* Set ring address */
737         DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
738         WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
739         /* Force read & write ptr to 0 */
740         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
741         WREG32(RADEON_CP_RB_RPTR_WR, 0);
742         WREG32(RADEON_CP_RB_WPTR, 0);
743         WREG32(RADEON_CP_RB_CNTL, tmp);
744         udelay(10);
745         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
746         rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
747         /* Set cp mode to bus mastering & enable cp*/
748         WREG32(RADEON_CP_CSQ_MODE,
749                REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
750                REG_SET(RADEON_INDIRECT1_START, indirect1_start));
751         WREG32(0x718, 0);
752         WREG32(0x744, 0x00004D4D);
753         WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
754         radeon_ring_start(rdev);
755         r = radeon_ring_test(rdev);
756         if (r) {
757                 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
758                 return r;
759         }
760         rdev->cp.ready = true;
761         return 0;
762 }
763
764 void r100_cp_fini(struct radeon_device *rdev)
765 {
766         if (r100_cp_wait_for_idle(rdev)) {
767                 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
768         }
769         /* Disable ring */
770         r100_cp_disable(rdev);
771         radeon_ring_fini(rdev);
772         DRM_INFO("radeon: cp finalized\n");
773 }
774
775 void r100_cp_disable(struct radeon_device *rdev)
776 {
777         /* Disable ring */
778         rdev->cp.ready = false;
779         WREG32(RADEON_CP_CSQ_MODE, 0);
780         WREG32(RADEON_CP_CSQ_CNTL, 0);
781         if (r100_gui_wait_for_idle(rdev)) {
782                 printk(KERN_WARNING "Failed to wait GUI idle while "
783                        "programming pipes. Bad things might happen.\n");
784         }
785 }
786
787 int r100_cp_reset(struct radeon_device *rdev)
788 {
789         uint32_t tmp;
790         bool reinit_cp;
791         int i;
792
793         reinit_cp = rdev->cp.ready;
794         rdev->cp.ready = false;
795         WREG32(RADEON_CP_CSQ_MODE, 0);
796         WREG32(RADEON_CP_CSQ_CNTL, 0);
797         WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
798         (void)RREG32(RADEON_RBBM_SOFT_RESET);
799         udelay(200);
800         WREG32(RADEON_RBBM_SOFT_RESET, 0);
801         /* Wait to prevent race in RBBM_STATUS */
802         mdelay(1);
803         for (i = 0; i < rdev->usec_timeout; i++) {
804                 tmp = RREG32(RADEON_RBBM_STATUS);
805                 if (!(tmp & (1 << 16))) {
806                         DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
807                                  tmp);
808                         if (reinit_cp) {
809                                 return r100_cp_init(rdev, rdev->cp.ring_size);
810                         }
811                         return 0;
812                 }
813                 DRM_UDELAY(1);
814         }
815         tmp = RREG32(RADEON_RBBM_STATUS);
816         DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp);
817         return -1;
818 }
819
820 void r100_cp_commit(struct radeon_device *rdev)
821 {
822         WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
823         (void)RREG32(RADEON_CP_RB_WPTR);
824 }
825
826
827 /*
828  * CS functions
829  */
830 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
831                           struct radeon_cs_packet *pkt,
832                           const unsigned *auth, unsigned n,
833                           radeon_packet0_check_t check)
834 {
835         unsigned reg;
836         unsigned i, j, m;
837         unsigned idx;
838         int r;
839
840         idx = pkt->idx + 1;
841         reg = pkt->reg;
842         /* Check that register fall into register range
843          * determined by the number of entry (n) in the
844          * safe register bitmap.
845          */
846         if (pkt->one_reg_wr) {
847                 if ((reg >> 7) > n) {
848                         return -EINVAL;
849                 }
850         } else {
851                 if (((reg + (pkt->count << 2)) >> 7) > n) {
852                         return -EINVAL;
853                 }
854         }
855         for (i = 0; i <= pkt->count; i++, idx++) {
856                 j = (reg >> 7);
857                 m = 1 << ((reg >> 2) & 31);
858                 if (auth[j] & m) {
859                         r = check(p, pkt, idx, reg);
860                         if (r) {
861                                 return r;
862                         }
863                 }
864                 if (pkt->one_reg_wr) {
865                         if (!(auth[j] & m)) {
866                                 break;
867                         }
868                 } else {
869                         reg += 4;
870                 }
871         }
872         return 0;
873 }
874
875 void r100_cs_dump_packet(struct radeon_cs_parser *p,
876                          struct radeon_cs_packet *pkt)
877 {
878         volatile uint32_t *ib;
879         unsigned i;
880         unsigned idx;
881
882         ib = p->ib->ptr;
883         idx = pkt->idx;
884         for (i = 0; i <= (pkt->count + 1); i++, idx++) {
885                 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
886         }
887 }
888
889 /**
890  * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
891  * @parser:     parser structure holding parsing context.
892  * @pkt:        where to store packet informations
893  *
894  * Assume that chunk_ib_index is properly set. Will return -EINVAL
895  * if packet is bigger than remaining ib size. or if packets is unknown.
896  **/
897 int r100_cs_packet_parse(struct radeon_cs_parser *p,
898                          struct radeon_cs_packet *pkt,
899                          unsigned idx)
900 {
901         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
902         uint32_t header;
903
904         if (idx >= ib_chunk->length_dw) {
905                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
906                           idx, ib_chunk->length_dw);
907                 return -EINVAL;
908         }
909         header = radeon_get_ib_value(p, idx);
910         pkt->idx = idx;
911         pkt->type = CP_PACKET_GET_TYPE(header);
912         pkt->count = CP_PACKET_GET_COUNT(header);
913         switch (pkt->type) {
914         case PACKET_TYPE0:
915                 pkt->reg = CP_PACKET0_GET_REG(header);
916                 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
917                 break;
918         case PACKET_TYPE3:
919                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
920                 break;
921         case PACKET_TYPE2:
922                 pkt->count = -1;
923                 break;
924         default:
925                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
926                 return -EINVAL;
927         }
928         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
929                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
930                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
931                 return -EINVAL;
932         }
933         return 0;
934 }
935
936 /**
937  * r100_cs_packet_next_vline() - parse userspace VLINE packet
938  * @parser:             parser structure holding parsing context.
939  *
940  * Userspace sends a special sequence for VLINE waits.
941  * PACKET0 - VLINE_START_END + value
942  * PACKET0 - WAIT_UNTIL +_value
943  * RELOC (P3) - crtc_id in reloc.
944  *
945  * This function parses this and relocates the VLINE START END
946  * and WAIT UNTIL packets to the correct crtc.
947  * It also detects a switched off crtc and nulls out the
948  * wait in that case.
949  */
950 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
951 {
952         struct drm_mode_object *obj;
953         struct drm_crtc *crtc;
954         struct radeon_crtc *radeon_crtc;
955         struct radeon_cs_packet p3reloc, waitreloc;
956         int crtc_id;
957         int r;
958         uint32_t header, h_idx, reg;
959         volatile uint32_t *ib;
960
961         ib = p->ib->ptr;
962
963         /* parse the wait until */
964         r = r100_cs_packet_parse(p, &waitreloc, p->idx);
965         if (r)
966                 return r;
967
968         /* check its a wait until and only 1 count */
969         if (waitreloc.reg != RADEON_WAIT_UNTIL ||
970             waitreloc.count != 0) {
971                 DRM_ERROR("vline wait had illegal wait until segment\n");
972                 r = -EINVAL;
973                 return r;
974         }
975
976         if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
977                 DRM_ERROR("vline wait had illegal wait until\n");
978                 r = -EINVAL;
979                 return r;
980         }
981
982         /* jump over the NOP */
983         r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
984         if (r)
985                 return r;
986
987         h_idx = p->idx - 2;
988         p->idx += waitreloc.count + 2;
989         p->idx += p3reloc.count + 2;
990
991         header = radeon_get_ib_value(p, h_idx);
992         crtc_id = radeon_get_ib_value(p, h_idx + 5);
993         reg = CP_PACKET0_GET_REG(header);
994         mutex_lock(&p->rdev->ddev->mode_config.mutex);
995         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
996         if (!obj) {
997                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
998                 r = -EINVAL;
999                 goto out;
1000         }
1001         crtc = obj_to_crtc(obj);
1002         radeon_crtc = to_radeon_crtc(crtc);
1003         crtc_id = radeon_crtc->crtc_id;
1004
1005         if (!crtc->enabled) {
1006                 /* if the CRTC isn't enabled - we need to nop out the wait until */
1007                 ib[h_idx + 2] = PACKET2(0);
1008                 ib[h_idx + 3] = PACKET2(0);
1009         } else if (crtc_id == 1) {
1010                 switch (reg) {
1011                 case AVIVO_D1MODE_VLINE_START_END:
1012                         header &= ~R300_CP_PACKET0_REG_MASK;
1013                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1014                         break;
1015                 case RADEON_CRTC_GUI_TRIG_VLINE:
1016                         header &= ~R300_CP_PACKET0_REG_MASK;
1017                         header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1018                         break;
1019                 default:
1020                         DRM_ERROR("unknown crtc reloc\n");
1021                         r = -EINVAL;
1022                         goto out;
1023                 }
1024                 ib[h_idx] = header;
1025                 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1026         }
1027 out:
1028         mutex_unlock(&p->rdev->ddev->mode_config.mutex);
1029         return r;
1030 }
1031
1032 /**
1033  * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1034  * @parser:             parser structure holding parsing context.
1035  * @data:               pointer to relocation data
1036  * @offset_start:       starting offset
1037  * @offset_mask:        offset mask (to align start offset on)
1038  * @reloc:              reloc informations
1039  *
1040  * Check next packet is relocation packet3, do bo validation and compute
1041  * GPU offset using the provided start.
1042  **/
1043 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1044                               struct radeon_cs_reloc **cs_reloc)
1045 {
1046         struct radeon_cs_chunk *relocs_chunk;
1047         struct radeon_cs_packet p3reloc;
1048         unsigned idx;
1049         int r;
1050
1051         if (p->chunk_relocs_idx == -1) {
1052                 DRM_ERROR("No relocation chunk !\n");
1053                 return -EINVAL;
1054         }
1055         *cs_reloc = NULL;
1056         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1057         r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1058         if (r) {
1059                 return r;
1060         }
1061         p->idx += p3reloc.count + 2;
1062         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1063                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1064                           p3reloc.idx);
1065                 r100_cs_dump_packet(p, &p3reloc);
1066                 return -EINVAL;
1067         }
1068         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1069         if (idx >= relocs_chunk->length_dw) {
1070                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1071                           idx, relocs_chunk->length_dw);
1072                 r100_cs_dump_packet(p, &p3reloc);
1073                 return -EINVAL;
1074         }
1075         /* FIXME: we assume reloc size is 4 dwords */
1076         *cs_reloc = p->relocs_ptr[(idx / 4)];
1077         return 0;
1078 }
1079
1080 static int r100_get_vtx_size(uint32_t vtx_fmt)
1081 {
1082         int vtx_size;
1083         vtx_size = 2;
1084         /* ordered according to bits in spec */
1085         if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1086                 vtx_size++;
1087         if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1088                 vtx_size += 3;
1089         if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1090                 vtx_size++;
1091         if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1092                 vtx_size++;
1093         if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1094                 vtx_size += 3;
1095         if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1096                 vtx_size++;
1097         if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1098                 vtx_size++;
1099         if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1100                 vtx_size += 2;
1101         if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1102                 vtx_size += 2;
1103         if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1104                 vtx_size++;
1105         if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1106                 vtx_size += 2;
1107         if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1108                 vtx_size++;
1109         if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1110                 vtx_size += 2;
1111         if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1112                 vtx_size++;
1113         if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1114                 vtx_size++;
1115         /* blend weight */
1116         if (vtx_fmt & (0x7 << 15))
1117                 vtx_size += (vtx_fmt >> 15) & 0x7;
1118         if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1119                 vtx_size += 3;
1120         if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1121                 vtx_size += 2;
1122         if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1123                 vtx_size++;
1124         if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1125                 vtx_size++;
1126         if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1127                 vtx_size++;
1128         if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1129                 vtx_size++;
1130         return vtx_size;
1131 }
1132
1133 static int r100_packet0_check(struct radeon_cs_parser *p,
1134                               struct radeon_cs_packet *pkt,
1135                               unsigned idx, unsigned reg)
1136 {
1137         struct radeon_cs_reloc *reloc;
1138         struct r100_cs_track *track;
1139         volatile uint32_t *ib;
1140         uint32_t tmp;
1141         int r;
1142         int i, face;
1143         u32 tile_flags = 0;
1144         u32 idx_value;
1145
1146         ib = p->ib->ptr;
1147         track = (struct r100_cs_track *)p->track;
1148
1149         idx_value = radeon_get_ib_value(p, idx);
1150
1151         switch (reg) {
1152         case RADEON_CRTC_GUI_TRIG_VLINE:
1153                 r = r100_cs_packet_parse_vline(p);
1154                 if (r) {
1155                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1156                                   idx, reg);
1157                         r100_cs_dump_packet(p, pkt);
1158                         return r;
1159                 }
1160                 break;
1161                 /* FIXME: only allow PACKET3 blit? easier to check for out of
1162                  * range access */
1163         case RADEON_DST_PITCH_OFFSET:
1164         case RADEON_SRC_PITCH_OFFSET:
1165                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1166                 if (r)
1167                         return r;
1168                 break;
1169         case RADEON_RB3D_DEPTHOFFSET:
1170                 r = r100_cs_packet_next_reloc(p, &reloc);
1171                 if (r) {
1172                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1173                                   idx, reg);
1174                         r100_cs_dump_packet(p, pkt);
1175                         return r;
1176                 }
1177                 track->zb.robj = reloc->robj;
1178                 track->zb.offset = idx_value;
1179                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1180                 break;
1181         case RADEON_RB3D_COLOROFFSET:
1182                 r = r100_cs_packet_next_reloc(p, &reloc);
1183                 if (r) {
1184                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1185                                   idx, reg);
1186                         r100_cs_dump_packet(p, pkt);
1187                         return r;
1188                 }
1189                 track->cb[0].robj = reloc->robj;
1190                 track->cb[0].offset = idx_value;
1191                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1192                 break;
1193         case RADEON_PP_TXOFFSET_0:
1194         case RADEON_PP_TXOFFSET_1:
1195         case RADEON_PP_TXOFFSET_2:
1196                 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1197                 r = r100_cs_packet_next_reloc(p, &reloc);
1198                 if (r) {
1199                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1200                                   idx, reg);
1201                         r100_cs_dump_packet(p, pkt);
1202                         return r;
1203                 }
1204                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1205                 track->textures[i].robj = reloc->robj;
1206                 break;
1207         case RADEON_PP_CUBIC_OFFSET_T0_0:
1208         case RADEON_PP_CUBIC_OFFSET_T0_1:
1209         case RADEON_PP_CUBIC_OFFSET_T0_2:
1210         case RADEON_PP_CUBIC_OFFSET_T0_3:
1211         case RADEON_PP_CUBIC_OFFSET_T0_4:
1212                 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1213                 r = r100_cs_packet_next_reloc(p, &reloc);
1214                 if (r) {
1215                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1216                                   idx, reg);
1217                         r100_cs_dump_packet(p, pkt);
1218                         return r;
1219                 }
1220                 track->textures[0].cube_info[i].offset = idx_value;
1221                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1222                 track->textures[0].cube_info[i].robj = reloc->robj;
1223                 break;
1224         case RADEON_PP_CUBIC_OFFSET_T1_0:
1225         case RADEON_PP_CUBIC_OFFSET_T1_1:
1226         case RADEON_PP_CUBIC_OFFSET_T1_2:
1227         case RADEON_PP_CUBIC_OFFSET_T1_3:
1228         case RADEON_PP_CUBIC_OFFSET_T1_4:
1229                 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1230                 r = r100_cs_packet_next_reloc(p, &reloc);
1231                 if (r) {
1232                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1233                                   idx, reg);
1234                         r100_cs_dump_packet(p, pkt);
1235                         return r;
1236                 }
1237                 track->textures[1].cube_info[i].offset = idx_value;
1238                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1239                 track->textures[1].cube_info[i].robj = reloc->robj;
1240                 break;
1241         case RADEON_PP_CUBIC_OFFSET_T2_0:
1242         case RADEON_PP_CUBIC_OFFSET_T2_1:
1243         case RADEON_PP_CUBIC_OFFSET_T2_2:
1244         case RADEON_PP_CUBIC_OFFSET_T2_3:
1245         case RADEON_PP_CUBIC_OFFSET_T2_4:
1246                 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1247                 r = r100_cs_packet_next_reloc(p, &reloc);
1248                 if (r) {
1249                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1250                                   idx, reg);
1251                         r100_cs_dump_packet(p, pkt);
1252                         return r;
1253                 }
1254                 track->textures[2].cube_info[i].offset = idx_value;
1255                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1256                 track->textures[2].cube_info[i].robj = reloc->robj;
1257                 break;
1258         case RADEON_RE_WIDTH_HEIGHT:
1259                 track->maxy = ((idx_value >> 16) & 0x7FF);
1260                 break;
1261         case RADEON_RB3D_COLORPITCH:
1262                 r = r100_cs_packet_next_reloc(p, &reloc);
1263                 if (r) {
1264                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1265                                   idx, reg);
1266                         r100_cs_dump_packet(p, pkt);
1267                         return r;
1268                 }
1269
1270                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1271                         tile_flags |= RADEON_COLOR_TILE_ENABLE;
1272                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1273                         tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1274
1275                 tmp = idx_value & ~(0x7 << 16);
1276                 tmp |= tile_flags;
1277                 ib[idx] = tmp;
1278
1279                 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1280                 break;
1281         case RADEON_RB3D_DEPTHPITCH:
1282                 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1283                 break;
1284         case RADEON_RB3D_CNTL:
1285                 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1286                 case 7:
1287                 case 8:
1288                 case 9:
1289                 case 11:
1290                 case 12:
1291                         track->cb[0].cpp = 1;
1292                         break;
1293                 case 3:
1294                 case 4:
1295                 case 15:
1296                         track->cb[0].cpp = 2;
1297                         break;
1298                 case 6:
1299                         track->cb[0].cpp = 4;
1300                         break;
1301                 default:
1302                         DRM_ERROR("Invalid color buffer format (%d) !\n",
1303                                   ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1304                         return -EINVAL;
1305                 }
1306                 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1307                 break;
1308         case RADEON_RB3D_ZSTENCILCNTL:
1309                 switch (idx_value & 0xf) {
1310                 case 0:
1311                         track->zb.cpp = 2;
1312                         break;
1313                 case 2:
1314                 case 3:
1315                 case 4:
1316                 case 5:
1317                 case 9:
1318                 case 11:
1319                         track->zb.cpp = 4;
1320                         break;
1321                 default:
1322                         break;
1323                 }
1324                 break;
1325         case RADEON_RB3D_ZPASS_ADDR:
1326                 r = r100_cs_packet_next_reloc(p, &reloc);
1327                 if (r) {
1328                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1329                                   idx, reg);
1330                         r100_cs_dump_packet(p, pkt);
1331                         return r;
1332                 }
1333                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1334                 break;
1335         case RADEON_PP_CNTL:
1336                 {
1337                         uint32_t temp = idx_value >> 4;
1338                         for (i = 0; i < track->num_texture; i++)
1339                                 track->textures[i].enabled = !!(temp & (1 << i));
1340                 }
1341                 break;
1342         case RADEON_SE_VF_CNTL:
1343                 track->vap_vf_cntl = idx_value;
1344                 break;
1345         case RADEON_SE_VTX_FMT:
1346                 track->vtx_size = r100_get_vtx_size(idx_value);
1347                 break;
1348         case RADEON_PP_TEX_SIZE_0:
1349         case RADEON_PP_TEX_SIZE_1:
1350         case RADEON_PP_TEX_SIZE_2:
1351                 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1352                 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1353                 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1354                 break;
1355         case RADEON_PP_TEX_PITCH_0:
1356         case RADEON_PP_TEX_PITCH_1:
1357         case RADEON_PP_TEX_PITCH_2:
1358                 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1359                 track->textures[i].pitch = idx_value + 32;
1360                 break;
1361         case RADEON_PP_TXFILTER_0:
1362         case RADEON_PP_TXFILTER_1:
1363         case RADEON_PP_TXFILTER_2:
1364                 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1365                 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1366                                                  >> RADEON_MAX_MIP_LEVEL_SHIFT);
1367                 tmp = (idx_value >> 23) & 0x7;
1368                 if (tmp == 2 || tmp == 6)
1369                         track->textures[i].roundup_w = false;
1370                 tmp = (idx_value >> 27) & 0x7;
1371                 if (tmp == 2 || tmp == 6)
1372                         track->textures[i].roundup_h = false;
1373                 break;
1374         case RADEON_PP_TXFORMAT_0:
1375         case RADEON_PP_TXFORMAT_1:
1376         case RADEON_PP_TXFORMAT_2:
1377                 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1378                 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1379                         track->textures[i].use_pitch = 1;
1380                 } else {
1381                         track->textures[i].use_pitch = 0;
1382                         track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1383                         track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1384                 }
1385                 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1386                         track->textures[i].tex_coord_type = 2;
1387                 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1388                 case RADEON_TXFORMAT_I8:
1389                 case RADEON_TXFORMAT_RGB332:
1390                 case RADEON_TXFORMAT_Y8:
1391                         track->textures[i].cpp = 1;
1392                         break;
1393                 case RADEON_TXFORMAT_AI88:
1394                 case RADEON_TXFORMAT_ARGB1555:
1395                 case RADEON_TXFORMAT_RGB565:
1396                 case RADEON_TXFORMAT_ARGB4444:
1397                 case RADEON_TXFORMAT_VYUY422:
1398                 case RADEON_TXFORMAT_YVYU422:
1399                 case RADEON_TXFORMAT_SHADOW16:
1400                 case RADEON_TXFORMAT_LDUDV655:
1401                 case RADEON_TXFORMAT_DUDV88:
1402                         track->textures[i].cpp = 2;
1403                         break;
1404                 case RADEON_TXFORMAT_ARGB8888:
1405                 case RADEON_TXFORMAT_RGBA8888:
1406                 case RADEON_TXFORMAT_SHADOW32:
1407                 case RADEON_TXFORMAT_LDUDUV8888:
1408                         track->textures[i].cpp = 4;
1409                         break;
1410                 case RADEON_TXFORMAT_DXT1:
1411                         track->textures[i].cpp = 1;
1412                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1413                         break;
1414                 case RADEON_TXFORMAT_DXT23:
1415                 case RADEON_TXFORMAT_DXT45:
1416                         track->textures[i].cpp = 1;
1417                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1418                         break;
1419                 }
1420                 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1421                 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1422                 break;
1423         case RADEON_PP_CUBIC_FACES_0:
1424         case RADEON_PP_CUBIC_FACES_1:
1425         case RADEON_PP_CUBIC_FACES_2:
1426                 tmp = idx_value;
1427                 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1428                 for (face = 0; face < 4; face++) {
1429                         track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1430                         track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1431                 }
1432                 break;
1433         default:
1434                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1435                        reg, idx);
1436                 return -EINVAL;
1437         }
1438         return 0;
1439 }
1440
1441 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1442                                          struct radeon_cs_packet *pkt,
1443                                          struct radeon_bo *robj)
1444 {
1445         unsigned idx;
1446         u32 value;
1447         idx = pkt->idx + 1;
1448         value = radeon_get_ib_value(p, idx + 2);
1449         if ((value + 1) > radeon_bo_size(robj)) {
1450                 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1451                           "(need %u have %lu) !\n",
1452                           value + 1,
1453                           radeon_bo_size(robj));
1454                 return -EINVAL;
1455         }
1456         return 0;
1457 }
1458
1459 static int r100_packet3_check(struct radeon_cs_parser *p,
1460                               struct radeon_cs_packet *pkt)
1461 {
1462         struct radeon_cs_reloc *reloc;
1463         struct r100_cs_track *track;
1464         unsigned idx;
1465         volatile uint32_t *ib;
1466         int r;
1467
1468         ib = p->ib->ptr;
1469         idx = pkt->idx + 1;
1470         track = (struct r100_cs_track *)p->track;
1471         switch (pkt->opcode) {
1472         case PACKET3_3D_LOAD_VBPNTR:
1473                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1474                 if (r)
1475                         return r;
1476                 break;
1477         case PACKET3_INDX_BUFFER:
1478                 r = r100_cs_packet_next_reloc(p, &reloc);
1479                 if (r) {
1480                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1481                         r100_cs_dump_packet(p, pkt);
1482                         return r;
1483                 }
1484                 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1485                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1486                 if (r) {
1487                         return r;
1488                 }
1489                 break;
1490         case 0x23:
1491                 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1492                 r = r100_cs_packet_next_reloc(p, &reloc);
1493                 if (r) {
1494                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1495                         r100_cs_dump_packet(p, pkt);
1496                         return r;
1497                 }
1498                 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1499                 track->num_arrays = 1;
1500                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1501
1502                 track->arrays[0].robj = reloc->robj;
1503                 track->arrays[0].esize = track->vtx_size;
1504
1505                 track->max_indx = radeon_get_ib_value(p, idx+1);
1506
1507                 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1508                 track->immd_dwords = pkt->count - 1;
1509                 r = r100_cs_track_check(p->rdev, track);
1510                 if (r)
1511                         return r;
1512                 break;
1513         case PACKET3_3D_DRAW_IMMD:
1514                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1515                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1516                         return -EINVAL;
1517                 }
1518                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1519                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1520                 track->immd_dwords = pkt->count - 1;
1521                 r = r100_cs_track_check(p->rdev, track);
1522                 if (r)
1523                         return r;
1524                 break;
1525                 /* triggers drawing using in-packet vertex data */
1526         case PACKET3_3D_DRAW_IMMD_2:
1527                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1528                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1529                         return -EINVAL;
1530                 }
1531                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1532                 track->immd_dwords = pkt->count;
1533                 r = r100_cs_track_check(p->rdev, track);
1534                 if (r)
1535                         return r;
1536                 break;
1537                 /* triggers drawing using in-packet vertex data */
1538         case PACKET3_3D_DRAW_VBUF_2:
1539                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1540                 r = r100_cs_track_check(p->rdev, track);
1541                 if (r)
1542                         return r;
1543                 break;
1544                 /* triggers drawing of vertex buffers setup elsewhere */
1545         case PACKET3_3D_DRAW_INDX_2:
1546                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1547                 r = r100_cs_track_check(p->rdev, track);
1548                 if (r)
1549                         return r;
1550                 break;
1551                 /* triggers drawing using indices to vertex buffer */
1552         case PACKET3_3D_DRAW_VBUF:
1553                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1554                 r = r100_cs_track_check(p->rdev, track);
1555                 if (r)
1556                         return r;
1557                 break;
1558                 /* triggers drawing of vertex buffers setup elsewhere */
1559         case PACKET3_3D_DRAW_INDX:
1560                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1561                 r = r100_cs_track_check(p->rdev, track);
1562                 if (r)
1563                         return r;
1564                 break;
1565                 /* triggers drawing using indices to vertex buffer */
1566         case PACKET3_NOP:
1567                 break;
1568         default:
1569                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1570                 return -EINVAL;
1571         }
1572         return 0;
1573 }
1574
1575 int r100_cs_parse(struct radeon_cs_parser *p)
1576 {
1577         struct radeon_cs_packet pkt;
1578         struct r100_cs_track *track;
1579         int r;
1580
1581         track = kzalloc(sizeof(*track), GFP_KERNEL);
1582         r100_cs_track_clear(p->rdev, track);
1583         p->track = track;
1584         do {
1585                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1586                 if (r) {
1587                         return r;
1588                 }
1589                 p->idx += pkt.count + 2;
1590                 switch (pkt.type) {
1591                         case PACKET_TYPE0:
1592                                 if (p->rdev->family >= CHIP_R200)
1593                                         r = r100_cs_parse_packet0(p, &pkt,
1594                                                                   p->rdev->config.r100.reg_safe_bm,
1595                                                                   p->rdev->config.r100.reg_safe_bm_size,
1596                                                                   &r200_packet0_check);
1597                                 else
1598                                         r = r100_cs_parse_packet0(p, &pkt,
1599                                                                   p->rdev->config.r100.reg_safe_bm,
1600                                                                   p->rdev->config.r100.reg_safe_bm_size,
1601                                                                   &r100_packet0_check);
1602                                 break;
1603                         case PACKET_TYPE2:
1604                                 break;
1605                         case PACKET_TYPE3:
1606                                 r = r100_packet3_check(p, &pkt);
1607                                 break;
1608                         default:
1609                                 DRM_ERROR("Unknown packet type %d !\n",
1610                                           pkt.type);
1611                                 return -EINVAL;
1612                 }
1613                 if (r) {
1614                         return r;
1615                 }
1616         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1617         return 0;
1618 }
1619
1620
1621 /*
1622  * Global GPU functions
1623  */
1624 void r100_errata(struct radeon_device *rdev)
1625 {
1626         rdev->pll_errata = 0;
1627
1628         if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1629                 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1630         }
1631
1632         if (rdev->family == CHIP_RV100 ||
1633             rdev->family == CHIP_RS100 ||
1634             rdev->family == CHIP_RS200) {
1635                 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1636         }
1637 }
1638
1639 /* Wait for vertical sync on primary CRTC */
1640 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1641 {
1642         uint32_t crtc_gen_cntl, tmp;
1643         int i;
1644
1645         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1646         if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1647             !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1648                 return;
1649         }
1650         /* Clear the CRTC_VBLANK_SAVE bit */
1651         WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1652         for (i = 0; i < rdev->usec_timeout; i++) {
1653                 tmp = RREG32(RADEON_CRTC_STATUS);
1654                 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1655                         return;
1656                 }
1657                 DRM_UDELAY(1);
1658         }
1659 }
1660
1661 /* Wait for vertical sync on secondary CRTC */
1662 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1663 {
1664         uint32_t crtc2_gen_cntl, tmp;
1665         int i;
1666
1667         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1668         if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1669             !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1670                 return;
1671
1672         /* Clear the CRTC_VBLANK_SAVE bit */
1673         WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1674         for (i = 0; i < rdev->usec_timeout; i++) {
1675                 tmp = RREG32(RADEON_CRTC2_STATUS);
1676                 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1677                         return;
1678                 }
1679                 DRM_UDELAY(1);
1680         }
1681 }
1682
1683 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1684 {
1685         unsigned i;
1686         uint32_t tmp;
1687
1688         for (i = 0; i < rdev->usec_timeout; i++) {
1689                 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1690                 if (tmp >= n) {
1691                         return 0;
1692                 }
1693                 DRM_UDELAY(1);
1694         }
1695         return -1;
1696 }
1697
1698 int r100_gui_wait_for_idle(struct radeon_device *rdev)
1699 {
1700         unsigned i;
1701         uint32_t tmp;
1702
1703         if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1704                 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1705                        " Bad things might happen.\n");
1706         }
1707         for (i = 0; i < rdev->usec_timeout; i++) {
1708                 tmp = RREG32(RADEON_RBBM_STATUS);
1709                 if (!(tmp & RADEON_RBBM_ACTIVE)) {
1710                         return 0;
1711                 }
1712                 DRM_UDELAY(1);
1713         }
1714         return -1;
1715 }
1716
1717 int r100_mc_wait_for_idle(struct radeon_device *rdev)
1718 {
1719         unsigned i;
1720         uint32_t tmp;
1721
1722         for (i = 0; i < rdev->usec_timeout; i++) {
1723                 /* read MC_STATUS */
1724                 tmp = RREG32(RADEON_MC_STATUS);
1725                 if (tmp & RADEON_MC_IDLE) {
1726                         return 0;
1727                 }
1728                 DRM_UDELAY(1);
1729         }
1730         return -1;
1731 }
1732
1733 void r100_gpu_init(struct radeon_device *rdev)
1734 {
1735         /* TODO: anythings to do here ? pipes ? */
1736         r100_hdp_reset(rdev);
1737 }
1738
1739 void r100_hdp_reset(struct radeon_device *rdev)
1740 {
1741         uint32_t tmp;
1742
1743         tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
1744         tmp |= (7 << 28);
1745         WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
1746         (void)RREG32(RADEON_HOST_PATH_CNTL);
1747         udelay(200);
1748         WREG32(RADEON_RBBM_SOFT_RESET, 0);
1749         WREG32(RADEON_HOST_PATH_CNTL, tmp);
1750         (void)RREG32(RADEON_HOST_PATH_CNTL);
1751 }
1752
1753 int r100_rb2d_reset(struct radeon_device *rdev)
1754 {
1755         uint32_t tmp;
1756         int i;
1757
1758         WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2);
1759         (void)RREG32(RADEON_RBBM_SOFT_RESET);
1760         udelay(200);
1761         WREG32(RADEON_RBBM_SOFT_RESET, 0);
1762         /* Wait to prevent race in RBBM_STATUS */
1763         mdelay(1);
1764         for (i = 0; i < rdev->usec_timeout; i++) {
1765                 tmp = RREG32(RADEON_RBBM_STATUS);
1766                 if (!(tmp & (1 << 26))) {
1767                         DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
1768                                  tmp);
1769                         return 0;
1770                 }
1771                 DRM_UDELAY(1);
1772         }
1773         tmp = RREG32(RADEON_RBBM_STATUS);
1774         DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);
1775         return -1;
1776 }
1777
1778 int r100_gpu_reset(struct radeon_device *rdev)
1779 {
1780         uint32_t status;
1781
1782         /* reset order likely matter */
1783         status = RREG32(RADEON_RBBM_STATUS);
1784         /* reset HDP */
1785         r100_hdp_reset(rdev);
1786         /* reset rb2d */
1787         if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
1788                 r100_rb2d_reset(rdev);
1789         }
1790         /* TODO: reset 3D engine */
1791         /* reset CP */
1792         status = RREG32(RADEON_RBBM_STATUS);
1793         if (status & (1 << 16)) {
1794                 r100_cp_reset(rdev);
1795         }
1796         /* Check if GPU is idle */
1797         status = RREG32(RADEON_RBBM_STATUS);
1798         if (status & RADEON_RBBM_ACTIVE) {
1799                 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
1800                 return -1;
1801         }
1802         DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
1803         return 0;
1804 }
1805
1806 void r100_set_common_regs(struct radeon_device *rdev)
1807 {
1808         struct drm_device *dev = rdev->ddev;
1809         bool force_dac2 = false;
1810
1811         /* set these so they don't interfere with anything */
1812         WREG32(RADEON_OV0_SCALE_CNTL, 0);
1813         WREG32(RADEON_SUBPIC_CNTL, 0);
1814         WREG32(RADEON_VIPH_CONTROL, 0);
1815         WREG32(RADEON_I2C_CNTL_1, 0);
1816         WREG32(RADEON_DVI_I2C_CNTL_1, 0);
1817         WREG32(RADEON_CAP0_TRIG_CNTL, 0);
1818         WREG32(RADEON_CAP1_TRIG_CNTL, 0);
1819
1820         /* always set up dac2 on rn50 and some rv100 as lots
1821          * of servers seem to wire it up to a VGA port but
1822          * don't report it in the bios connector
1823          * table.
1824          */
1825         switch (dev->pdev->device) {
1826                 /* RN50 */
1827         case 0x515e:
1828         case 0x5969:
1829                 force_dac2 = true;
1830                 break;
1831                 /* RV100*/
1832         case 0x5159:
1833         case 0x515a:
1834                 /* DELL triple head servers */
1835                 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
1836                     ((dev->pdev->subsystem_device == 0x016c) ||
1837                      (dev->pdev->subsystem_device == 0x016d) ||
1838                      (dev->pdev->subsystem_device == 0x016e) ||
1839                      (dev->pdev->subsystem_device == 0x016f) ||
1840                      (dev->pdev->subsystem_device == 0x0170) ||
1841                      (dev->pdev->subsystem_device == 0x017d) ||
1842                      (dev->pdev->subsystem_device == 0x017e) ||
1843                      (dev->pdev->subsystem_device == 0x0183) ||
1844                      (dev->pdev->subsystem_device == 0x018a) ||
1845                      (dev->pdev->subsystem_device == 0x019a)))
1846                         force_dac2 = true;
1847                 break;
1848         }
1849
1850         if (force_dac2) {
1851                 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1852                 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1853                 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
1854
1855                 /* For CRT on DAC2, don't turn it on if BIOS didn't
1856                    enable it, even it's detected.
1857                 */
1858
1859                 /* force it to crtc0 */
1860                 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
1861                 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
1862                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1863
1864                 /* set up the TV DAC */
1865                 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
1866                                  RADEON_TV_DAC_STD_MASK |
1867                                  RADEON_TV_DAC_RDACPD |
1868                                  RADEON_TV_DAC_GDACPD |
1869                                  RADEON_TV_DAC_BDACPD |
1870                                  RADEON_TV_DAC_BGADJ_MASK |
1871                                  RADEON_TV_DAC_DACADJ_MASK);
1872                 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
1873                                 RADEON_TV_DAC_NHOLD |
1874                                 RADEON_TV_DAC_STD_PS2 |
1875                                 (0x58 << 16));
1876
1877                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1878                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1879                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1880         }
1881 }
1882
1883 /*
1884  * VRAM info
1885  */
1886 static void r100_vram_get_type(struct radeon_device *rdev)
1887 {
1888         uint32_t tmp;
1889
1890         rdev->mc.vram_is_ddr = false;
1891         if (rdev->flags & RADEON_IS_IGP)
1892                 rdev->mc.vram_is_ddr = true;
1893         else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
1894                 rdev->mc.vram_is_ddr = true;
1895         if ((rdev->family == CHIP_RV100) ||
1896             (rdev->family == CHIP_RS100) ||
1897             (rdev->family == CHIP_RS200)) {
1898                 tmp = RREG32(RADEON_MEM_CNTL);
1899                 if (tmp & RV100_HALF_MODE) {
1900                         rdev->mc.vram_width = 32;
1901                 } else {
1902                         rdev->mc.vram_width = 64;
1903                 }
1904                 if (rdev->flags & RADEON_SINGLE_CRTC) {
1905                         rdev->mc.vram_width /= 4;
1906                         rdev->mc.vram_is_ddr = true;
1907                 }
1908         } else if (rdev->family <= CHIP_RV280) {
1909                 tmp = RREG32(RADEON_MEM_CNTL);
1910                 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
1911                         rdev->mc.vram_width = 128;
1912                 } else {
1913                         rdev->mc.vram_width = 64;
1914                 }
1915         } else {
1916                 /* newer IGPs */
1917                 rdev->mc.vram_width = 128;
1918         }
1919 }
1920
1921 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
1922 {
1923         u32 aper_size;
1924         u8 byte;
1925
1926         aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1927
1928         /* Set HDP_APER_CNTL only on cards that are known not to be broken,
1929          * that is has the 2nd generation multifunction PCI interface
1930          */
1931         if (rdev->family == CHIP_RV280 ||
1932             rdev->family >= CHIP_RV350) {
1933                 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
1934                        ~RADEON_HDP_APER_CNTL);
1935                 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
1936                 return aper_size * 2;
1937         }
1938
1939         /* Older cards have all sorts of funny issues to deal with. First
1940          * check if it's a multifunction card by reading the PCI config
1941          * header type... Limit those to one aperture size
1942          */
1943         pci_read_config_byte(rdev->pdev, 0xe, &byte);
1944         if (byte & 0x80) {
1945                 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
1946                 DRM_INFO("Limiting VRAM to one aperture\n");
1947                 return aper_size;
1948         }
1949
1950         /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
1951          * have set it up. We don't write this as it's broken on some ASICs but
1952          * we expect the BIOS to have done the right thing (might be too optimistic...)
1953          */
1954         if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
1955                 return aper_size * 2;
1956         return aper_size;
1957 }
1958
1959 void r100_vram_init_sizes(struct radeon_device *rdev)
1960 {
1961         u64 config_aper_size;
1962
1963         /* work out accessible VRAM */
1964         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1965         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1966         rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
1967         /* FIXME we don't use the second aperture yet when we could use it */
1968         if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
1969                 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1970         config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1971         if (rdev->flags & RADEON_IS_IGP) {
1972                 uint32_t tom;
1973                 /* read NB_TOM to get the amount of ram stolen for the GPU */
1974                 tom = RREG32(RADEON_NB_TOM);
1975                 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
1976                 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1977                 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1978         } else {
1979                 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
1980                 /* Some production boards of m6 will report 0
1981                  * if it's 8 MB
1982                  */
1983                 if (rdev->mc.real_vram_size == 0) {
1984                         rdev->mc.real_vram_size = 8192 * 1024;
1985                         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1986                 }
1987                 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - 
1988                  * Novell bug 204882 + along with lots of ubuntu ones
1989                  */
1990                 if (config_aper_size > rdev->mc.real_vram_size)
1991                         rdev->mc.mc_vram_size = config_aper_size;
1992                 else
1993                         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1994         }
1995         /* FIXME remove this once we support unmappable VRAM */
1996         if (rdev->mc.mc_vram_size > rdev->mc.aper_size) {
1997                 rdev->mc.mc_vram_size = rdev->mc.aper_size;
1998                 rdev->mc.real_vram_size = rdev->mc.aper_size;
1999         }
2000 }
2001
2002 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2003 {
2004         uint32_t temp;
2005
2006         temp = RREG32(RADEON_CONFIG_CNTL);
2007         if (state == false) {
2008                 temp &= ~(1<<8);
2009                 temp |= (1<<9);
2010         } else {
2011                 temp &= ~(1<<9);
2012         }
2013         WREG32(RADEON_CONFIG_CNTL, temp);
2014 }
2015
2016 void r100_mc_init(struct radeon_device *rdev)
2017 {
2018         u64 base;
2019
2020         r100_vram_get_type(rdev);
2021         r100_vram_init_sizes(rdev);
2022         base = rdev->mc.aper_base;
2023         if (rdev->flags & RADEON_IS_IGP)
2024                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2025         radeon_vram_location(rdev, &rdev->mc, base);
2026         if (!(rdev->flags & RADEON_IS_AGP))
2027                 radeon_gtt_location(rdev, &rdev->mc);
2028         radeon_update_bandwidth_info(rdev);
2029 }
2030
2031
2032 /*
2033  * Indirect registers accessor
2034  */
2035 void r100_pll_errata_after_index(struct radeon_device *rdev)
2036 {
2037         if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
2038                 return;
2039         }
2040         (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2041         (void)RREG32(RADEON_CRTC_GEN_CNTL);
2042 }
2043
2044 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2045 {
2046         /* This workarounds is necessary on RV100, RS100 and RS200 chips
2047          * or the chip could hang on a subsequent access
2048          */
2049         if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2050                 udelay(5000);
2051         }
2052
2053         /* This function is required to workaround a hardware bug in some (all?)
2054          * revisions of the R300.  This workaround should be called after every
2055          * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
2056          * may not be correct.
2057          */
2058         if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2059                 uint32_t save, tmp;
2060
2061                 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2062                 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2063                 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2064                 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2065                 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2066         }
2067 }
2068
2069 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2070 {
2071         uint32_t data;
2072
2073         WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2074         r100_pll_errata_after_index(rdev);
2075         data = RREG32(RADEON_CLOCK_CNTL_DATA);
2076         r100_pll_errata_after_data(rdev);
2077         return data;
2078 }
2079
2080 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2081 {
2082         WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2083         r100_pll_errata_after_index(rdev);
2084         WREG32(RADEON_CLOCK_CNTL_DATA, v);
2085         r100_pll_errata_after_data(rdev);
2086 }
2087
2088 void r100_set_safe_registers(struct radeon_device *rdev)
2089 {
2090         if (ASIC_IS_RN50(rdev)) {
2091                 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2092                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2093         } else if (rdev->family < CHIP_R200) {
2094                 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2095                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2096         } else {
2097                 r200_set_safe_registers(rdev);
2098         }
2099 }
2100
2101 /*
2102  * Debugfs info
2103  */
2104 #if defined(CONFIG_DEBUG_FS)
2105 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2106 {
2107         struct drm_info_node *node = (struct drm_info_node *) m->private;
2108         struct drm_device *dev = node->minor->dev;
2109         struct radeon_device *rdev = dev->dev_private;
2110         uint32_t reg, value;
2111         unsigned i;
2112
2113         seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2114         seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2115         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2116         for (i = 0; i < 64; i++) {
2117                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2118                 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2119                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2120                 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2121                 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2122         }
2123         return 0;
2124 }
2125
2126 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2127 {
2128         struct drm_info_node *node = (struct drm_info_node *) m->private;
2129         struct drm_device *dev = node->minor->dev;
2130         struct radeon_device *rdev = dev->dev_private;
2131         uint32_t rdp, wdp;
2132         unsigned count, i, j;
2133
2134         radeon_ring_free_size(rdev);
2135         rdp = RREG32(RADEON_CP_RB_RPTR);
2136         wdp = RREG32(RADEON_CP_RB_WPTR);
2137         count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2138         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2139         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2140         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2141         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2142         seq_printf(m, "%u dwords in ring\n", count);
2143         for (j = 0; j <= count; j++) {
2144                 i = (rdp + j) & rdev->cp.ptr_mask;
2145                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2146         }
2147         return 0;
2148 }
2149
2150
2151 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2152 {
2153         struct drm_info_node *node = (struct drm_info_node *) m->private;
2154         struct drm_device *dev = node->minor->dev;
2155         struct radeon_device *rdev = dev->dev_private;
2156         uint32_t csq_stat, csq2_stat, tmp;
2157         unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2158         unsigned i;
2159
2160         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2161         seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2162         csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2163         csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2164         r_rptr = (csq_stat >> 0) & 0x3ff;
2165         r_wptr = (csq_stat >> 10) & 0x3ff;
2166         ib1_rptr = (csq_stat >> 20) & 0x3ff;
2167         ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2168         ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2169         ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2170         seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2171         seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2172         seq_printf(m, "Ring rptr %u\n", r_rptr);
2173         seq_printf(m, "Ring wptr %u\n", r_wptr);
2174         seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2175         seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2176         seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2177         seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2178         /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2179          * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2180         seq_printf(m, "Ring fifo:\n");
2181         for (i = 0; i < 256; i++) {
2182                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2183                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2184                 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2185         }
2186         seq_printf(m, "Indirect1 fifo:\n");
2187         for (i = 256; i <= 512; i++) {
2188                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2189                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2190                 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2191         }
2192         seq_printf(m, "Indirect2 fifo:\n");
2193         for (i = 640; i < ib1_wptr; i++) {
2194                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2195                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2196                 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2197         }
2198         return 0;
2199 }
2200
2201 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2202 {
2203         struct drm_info_node *node = (struct drm_info_node *) m->private;
2204         struct drm_device *dev = node->minor->dev;
2205         struct radeon_device *rdev = dev->dev_private;
2206         uint32_t tmp;
2207
2208         tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2209         seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2210         tmp = RREG32(RADEON_MC_FB_LOCATION);
2211         seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2212         tmp = RREG32(RADEON_BUS_CNTL);
2213         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2214         tmp = RREG32(RADEON_MC_AGP_LOCATION);
2215         seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2216         tmp = RREG32(RADEON_AGP_BASE);
2217         seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2218         tmp = RREG32(RADEON_HOST_PATH_CNTL);
2219         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2220         tmp = RREG32(0x01D0);
2221         seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2222         tmp = RREG32(RADEON_AIC_LO_ADDR);
2223         seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2224         tmp = RREG32(RADEON_AIC_HI_ADDR);
2225         seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2226         tmp = RREG32(0x01E4);
2227         seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2228         return 0;
2229 }
2230
2231 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2232         {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2233 };
2234
2235 static struct drm_info_list r100_debugfs_cp_list[] = {
2236         {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2237         {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2238 };
2239
2240 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2241         {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2242 };
2243 #endif
2244
2245 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2246 {
2247 #if defined(CONFIG_DEBUG_FS)
2248         return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2249 #else
2250         return 0;
2251 #endif
2252 }
2253
2254 int r100_debugfs_cp_init(struct radeon_device *rdev)
2255 {
2256 #if defined(CONFIG_DEBUG_FS)
2257         return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2258 #else
2259         return 0;
2260 #endif
2261 }
2262
2263 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2264 {
2265 #if defined(CONFIG_DEBUG_FS)
2266         return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2267 #else
2268         return 0;
2269 #endif
2270 }
2271
2272 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2273                          uint32_t tiling_flags, uint32_t pitch,
2274                          uint32_t offset, uint32_t obj_size)
2275 {
2276         int surf_index = reg * 16;
2277         int flags = 0;
2278
2279         /* r100/r200 divide by 16 */
2280         if (rdev->family < CHIP_R300)
2281                 flags = pitch / 16;
2282         else
2283                 flags = pitch / 8;
2284
2285         if (rdev->family <= CHIP_RS200) {
2286                 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2287                                  == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2288                         flags |= RADEON_SURF_TILE_COLOR_BOTH;
2289                 if (tiling_flags & RADEON_TILING_MACRO)
2290                         flags |= RADEON_SURF_TILE_COLOR_MACRO;
2291         } else if (rdev->family <= CHIP_RV280) {
2292                 if (tiling_flags & (RADEON_TILING_MACRO))
2293                         flags |= R200_SURF_TILE_COLOR_MACRO;
2294                 if (tiling_flags & RADEON_TILING_MICRO)
2295                         flags |= R200_SURF_TILE_COLOR_MICRO;
2296         } else {
2297                 if (tiling_flags & RADEON_TILING_MACRO)
2298                         flags |= R300_SURF_TILE_MACRO;
2299                 if (tiling_flags & RADEON_TILING_MICRO)
2300                         flags |= R300_SURF_TILE_MICRO;
2301         }
2302
2303         if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2304                 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2305         if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2306                 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2307
2308         DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2309         WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2310         WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2311         WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2312         return 0;
2313 }
2314
2315 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2316 {
2317         int surf_index = reg * 16;
2318         WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2319 }
2320
2321 void r100_bandwidth_update(struct radeon_device *rdev)
2322 {
2323         fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2324         fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2325         fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2326         uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2327         fixed20_12 memtcas_ff[8] = {
2328                 fixed_init(1),
2329                 fixed_init(2),
2330                 fixed_init(3),
2331                 fixed_init(0),
2332                 fixed_init_half(1),
2333                 fixed_init_half(2),
2334                 fixed_init(0),
2335         };
2336         fixed20_12 memtcas_rs480_ff[8] = {
2337                 fixed_init(0),
2338                 fixed_init(1),
2339                 fixed_init(2),
2340                 fixed_init(3),
2341                 fixed_init(0),
2342                 fixed_init_half(1),
2343                 fixed_init_half(2),
2344                 fixed_init_half(3),
2345         };
2346         fixed20_12 memtcas2_ff[8] = {
2347                 fixed_init(0),
2348                 fixed_init(1),
2349                 fixed_init(2),
2350                 fixed_init(3),
2351                 fixed_init(4),
2352                 fixed_init(5),
2353                 fixed_init(6),
2354                 fixed_init(7),
2355         };
2356         fixed20_12 memtrbs[8] = {
2357                 fixed_init(1),
2358                 fixed_init_half(1),
2359                 fixed_init(2),
2360                 fixed_init_half(2),
2361                 fixed_init(3),
2362                 fixed_init_half(3),
2363                 fixed_init(4),
2364                 fixed_init_half(4)
2365         };
2366         fixed20_12 memtrbs_r4xx[8] = {
2367                 fixed_init(4),
2368                 fixed_init(5),
2369                 fixed_init(6),
2370                 fixed_init(7),
2371                 fixed_init(8),
2372                 fixed_init(9),
2373                 fixed_init(10),
2374                 fixed_init(11)
2375         };
2376         fixed20_12 min_mem_eff;
2377         fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2378         fixed20_12 cur_latency_mclk, cur_latency_sclk;
2379         fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2380                 disp_drain_rate2, read_return_rate;
2381         fixed20_12 time_disp1_drop_priority;
2382         int c;
2383         int cur_size = 16;       /* in octawords */
2384         int critical_point = 0, critical_point2;
2385 /*      uint32_t read_return_rate, time_disp1_drop_priority; */
2386         int stop_req, max_stop_req;
2387         struct drm_display_mode *mode1 = NULL;
2388         struct drm_display_mode *mode2 = NULL;
2389         uint32_t pixel_bytes1 = 0;
2390         uint32_t pixel_bytes2 = 0;
2391
2392         if (rdev->mode_info.crtcs[0]->base.enabled) {
2393                 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2394                 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2395         }
2396         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2397                 if (rdev->mode_info.crtcs[1]->base.enabled) {
2398                         mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2399                         pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2400                 }
2401         }
2402
2403         min_mem_eff.full = rfixed_const_8(0);
2404         /* get modes */
2405         if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2406                 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2407                 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2408                 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2409                 /* check crtc enables */
2410                 if (mode2)
2411                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2412                 if (mode1)
2413                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2414                 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2415         }
2416
2417         /*
2418          * determine is there is enough bw for current mode
2419          */
2420         sclk_ff = rdev->pm.sclk;
2421         mclk_ff = rdev->pm.mclk;
2422
2423         temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2424         temp_ff.full = rfixed_const(temp);
2425         mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
2426
2427         pix_clk.full = 0;
2428         pix_clk2.full = 0;
2429         peak_disp_bw.full = 0;
2430         if (mode1) {
2431                 temp_ff.full = rfixed_const(1000);
2432                 pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
2433                 pix_clk.full = rfixed_div(pix_clk, temp_ff);
2434                 temp_ff.full = rfixed_const(pixel_bytes1);
2435                 peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
2436         }
2437         if (mode2) {
2438                 temp_ff.full = rfixed_const(1000);
2439                 pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
2440                 pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
2441                 temp_ff.full = rfixed_const(pixel_bytes2);
2442                 peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
2443         }
2444
2445         mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
2446         if (peak_disp_bw.full >= mem_bw.full) {
2447                 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2448                           "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2449         }
2450
2451         /*  Get values from the EXT_MEM_CNTL register...converting its contents. */
2452         temp = RREG32(RADEON_MEM_TIMING_CNTL);
2453         if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2454                 mem_trcd = ((temp >> 2) & 0x3) + 1;
2455                 mem_trp  = ((temp & 0x3)) + 1;
2456                 mem_tras = ((temp & 0x70) >> 4) + 1;
2457         } else if (rdev->family == CHIP_R300 ||
2458                    rdev->family == CHIP_R350) { /* r300, r350 */
2459                 mem_trcd = (temp & 0x7) + 1;
2460                 mem_trp = ((temp >> 8) & 0x7) + 1;
2461                 mem_tras = ((temp >> 11) & 0xf) + 4;
2462         } else if (rdev->family == CHIP_RV350 ||
2463                    rdev->family <= CHIP_RV380) {
2464                 /* rv3x0 */
2465                 mem_trcd = (temp & 0x7) + 3;
2466                 mem_trp = ((temp >> 8) & 0x7) + 3;
2467                 mem_tras = ((temp >> 11) & 0xf) + 6;
2468         } else if (rdev->family == CHIP_R420 ||
2469                    rdev->family == CHIP_R423 ||
2470                    rdev->family == CHIP_RV410) {
2471                 /* r4xx */
2472                 mem_trcd = (temp & 0xf) + 3;
2473                 if (mem_trcd > 15)
2474                         mem_trcd = 15;
2475                 mem_trp = ((temp >> 8) & 0xf) + 3;
2476                 if (mem_trp > 15)
2477                         mem_trp = 15;
2478                 mem_tras = ((temp >> 12) & 0x1f) + 6;
2479                 if (mem_tras > 31)
2480                         mem_tras = 31;
2481         } else { /* RV200, R200 */
2482                 mem_trcd = (temp & 0x7) + 1;
2483                 mem_trp = ((temp >> 8) & 0x7) + 1;
2484                 mem_tras = ((temp >> 12) & 0xf) + 4;
2485         }
2486         /* convert to FF */
2487         trcd_ff.full = rfixed_const(mem_trcd);
2488         trp_ff.full = rfixed_const(mem_trp);
2489         tras_ff.full = rfixed_const(mem_tras);
2490
2491         /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2492         temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2493         data = (temp & (7 << 20)) >> 20;
2494         if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2495                 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2496                         tcas_ff = memtcas_rs480_ff[data];
2497                 else
2498                         tcas_ff = memtcas_ff[data];
2499         } else
2500                 tcas_ff = memtcas2_ff[data];
2501
2502         if (rdev->family == CHIP_RS400 ||
2503             rdev->family == CHIP_RS480) {
2504                 /* extra cas latency stored in bits 23-25 0-4 clocks */
2505                 data = (temp >> 23) & 0x7;
2506                 if (data < 5)
2507                         tcas_ff.full += rfixed_const(data);
2508         }
2509
2510         if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2511                 /* on the R300, Tcas is included in Trbs.
2512                  */
2513                 temp = RREG32(RADEON_MEM_CNTL);
2514                 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2515                 if (data == 1) {
2516                         if (R300_MEM_USE_CD_CH_ONLY & temp) {
2517                                 temp = RREG32(R300_MC_IND_INDEX);
2518                                 temp &= ~R300_MC_IND_ADDR_MASK;
2519                                 temp |= R300_MC_READ_CNTL_CD_mcind;
2520                                 WREG32(R300_MC_IND_INDEX, temp);
2521                                 temp = RREG32(R300_MC_IND_DATA);
2522                                 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2523                         } else {
2524                                 temp = RREG32(R300_MC_READ_CNTL_AB);
2525                                 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2526                         }
2527                 } else {
2528                         temp = RREG32(R300_MC_READ_CNTL_AB);
2529                         data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2530                 }
2531                 if (rdev->family == CHIP_RV410 ||
2532                     rdev->family == CHIP_R420 ||
2533                     rdev->family == CHIP_R423)
2534                         trbs_ff = memtrbs_r4xx[data];
2535                 else
2536                         trbs_ff = memtrbs[data];
2537                 tcas_ff.full += trbs_ff.full;
2538         }
2539
2540         sclk_eff_ff.full = sclk_ff.full;
2541
2542         if (rdev->flags & RADEON_IS_AGP) {
2543                 fixed20_12 agpmode_ff;
2544                 agpmode_ff.full = rfixed_const(radeon_agpmode);
2545                 temp_ff.full = rfixed_const_666(16);
2546                 sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
2547         }
2548         /* TODO PCIE lanes may affect this - agpmode == 16?? */
2549
2550         if (ASIC_IS_R300(rdev)) {
2551                 sclk_delay_ff.full = rfixed_const(250);
2552         } else {
2553                 if ((rdev->family == CHIP_RV100) ||
2554                     rdev->flags & RADEON_IS_IGP) {
2555                         if (rdev->mc.vram_is_ddr)
2556                                 sclk_delay_ff.full = rfixed_const(41);
2557                         else
2558                                 sclk_delay_ff.full = rfixed_const(33);
2559                 } else {
2560                         if (rdev->mc.vram_width == 128)
2561                                 sclk_delay_ff.full = rfixed_const(57);
2562                         else
2563                                 sclk_delay_ff.full = rfixed_const(41);
2564                 }
2565         }
2566
2567         mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
2568
2569         if (rdev->mc.vram_is_ddr) {
2570                 if (rdev->mc.vram_width == 32) {
2571                         k1.full = rfixed_const(40);
2572                         c  = 3;
2573                 } else {
2574                         k1.full = rfixed_const(20);
2575                         c  = 1;
2576                 }
2577         } else {
2578                 k1.full = rfixed_const(40);
2579                 c  = 3;
2580         }
2581
2582         temp_ff.full = rfixed_const(2);
2583         mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
2584         temp_ff.full = rfixed_const(c);
2585         mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
2586         temp_ff.full = rfixed_const(4);
2587         mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
2588         mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
2589         mc_latency_mclk.full += k1.full;
2590
2591         mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
2592         mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
2593
2594         /*
2595           HW cursor time assuming worst case of full size colour cursor.
2596         */
2597         temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2598         temp_ff.full += trcd_ff.full;
2599         if (temp_ff.full < tras_ff.full)
2600                 temp_ff.full = tras_ff.full;
2601         cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
2602
2603         temp_ff.full = rfixed_const(cur_size);
2604         cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
2605         /*
2606           Find the total latency for the display data.
2607         */
2608         disp_latency_overhead.full = rfixed_const(8);
2609         disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
2610         mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2611         mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2612
2613         if (mc_latency_mclk.full > mc_latency_sclk.full)
2614                 disp_latency.full = mc_latency_mclk.full;
2615         else
2616                 disp_latency.full = mc_latency_sclk.full;
2617
2618         /* setup Max GRPH_STOP_REQ default value */
2619         if (ASIC_IS_RV100(rdev))
2620                 max_stop_req = 0x5c;
2621         else
2622                 max_stop_req = 0x7c;
2623
2624         if (mode1) {
2625                 /*  CRTC1
2626                     Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2627                     GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2628                 */
2629                 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2630
2631                 if (stop_req > max_stop_req)
2632                         stop_req = max_stop_req;
2633
2634                 /*
2635                   Find the drain rate of the display buffer.
2636                 */
2637                 temp_ff.full = rfixed_const((16/pixel_bytes1));
2638                 disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
2639
2640                 /*
2641                   Find the critical point of the display buffer.
2642                 */
2643                 crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
2644                 crit_point_ff.full += rfixed_const_half(0);
2645
2646                 critical_point = rfixed_trunc(crit_point_ff);
2647
2648                 if (rdev->disp_priority == 2) {
2649                         critical_point = 0;
2650                 }
2651
2652                 /*
2653                   The critical point should never be above max_stop_req-4.  Setting
2654                   GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2655                 */
2656                 if (max_stop_req - critical_point < 4)
2657                         critical_point = 0;
2658
2659                 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
2660                         /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
2661                         critical_point = 0x10;
2662                 }
2663
2664                 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
2665                 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
2666                 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2667                 temp &= ~(RADEON_GRPH_START_REQ_MASK);
2668                 if ((rdev->family == CHIP_R350) &&
2669                     (stop_req > 0x15)) {
2670                         stop_req -= 0x10;
2671                 }
2672                 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2673                 temp |= RADEON_GRPH_BUFFER_SIZE;
2674                 temp &= ~(RADEON_GRPH_CRITICAL_CNTL   |
2675                           RADEON_GRPH_CRITICAL_AT_SOF |
2676                           RADEON_GRPH_STOP_CNTL);
2677                 /*
2678                   Write the result into the register.
2679                 */
2680                 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2681                                                        (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2682
2683 #if 0
2684                 if ((rdev->family == CHIP_RS400) ||
2685                     (rdev->family == CHIP_RS480)) {
2686                         /* attempt to program RS400 disp regs correctly ??? */
2687                         temp = RREG32(RS400_DISP1_REG_CNTL);
2688                         temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
2689                                   RS400_DISP1_STOP_REQ_LEVEL_MASK);
2690                         WREG32(RS400_DISP1_REQ_CNTL1, (temp |
2691                                                        (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2692                                                        (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2693                         temp = RREG32(RS400_DMIF_MEM_CNTL1);
2694                         temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
2695                                   RS400_DISP1_CRITICAL_POINT_STOP_MASK);
2696                         WREG32(RS400_DMIF_MEM_CNTL1, (temp |
2697                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
2698                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
2699                 }
2700 #endif
2701
2702                 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
2703                           /*      (unsigned int)info->SavedReg->grph_buffer_cntl, */
2704                           (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
2705         }
2706
2707         if (mode2) {
2708                 u32 grph2_cntl;
2709                 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
2710
2711                 if (stop_req > max_stop_req)
2712                         stop_req = max_stop_req;
2713
2714                 /*
2715                   Find the drain rate of the display buffer.
2716                 */
2717                 temp_ff.full = rfixed_const((16/pixel_bytes2));
2718                 disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
2719
2720                 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
2721                 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
2722                 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2723                 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
2724                 if ((rdev->family == CHIP_R350) &&
2725                     (stop_req > 0x15)) {
2726                         stop_req -= 0x10;
2727                 }
2728                 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2729                 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
2730                 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL   |
2731                           RADEON_GRPH_CRITICAL_AT_SOF |
2732                           RADEON_GRPH_STOP_CNTL);
2733
2734                 if ((rdev->family == CHIP_RS100) ||
2735                     (rdev->family == CHIP_RS200))
2736                         critical_point2 = 0;
2737                 else {
2738                         temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
2739                         temp_ff.full = rfixed_const(temp);
2740                         temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
2741                         if (sclk_ff.full < temp_ff.full)
2742                                 temp_ff.full = sclk_ff.full;
2743
2744                         read_return_rate.full = temp_ff.full;
2745
2746                         if (mode1) {
2747                                 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
2748                                 time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
2749                         } else {
2750                                 time_disp1_drop_priority.full = 0;
2751                         }
2752                         crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
2753                         crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
2754                         crit_point_ff.full += rfixed_const_half(0);
2755
2756                         critical_point2 = rfixed_trunc(crit_point_ff);
2757
2758                         if (rdev->disp_priority == 2) {
2759                                 critical_point2 = 0;
2760                         }
2761
2762                         if (max_stop_req - critical_point2 < 4)
2763                                 critical_point2 = 0;
2764
2765                 }
2766
2767                 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
2768                         /* some R300 cards have problem with this set to 0 */
2769                         critical_point2 = 0x10;
2770                 }
2771
2772                 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2773                                                   (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2774
2775                 if ((rdev->family == CHIP_RS400) ||
2776                     (rdev->family == CHIP_RS480)) {
2777 #if 0
2778                         /* attempt to program RS400 disp2 regs correctly ??? */
2779                         temp = RREG32(RS400_DISP2_REQ_CNTL1);
2780                         temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
2781                                   RS400_DISP2_STOP_REQ_LEVEL_MASK);
2782                         WREG32(RS400_DISP2_REQ_CNTL1, (temp |
2783                                                        (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2784                                                        (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2785                         temp = RREG32(RS400_DISP2_REQ_CNTL2);
2786                         temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
2787                                   RS400_DISP2_CRITICAL_POINT_STOP_MASK);
2788                         WREG32(RS400_DISP2_REQ_CNTL2, (temp |
2789                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
2790                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
2791 #endif
2792                         WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
2793                         WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
2794                         WREG32(RS400_DMIF_MEM_CNTL1,  0x29CA71DC);
2795                         WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
2796                 }
2797
2798                 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
2799                           (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
2800         }
2801 }
2802
2803 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2804 {
2805         DRM_ERROR("pitch                      %d\n", t->pitch);
2806         DRM_ERROR("use_pitch                  %d\n", t->use_pitch);
2807         DRM_ERROR("width                      %d\n", t->width);
2808         DRM_ERROR("width_11                   %d\n", t->width_11);
2809         DRM_ERROR("height                     %d\n", t->height);
2810         DRM_ERROR("height_11                  %d\n", t->height_11);
2811         DRM_ERROR("num levels                 %d\n", t->num_levels);
2812         DRM_ERROR("depth                      %d\n", t->txdepth);
2813         DRM_ERROR("bpp                        %d\n", t->cpp);
2814         DRM_ERROR("coordinate type            %d\n", t->tex_coord_type);
2815         DRM_ERROR("width round to power of 2  %d\n", t->roundup_w);
2816         DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2817         DRM_ERROR("compress format            %d\n", t->compress_format);
2818 }
2819
2820 static int r100_cs_track_cube(struct radeon_device *rdev,
2821                               struct r100_cs_track *track, unsigned idx)
2822 {
2823         unsigned face, w, h;
2824         struct radeon_bo *cube_robj;
2825         unsigned long size;
2826
2827         for (face = 0; face < 5; face++) {
2828                 cube_robj = track->textures[idx].cube_info[face].robj;
2829                 w = track->textures[idx].cube_info[face].width;
2830                 h = track->textures[idx].cube_info[face].height;
2831
2832                 size = w * h;
2833                 size *= track->textures[idx].cpp;
2834
2835                 size += track->textures[idx].cube_info[face].offset;
2836
2837                 if (size > radeon_bo_size(cube_robj)) {
2838                         DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2839                                   size, radeon_bo_size(cube_robj));
2840                         r100_cs_track_texture_print(&track->textures[idx]);
2841                         return -1;
2842                 }
2843         }
2844         return 0;
2845 }
2846
2847 static int r100_track_compress_size(int compress_format, int w, int h)
2848 {
2849         int block_width, block_height, block_bytes;
2850         int wblocks, hblocks;
2851         int min_wblocks;
2852         int sz;
2853
2854         block_width = 4;
2855         block_height = 4;
2856
2857         switch (compress_format) {
2858         case R100_TRACK_COMP_DXT1:
2859                 block_bytes = 8;
2860                 min_wblocks = 4;
2861                 break;
2862         default:
2863         case R100_TRACK_COMP_DXT35:
2864                 block_bytes = 16;
2865                 min_wblocks = 2;
2866                 break;
2867         }
2868
2869         hblocks = (h + block_height - 1) / block_height;
2870         wblocks = (w + block_width - 1) / block_width;
2871         if (wblocks < min_wblocks)
2872                 wblocks = min_wblocks;
2873         sz = wblocks * hblocks * block_bytes;
2874         return sz;
2875 }
2876
2877 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2878                                        struct r100_cs_track *track)
2879 {
2880         struct radeon_bo *robj;
2881         unsigned long size;
2882         unsigned u, i, w, h;
2883         int ret;
2884
2885         for (u = 0; u < track->num_texture; u++) {
2886                 if (!track->textures[u].enabled)
2887                         continue;
2888                 robj = track->textures[u].robj;
2889                 if (robj == NULL) {
2890                         DRM_ERROR("No texture bound to unit %u\n", u);
2891                         return -EINVAL;
2892                 }
2893                 size = 0;
2894                 for (i = 0; i <= track->textures[u].num_levels; i++) {
2895                         if (track->textures[u].use_pitch) {
2896                                 if (rdev->family < CHIP_R300)
2897                                         w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2898                                 else
2899                                         w = track->textures[u].pitch / (1 << i);
2900                         } else {
2901                                 w = track->textures[u].width;
2902                                 if (rdev->family >= CHIP_RV515)
2903                                         w |= track->textures[u].width_11;
2904                                 w = w / (1 << i);
2905                                 if (track->textures[u].roundup_w)
2906                                         w = roundup_pow_of_two(w);
2907                         }
2908                         h = track->textures[u].height;
2909                         if (rdev->family >= CHIP_RV515)
2910                                 h |= track->textures[u].height_11;
2911                         h = h / (1 << i);
2912                         if (track->textures[u].roundup_h)
2913                                 h = roundup_pow_of_two(h);
2914                         if (track->textures[u].compress_format) {
2915
2916                                 size += r100_track_compress_size(track->textures[u].compress_format, w, h);
2917                                 /* compressed textures are block based */
2918                         } else
2919                                 size += w * h;
2920                 }
2921                 size *= track->textures[u].cpp;
2922
2923                 switch (track->textures[u].tex_coord_type) {
2924                 case 0:
2925                         break;
2926                 case 1:
2927                         size *= (1 << track->textures[u].txdepth);
2928                         break;
2929                 case 2:
2930                         if (track->separate_cube) {
2931                                 ret = r100_cs_track_cube(rdev, track, u);
2932                                 if (ret)
2933                                         return ret;
2934                         } else
2935                                 size *= 6;
2936                         break;
2937                 default:
2938                         DRM_ERROR("Invalid texture coordinate type %u for unit "
2939                                   "%u\n", track->textures[u].tex_coord_type, u);
2940                         return -EINVAL;
2941                 }
2942                 if (size > radeon_bo_size(robj)) {
2943                         DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2944                                   "%lu\n", u, size, radeon_bo_size(robj));
2945                         r100_cs_track_texture_print(&track->textures[u]);
2946                         return -EINVAL;
2947                 }
2948         }
2949         return 0;
2950 }
2951
2952 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2953 {
2954         unsigned i;
2955         unsigned long size;
2956         unsigned prim_walk;
2957         unsigned nverts;
2958
2959         for (i = 0; i < track->num_cb; i++) {
2960                 if (track->cb[i].robj == NULL) {
2961                         if (!(track->fastfill || track->color_channel_mask ||
2962                               track->blend_read_enable)) {
2963                                 continue;
2964                         }
2965                         DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2966                         return -EINVAL;
2967                 }
2968                 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2969                 size += track->cb[i].offset;
2970                 if (size > radeon_bo_size(track->cb[i].robj)) {
2971                         DRM_ERROR("[drm] Buffer too small for color buffer %d "
2972                                   "(need %lu have %lu) !\n", i, size,
2973                                   radeon_bo_size(track->cb[i].robj));
2974                         DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2975                                   i, track->cb[i].pitch, track->cb[i].cpp,
2976                                   track->cb[i].offset, track->maxy);
2977                         return -EINVAL;
2978                 }
2979         }
2980         if (track->z_enabled) {
2981                 if (track->zb.robj == NULL) {
2982                         DRM_ERROR("[drm] No buffer for z buffer !\n");
2983                         return -EINVAL;
2984                 }
2985                 size = track->zb.pitch * track->zb.cpp * track->maxy;
2986                 size += track->zb.offset;
2987                 if (size > radeon_bo_size(track->zb.robj)) {
2988                         DRM_ERROR("[drm] Buffer too small for z buffer "
2989                                   "(need %lu have %lu) !\n", size,
2990                                   radeon_bo_size(track->zb.robj));
2991                         DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2992                                   track->zb.pitch, track->zb.cpp,
2993                                   track->zb.offset, track->maxy);
2994                         return -EINVAL;
2995                 }
2996         }
2997         prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2998         nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2999         switch (prim_walk) {
3000         case 1:
3001                 for (i = 0; i < track->num_arrays; i++) {
3002                         size = track->arrays[i].esize * track->max_indx * 4;
3003                         if (track->arrays[i].robj == NULL) {
3004                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3005                                           "bound\n", prim_walk, i);
3006                                 return -EINVAL;
3007                         }
3008                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3009                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3010                                         "need %lu dwords have %lu dwords\n",
3011                                         prim_walk, i, size >> 2,
3012                                         radeon_bo_size(track->arrays[i].robj)
3013                                         >> 2);
3014                                 DRM_ERROR("Max indices %u\n", track->max_indx);
3015                                 return -EINVAL;
3016                         }
3017                 }
3018                 break;
3019         case 2:
3020                 for (i = 0; i < track->num_arrays; i++) {
3021                         size = track->arrays[i].esize * (nverts - 1) * 4;
3022                         if (track->arrays[i].robj == NULL) {
3023                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3024                                           "bound\n", prim_walk, i);
3025                                 return -EINVAL;
3026                         }
3027                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3028                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3029                                         "need %lu dwords have %lu dwords\n",
3030                                         prim_walk, i, size >> 2,
3031                                         radeon_bo_size(track->arrays[i].robj)
3032                                         >> 2);
3033                                 return -EINVAL;
3034                         }
3035                 }
3036                 break;
3037         case 3:
3038                 size = track->vtx_size * nverts;
3039                 if (size != track->immd_dwords) {
3040                         DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3041                                   track->immd_dwords, size);
3042                         DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3043                                   nverts, track->vtx_size);
3044                         return -EINVAL;
3045                 }
3046                 break;
3047         default:
3048                 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3049                           prim_walk);
3050                 return -EINVAL;
3051         }
3052         return r100_cs_track_texture_check(rdev, track);
3053 }
3054
3055 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3056 {
3057         unsigned i, face;
3058
3059         if (rdev->family < CHIP_R300) {
3060                 track->num_cb = 1;
3061                 if (rdev->family <= CHIP_RS200)
3062                         track->num_texture = 3;
3063                 else
3064                         track->num_texture = 6;
3065                 track->maxy = 2048;
3066                 track->separate_cube = 1;
3067         } else {
3068                 track->num_cb = 4;
3069                 track->num_texture = 16;
3070                 track->maxy = 4096;
3071                 track->separate_cube = 0;
3072         }
3073
3074         for (i = 0; i < track->num_cb; i++) {
3075                 track->cb[i].robj = NULL;
3076                 track->cb[i].pitch = 8192;
3077                 track->cb[i].cpp = 16;
3078                 track->cb[i].offset = 0;
3079         }
3080         track->z_enabled = true;
3081         track->zb.robj = NULL;
3082         track->zb.pitch = 8192;
3083         track->zb.cpp = 4;
3084         track->zb.offset = 0;
3085         track->vtx_size = 0x7F;
3086         track->immd_dwords = 0xFFFFFFFFUL;
3087         track->num_arrays = 11;
3088         track->max_indx = 0x00FFFFFFUL;
3089         for (i = 0; i < track->num_arrays; i++) {
3090                 track->arrays[i].robj = NULL;
3091                 track->arrays[i].esize = 0x7F;
3092         }
3093         for (i = 0; i < track->num_texture; i++) {
3094                 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
3095                 track->textures[i].pitch = 16536;
3096                 track->textures[i].width = 16536;
3097                 track->textures[i].height = 16536;
3098                 track->textures[i].width_11 = 1 << 11;
3099                 track->textures[i].height_11 = 1 << 11;
3100                 track->textures[i].num_levels = 12;
3101                 if (rdev->family <= CHIP_RS200) {
3102                         track->textures[i].tex_coord_type = 0;
3103                         track->textures[i].txdepth = 0;
3104                 } else {
3105                         track->textures[i].txdepth = 16;
3106                         track->textures[i].tex_coord_type = 1;
3107                 }
3108                 track->textures[i].cpp = 64;
3109                 track->textures[i].robj = NULL;
3110                 /* CS IB emission code makes sure texture unit are disabled */
3111                 track->textures[i].enabled = false;
3112                 track->textures[i].roundup_w = true;
3113                 track->textures[i].roundup_h = true;
3114                 if (track->separate_cube)
3115                         for (face = 0; face < 5; face++) {
3116                                 track->textures[i].cube_info[face].robj = NULL;
3117                                 track->textures[i].cube_info[face].width = 16536;
3118                                 track->textures[i].cube_info[face].height = 16536;
3119                                 track->textures[i].cube_info[face].offset = 0;
3120                         }
3121         }
3122 }
3123
3124 int r100_ring_test(struct radeon_device *rdev)
3125 {
3126         uint32_t scratch;
3127         uint32_t tmp = 0;
3128         unsigned i;
3129         int r;
3130
3131         r = radeon_scratch_get(rdev, &scratch);
3132         if (r) {
3133                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3134                 return r;
3135         }
3136         WREG32(scratch, 0xCAFEDEAD);
3137         r = radeon_ring_lock(rdev, 2);
3138         if (r) {
3139                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3140                 radeon_scratch_free(rdev, scratch);
3141                 return r;
3142         }
3143         radeon_ring_write(rdev, PACKET0(scratch, 0));
3144         radeon_ring_write(rdev, 0xDEADBEEF);
3145         radeon_ring_unlock_commit(rdev);
3146         for (i = 0; i < rdev->usec_timeout; i++) {
3147                 tmp = RREG32(scratch);
3148                 if (tmp == 0xDEADBEEF) {
3149                         break;
3150                 }
3151                 DRM_UDELAY(1);
3152         }
3153         if (i < rdev->usec_timeout) {
3154                 DRM_INFO("ring test succeeded in %d usecs\n", i);
3155         } else {
3156                 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
3157                           scratch, tmp);
3158                 r = -EINVAL;
3159         }
3160         radeon_scratch_free(rdev, scratch);
3161         return r;
3162 }
3163
3164 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3165 {
3166         radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3167         radeon_ring_write(rdev, ib->gpu_addr);
3168         radeon_ring_write(rdev, ib->length_dw);
3169 }
3170
3171 int r100_ib_test(struct radeon_device *rdev)
3172 {
3173         struct radeon_ib *ib;
3174         uint32_t scratch;
3175         uint32_t tmp = 0;
3176         unsigned i;
3177         int r;
3178
3179         r = radeon_scratch_get(rdev, &scratch);
3180         if (r) {
3181                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3182                 return r;
3183         }
3184         WREG32(scratch, 0xCAFEDEAD);
3185         r = radeon_ib_get(rdev, &ib);
3186         if (r) {
3187                 return r;
3188         }
3189         ib->ptr[0] = PACKET0(scratch, 0);
3190         ib->ptr[1] = 0xDEADBEEF;
3191         ib->ptr[2] = PACKET2(0);
3192         ib->ptr[3] = PACKET2(0);
3193         ib->ptr[4] = PACKET2(0);
3194         ib->ptr[5] = PACKET2(0);
3195         ib->ptr[6] = PACKET2(0);
3196         ib->ptr[7] = PACKET2(0);
3197         ib->length_dw = 8;
3198         r = radeon_ib_schedule(rdev, ib);
3199         if (r) {
3200                 radeon_scratch_free(rdev, scratch);
3201                 radeon_ib_free(rdev, &ib);
3202                 return r;
3203         }
3204         r = radeon_fence_wait(ib->fence, false);
3205         if (r) {
3206                 return r;
3207         }
3208         for (i = 0; i < rdev->usec_timeout; i++) {
3209                 tmp = RREG32(scratch);
3210                 if (tmp == 0xDEADBEEF) {
3211                         break;
3212                 }
3213                 DRM_UDELAY(1);
3214         }
3215         if (i < rdev->usec_timeout) {
3216                 DRM_INFO("ib test succeeded in %u usecs\n", i);
3217         } else {
3218                 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3219                           scratch, tmp);
3220                 r = -EINVAL;
3221         }
3222         radeon_scratch_free(rdev, scratch);
3223         radeon_ib_free(rdev, &ib);
3224         return r;
3225 }
3226
3227 void r100_ib_fini(struct radeon_device *rdev)
3228 {
3229         radeon_ib_pool_fini(rdev);
3230 }
3231
3232 int r100_ib_init(struct radeon_device *rdev)
3233 {
3234         int r;
3235
3236         r = radeon_ib_pool_init(rdev);
3237         if (r) {
3238                 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
3239                 r100_ib_fini(rdev);
3240                 return r;
3241         }
3242         r = r100_ib_test(rdev);
3243         if (r) {
3244                 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
3245                 r100_ib_fini(rdev);
3246                 return r;
3247         }
3248         return 0;
3249 }
3250
3251 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3252 {
3253         /* Shutdown CP we shouldn't need to do that but better be safe than
3254          * sorry
3255          */
3256         rdev->cp.ready = false;
3257         WREG32(R_000740_CP_CSQ_CNTL, 0);
3258
3259         /* Save few CRTC registers */
3260         save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3261         save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3262         save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3263         save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3264         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3265                 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3266                 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3267         }
3268
3269         /* Disable VGA aperture access */
3270         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3271         /* Disable cursor, overlay, crtc */
3272         WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3273         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3274                                         S_000054_CRTC_DISPLAY_DIS(1));
3275         WREG32(R_000050_CRTC_GEN_CNTL,
3276                         (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3277                         S_000050_CRTC_DISP_REQ_EN_B(1));
3278         WREG32(R_000420_OV0_SCALE_CNTL,
3279                 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3280         WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3281         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3282                 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3283                                                 S_000360_CUR2_LOCK(1));
3284                 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3285                         (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3286                         S_0003F8_CRTC2_DISPLAY_DIS(1) |
3287                         S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3288                 WREG32(R_000360_CUR2_OFFSET,
3289                         C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3290         }
3291 }
3292
3293 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3294 {
3295         /* Update base address for crtc */
3296         WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3297         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3298                 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3299         }
3300         /* Restore CRTC registers */
3301         WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3302         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3303         WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3304         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3305                 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3306         }
3307 }
3308
3309 void r100_vga_render_disable(struct radeon_device *rdev)
3310 {
3311         u32 tmp;
3312
3313         tmp = RREG8(R_0003C2_GENMO_WT);
3314         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3315 }
3316
3317 static void r100_debugfs(struct radeon_device *rdev)
3318 {
3319         int r;
3320
3321         r = r100_debugfs_mc_info_init(rdev);
3322         if (r)
3323                 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3324 }
3325
3326 static void r100_mc_program(struct radeon_device *rdev)
3327 {
3328         struct r100_mc_save save;
3329
3330         /* Stops all mc clients */
3331         r100_mc_stop(rdev, &save);
3332         if (rdev->flags & RADEON_IS_AGP) {
3333                 WREG32(R_00014C_MC_AGP_LOCATION,
3334                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3335                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3336                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3337                 if (rdev->family > CHIP_RV200)
3338                         WREG32(R_00015C_AGP_BASE_2,
3339                                 upper_32_bits(rdev->mc.agp_base) & 0xff);
3340         } else {
3341                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3342                 WREG32(R_000170_AGP_BASE, 0);
3343                 if (rdev->family > CHIP_RV200)
3344                         WREG32(R_00015C_AGP_BASE_2, 0);
3345         }
3346         /* Wait for mc idle */
3347         if (r100_mc_wait_for_idle(rdev))
3348                 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3349         /* Program MC, should be a 32bits limited address space */
3350         WREG32(R_000148_MC_FB_LOCATION,
3351                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3352                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3353         r100_mc_resume(rdev, &save);
3354 }
3355
3356 void r100_clock_startup(struct radeon_device *rdev)
3357 {
3358         u32 tmp;
3359
3360         if (radeon_dynclks != -1 && radeon_dynclks)
3361                 radeon_legacy_set_clock_gating(rdev, 1);
3362         /* We need to force on some of the block */
3363         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3364         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3365         if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3366                 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3367         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3368 }
3369
3370 static int r100_startup(struct radeon_device *rdev)
3371 {
3372         int r;
3373
3374         /* set common regs */
3375         r100_set_common_regs(rdev);
3376         /* program mc */
3377         r100_mc_program(rdev);
3378         /* Resume clock */
3379         r100_clock_startup(rdev);
3380         /* Initialize GPU configuration (# pipes, ...) */
3381         r100_gpu_init(rdev);
3382         /* Initialize GART (initialize after TTM so we can allocate
3383          * memory through TTM but finalize after TTM) */
3384         r100_enable_bm(rdev);
3385         if (rdev->flags & RADEON_IS_PCI) {
3386                 r = r100_pci_gart_enable(rdev);
3387                 if (r)
3388                         return r;
3389         }
3390         /* Enable IRQ */
3391         r100_irq_set(rdev);
3392         rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3393         /* 1M ring buffer */
3394         r = r100_cp_init(rdev, 1024 * 1024);
3395         if (r) {
3396                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3397                 return r;
3398         }
3399         r = r100_wb_init(rdev);
3400         if (r)
3401                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
3402         r = r100_ib_init(rdev);
3403         if (r) {
3404                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
3405                 return r;
3406         }
3407         return 0;
3408 }
3409
3410 int r100_resume(struct radeon_device *rdev)
3411 {
3412         /* Make sur GART are not working */
3413         if (rdev->flags & RADEON_IS_PCI)
3414                 r100_pci_gart_disable(rdev);
3415         /* Resume clock before doing reset */
3416         r100_clock_startup(rdev);
3417         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3418         if (radeon_gpu_reset(rdev)) {
3419                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3420                         RREG32(R_000E40_RBBM_STATUS),
3421                         RREG32(R_0007C0_CP_STAT));
3422         }
3423         /* post */
3424         radeon_combios_asic_init(rdev->ddev);
3425         /* Resume clock after posting */
3426         r100_clock_startup(rdev);
3427         /* Initialize surface registers */
3428         radeon_surface_init(rdev);
3429         return r100_startup(rdev);
3430 }
3431
3432 int r100_suspend(struct radeon_device *rdev)
3433 {
3434         r100_cp_disable(rdev);
3435         r100_wb_disable(rdev);
3436         r100_irq_disable(rdev);
3437         if (rdev->flags & RADEON_IS_PCI)
3438                 r100_pci_gart_disable(rdev);
3439         return 0;
3440 }
3441
3442 void r100_fini(struct radeon_device *rdev)
3443 {
3444         radeon_pm_fini(rdev);
3445         r100_cp_fini(rdev);
3446         r100_wb_fini(rdev);
3447         r100_ib_fini(rdev);
3448         radeon_gem_fini(rdev);
3449         if (rdev->flags & RADEON_IS_PCI)
3450                 r100_pci_gart_fini(rdev);
3451         radeon_agp_fini(rdev);
3452         radeon_irq_kms_fini(rdev);
3453         radeon_fence_driver_fini(rdev);
3454         radeon_bo_fini(rdev);
3455         radeon_atombios_fini(rdev);
3456         kfree(rdev->bios);
3457         rdev->bios = NULL;
3458 }
3459
3460 int r100_init(struct radeon_device *rdev)
3461 {
3462         int r;
3463
3464         /* Register debugfs file specific to this group of asics */
3465         r100_debugfs(rdev);
3466         /* Disable VGA */
3467         r100_vga_render_disable(rdev);
3468         /* Initialize scratch registers */
3469         radeon_scratch_init(rdev);
3470         /* Initialize surface registers */
3471         radeon_surface_init(rdev);
3472         /* TODO: disable VGA need to use VGA request */
3473         /* BIOS*/
3474         if (!radeon_get_bios(rdev)) {
3475                 if (ASIC_IS_AVIVO(rdev))
3476                         return -EINVAL;
3477         }
3478         if (rdev->is_atom_bios) {
3479                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3480                 return -EINVAL;
3481         } else {
3482                 r = radeon_combios_init(rdev);
3483                 if (r)
3484                         return r;
3485         }
3486         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3487         if (radeon_gpu_reset(rdev)) {
3488                 dev_warn(rdev->dev,
3489                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3490                         RREG32(R_000E40_RBBM_STATUS),
3491                         RREG32(R_0007C0_CP_STAT));
3492         }
3493         /* check if cards are posted or not */
3494         if (radeon_boot_test_post_card(rdev) == false)
3495                 return -EINVAL;
3496         /* Set asic errata */
3497         r100_errata(rdev);
3498         /* Initialize clocks */
3499         radeon_get_clock_info(rdev->ddev);
3500         /* Initialize power management */
3501         radeon_pm_init(rdev);
3502         /* initialize AGP */
3503         if (rdev->flags & RADEON_IS_AGP) {
3504                 r = radeon_agp_init(rdev);
3505                 if (r) {
3506                         radeon_agp_disable(rdev);
3507                 }
3508         }
3509         /* initialize VRAM */
3510         r100_mc_init(rdev);
3511         /* Fence driver */
3512         r = radeon_fence_driver_init(rdev);
3513         if (r)
3514                 return r;
3515         r = radeon_irq_kms_init(rdev);
3516         if (r)
3517                 return r;
3518         /* Memory manager */
3519         r = radeon_bo_init(rdev);
3520         if (r)
3521                 return r;
3522         if (rdev->flags & RADEON_IS_PCI) {
3523                 r = r100_pci_gart_init(rdev);
3524                 if (r)
3525                         return r;
3526         }
3527         r100_set_safe_registers(rdev);
3528         rdev->accel_working = true;
3529         r = r100_startup(rdev);
3530         if (r) {
3531                 /* Somethings want wront with the accel init stop accel */
3532                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3533                 r100_cp_fini(rdev);
3534                 r100_wb_fini(rdev);
3535                 r100_ib_fini(rdev);
3536                 radeon_irq_kms_fini(rdev);
3537                 if (rdev->flags & RADEON_IS_PCI)
3538                         r100_pci_gart_fini(rdev);
3539                 rdev->accel_working = false;
3540         }
3541         return 0;
3542 }