include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit...
[linux-2.6.git] / drivers / gpu / drm / radeon / r100.c
1 /*
2  * Copyright 2008 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  * Copyright 2009 Jerome Glisse.
5  *
6  * Permission is hereby granted, free of charge, to any person obtaining a
7  * copy of this software and associated documentation files (the "Software"),
8  * to deal in the Software without restriction, including without limitation
9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10  * and/or sell copies of the Software, and to permit persons to whom the
11  * Software is furnished to do so, subject to the following conditions:
12  *
13  * The above copyright notice and this permission notice shall be included in
14  * all copies or substantial portions of the Software.
15  *
16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22  * OTHER DEALINGS IN THE SOFTWARE.
23  *
24  * Authors: Dave Airlie
25  *          Alex Deucher
26  *          Jerome Glisse
27  */
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
30 #include "drmP.h"
31 #include "drm.h"
32 #include "radeon_drm.h"
33 #include "radeon_reg.h"
34 #include "radeon.h"
35 #include "r100d.h"
36 #include "rs100d.h"
37 #include "rv200d.h"
38 #include "rv250d.h"
39
40 #include <linux/firmware.h>
41 #include <linux/platform_device.h>
42
43 #include "r100_reg_safe.h"
44 #include "rn50_reg_safe.h"
45
46 /* Firmware Names */
47 #define FIRMWARE_R100           "radeon/R100_cp.bin"
48 #define FIRMWARE_R200           "radeon/R200_cp.bin"
49 #define FIRMWARE_R300           "radeon/R300_cp.bin"
50 #define FIRMWARE_R420           "radeon/R420_cp.bin"
51 #define FIRMWARE_RS690          "radeon/RS690_cp.bin"
52 #define FIRMWARE_RS600          "radeon/RS600_cp.bin"
53 #define FIRMWARE_R520           "radeon/R520_cp.bin"
54
55 MODULE_FIRMWARE(FIRMWARE_R100);
56 MODULE_FIRMWARE(FIRMWARE_R200);
57 MODULE_FIRMWARE(FIRMWARE_R300);
58 MODULE_FIRMWARE(FIRMWARE_R420);
59 MODULE_FIRMWARE(FIRMWARE_RS690);
60 MODULE_FIRMWARE(FIRMWARE_RS600);
61 MODULE_FIRMWARE(FIRMWARE_R520);
62
63 #include "r100_track.h"
64
65 /* This files gather functions specifics to:
66  * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
67  */
68
69 /* hpd for digital panel detect/disconnect */
70 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
71 {
72         bool connected = false;
73
74         switch (hpd) {
75         case RADEON_HPD_1:
76                 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
77                         connected = true;
78                 break;
79         case RADEON_HPD_2:
80                 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
81                         connected = true;
82                 break;
83         default:
84                 break;
85         }
86         return connected;
87 }
88
89 void r100_hpd_set_polarity(struct radeon_device *rdev,
90                            enum radeon_hpd_id hpd)
91 {
92         u32 tmp;
93         bool connected = r100_hpd_sense(rdev, hpd);
94
95         switch (hpd) {
96         case RADEON_HPD_1:
97                 tmp = RREG32(RADEON_FP_GEN_CNTL);
98                 if (connected)
99                         tmp &= ~RADEON_FP_DETECT_INT_POL;
100                 else
101                         tmp |= RADEON_FP_DETECT_INT_POL;
102                 WREG32(RADEON_FP_GEN_CNTL, tmp);
103                 break;
104         case RADEON_HPD_2:
105                 tmp = RREG32(RADEON_FP2_GEN_CNTL);
106                 if (connected)
107                         tmp &= ~RADEON_FP2_DETECT_INT_POL;
108                 else
109                         tmp |= RADEON_FP2_DETECT_INT_POL;
110                 WREG32(RADEON_FP2_GEN_CNTL, tmp);
111                 break;
112         default:
113                 break;
114         }
115 }
116
117 void r100_hpd_init(struct radeon_device *rdev)
118 {
119         struct drm_device *dev = rdev->ddev;
120         struct drm_connector *connector;
121
122         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
123                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
124                 switch (radeon_connector->hpd.hpd) {
125                 case RADEON_HPD_1:
126                         rdev->irq.hpd[0] = true;
127                         break;
128                 case RADEON_HPD_2:
129                         rdev->irq.hpd[1] = true;
130                         break;
131                 default:
132                         break;
133                 }
134         }
135         if (rdev->irq.installed)
136                 r100_irq_set(rdev);
137 }
138
139 void r100_hpd_fini(struct radeon_device *rdev)
140 {
141         struct drm_device *dev = rdev->ddev;
142         struct drm_connector *connector;
143
144         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
145                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
146                 switch (radeon_connector->hpd.hpd) {
147                 case RADEON_HPD_1:
148                         rdev->irq.hpd[0] = false;
149                         break;
150                 case RADEON_HPD_2:
151                         rdev->irq.hpd[1] = false;
152                         break;
153                 default:
154                         break;
155                 }
156         }
157 }
158
159 /*
160  * PCI GART
161  */
162 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
163 {
164         /* TODO: can we do somethings here ? */
165         /* It seems hw only cache one entry so we should discard this
166          * entry otherwise if first GPU GART read hit this entry it
167          * could end up in wrong address. */
168 }
169
170 int r100_pci_gart_init(struct radeon_device *rdev)
171 {
172         int r;
173
174         if (rdev->gart.table.ram.ptr) {
175                 WARN(1, "R100 PCI GART already initialized.\n");
176                 return 0;
177         }
178         /* Initialize common gart structure */
179         r = radeon_gart_init(rdev);
180         if (r)
181                 return r;
182         rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
183         rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
184         rdev->asic->gart_set_page = &r100_pci_gart_set_page;
185         return radeon_gart_table_ram_alloc(rdev);
186 }
187
188 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
189 void r100_enable_bm(struct radeon_device *rdev)
190 {
191         uint32_t tmp;
192         /* Enable bus mastering */
193         tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
194         WREG32(RADEON_BUS_CNTL, tmp);
195 }
196
197 int r100_pci_gart_enable(struct radeon_device *rdev)
198 {
199         uint32_t tmp;
200
201         radeon_gart_restore(rdev);
202         /* discard memory request outside of configured range */
203         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
204         WREG32(RADEON_AIC_CNTL, tmp);
205         /* set address range for PCI address translate */
206         WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
207         WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
208         /* set PCI GART page-table base address */
209         WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
210         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
211         WREG32(RADEON_AIC_CNTL, tmp);
212         r100_pci_gart_tlb_flush(rdev);
213         rdev->gart.ready = true;
214         return 0;
215 }
216
217 void r100_pci_gart_disable(struct radeon_device *rdev)
218 {
219         uint32_t tmp;
220
221         /* discard memory request outside of configured range */
222         tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
223         WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
224         WREG32(RADEON_AIC_LO_ADDR, 0);
225         WREG32(RADEON_AIC_HI_ADDR, 0);
226 }
227
228 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
229 {
230         if (i < 0 || i > rdev->gart.num_gpu_pages) {
231                 return -EINVAL;
232         }
233         rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
234         return 0;
235 }
236
237 void r100_pci_gart_fini(struct radeon_device *rdev)
238 {
239         r100_pci_gart_disable(rdev);
240         radeon_gart_table_ram_free(rdev);
241         radeon_gart_fini(rdev);
242 }
243
244 int r100_irq_set(struct radeon_device *rdev)
245 {
246         uint32_t tmp = 0;
247
248         if (!rdev->irq.installed) {
249                 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
250                 WREG32(R_000040_GEN_INT_CNTL, 0);
251                 return -EINVAL;
252         }
253         if (rdev->irq.sw_int) {
254                 tmp |= RADEON_SW_INT_ENABLE;
255         }
256         if (rdev->irq.crtc_vblank_int[0]) {
257                 tmp |= RADEON_CRTC_VBLANK_MASK;
258         }
259         if (rdev->irq.crtc_vblank_int[1]) {
260                 tmp |= RADEON_CRTC2_VBLANK_MASK;
261         }
262         if (rdev->irq.hpd[0]) {
263                 tmp |= RADEON_FP_DETECT_MASK;
264         }
265         if (rdev->irq.hpd[1]) {
266                 tmp |= RADEON_FP2_DETECT_MASK;
267         }
268         WREG32(RADEON_GEN_INT_CNTL, tmp);
269         return 0;
270 }
271
272 void r100_irq_disable(struct radeon_device *rdev)
273 {
274         u32 tmp;
275
276         WREG32(R_000040_GEN_INT_CNTL, 0);
277         /* Wait and acknowledge irq */
278         mdelay(1);
279         tmp = RREG32(R_000044_GEN_INT_STATUS);
280         WREG32(R_000044_GEN_INT_STATUS, tmp);
281 }
282
283 static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
284 {
285         uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
286         uint32_t irq_mask = RADEON_SW_INT_TEST |
287                 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
288                 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
289
290         if (irqs) {
291                 WREG32(RADEON_GEN_INT_STATUS, irqs);
292         }
293         return irqs & irq_mask;
294 }
295
296 int r100_irq_process(struct radeon_device *rdev)
297 {
298         uint32_t status, msi_rearm;
299         bool queue_hotplug = false;
300
301         status = r100_irq_ack(rdev);
302         if (!status) {
303                 return IRQ_NONE;
304         }
305         if (rdev->shutdown) {
306                 return IRQ_NONE;
307         }
308         while (status) {
309                 /* SW interrupt */
310                 if (status & RADEON_SW_INT_TEST) {
311                         radeon_fence_process(rdev);
312                 }
313                 /* Vertical blank interrupts */
314                 if (status & RADEON_CRTC_VBLANK_STAT) {
315                         drm_handle_vblank(rdev->ddev, 0);
316                         wake_up(&rdev->irq.vblank_queue);
317                 }
318                 if (status & RADEON_CRTC2_VBLANK_STAT) {
319                         drm_handle_vblank(rdev->ddev, 1);
320                         wake_up(&rdev->irq.vblank_queue);
321                 }
322                 if (status & RADEON_FP_DETECT_STAT) {
323                         queue_hotplug = true;
324                         DRM_DEBUG("HPD1\n");
325                 }
326                 if (status & RADEON_FP2_DETECT_STAT) {
327                         queue_hotplug = true;
328                         DRM_DEBUG("HPD2\n");
329                 }
330                 status = r100_irq_ack(rdev);
331         }
332         if (queue_hotplug)
333                 queue_work(rdev->wq, &rdev->hotplug_work);
334         if (rdev->msi_enabled) {
335                 switch (rdev->family) {
336                 case CHIP_RS400:
337                 case CHIP_RS480:
338                         msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
339                         WREG32(RADEON_AIC_CNTL, msi_rearm);
340                         WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
341                         break;
342                 default:
343                         msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
344                         WREG32(RADEON_MSI_REARM_EN, msi_rearm);
345                         WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
346                         break;
347                 }
348         }
349         return IRQ_HANDLED;
350 }
351
352 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
353 {
354         if (crtc == 0)
355                 return RREG32(RADEON_CRTC_CRNT_FRAME);
356         else
357                 return RREG32(RADEON_CRTC2_CRNT_FRAME);
358 }
359
360 /* Who ever call radeon_fence_emit should call ring_lock and ask
361  * for enough space (today caller are ib schedule and buffer move) */
362 void r100_fence_ring_emit(struct radeon_device *rdev,
363                           struct radeon_fence *fence)
364 {
365         /* We have to make sure that caches are flushed before
366          * CPU might read something from VRAM. */
367         radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
368         radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
369         radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
370         radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
371         /* Wait until IDLE & CLEAN */
372         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
373         radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
374         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
375         radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
376                                 RADEON_HDP_READ_BUFFER_INVALIDATE);
377         radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
378         radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
379         /* Emit fence sequence & fire IRQ */
380         radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
381         radeon_ring_write(rdev, fence->seq);
382         radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
383         radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
384 }
385
386 int r100_wb_init(struct radeon_device *rdev)
387 {
388         int r;
389
390         if (rdev->wb.wb_obj == NULL) {
391                 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
392                                         RADEON_GEM_DOMAIN_GTT,
393                                         &rdev->wb.wb_obj);
394                 if (r) {
395                         dev_err(rdev->dev, "(%d) create WB buffer failed\n", r);
396                         return r;
397                 }
398                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
399                 if (unlikely(r != 0))
400                         return r;
401                 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
402                                         &rdev->wb.gpu_addr);
403                 if (r) {
404                         dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r);
405                         radeon_bo_unreserve(rdev->wb.wb_obj);
406                         return r;
407                 }
408                 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
409                 radeon_bo_unreserve(rdev->wb.wb_obj);
410                 if (r) {
411                         dev_err(rdev->dev, "(%d) map WB buffer failed\n", r);
412                         return r;
413                 }
414         }
415         WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
416         WREG32(R_00070C_CP_RB_RPTR_ADDR,
417                 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
418         WREG32(R_000770_SCRATCH_UMSK, 0xff);
419         return 0;
420 }
421
422 void r100_wb_disable(struct radeon_device *rdev)
423 {
424         WREG32(R_000770_SCRATCH_UMSK, 0);
425 }
426
427 void r100_wb_fini(struct radeon_device *rdev)
428 {
429         int r;
430
431         r100_wb_disable(rdev);
432         if (rdev->wb.wb_obj) {
433                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
434                 if (unlikely(r != 0)) {
435                         dev_err(rdev->dev, "(%d) can't finish WB\n", r);
436                         return;
437                 }
438                 radeon_bo_kunmap(rdev->wb.wb_obj);
439                 radeon_bo_unpin(rdev->wb.wb_obj);
440                 radeon_bo_unreserve(rdev->wb.wb_obj);
441                 radeon_bo_unref(&rdev->wb.wb_obj);
442                 rdev->wb.wb = NULL;
443                 rdev->wb.wb_obj = NULL;
444         }
445 }
446
447 int r100_copy_blit(struct radeon_device *rdev,
448                    uint64_t src_offset,
449                    uint64_t dst_offset,
450                    unsigned num_pages,
451                    struct radeon_fence *fence)
452 {
453         uint32_t cur_pages;
454         uint32_t stride_bytes = PAGE_SIZE;
455         uint32_t pitch;
456         uint32_t stride_pixels;
457         unsigned ndw;
458         int num_loops;
459         int r = 0;
460
461         /* radeon limited to 16k stride */
462         stride_bytes &= 0x3fff;
463         /* radeon pitch is /64 */
464         pitch = stride_bytes / 64;
465         stride_pixels = stride_bytes / 4;
466         num_loops = DIV_ROUND_UP(num_pages, 8191);
467
468         /* Ask for enough room for blit + flush + fence */
469         ndw = 64 + (10 * num_loops);
470         r = radeon_ring_lock(rdev, ndw);
471         if (r) {
472                 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
473                 return -EINVAL;
474         }
475         while (num_pages > 0) {
476                 cur_pages = num_pages;
477                 if (cur_pages > 8191) {
478                         cur_pages = 8191;
479                 }
480                 num_pages -= cur_pages;
481
482                 /* pages are in Y direction - height
483                    page width in X direction - width */
484                 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
485                 radeon_ring_write(rdev,
486                                   RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
487                                   RADEON_GMC_DST_PITCH_OFFSET_CNTL |
488                                   RADEON_GMC_SRC_CLIPPING |
489                                   RADEON_GMC_DST_CLIPPING |
490                                   RADEON_GMC_BRUSH_NONE |
491                                   (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
492                                   RADEON_GMC_SRC_DATATYPE_COLOR |
493                                   RADEON_ROP3_S |
494                                   RADEON_DP_SRC_SOURCE_MEMORY |
495                                   RADEON_GMC_CLR_CMP_CNTL_DIS |
496                                   RADEON_GMC_WR_MSK_DIS);
497                 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
498                 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
499                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
500                 radeon_ring_write(rdev, 0);
501                 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
502                 radeon_ring_write(rdev, num_pages);
503                 radeon_ring_write(rdev, num_pages);
504                 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
505         }
506         radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
507         radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
508         radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
509         radeon_ring_write(rdev,
510                           RADEON_WAIT_2D_IDLECLEAN |
511                           RADEON_WAIT_HOST_IDLECLEAN |
512                           RADEON_WAIT_DMA_GUI_IDLE);
513         if (fence) {
514                 r = radeon_fence_emit(rdev, fence);
515         }
516         radeon_ring_unlock_commit(rdev);
517         return r;
518 }
519
520 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
521 {
522         unsigned i;
523         u32 tmp;
524
525         for (i = 0; i < rdev->usec_timeout; i++) {
526                 tmp = RREG32(R_000E40_RBBM_STATUS);
527                 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
528                         return 0;
529                 }
530                 udelay(1);
531         }
532         return -1;
533 }
534
535 void r100_ring_start(struct radeon_device *rdev)
536 {
537         int r;
538
539         r = radeon_ring_lock(rdev, 2);
540         if (r) {
541                 return;
542         }
543         radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
544         radeon_ring_write(rdev,
545                           RADEON_ISYNC_ANY2D_IDLE3D |
546                           RADEON_ISYNC_ANY3D_IDLE2D |
547                           RADEON_ISYNC_WAIT_IDLEGUI |
548                           RADEON_ISYNC_CPSCRATCH_IDLEGUI);
549         radeon_ring_unlock_commit(rdev);
550 }
551
552
553 /* Load the microcode for the CP */
554 static int r100_cp_init_microcode(struct radeon_device *rdev)
555 {
556         struct platform_device *pdev;
557         const char *fw_name = NULL;
558         int err;
559
560         DRM_DEBUG("\n");
561
562         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
563         err = IS_ERR(pdev);
564         if (err) {
565                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
566                 return -EINVAL;
567         }
568         if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
569             (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
570             (rdev->family == CHIP_RS200)) {
571                 DRM_INFO("Loading R100 Microcode\n");
572                 fw_name = FIRMWARE_R100;
573         } else if ((rdev->family == CHIP_R200) ||
574                    (rdev->family == CHIP_RV250) ||
575                    (rdev->family == CHIP_RV280) ||
576                    (rdev->family == CHIP_RS300)) {
577                 DRM_INFO("Loading R200 Microcode\n");
578                 fw_name = FIRMWARE_R200;
579         } else if ((rdev->family == CHIP_R300) ||
580                    (rdev->family == CHIP_R350) ||
581                    (rdev->family == CHIP_RV350) ||
582                    (rdev->family == CHIP_RV380) ||
583                    (rdev->family == CHIP_RS400) ||
584                    (rdev->family == CHIP_RS480)) {
585                 DRM_INFO("Loading R300 Microcode\n");
586                 fw_name = FIRMWARE_R300;
587         } else if ((rdev->family == CHIP_R420) ||
588                    (rdev->family == CHIP_R423) ||
589                    (rdev->family == CHIP_RV410)) {
590                 DRM_INFO("Loading R400 Microcode\n");
591                 fw_name = FIRMWARE_R420;
592         } else if ((rdev->family == CHIP_RS690) ||
593                    (rdev->family == CHIP_RS740)) {
594                 DRM_INFO("Loading RS690/RS740 Microcode\n");
595                 fw_name = FIRMWARE_RS690;
596         } else if (rdev->family == CHIP_RS600) {
597                 DRM_INFO("Loading RS600 Microcode\n");
598                 fw_name = FIRMWARE_RS600;
599         } else if ((rdev->family == CHIP_RV515) ||
600                    (rdev->family == CHIP_R520) ||
601                    (rdev->family == CHIP_RV530) ||
602                    (rdev->family == CHIP_R580) ||
603                    (rdev->family == CHIP_RV560) ||
604                    (rdev->family == CHIP_RV570)) {
605                 DRM_INFO("Loading R500 Microcode\n");
606                 fw_name = FIRMWARE_R520;
607         }
608
609         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
610         platform_device_unregister(pdev);
611         if (err) {
612                 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
613                        fw_name);
614         } else if (rdev->me_fw->size % 8) {
615                 printk(KERN_ERR
616                        "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
617                        rdev->me_fw->size, fw_name);
618                 err = -EINVAL;
619                 release_firmware(rdev->me_fw);
620                 rdev->me_fw = NULL;
621         }
622         return err;
623 }
624
625 static void r100_cp_load_microcode(struct radeon_device *rdev)
626 {
627         const __be32 *fw_data;
628         int i, size;
629
630         if (r100_gui_wait_for_idle(rdev)) {
631                 printk(KERN_WARNING "Failed to wait GUI idle while "
632                        "programming pipes. Bad things might happen.\n");
633         }
634
635         if (rdev->me_fw) {
636                 size = rdev->me_fw->size / 4;
637                 fw_data = (const __be32 *)&rdev->me_fw->data[0];
638                 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
639                 for (i = 0; i < size; i += 2) {
640                         WREG32(RADEON_CP_ME_RAM_DATAH,
641                                be32_to_cpup(&fw_data[i]));
642                         WREG32(RADEON_CP_ME_RAM_DATAL,
643                                be32_to_cpup(&fw_data[i + 1]));
644                 }
645         }
646 }
647
648 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
649 {
650         unsigned rb_bufsz;
651         unsigned rb_blksz;
652         unsigned max_fetch;
653         unsigned pre_write_timer;
654         unsigned pre_write_limit;
655         unsigned indirect2_start;
656         unsigned indirect1_start;
657         uint32_t tmp;
658         int r;
659
660         if (r100_debugfs_cp_init(rdev)) {
661                 DRM_ERROR("Failed to register debugfs file for CP !\n");
662         }
663         /* Reset CP */
664         tmp = RREG32(RADEON_CP_CSQ_STAT);
665         if ((tmp & (1 << 31))) {
666                 DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
667                 WREG32(RADEON_CP_CSQ_MODE, 0);
668                 WREG32(RADEON_CP_CSQ_CNTL, 0);
669                 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
670                 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
671                 mdelay(2);
672                 WREG32(RADEON_RBBM_SOFT_RESET, 0);
673                 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
674                 mdelay(2);
675                 tmp = RREG32(RADEON_CP_CSQ_STAT);
676                 if ((tmp & (1 << 31))) {
677                         DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp);
678                 }
679         } else {
680                 DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
681         }
682
683         if (!rdev->me_fw) {
684                 r = r100_cp_init_microcode(rdev);
685                 if (r) {
686                         DRM_ERROR("Failed to load firmware!\n");
687                         return r;
688                 }
689         }
690
691         /* Align ring size */
692         rb_bufsz = drm_order(ring_size / 8);
693         ring_size = (1 << (rb_bufsz + 1)) * 4;
694         r100_cp_load_microcode(rdev);
695         r = radeon_ring_init(rdev, ring_size);
696         if (r) {
697                 return r;
698         }
699         /* Each time the cp read 1024 bytes (16 dword/quadword) update
700          * the rptr copy in system ram */
701         rb_blksz = 9;
702         /* cp will read 128bytes at a time (4 dwords) */
703         max_fetch = 1;
704         rdev->cp.align_mask = 16 - 1;
705         /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
706         pre_write_timer = 64;
707         /* Force CP_RB_WPTR write if written more than one time before the
708          * delay expire
709          */
710         pre_write_limit = 0;
711         /* Setup the cp cache like this (cache size is 96 dwords) :
712          *      RING            0  to 15
713          *      INDIRECT1       16 to 79
714          *      INDIRECT2       80 to 95
715          * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
716          *    indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
717          *    indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
718          * Idea being that most of the gpu cmd will be through indirect1 buffer
719          * so it gets the bigger cache.
720          */
721         indirect2_start = 80;
722         indirect1_start = 16;
723         /* cp setup */
724         WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
725         tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
726                REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
727                REG_SET(RADEON_MAX_FETCH, max_fetch) |
728                RADEON_RB_NO_UPDATE);
729 #ifdef __BIG_ENDIAN
730         tmp |= RADEON_BUF_SWAP_32BIT;
731 #endif
732         WREG32(RADEON_CP_RB_CNTL, tmp);
733
734         /* Set ring address */
735         DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
736         WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
737         /* Force read & write ptr to 0 */
738         WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
739         WREG32(RADEON_CP_RB_RPTR_WR, 0);
740         WREG32(RADEON_CP_RB_WPTR, 0);
741         WREG32(RADEON_CP_RB_CNTL, tmp);
742         udelay(10);
743         rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
744         rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
745         /* Set cp mode to bus mastering & enable cp*/
746         WREG32(RADEON_CP_CSQ_MODE,
747                REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
748                REG_SET(RADEON_INDIRECT1_START, indirect1_start));
749         WREG32(0x718, 0);
750         WREG32(0x744, 0x00004D4D);
751         WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
752         radeon_ring_start(rdev);
753         r = radeon_ring_test(rdev);
754         if (r) {
755                 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
756                 return r;
757         }
758         rdev->cp.ready = true;
759         return 0;
760 }
761
762 void r100_cp_fini(struct radeon_device *rdev)
763 {
764         if (r100_cp_wait_for_idle(rdev)) {
765                 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
766         }
767         /* Disable ring */
768         r100_cp_disable(rdev);
769         radeon_ring_fini(rdev);
770         DRM_INFO("radeon: cp finalized\n");
771 }
772
773 void r100_cp_disable(struct radeon_device *rdev)
774 {
775         /* Disable ring */
776         rdev->cp.ready = false;
777         WREG32(RADEON_CP_CSQ_MODE, 0);
778         WREG32(RADEON_CP_CSQ_CNTL, 0);
779         if (r100_gui_wait_for_idle(rdev)) {
780                 printk(KERN_WARNING "Failed to wait GUI idle while "
781                        "programming pipes. Bad things might happen.\n");
782         }
783 }
784
785 int r100_cp_reset(struct radeon_device *rdev)
786 {
787         uint32_t tmp;
788         bool reinit_cp;
789         int i;
790
791         reinit_cp = rdev->cp.ready;
792         rdev->cp.ready = false;
793         WREG32(RADEON_CP_CSQ_MODE, 0);
794         WREG32(RADEON_CP_CSQ_CNTL, 0);
795         WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
796         (void)RREG32(RADEON_RBBM_SOFT_RESET);
797         udelay(200);
798         WREG32(RADEON_RBBM_SOFT_RESET, 0);
799         /* Wait to prevent race in RBBM_STATUS */
800         mdelay(1);
801         for (i = 0; i < rdev->usec_timeout; i++) {
802                 tmp = RREG32(RADEON_RBBM_STATUS);
803                 if (!(tmp & (1 << 16))) {
804                         DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
805                                  tmp);
806                         if (reinit_cp) {
807                                 return r100_cp_init(rdev, rdev->cp.ring_size);
808                         }
809                         return 0;
810                 }
811                 DRM_UDELAY(1);
812         }
813         tmp = RREG32(RADEON_RBBM_STATUS);
814         DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp);
815         return -1;
816 }
817
818 void r100_cp_commit(struct radeon_device *rdev)
819 {
820         WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
821         (void)RREG32(RADEON_CP_RB_WPTR);
822 }
823
824
825 /*
826  * CS functions
827  */
828 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
829                           struct radeon_cs_packet *pkt,
830                           const unsigned *auth, unsigned n,
831                           radeon_packet0_check_t check)
832 {
833         unsigned reg;
834         unsigned i, j, m;
835         unsigned idx;
836         int r;
837
838         idx = pkt->idx + 1;
839         reg = pkt->reg;
840         /* Check that register fall into register range
841          * determined by the number of entry (n) in the
842          * safe register bitmap.
843          */
844         if (pkt->one_reg_wr) {
845                 if ((reg >> 7) > n) {
846                         return -EINVAL;
847                 }
848         } else {
849                 if (((reg + (pkt->count << 2)) >> 7) > n) {
850                         return -EINVAL;
851                 }
852         }
853         for (i = 0; i <= pkt->count; i++, idx++) {
854                 j = (reg >> 7);
855                 m = 1 << ((reg >> 2) & 31);
856                 if (auth[j] & m) {
857                         r = check(p, pkt, idx, reg);
858                         if (r) {
859                                 return r;
860                         }
861                 }
862                 if (pkt->one_reg_wr) {
863                         if (!(auth[j] & m)) {
864                                 break;
865                         }
866                 } else {
867                         reg += 4;
868                 }
869         }
870         return 0;
871 }
872
873 void r100_cs_dump_packet(struct radeon_cs_parser *p,
874                          struct radeon_cs_packet *pkt)
875 {
876         volatile uint32_t *ib;
877         unsigned i;
878         unsigned idx;
879
880         ib = p->ib->ptr;
881         idx = pkt->idx;
882         for (i = 0; i <= (pkt->count + 1); i++, idx++) {
883                 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
884         }
885 }
886
887 /**
888  * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
889  * @parser:     parser structure holding parsing context.
890  * @pkt:        where to store packet informations
891  *
892  * Assume that chunk_ib_index is properly set. Will return -EINVAL
893  * if packet is bigger than remaining ib size. or if packets is unknown.
894  **/
895 int r100_cs_packet_parse(struct radeon_cs_parser *p,
896                          struct radeon_cs_packet *pkt,
897                          unsigned idx)
898 {
899         struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
900         uint32_t header;
901
902         if (idx >= ib_chunk->length_dw) {
903                 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
904                           idx, ib_chunk->length_dw);
905                 return -EINVAL;
906         }
907         header = radeon_get_ib_value(p, idx);
908         pkt->idx = idx;
909         pkt->type = CP_PACKET_GET_TYPE(header);
910         pkt->count = CP_PACKET_GET_COUNT(header);
911         switch (pkt->type) {
912         case PACKET_TYPE0:
913                 pkt->reg = CP_PACKET0_GET_REG(header);
914                 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
915                 break;
916         case PACKET_TYPE3:
917                 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
918                 break;
919         case PACKET_TYPE2:
920                 pkt->count = -1;
921                 break;
922         default:
923                 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
924                 return -EINVAL;
925         }
926         if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
927                 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
928                           pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
929                 return -EINVAL;
930         }
931         return 0;
932 }
933
934 /**
935  * r100_cs_packet_next_vline() - parse userspace VLINE packet
936  * @parser:             parser structure holding parsing context.
937  *
938  * Userspace sends a special sequence for VLINE waits.
939  * PACKET0 - VLINE_START_END + value
940  * PACKET0 - WAIT_UNTIL +_value
941  * RELOC (P3) - crtc_id in reloc.
942  *
943  * This function parses this and relocates the VLINE START END
944  * and WAIT UNTIL packets to the correct crtc.
945  * It also detects a switched off crtc and nulls out the
946  * wait in that case.
947  */
948 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
949 {
950         struct drm_mode_object *obj;
951         struct drm_crtc *crtc;
952         struct radeon_crtc *radeon_crtc;
953         struct radeon_cs_packet p3reloc, waitreloc;
954         int crtc_id;
955         int r;
956         uint32_t header, h_idx, reg;
957         volatile uint32_t *ib;
958
959         ib = p->ib->ptr;
960
961         /* parse the wait until */
962         r = r100_cs_packet_parse(p, &waitreloc, p->idx);
963         if (r)
964                 return r;
965
966         /* check its a wait until and only 1 count */
967         if (waitreloc.reg != RADEON_WAIT_UNTIL ||
968             waitreloc.count != 0) {
969                 DRM_ERROR("vline wait had illegal wait until segment\n");
970                 r = -EINVAL;
971                 return r;
972         }
973
974         if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
975                 DRM_ERROR("vline wait had illegal wait until\n");
976                 r = -EINVAL;
977                 return r;
978         }
979
980         /* jump over the NOP */
981         r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
982         if (r)
983                 return r;
984
985         h_idx = p->idx - 2;
986         p->idx += waitreloc.count + 2;
987         p->idx += p3reloc.count + 2;
988
989         header = radeon_get_ib_value(p, h_idx);
990         crtc_id = radeon_get_ib_value(p, h_idx + 5);
991         reg = CP_PACKET0_GET_REG(header);
992         mutex_lock(&p->rdev->ddev->mode_config.mutex);
993         obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
994         if (!obj) {
995                 DRM_ERROR("cannot find crtc %d\n", crtc_id);
996                 r = -EINVAL;
997                 goto out;
998         }
999         crtc = obj_to_crtc(obj);
1000         radeon_crtc = to_radeon_crtc(crtc);
1001         crtc_id = radeon_crtc->crtc_id;
1002
1003         if (!crtc->enabled) {
1004                 /* if the CRTC isn't enabled - we need to nop out the wait until */
1005                 ib[h_idx + 2] = PACKET2(0);
1006                 ib[h_idx + 3] = PACKET2(0);
1007         } else if (crtc_id == 1) {
1008                 switch (reg) {
1009                 case AVIVO_D1MODE_VLINE_START_END:
1010                         header &= ~R300_CP_PACKET0_REG_MASK;
1011                         header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1012                         break;
1013                 case RADEON_CRTC_GUI_TRIG_VLINE:
1014                         header &= ~R300_CP_PACKET0_REG_MASK;
1015                         header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1016                         break;
1017                 default:
1018                         DRM_ERROR("unknown crtc reloc\n");
1019                         r = -EINVAL;
1020                         goto out;
1021                 }
1022                 ib[h_idx] = header;
1023                 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1024         }
1025 out:
1026         mutex_unlock(&p->rdev->ddev->mode_config.mutex);
1027         return r;
1028 }
1029
1030 /**
1031  * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1032  * @parser:             parser structure holding parsing context.
1033  * @data:               pointer to relocation data
1034  * @offset_start:       starting offset
1035  * @offset_mask:        offset mask (to align start offset on)
1036  * @reloc:              reloc informations
1037  *
1038  * Check next packet is relocation packet3, do bo validation and compute
1039  * GPU offset using the provided start.
1040  **/
1041 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1042                               struct radeon_cs_reloc **cs_reloc)
1043 {
1044         struct radeon_cs_chunk *relocs_chunk;
1045         struct radeon_cs_packet p3reloc;
1046         unsigned idx;
1047         int r;
1048
1049         if (p->chunk_relocs_idx == -1) {
1050                 DRM_ERROR("No relocation chunk !\n");
1051                 return -EINVAL;
1052         }
1053         *cs_reloc = NULL;
1054         relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1055         r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1056         if (r) {
1057                 return r;
1058         }
1059         p->idx += p3reloc.count + 2;
1060         if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1061                 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1062                           p3reloc.idx);
1063                 r100_cs_dump_packet(p, &p3reloc);
1064                 return -EINVAL;
1065         }
1066         idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1067         if (idx >= relocs_chunk->length_dw) {
1068                 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1069                           idx, relocs_chunk->length_dw);
1070                 r100_cs_dump_packet(p, &p3reloc);
1071                 return -EINVAL;
1072         }
1073         /* FIXME: we assume reloc size is 4 dwords */
1074         *cs_reloc = p->relocs_ptr[(idx / 4)];
1075         return 0;
1076 }
1077
1078 static int r100_get_vtx_size(uint32_t vtx_fmt)
1079 {
1080         int vtx_size;
1081         vtx_size = 2;
1082         /* ordered according to bits in spec */
1083         if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1084                 vtx_size++;
1085         if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1086                 vtx_size += 3;
1087         if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1088                 vtx_size++;
1089         if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1090                 vtx_size++;
1091         if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1092                 vtx_size += 3;
1093         if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1094                 vtx_size++;
1095         if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1096                 vtx_size++;
1097         if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1098                 vtx_size += 2;
1099         if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1100                 vtx_size += 2;
1101         if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1102                 vtx_size++;
1103         if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1104                 vtx_size += 2;
1105         if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1106                 vtx_size++;
1107         if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1108                 vtx_size += 2;
1109         if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1110                 vtx_size++;
1111         if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1112                 vtx_size++;
1113         /* blend weight */
1114         if (vtx_fmt & (0x7 << 15))
1115                 vtx_size += (vtx_fmt >> 15) & 0x7;
1116         if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1117                 vtx_size += 3;
1118         if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1119                 vtx_size += 2;
1120         if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1121                 vtx_size++;
1122         if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1123                 vtx_size++;
1124         if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1125                 vtx_size++;
1126         if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1127                 vtx_size++;
1128         return vtx_size;
1129 }
1130
1131 static int r100_packet0_check(struct radeon_cs_parser *p,
1132                               struct radeon_cs_packet *pkt,
1133                               unsigned idx, unsigned reg)
1134 {
1135         struct radeon_cs_reloc *reloc;
1136         struct r100_cs_track *track;
1137         volatile uint32_t *ib;
1138         uint32_t tmp;
1139         int r;
1140         int i, face;
1141         u32 tile_flags = 0;
1142         u32 idx_value;
1143
1144         ib = p->ib->ptr;
1145         track = (struct r100_cs_track *)p->track;
1146
1147         idx_value = radeon_get_ib_value(p, idx);
1148
1149         switch (reg) {
1150         case RADEON_CRTC_GUI_TRIG_VLINE:
1151                 r = r100_cs_packet_parse_vline(p);
1152                 if (r) {
1153                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1154                                   idx, reg);
1155                         r100_cs_dump_packet(p, pkt);
1156                         return r;
1157                 }
1158                 break;
1159                 /* FIXME: only allow PACKET3 blit? easier to check for out of
1160                  * range access */
1161         case RADEON_DST_PITCH_OFFSET:
1162         case RADEON_SRC_PITCH_OFFSET:
1163                 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1164                 if (r)
1165                         return r;
1166                 break;
1167         case RADEON_RB3D_DEPTHOFFSET:
1168                 r = r100_cs_packet_next_reloc(p, &reloc);
1169                 if (r) {
1170                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1171                                   idx, reg);
1172                         r100_cs_dump_packet(p, pkt);
1173                         return r;
1174                 }
1175                 track->zb.robj = reloc->robj;
1176                 track->zb.offset = idx_value;
1177                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1178                 break;
1179         case RADEON_RB3D_COLOROFFSET:
1180                 r = r100_cs_packet_next_reloc(p, &reloc);
1181                 if (r) {
1182                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1183                                   idx, reg);
1184                         r100_cs_dump_packet(p, pkt);
1185                         return r;
1186                 }
1187                 track->cb[0].robj = reloc->robj;
1188                 track->cb[0].offset = idx_value;
1189                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1190                 break;
1191         case RADEON_PP_TXOFFSET_0:
1192         case RADEON_PP_TXOFFSET_1:
1193         case RADEON_PP_TXOFFSET_2:
1194                 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1195                 r = r100_cs_packet_next_reloc(p, &reloc);
1196                 if (r) {
1197                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1198                                   idx, reg);
1199                         r100_cs_dump_packet(p, pkt);
1200                         return r;
1201                 }
1202                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1203                 track->textures[i].robj = reloc->robj;
1204                 break;
1205         case RADEON_PP_CUBIC_OFFSET_T0_0:
1206         case RADEON_PP_CUBIC_OFFSET_T0_1:
1207         case RADEON_PP_CUBIC_OFFSET_T0_2:
1208         case RADEON_PP_CUBIC_OFFSET_T0_3:
1209         case RADEON_PP_CUBIC_OFFSET_T0_4:
1210                 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1211                 r = r100_cs_packet_next_reloc(p, &reloc);
1212                 if (r) {
1213                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1214                                   idx, reg);
1215                         r100_cs_dump_packet(p, pkt);
1216                         return r;
1217                 }
1218                 track->textures[0].cube_info[i].offset = idx_value;
1219                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1220                 track->textures[0].cube_info[i].robj = reloc->robj;
1221                 break;
1222         case RADEON_PP_CUBIC_OFFSET_T1_0:
1223         case RADEON_PP_CUBIC_OFFSET_T1_1:
1224         case RADEON_PP_CUBIC_OFFSET_T1_2:
1225         case RADEON_PP_CUBIC_OFFSET_T1_3:
1226         case RADEON_PP_CUBIC_OFFSET_T1_4:
1227                 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1228                 r = r100_cs_packet_next_reloc(p, &reloc);
1229                 if (r) {
1230                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1231                                   idx, reg);
1232                         r100_cs_dump_packet(p, pkt);
1233                         return r;
1234                 }
1235                 track->textures[1].cube_info[i].offset = idx_value;
1236                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1237                 track->textures[1].cube_info[i].robj = reloc->robj;
1238                 break;
1239         case RADEON_PP_CUBIC_OFFSET_T2_0:
1240         case RADEON_PP_CUBIC_OFFSET_T2_1:
1241         case RADEON_PP_CUBIC_OFFSET_T2_2:
1242         case RADEON_PP_CUBIC_OFFSET_T2_3:
1243         case RADEON_PP_CUBIC_OFFSET_T2_4:
1244                 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1245                 r = r100_cs_packet_next_reloc(p, &reloc);
1246                 if (r) {
1247                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1248                                   idx, reg);
1249                         r100_cs_dump_packet(p, pkt);
1250                         return r;
1251                 }
1252                 track->textures[2].cube_info[i].offset = idx_value;
1253                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1254                 track->textures[2].cube_info[i].robj = reloc->robj;
1255                 break;
1256         case RADEON_RE_WIDTH_HEIGHT:
1257                 track->maxy = ((idx_value >> 16) & 0x7FF);
1258                 break;
1259         case RADEON_RB3D_COLORPITCH:
1260                 r = r100_cs_packet_next_reloc(p, &reloc);
1261                 if (r) {
1262                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1263                                   idx, reg);
1264                         r100_cs_dump_packet(p, pkt);
1265                         return r;
1266                 }
1267
1268                 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1269                         tile_flags |= RADEON_COLOR_TILE_ENABLE;
1270                 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1271                         tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1272
1273                 tmp = idx_value & ~(0x7 << 16);
1274                 tmp |= tile_flags;
1275                 ib[idx] = tmp;
1276
1277                 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1278                 break;
1279         case RADEON_RB3D_DEPTHPITCH:
1280                 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1281                 break;
1282         case RADEON_RB3D_CNTL:
1283                 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1284                 case 7:
1285                 case 8:
1286                 case 9:
1287                 case 11:
1288                 case 12:
1289                         track->cb[0].cpp = 1;
1290                         break;
1291                 case 3:
1292                 case 4:
1293                 case 15:
1294                         track->cb[0].cpp = 2;
1295                         break;
1296                 case 6:
1297                         track->cb[0].cpp = 4;
1298                         break;
1299                 default:
1300                         DRM_ERROR("Invalid color buffer format (%d) !\n",
1301                                   ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1302                         return -EINVAL;
1303                 }
1304                 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1305                 break;
1306         case RADEON_RB3D_ZSTENCILCNTL:
1307                 switch (idx_value & 0xf) {
1308                 case 0:
1309                         track->zb.cpp = 2;
1310                         break;
1311                 case 2:
1312                 case 3:
1313                 case 4:
1314                 case 5:
1315                 case 9:
1316                 case 11:
1317                         track->zb.cpp = 4;
1318                         break;
1319                 default:
1320                         break;
1321                 }
1322                 break;
1323         case RADEON_RB3D_ZPASS_ADDR:
1324                 r = r100_cs_packet_next_reloc(p, &reloc);
1325                 if (r) {
1326                         DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1327                                   idx, reg);
1328                         r100_cs_dump_packet(p, pkt);
1329                         return r;
1330                 }
1331                 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1332                 break;
1333         case RADEON_PP_CNTL:
1334                 {
1335                         uint32_t temp = idx_value >> 4;
1336                         for (i = 0; i < track->num_texture; i++)
1337                                 track->textures[i].enabled = !!(temp & (1 << i));
1338                 }
1339                 break;
1340         case RADEON_SE_VF_CNTL:
1341                 track->vap_vf_cntl = idx_value;
1342                 break;
1343         case RADEON_SE_VTX_FMT:
1344                 track->vtx_size = r100_get_vtx_size(idx_value);
1345                 break;
1346         case RADEON_PP_TEX_SIZE_0:
1347         case RADEON_PP_TEX_SIZE_1:
1348         case RADEON_PP_TEX_SIZE_2:
1349                 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1350                 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1351                 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1352                 break;
1353         case RADEON_PP_TEX_PITCH_0:
1354         case RADEON_PP_TEX_PITCH_1:
1355         case RADEON_PP_TEX_PITCH_2:
1356                 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1357                 track->textures[i].pitch = idx_value + 32;
1358                 break;
1359         case RADEON_PP_TXFILTER_0:
1360         case RADEON_PP_TXFILTER_1:
1361         case RADEON_PP_TXFILTER_2:
1362                 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1363                 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1364                                                  >> RADEON_MAX_MIP_LEVEL_SHIFT);
1365                 tmp = (idx_value >> 23) & 0x7;
1366                 if (tmp == 2 || tmp == 6)
1367                         track->textures[i].roundup_w = false;
1368                 tmp = (idx_value >> 27) & 0x7;
1369                 if (tmp == 2 || tmp == 6)
1370                         track->textures[i].roundup_h = false;
1371                 break;
1372         case RADEON_PP_TXFORMAT_0:
1373         case RADEON_PP_TXFORMAT_1:
1374         case RADEON_PP_TXFORMAT_2:
1375                 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1376                 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1377                         track->textures[i].use_pitch = 1;
1378                 } else {
1379                         track->textures[i].use_pitch = 0;
1380                         track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1381                         track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1382                 }
1383                 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1384                         track->textures[i].tex_coord_type = 2;
1385                 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1386                 case RADEON_TXFORMAT_I8:
1387                 case RADEON_TXFORMAT_RGB332:
1388                 case RADEON_TXFORMAT_Y8:
1389                         track->textures[i].cpp = 1;
1390                         break;
1391                 case RADEON_TXFORMAT_AI88:
1392                 case RADEON_TXFORMAT_ARGB1555:
1393                 case RADEON_TXFORMAT_RGB565:
1394                 case RADEON_TXFORMAT_ARGB4444:
1395                 case RADEON_TXFORMAT_VYUY422:
1396                 case RADEON_TXFORMAT_YVYU422:
1397                 case RADEON_TXFORMAT_SHADOW16:
1398                 case RADEON_TXFORMAT_LDUDV655:
1399                 case RADEON_TXFORMAT_DUDV88:
1400                         track->textures[i].cpp = 2;
1401                         break;
1402                 case RADEON_TXFORMAT_ARGB8888:
1403                 case RADEON_TXFORMAT_RGBA8888:
1404                 case RADEON_TXFORMAT_SHADOW32:
1405                 case RADEON_TXFORMAT_LDUDUV8888:
1406                         track->textures[i].cpp = 4;
1407                         break;
1408                 case RADEON_TXFORMAT_DXT1:
1409                         track->textures[i].cpp = 1;
1410                         track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1411                         break;
1412                 case RADEON_TXFORMAT_DXT23:
1413                 case RADEON_TXFORMAT_DXT45:
1414                         track->textures[i].cpp = 1;
1415                         track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1416                         break;
1417                 }
1418                 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1419                 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1420                 break;
1421         case RADEON_PP_CUBIC_FACES_0:
1422         case RADEON_PP_CUBIC_FACES_1:
1423         case RADEON_PP_CUBIC_FACES_2:
1424                 tmp = idx_value;
1425                 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1426                 for (face = 0; face < 4; face++) {
1427                         track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1428                         track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1429                 }
1430                 break;
1431         default:
1432                 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1433                        reg, idx);
1434                 return -EINVAL;
1435         }
1436         return 0;
1437 }
1438
1439 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1440                                          struct radeon_cs_packet *pkt,
1441                                          struct radeon_bo *robj)
1442 {
1443         unsigned idx;
1444         u32 value;
1445         idx = pkt->idx + 1;
1446         value = radeon_get_ib_value(p, idx + 2);
1447         if ((value + 1) > radeon_bo_size(robj)) {
1448                 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1449                           "(need %u have %lu) !\n",
1450                           value + 1,
1451                           radeon_bo_size(robj));
1452                 return -EINVAL;
1453         }
1454         return 0;
1455 }
1456
1457 static int r100_packet3_check(struct radeon_cs_parser *p,
1458                               struct radeon_cs_packet *pkt)
1459 {
1460         struct radeon_cs_reloc *reloc;
1461         struct r100_cs_track *track;
1462         unsigned idx;
1463         volatile uint32_t *ib;
1464         int r;
1465
1466         ib = p->ib->ptr;
1467         idx = pkt->idx + 1;
1468         track = (struct r100_cs_track *)p->track;
1469         switch (pkt->opcode) {
1470         case PACKET3_3D_LOAD_VBPNTR:
1471                 r = r100_packet3_load_vbpntr(p, pkt, idx);
1472                 if (r)
1473                         return r;
1474                 break;
1475         case PACKET3_INDX_BUFFER:
1476                 r = r100_cs_packet_next_reloc(p, &reloc);
1477                 if (r) {
1478                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1479                         r100_cs_dump_packet(p, pkt);
1480                         return r;
1481                 }
1482                 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1483                 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1484                 if (r) {
1485                         return r;
1486                 }
1487                 break;
1488         case 0x23:
1489                 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1490                 r = r100_cs_packet_next_reloc(p, &reloc);
1491                 if (r) {
1492                         DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1493                         r100_cs_dump_packet(p, pkt);
1494                         return r;
1495                 }
1496                 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1497                 track->num_arrays = 1;
1498                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1499
1500                 track->arrays[0].robj = reloc->robj;
1501                 track->arrays[0].esize = track->vtx_size;
1502
1503                 track->max_indx = radeon_get_ib_value(p, idx+1);
1504
1505                 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1506                 track->immd_dwords = pkt->count - 1;
1507                 r = r100_cs_track_check(p->rdev, track);
1508                 if (r)
1509                         return r;
1510                 break;
1511         case PACKET3_3D_DRAW_IMMD:
1512                 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1513                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1514                         return -EINVAL;
1515                 }
1516                 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1517                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1518                 track->immd_dwords = pkt->count - 1;
1519                 r = r100_cs_track_check(p->rdev, track);
1520                 if (r)
1521                         return r;
1522                 break;
1523                 /* triggers drawing using in-packet vertex data */
1524         case PACKET3_3D_DRAW_IMMD_2:
1525                 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1526                         DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1527                         return -EINVAL;
1528                 }
1529                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1530                 track->immd_dwords = pkt->count;
1531                 r = r100_cs_track_check(p->rdev, track);
1532                 if (r)
1533                         return r;
1534                 break;
1535                 /* triggers drawing using in-packet vertex data */
1536         case PACKET3_3D_DRAW_VBUF_2:
1537                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1538                 r = r100_cs_track_check(p->rdev, track);
1539                 if (r)
1540                         return r;
1541                 break;
1542                 /* triggers drawing of vertex buffers setup elsewhere */
1543         case PACKET3_3D_DRAW_INDX_2:
1544                 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1545                 r = r100_cs_track_check(p->rdev, track);
1546                 if (r)
1547                         return r;
1548                 break;
1549                 /* triggers drawing using indices to vertex buffer */
1550         case PACKET3_3D_DRAW_VBUF:
1551                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1552                 r = r100_cs_track_check(p->rdev, track);
1553                 if (r)
1554                         return r;
1555                 break;
1556                 /* triggers drawing of vertex buffers setup elsewhere */
1557         case PACKET3_3D_DRAW_INDX:
1558                 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1559                 r = r100_cs_track_check(p->rdev, track);
1560                 if (r)
1561                         return r;
1562                 break;
1563                 /* triggers drawing using indices to vertex buffer */
1564         case PACKET3_NOP:
1565                 break;
1566         default:
1567                 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1568                 return -EINVAL;
1569         }
1570         return 0;
1571 }
1572
1573 int r100_cs_parse(struct radeon_cs_parser *p)
1574 {
1575         struct radeon_cs_packet pkt;
1576         struct r100_cs_track *track;
1577         int r;
1578
1579         track = kzalloc(sizeof(*track), GFP_KERNEL);
1580         r100_cs_track_clear(p->rdev, track);
1581         p->track = track;
1582         do {
1583                 r = r100_cs_packet_parse(p, &pkt, p->idx);
1584                 if (r) {
1585                         return r;
1586                 }
1587                 p->idx += pkt.count + 2;
1588                 switch (pkt.type) {
1589                         case PACKET_TYPE0:
1590                                 if (p->rdev->family >= CHIP_R200)
1591                                         r = r100_cs_parse_packet0(p, &pkt,
1592                                                                   p->rdev->config.r100.reg_safe_bm,
1593                                                                   p->rdev->config.r100.reg_safe_bm_size,
1594                                                                   &r200_packet0_check);
1595                                 else
1596                                         r = r100_cs_parse_packet0(p, &pkt,
1597                                                                   p->rdev->config.r100.reg_safe_bm,
1598                                                                   p->rdev->config.r100.reg_safe_bm_size,
1599                                                                   &r100_packet0_check);
1600                                 break;
1601                         case PACKET_TYPE2:
1602                                 break;
1603                         case PACKET_TYPE3:
1604                                 r = r100_packet3_check(p, &pkt);
1605                                 break;
1606                         default:
1607                                 DRM_ERROR("Unknown packet type %d !\n",
1608                                           pkt.type);
1609                                 return -EINVAL;
1610                 }
1611                 if (r) {
1612                         return r;
1613                 }
1614         } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1615         return 0;
1616 }
1617
1618
1619 /*
1620  * Global GPU functions
1621  */
1622 void r100_errata(struct radeon_device *rdev)
1623 {
1624         rdev->pll_errata = 0;
1625
1626         if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1627                 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1628         }
1629
1630         if (rdev->family == CHIP_RV100 ||
1631             rdev->family == CHIP_RS100 ||
1632             rdev->family == CHIP_RS200) {
1633                 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1634         }
1635 }
1636
1637 /* Wait for vertical sync on primary CRTC */
1638 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1639 {
1640         uint32_t crtc_gen_cntl, tmp;
1641         int i;
1642
1643         crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1644         if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1645             !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1646                 return;
1647         }
1648         /* Clear the CRTC_VBLANK_SAVE bit */
1649         WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1650         for (i = 0; i < rdev->usec_timeout; i++) {
1651                 tmp = RREG32(RADEON_CRTC_STATUS);
1652                 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1653                         return;
1654                 }
1655                 DRM_UDELAY(1);
1656         }
1657 }
1658
1659 /* Wait for vertical sync on secondary CRTC */
1660 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1661 {
1662         uint32_t crtc2_gen_cntl, tmp;
1663         int i;
1664
1665         crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1666         if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1667             !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1668                 return;
1669
1670         /* Clear the CRTC_VBLANK_SAVE bit */
1671         WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1672         for (i = 0; i < rdev->usec_timeout; i++) {
1673                 tmp = RREG32(RADEON_CRTC2_STATUS);
1674                 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1675                         return;
1676                 }
1677                 DRM_UDELAY(1);
1678         }
1679 }
1680
1681 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1682 {
1683         unsigned i;
1684         uint32_t tmp;
1685
1686         for (i = 0; i < rdev->usec_timeout; i++) {
1687                 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1688                 if (tmp >= n) {
1689                         return 0;
1690                 }
1691                 DRM_UDELAY(1);
1692         }
1693         return -1;
1694 }
1695
1696 int r100_gui_wait_for_idle(struct radeon_device *rdev)
1697 {
1698         unsigned i;
1699         uint32_t tmp;
1700
1701         if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1702                 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1703                        " Bad things might happen.\n");
1704         }
1705         for (i = 0; i < rdev->usec_timeout; i++) {
1706                 tmp = RREG32(RADEON_RBBM_STATUS);
1707                 if (!(tmp & RADEON_RBBM_ACTIVE)) {
1708                         return 0;
1709                 }
1710                 DRM_UDELAY(1);
1711         }
1712         return -1;
1713 }
1714
1715 int r100_mc_wait_for_idle(struct radeon_device *rdev)
1716 {
1717         unsigned i;
1718         uint32_t tmp;
1719
1720         for (i = 0; i < rdev->usec_timeout; i++) {
1721                 /* read MC_STATUS */
1722                 tmp = RREG32(RADEON_MC_STATUS);
1723                 if (tmp & RADEON_MC_IDLE) {
1724                         return 0;
1725                 }
1726                 DRM_UDELAY(1);
1727         }
1728         return -1;
1729 }
1730
1731 void r100_gpu_init(struct radeon_device *rdev)
1732 {
1733         /* TODO: anythings to do here ? pipes ? */
1734         r100_hdp_reset(rdev);
1735 }
1736
1737 void r100_hdp_reset(struct radeon_device *rdev)
1738 {
1739         uint32_t tmp;
1740
1741         tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
1742         tmp |= (7 << 28);
1743         WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
1744         (void)RREG32(RADEON_HOST_PATH_CNTL);
1745         udelay(200);
1746         WREG32(RADEON_RBBM_SOFT_RESET, 0);
1747         WREG32(RADEON_HOST_PATH_CNTL, tmp);
1748         (void)RREG32(RADEON_HOST_PATH_CNTL);
1749 }
1750
1751 int r100_rb2d_reset(struct radeon_device *rdev)
1752 {
1753         uint32_t tmp;
1754         int i;
1755
1756         WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2);
1757         (void)RREG32(RADEON_RBBM_SOFT_RESET);
1758         udelay(200);
1759         WREG32(RADEON_RBBM_SOFT_RESET, 0);
1760         /* Wait to prevent race in RBBM_STATUS */
1761         mdelay(1);
1762         for (i = 0; i < rdev->usec_timeout; i++) {
1763                 tmp = RREG32(RADEON_RBBM_STATUS);
1764                 if (!(tmp & (1 << 26))) {
1765                         DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
1766                                  tmp);
1767                         return 0;
1768                 }
1769                 DRM_UDELAY(1);
1770         }
1771         tmp = RREG32(RADEON_RBBM_STATUS);
1772         DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);
1773         return -1;
1774 }
1775
1776 int r100_gpu_reset(struct radeon_device *rdev)
1777 {
1778         uint32_t status;
1779
1780         /* reset order likely matter */
1781         status = RREG32(RADEON_RBBM_STATUS);
1782         /* reset HDP */
1783         r100_hdp_reset(rdev);
1784         /* reset rb2d */
1785         if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
1786                 r100_rb2d_reset(rdev);
1787         }
1788         /* TODO: reset 3D engine */
1789         /* reset CP */
1790         status = RREG32(RADEON_RBBM_STATUS);
1791         if (status & (1 << 16)) {
1792                 r100_cp_reset(rdev);
1793         }
1794         /* Check if GPU is idle */
1795         status = RREG32(RADEON_RBBM_STATUS);
1796         if (status & RADEON_RBBM_ACTIVE) {
1797                 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
1798                 return -1;
1799         }
1800         DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
1801         return 0;
1802 }
1803
1804 void r100_set_common_regs(struct radeon_device *rdev)
1805 {
1806         struct drm_device *dev = rdev->ddev;
1807         bool force_dac2 = false;
1808
1809         /* set these so they don't interfere with anything */
1810         WREG32(RADEON_OV0_SCALE_CNTL, 0);
1811         WREG32(RADEON_SUBPIC_CNTL, 0);
1812         WREG32(RADEON_VIPH_CONTROL, 0);
1813         WREG32(RADEON_I2C_CNTL_1, 0);
1814         WREG32(RADEON_DVI_I2C_CNTL_1, 0);
1815         WREG32(RADEON_CAP0_TRIG_CNTL, 0);
1816         WREG32(RADEON_CAP1_TRIG_CNTL, 0);
1817
1818         /* always set up dac2 on rn50 and some rv100 as lots
1819          * of servers seem to wire it up to a VGA port but
1820          * don't report it in the bios connector
1821          * table.
1822          */
1823         switch (dev->pdev->device) {
1824                 /* RN50 */
1825         case 0x515e:
1826         case 0x5969:
1827                 force_dac2 = true;
1828                 break;
1829                 /* RV100*/
1830         case 0x5159:
1831         case 0x515a:
1832                 /* DELL triple head servers */
1833                 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
1834                     ((dev->pdev->subsystem_device == 0x016c) ||
1835                      (dev->pdev->subsystem_device == 0x016d) ||
1836                      (dev->pdev->subsystem_device == 0x016e) ||
1837                      (dev->pdev->subsystem_device == 0x016f) ||
1838                      (dev->pdev->subsystem_device == 0x0170) ||
1839                      (dev->pdev->subsystem_device == 0x017d) ||
1840                      (dev->pdev->subsystem_device == 0x017e) ||
1841                      (dev->pdev->subsystem_device == 0x0183) ||
1842                      (dev->pdev->subsystem_device == 0x018a) ||
1843                      (dev->pdev->subsystem_device == 0x019a)))
1844                         force_dac2 = true;
1845                 break;
1846         }
1847
1848         if (force_dac2) {
1849                 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1850                 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1851                 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
1852
1853                 /* For CRT on DAC2, don't turn it on if BIOS didn't
1854                    enable it, even it's detected.
1855                 */
1856
1857                 /* force it to crtc0 */
1858                 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
1859                 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
1860                 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1861
1862                 /* set up the TV DAC */
1863                 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
1864                                  RADEON_TV_DAC_STD_MASK |
1865                                  RADEON_TV_DAC_RDACPD |
1866                                  RADEON_TV_DAC_GDACPD |
1867                                  RADEON_TV_DAC_BDACPD |
1868                                  RADEON_TV_DAC_BGADJ_MASK |
1869                                  RADEON_TV_DAC_DACADJ_MASK);
1870                 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
1871                                 RADEON_TV_DAC_NHOLD |
1872                                 RADEON_TV_DAC_STD_PS2 |
1873                                 (0x58 << 16));
1874
1875                 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1876                 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1877                 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1878         }
1879 }
1880
1881 /*
1882  * VRAM info
1883  */
1884 static void r100_vram_get_type(struct radeon_device *rdev)
1885 {
1886         uint32_t tmp;
1887
1888         rdev->mc.vram_is_ddr = false;
1889         if (rdev->flags & RADEON_IS_IGP)
1890                 rdev->mc.vram_is_ddr = true;
1891         else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
1892                 rdev->mc.vram_is_ddr = true;
1893         if ((rdev->family == CHIP_RV100) ||
1894             (rdev->family == CHIP_RS100) ||
1895             (rdev->family == CHIP_RS200)) {
1896                 tmp = RREG32(RADEON_MEM_CNTL);
1897                 if (tmp & RV100_HALF_MODE) {
1898                         rdev->mc.vram_width = 32;
1899                 } else {
1900                         rdev->mc.vram_width = 64;
1901                 }
1902                 if (rdev->flags & RADEON_SINGLE_CRTC) {
1903                         rdev->mc.vram_width /= 4;
1904                         rdev->mc.vram_is_ddr = true;
1905                 }
1906         } else if (rdev->family <= CHIP_RV280) {
1907                 tmp = RREG32(RADEON_MEM_CNTL);
1908                 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
1909                         rdev->mc.vram_width = 128;
1910                 } else {
1911                         rdev->mc.vram_width = 64;
1912                 }
1913         } else {
1914                 /* newer IGPs */
1915                 rdev->mc.vram_width = 128;
1916         }
1917 }
1918
1919 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
1920 {
1921         u32 aper_size;
1922         u8 byte;
1923
1924         aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1925
1926         /* Set HDP_APER_CNTL only on cards that are known not to be broken,
1927          * that is has the 2nd generation multifunction PCI interface
1928          */
1929         if (rdev->family == CHIP_RV280 ||
1930             rdev->family >= CHIP_RV350) {
1931                 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
1932                        ~RADEON_HDP_APER_CNTL);
1933                 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
1934                 return aper_size * 2;
1935         }
1936
1937         /* Older cards have all sorts of funny issues to deal with. First
1938          * check if it's a multifunction card by reading the PCI config
1939          * header type... Limit those to one aperture size
1940          */
1941         pci_read_config_byte(rdev->pdev, 0xe, &byte);
1942         if (byte & 0x80) {
1943                 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
1944                 DRM_INFO("Limiting VRAM to one aperture\n");
1945                 return aper_size;
1946         }
1947
1948         /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
1949          * have set it up. We don't write this as it's broken on some ASICs but
1950          * we expect the BIOS to have done the right thing (might be too optimistic...)
1951          */
1952         if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
1953                 return aper_size * 2;
1954         return aper_size;
1955 }
1956
1957 void r100_vram_init_sizes(struct radeon_device *rdev)
1958 {
1959         u64 config_aper_size;
1960
1961         /* work out accessible VRAM */
1962         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1963         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1964         rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
1965         /* FIXME we don't use the second aperture yet when we could use it */
1966         if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
1967                 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1968         config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1969         if (rdev->flags & RADEON_IS_IGP) {
1970                 uint32_t tom;
1971                 /* read NB_TOM to get the amount of ram stolen for the GPU */
1972                 tom = RREG32(RADEON_NB_TOM);
1973                 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
1974                 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1975                 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1976         } else {
1977                 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
1978                 /* Some production boards of m6 will report 0
1979                  * if it's 8 MB
1980                  */
1981                 if (rdev->mc.real_vram_size == 0) {
1982                         rdev->mc.real_vram_size = 8192 * 1024;
1983                         WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1984                 }
1985                 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - 
1986                  * Novell bug 204882 + along with lots of ubuntu ones
1987                  */
1988                 if (config_aper_size > rdev->mc.real_vram_size)
1989                         rdev->mc.mc_vram_size = config_aper_size;
1990                 else
1991                         rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1992         }
1993         /* FIXME remove this once we support unmappable VRAM */
1994         if (rdev->mc.mc_vram_size > rdev->mc.aper_size) {
1995                 rdev->mc.mc_vram_size = rdev->mc.aper_size;
1996                 rdev->mc.real_vram_size = rdev->mc.aper_size;
1997         }
1998 }
1999
2000 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2001 {
2002         uint32_t temp;
2003
2004         temp = RREG32(RADEON_CONFIG_CNTL);
2005         if (state == false) {
2006                 temp &= ~(1<<8);
2007                 temp |= (1<<9);
2008         } else {
2009                 temp &= ~(1<<9);
2010         }
2011         WREG32(RADEON_CONFIG_CNTL, temp);
2012 }
2013
2014 void r100_mc_init(struct radeon_device *rdev)
2015 {
2016         u64 base;
2017
2018         r100_vram_get_type(rdev);
2019         r100_vram_init_sizes(rdev);
2020         base = rdev->mc.aper_base;
2021         if (rdev->flags & RADEON_IS_IGP)
2022                 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2023         radeon_vram_location(rdev, &rdev->mc, base);
2024         if (!(rdev->flags & RADEON_IS_AGP))
2025                 radeon_gtt_location(rdev, &rdev->mc);
2026 }
2027
2028
2029 /*
2030  * Indirect registers accessor
2031  */
2032 void r100_pll_errata_after_index(struct radeon_device *rdev)
2033 {
2034         if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
2035                 return;
2036         }
2037         (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2038         (void)RREG32(RADEON_CRTC_GEN_CNTL);
2039 }
2040
2041 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2042 {
2043         /* This workarounds is necessary on RV100, RS100 and RS200 chips
2044          * or the chip could hang on a subsequent access
2045          */
2046         if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2047                 udelay(5000);
2048         }
2049
2050         /* This function is required to workaround a hardware bug in some (all?)
2051          * revisions of the R300.  This workaround should be called after every
2052          * CLOCK_CNTL_INDEX register access.  If not, register reads afterward
2053          * may not be correct.
2054          */
2055         if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2056                 uint32_t save, tmp;
2057
2058                 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2059                 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2060                 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2061                 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2062                 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2063         }
2064 }
2065
2066 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2067 {
2068         uint32_t data;
2069
2070         WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2071         r100_pll_errata_after_index(rdev);
2072         data = RREG32(RADEON_CLOCK_CNTL_DATA);
2073         r100_pll_errata_after_data(rdev);
2074         return data;
2075 }
2076
2077 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2078 {
2079         WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2080         r100_pll_errata_after_index(rdev);
2081         WREG32(RADEON_CLOCK_CNTL_DATA, v);
2082         r100_pll_errata_after_data(rdev);
2083 }
2084
2085 void r100_set_safe_registers(struct radeon_device *rdev)
2086 {
2087         if (ASIC_IS_RN50(rdev)) {
2088                 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2089                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2090         } else if (rdev->family < CHIP_R200) {
2091                 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2092                 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2093         } else {
2094                 r200_set_safe_registers(rdev);
2095         }
2096 }
2097
2098 /*
2099  * Debugfs info
2100  */
2101 #if defined(CONFIG_DEBUG_FS)
2102 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2103 {
2104         struct drm_info_node *node = (struct drm_info_node *) m->private;
2105         struct drm_device *dev = node->minor->dev;
2106         struct radeon_device *rdev = dev->dev_private;
2107         uint32_t reg, value;
2108         unsigned i;
2109
2110         seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2111         seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2112         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2113         for (i = 0; i < 64; i++) {
2114                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2115                 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2116                 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2117                 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2118                 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2119         }
2120         return 0;
2121 }
2122
2123 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2124 {
2125         struct drm_info_node *node = (struct drm_info_node *) m->private;
2126         struct drm_device *dev = node->minor->dev;
2127         struct radeon_device *rdev = dev->dev_private;
2128         uint32_t rdp, wdp;
2129         unsigned count, i, j;
2130
2131         radeon_ring_free_size(rdev);
2132         rdp = RREG32(RADEON_CP_RB_RPTR);
2133         wdp = RREG32(RADEON_CP_RB_WPTR);
2134         count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2135         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2136         seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2137         seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2138         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2139         seq_printf(m, "%u dwords in ring\n", count);
2140         for (j = 0; j <= count; j++) {
2141                 i = (rdp + j) & rdev->cp.ptr_mask;
2142                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2143         }
2144         return 0;
2145 }
2146
2147
2148 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2149 {
2150         struct drm_info_node *node = (struct drm_info_node *) m->private;
2151         struct drm_device *dev = node->minor->dev;
2152         struct radeon_device *rdev = dev->dev_private;
2153         uint32_t csq_stat, csq2_stat, tmp;
2154         unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2155         unsigned i;
2156
2157         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2158         seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2159         csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2160         csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2161         r_rptr = (csq_stat >> 0) & 0x3ff;
2162         r_wptr = (csq_stat >> 10) & 0x3ff;
2163         ib1_rptr = (csq_stat >> 20) & 0x3ff;
2164         ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2165         ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2166         ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2167         seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2168         seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2169         seq_printf(m, "Ring rptr %u\n", r_rptr);
2170         seq_printf(m, "Ring wptr %u\n", r_wptr);
2171         seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2172         seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2173         seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2174         seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2175         /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2176          * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2177         seq_printf(m, "Ring fifo:\n");
2178         for (i = 0; i < 256; i++) {
2179                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2180                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2181                 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2182         }
2183         seq_printf(m, "Indirect1 fifo:\n");
2184         for (i = 256; i <= 512; i++) {
2185                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2186                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2187                 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2188         }
2189         seq_printf(m, "Indirect2 fifo:\n");
2190         for (i = 640; i < ib1_wptr; i++) {
2191                 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2192                 tmp = RREG32(RADEON_CP_CSQ_DATA);
2193                 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2194         }
2195         return 0;
2196 }
2197
2198 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2199 {
2200         struct drm_info_node *node = (struct drm_info_node *) m->private;
2201         struct drm_device *dev = node->minor->dev;
2202         struct radeon_device *rdev = dev->dev_private;
2203         uint32_t tmp;
2204
2205         tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2206         seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2207         tmp = RREG32(RADEON_MC_FB_LOCATION);
2208         seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2209         tmp = RREG32(RADEON_BUS_CNTL);
2210         seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2211         tmp = RREG32(RADEON_MC_AGP_LOCATION);
2212         seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2213         tmp = RREG32(RADEON_AGP_BASE);
2214         seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2215         tmp = RREG32(RADEON_HOST_PATH_CNTL);
2216         seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2217         tmp = RREG32(0x01D0);
2218         seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2219         tmp = RREG32(RADEON_AIC_LO_ADDR);
2220         seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2221         tmp = RREG32(RADEON_AIC_HI_ADDR);
2222         seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2223         tmp = RREG32(0x01E4);
2224         seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2225         return 0;
2226 }
2227
2228 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2229         {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2230 };
2231
2232 static struct drm_info_list r100_debugfs_cp_list[] = {
2233         {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2234         {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2235 };
2236
2237 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2238         {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2239 };
2240 #endif
2241
2242 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2243 {
2244 #if defined(CONFIG_DEBUG_FS)
2245         return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2246 #else
2247         return 0;
2248 #endif
2249 }
2250
2251 int r100_debugfs_cp_init(struct radeon_device *rdev)
2252 {
2253 #if defined(CONFIG_DEBUG_FS)
2254         return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2255 #else
2256         return 0;
2257 #endif
2258 }
2259
2260 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2261 {
2262 #if defined(CONFIG_DEBUG_FS)
2263         return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2264 #else
2265         return 0;
2266 #endif
2267 }
2268
2269 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2270                          uint32_t tiling_flags, uint32_t pitch,
2271                          uint32_t offset, uint32_t obj_size)
2272 {
2273         int surf_index = reg * 16;
2274         int flags = 0;
2275
2276         /* r100/r200 divide by 16 */
2277         if (rdev->family < CHIP_R300)
2278                 flags = pitch / 16;
2279         else
2280                 flags = pitch / 8;
2281
2282         if (rdev->family <= CHIP_RS200) {
2283                 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2284                                  == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2285                         flags |= RADEON_SURF_TILE_COLOR_BOTH;
2286                 if (tiling_flags & RADEON_TILING_MACRO)
2287                         flags |= RADEON_SURF_TILE_COLOR_MACRO;
2288         } else if (rdev->family <= CHIP_RV280) {
2289                 if (tiling_flags & (RADEON_TILING_MACRO))
2290                         flags |= R200_SURF_TILE_COLOR_MACRO;
2291                 if (tiling_flags & RADEON_TILING_MICRO)
2292                         flags |= R200_SURF_TILE_COLOR_MICRO;
2293         } else {
2294                 if (tiling_flags & RADEON_TILING_MACRO)
2295                         flags |= R300_SURF_TILE_MACRO;
2296                 if (tiling_flags & RADEON_TILING_MICRO)
2297                         flags |= R300_SURF_TILE_MICRO;
2298         }
2299
2300         if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2301                 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2302         if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2303                 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2304
2305         DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2306         WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2307         WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2308         WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2309         return 0;
2310 }
2311
2312 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2313 {
2314         int surf_index = reg * 16;
2315         WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2316 }
2317
2318 void r100_bandwidth_update(struct radeon_device *rdev)
2319 {
2320         fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2321         fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2322         fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2323         uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2324         fixed20_12 memtcas_ff[8] = {
2325                 fixed_init(1),
2326                 fixed_init(2),
2327                 fixed_init(3),
2328                 fixed_init(0),
2329                 fixed_init_half(1),
2330                 fixed_init_half(2),
2331                 fixed_init(0),
2332         };
2333         fixed20_12 memtcas_rs480_ff[8] = {
2334                 fixed_init(0),
2335                 fixed_init(1),
2336                 fixed_init(2),
2337                 fixed_init(3),
2338                 fixed_init(0),
2339                 fixed_init_half(1),
2340                 fixed_init_half(2),
2341                 fixed_init_half(3),
2342         };
2343         fixed20_12 memtcas2_ff[8] = {
2344                 fixed_init(0),
2345                 fixed_init(1),
2346                 fixed_init(2),
2347                 fixed_init(3),
2348                 fixed_init(4),
2349                 fixed_init(5),
2350                 fixed_init(6),
2351                 fixed_init(7),
2352         };
2353         fixed20_12 memtrbs[8] = {
2354                 fixed_init(1),
2355                 fixed_init_half(1),
2356                 fixed_init(2),
2357                 fixed_init_half(2),
2358                 fixed_init(3),
2359                 fixed_init_half(3),
2360                 fixed_init(4),
2361                 fixed_init_half(4)
2362         };
2363         fixed20_12 memtrbs_r4xx[8] = {
2364                 fixed_init(4),
2365                 fixed_init(5),
2366                 fixed_init(6),
2367                 fixed_init(7),
2368                 fixed_init(8),
2369                 fixed_init(9),
2370                 fixed_init(10),
2371                 fixed_init(11)
2372         };
2373         fixed20_12 min_mem_eff;
2374         fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2375         fixed20_12 cur_latency_mclk, cur_latency_sclk;
2376         fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2377                 disp_drain_rate2, read_return_rate;
2378         fixed20_12 time_disp1_drop_priority;
2379         int c;
2380         int cur_size = 16;       /* in octawords */
2381         int critical_point = 0, critical_point2;
2382 /*      uint32_t read_return_rate, time_disp1_drop_priority; */
2383         int stop_req, max_stop_req;
2384         struct drm_display_mode *mode1 = NULL;
2385         struct drm_display_mode *mode2 = NULL;
2386         uint32_t pixel_bytes1 = 0;
2387         uint32_t pixel_bytes2 = 0;
2388
2389         if (rdev->mode_info.crtcs[0]->base.enabled) {
2390                 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2391                 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2392         }
2393         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2394                 if (rdev->mode_info.crtcs[1]->base.enabled) {
2395                         mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2396                         pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2397                 }
2398         }
2399
2400         min_mem_eff.full = rfixed_const_8(0);
2401         /* get modes */
2402         if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2403                 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2404                 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2405                 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2406                 /* check crtc enables */
2407                 if (mode2)
2408                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2409                 if (mode1)
2410                         mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2411                 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2412         }
2413
2414         /*
2415          * determine is there is enough bw for current mode
2416          */
2417         mclk_ff.full = rfixed_const(rdev->clock.default_mclk);
2418         temp_ff.full = rfixed_const(100);
2419         mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
2420         sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
2421         sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
2422
2423         temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2424         temp_ff.full = rfixed_const(temp);
2425         mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
2426
2427         pix_clk.full = 0;
2428         pix_clk2.full = 0;
2429         peak_disp_bw.full = 0;
2430         if (mode1) {
2431                 temp_ff.full = rfixed_const(1000);
2432                 pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
2433                 pix_clk.full = rfixed_div(pix_clk, temp_ff);
2434                 temp_ff.full = rfixed_const(pixel_bytes1);
2435                 peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
2436         }
2437         if (mode2) {
2438                 temp_ff.full = rfixed_const(1000);
2439                 pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
2440                 pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
2441                 temp_ff.full = rfixed_const(pixel_bytes2);
2442                 peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
2443         }
2444
2445         mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
2446         if (peak_disp_bw.full >= mem_bw.full) {
2447                 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2448                           "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2449         }
2450
2451         /*  Get values from the EXT_MEM_CNTL register...converting its contents. */
2452         temp = RREG32(RADEON_MEM_TIMING_CNTL);
2453         if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2454                 mem_trcd = ((temp >> 2) & 0x3) + 1;
2455                 mem_trp  = ((temp & 0x3)) + 1;
2456                 mem_tras = ((temp & 0x70) >> 4) + 1;
2457         } else if (rdev->family == CHIP_R300 ||
2458                    rdev->family == CHIP_R350) { /* r300, r350 */
2459                 mem_trcd = (temp & 0x7) + 1;
2460                 mem_trp = ((temp >> 8) & 0x7) + 1;
2461                 mem_tras = ((temp >> 11) & 0xf) + 4;
2462         } else if (rdev->family == CHIP_RV350 ||
2463                    rdev->family <= CHIP_RV380) {
2464                 /* rv3x0 */
2465                 mem_trcd = (temp & 0x7) + 3;
2466                 mem_trp = ((temp >> 8) & 0x7) + 3;
2467                 mem_tras = ((temp >> 11) & 0xf) + 6;
2468         } else if (rdev->family == CHIP_R420 ||
2469                    rdev->family == CHIP_R423 ||
2470                    rdev->family == CHIP_RV410) {
2471                 /* r4xx */
2472                 mem_trcd = (temp & 0xf) + 3;
2473                 if (mem_trcd > 15)
2474                         mem_trcd = 15;
2475                 mem_trp = ((temp >> 8) & 0xf) + 3;
2476                 if (mem_trp > 15)
2477                         mem_trp = 15;
2478                 mem_tras = ((temp >> 12) & 0x1f) + 6;
2479                 if (mem_tras > 31)
2480                         mem_tras = 31;
2481         } else { /* RV200, R200 */
2482                 mem_trcd = (temp & 0x7) + 1;
2483                 mem_trp = ((temp >> 8) & 0x7) + 1;
2484                 mem_tras = ((temp >> 12) & 0xf) + 4;
2485         }
2486         /* convert to FF */
2487         trcd_ff.full = rfixed_const(mem_trcd);
2488         trp_ff.full = rfixed_const(mem_trp);
2489         tras_ff.full = rfixed_const(mem_tras);
2490
2491         /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2492         temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2493         data = (temp & (7 << 20)) >> 20;
2494         if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2495                 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2496                         tcas_ff = memtcas_rs480_ff[data];
2497                 else
2498                         tcas_ff = memtcas_ff[data];
2499         } else
2500                 tcas_ff = memtcas2_ff[data];
2501
2502         if (rdev->family == CHIP_RS400 ||
2503             rdev->family == CHIP_RS480) {
2504                 /* extra cas latency stored in bits 23-25 0-4 clocks */
2505                 data = (temp >> 23) & 0x7;
2506                 if (data < 5)
2507                         tcas_ff.full += rfixed_const(data);
2508         }
2509
2510         if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2511                 /* on the R300, Tcas is included in Trbs.
2512                  */
2513                 temp = RREG32(RADEON_MEM_CNTL);
2514                 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2515                 if (data == 1) {
2516                         if (R300_MEM_USE_CD_CH_ONLY & temp) {
2517                                 temp = RREG32(R300_MC_IND_INDEX);
2518                                 temp &= ~R300_MC_IND_ADDR_MASK;
2519                                 temp |= R300_MC_READ_CNTL_CD_mcind;
2520                                 WREG32(R300_MC_IND_INDEX, temp);
2521                                 temp = RREG32(R300_MC_IND_DATA);
2522                                 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2523                         } else {
2524                                 temp = RREG32(R300_MC_READ_CNTL_AB);
2525                                 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2526                         }
2527                 } else {
2528                         temp = RREG32(R300_MC_READ_CNTL_AB);
2529                         data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2530                 }
2531                 if (rdev->family == CHIP_RV410 ||
2532                     rdev->family == CHIP_R420 ||
2533                     rdev->family == CHIP_R423)
2534                         trbs_ff = memtrbs_r4xx[data];
2535                 else
2536                         trbs_ff = memtrbs[data];
2537                 tcas_ff.full += trbs_ff.full;
2538         }
2539
2540         sclk_eff_ff.full = sclk_ff.full;
2541
2542         if (rdev->flags & RADEON_IS_AGP) {
2543                 fixed20_12 agpmode_ff;
2544                 agpmode_ff.full = rfixed_const(radeon_agpmode);
2545                 temp_ff.full = rfixed_const_666(16);
2546                 sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
2547         }
2548         /* TODO PCIE lanes may affect this - agpmode == 16?? */
2549
2550         if (ASIC_IS_R300(rdev)) {
2551                 sclk_delay_ff.full = rfixed_const(250);
2552         } else {
2553                 if ((rdev->family == CHIP_RV100) ||
2554                     rdev->flags & RADEON_IS_IGP) {
2555                         if (rdev->mc.vram_is_ddr)
2556                                 sclk_delay_ff.full = rfixed_const(41);
2557                         else
2558                                 sclk_delay_ff.full = rfixed_const(33);
2559                 } else {
2560                         if (rdev->mc.vram_width == 128)
2561                                 sclk_delay_ff.full = rfixed_const(57);
2562                         else
2563                                 sclk_delay_ff.full = rfixed_const(41);
2564                 }
2565         }
2566
2567         mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
2568
2569         if (rdev->mc.vram_is_ddr) {
2570                 if (rdev->mc.vram_width == 32) {
2571                         k1.full = rfixed_const(40);
2572                         c  = 3;
2573                 } else {
2574                         k1.full = rfixed_const(20);
2575                         c  = 1;
2576                 }
2577         } else {
2578                 k1.full = rfixed_const(40);
2579                 c  = 3;
2580         }
2581
2582         temp_ff.full = rfixed_const(2);
2583         mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
2584         temp_ff.full = rfixed_const(c);
2585         mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
2586         temp_ff.full = rfixed_const(4);
2587         mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
2588         mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
2589         mc_latency_mclk.full += k1.full;
2590
2591         mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
2592         mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
2593
2594         /*
2595           HW cursor time assuming worst case of full size colour cursor.
2596         */
2597         temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2598         temp_ff.full += trcd_ff.full;
2599         if (temp_ff.full < tras_ff.full)
2600                 temp_ff.full = tras_ff.full;
2601         cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
2602
2603         temp_ff.full = rfixed_const(cur_size);
2604         cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
2605         /*
2606           Find the total latency for the display data.
2607         */
2608         disp_latency_overhead.full = rfixed_const(8);
2609         disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
2610         mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2611         mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2612
2613         if (mc_latency_mclk.full > mc_latency_sclk.full)
2614                 disp_latency.full = mc_latency_mclk.full;
2615         else
2616                 disp_latency.full = mc_latency_sclk.full;
2617
2618         /* setup Max GRPH_STOP_REQ default value */
2619         if (ASIC_IS_RV100(rdev))
2620                 max_stop_req = 0x5c;
2621         else
2622                 max_stop_req = 0x7c;
2623
2624         if (mode1) {
2625                 /*  CRTC1
2626                     Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2627                     GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2628                 */
2629                 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2630
2631                 if (stop_req > max_stop_req)
2632                         stop_req = max_stop_req;
2633
2634                 /*
2635                   Find the drain rate of the display buffer.
2636                 */
2637                 temp_ff.full = rfixed_const((16/pixel_bytes1));
2638                 disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
2639
2640                 /*
2641                   Find the critical point of the display buffer.
2642                 */
2643                 crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
2644                 crit_point_ff.full += rfixed_const_half(0);
2645
2646                 critical_point = rfixed_trunc(crit_point_ff);
2647
2648                 if (rdev->disp_priority == 2) {
2649                         critical_point = 0;
2650                 }
2651
2652                 /*
2653                   The critical point should never be above max_stop_req-4.  Setting
2654                   GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2655                 */
2656                 if (max_stop_req - critical_point < 4)
2657                         critical_point = 0;
2658
2659                 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
2660                         /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
2661                         critical_point = 0x10;
2662                 }
2663
2664                 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
2665                 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
2666                 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2667                 temp &= ~(RADEON_GRPH_START_REQ_MASK);
2668                 if ((rdev->family == CHIP_R350) &&
2669                     (stop_req > 0x15)) {
2670                         stop_req -= 0x10;
2671                 }
2672                 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2673                 temp |= RADEON_GRPH_BUFFER_SIZE;
2674                 temp &= ~(RADEON_GRPH_CRITICAL_CNTL   |
2675                           RADEON_GRPH_CRITICAL_AT_SOF |
2676                           RADEON_GRPH_STOP_CNTL);
2677                 /*
2678                   Write the result into the register.
2679                 */
2680                 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2681                                                        (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2682
2683 #if 0
2684                 if ((rdev->family == CHIP_RS400) ||
2685                     (rdev->family == CHIP_RS480)) {
2686                         /* attempt to program RS400 disp regs correctly ??? */
2687                         temp = RREG32(RS400_DISP1_REG_CNTL);
2688                         temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
2689                                   RS400_DISP1_STOP_REQ_LEVEL_MASK);
2690                         WREG32(RS400_DISP1_REQ_CNTL1, (temp |
2691                                                        (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2692                                                        (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2693                         temp = RREG32(RS400_DMIF_MEM_CNTL1);
2694                         temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
2695                                   RS400_DISP1_CRITICAL_POINT_STOP_MASK);
2696                         WREG32(RS400_DMIF_MEM_CNTL1, (temp |
2697                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
2698                                                       (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
2699                 }
2700 #endif
2701
2702                 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
2703                           /*      (unsigned int)info->SavedReg->grph_buffer_cntl, */
2704                           (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
2705         }
2706
2707         if (mode2) {
2708                 u32 grph2_cntl;
2709                 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
2710
2711                 if (stop_req > max_stop_req)
2712                         stop_req = max_stop_req;
2713
2714                 /*
2715                   Find the drain rate of the display buffer.
2716                 */
2717                 temp_ff.full = rfixed_const((16/pixel_bytes2));
2718                 disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
2719
2720                 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
2721                 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
2722                 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2723                 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
2724                 if ((rdev->family == CHIP_R350) &&
2725                     (stop_req > 0x15)) {
2726                         stop_req -= 0x10;
2727                 }
2728                 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2729                 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
2730                 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL   |
2731                           RADEON_GRPH_CRITICAL_AT_SOF |
2732                           RADEON_GRPH_STOP_CNTL);
2733
2734                 if ((rdev->family == CHIP_RS100) ||
2735                     (rdev->family == CHIP_RS200))
2736                         critical_point2 = 0;
2737                 else {
2738                         temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
2739                         temp_ff.full = rfixed_const(temp);
2740                         temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
2741                         if (sclk_ff.full < temp_ff.full)
2742                                 temp_ff.full = sclk_ff.full;
2743
2744                         read_return_rate.full = temp_ff.full;
2745
2746                         if (mode1) {
2747                                 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
2748                                 time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
2749                         } else {
2750                                 time_disp1_drop_priority.full = 0;
2751                         }
2752                         crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
2753                         crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
2754                         crit_point_ff.full += rfixed_const_half(0);
2755
2756                         critical_point2 = rfixed_trunc(crit_point_ff);
2757
2758                         if (rdev->disp_priority == 2) {
2759                                 critical_point2 = 0;
2760                         }
2761
2762                         if (max_stop_req - critical_point2 < 4)
2763                                 critical_point2 = 0;
2764
2765                 }
2766
2767                 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
2768                         /* some R300 cards have problem with this set to 0 */
2769                         critical_point2 = 0x10;
2770                 }
2771
2772                 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2773                                                   (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2774
2775                 if ((rdev->family == CHIP_RS400) ||
2776                     (rdev->family == CHIP_RS480)) {
2777 #if 0
2778                         /* attempt to program RS400 disp2 regs correctly ??? */
2779                         temp = RREG32(RS400_DISP2_REQ_CNTL1);
2780                         temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
2781                                   RS400_DISP2_STOP_REQ_LEVEL_MASK);
2782                         WREG32(RS400_DISP2_REQ_CNTL1, (temp |
2783                                                        (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2784                                                        (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2785                         temp = RREG32(RS400_DISP2_REQ_CNTL2);
2786                         temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
2787                                   RS400_DISP2_CRITICAL_POINT_STOP_MASK);
2788                         WREG32(RS400_DISP2_REQ_CNTL2, (temp |
2789                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
2790                                                        (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
2791 #endif
2792                         WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
2793                         WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
2794                         WREG32(RS400_DMIF_MEM_CNTL1,  0x29CA71DC);
2795                         WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
2796                 }
2797
2798                 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
2799                           (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
2800         }
2801 }
2802
2803 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2804 {
2805         DRM_ERROR("pitch                      %d\n", t->pitch);
2806         DRM_ERROR("use_pitch                  %d\n", t->use_pitch);
2807         DRM_ERROR("width                      %d\n", t->width);
2808         DRM_ERROR("width_11                   %d\n", t->width_11);
2809         DRM_ERROR("height                     %d\n", t->height);
2810         DRM_ERROR("height_11                  %d\n", t->height_11);
2811         DRM_ERROR("num levels                 %d\n", t->num_levels);
2812         DRM_ERROR("depth                      %d\n", t->txdepth);
2813         DRM_ERROR("bpp                        %d\n", t->cpp);
2814         DRM_ERROR("coordinate type            %d\n", t->tex_coord_type);
2815         DRM_ERROR("width round to power of 2  %d\n", t->roundup_w);
2816         DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2817         DRM_ERROR("compress format            %d\n", t->compress_format);
2818 }
2819
2820 static int r100_cs_track_cube(struct radeon_device *rdev,
2821                               struct r100_cs_track *track, unsigned idx)
2822 {
2823         unsigned face, w, h;
2824         struct radeon_bo *cube_robj;
2825         unsigned long size;
2826
2827         for (face = 0; face < 5; face++) {
2828                 cube_robj = track->textures[idx].cube_info[face].robj;
2829                 w = track->textures[idx].cube_info[face].width;
2830                 h = track->textures[idx].cube_info[face].height;
2831
2832                 size = w * h;
2833                 size *= track->textures[idx].cpp;
2834
2835                 size += track->textures[idx].cube_info[face].offset;
2836
2837                 if (size > radeon_bo_size(cube_robj)) {
2838                         DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2839                                   size, radeon_bo_size(cube_robj));
2840                         r100_cs_track_texture_print(&track->textures[idx]);
2841                         return -1;
2842                 }
2843         }
2844         return 0;
2845 }
2846
2847 static int r100_track_compress_size(int compress_format, int w, int h)
2848 {
2849         int block_width, block_height, block_bytes;
2850         int wblocks, hblocks;
2851         int min_wblocks;
2852         int sz;
2853
2854         block_width = 4;
2855         block_height = 4;
2856
2857         switch (compress_format) {
2858         case R100_TRACK_COMP_DXT1:
2859                 block_bytes = 8;
2860                 min_wblocks = 4;
2861                 break;
2862         default:
2863         case R100_TRACK_COMP_DXT35:
2864                 block_bytes = 16;
2865                 min_wblocks = 2;
2866                 break;
2867         }
2868
2869         hblocks = (h + block_height - 1) / block_height;
2870         wblocks = (w + block_width - 1) / block_width;
2871         if (wblocks < min_wblocks)
2872                 wblocks = min_wblocks;
2873         sz = wblocks * hblocks * block_bytes;
2874         return sz;
2875 }
2876
2877 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2878                                        struct r100_cs_track *track)
2879 {
2880         struct radeon_bo *robj;
2881         unsigned long size;
2882         unsigned u, i, w, h;
2883         int ret;
2884
2885         for (u = 0; u < track->num_texture; u++) {
2886                 if (!track->textures[u].enabled)
2887                         continue;
2888                 robj = track->textures[u].robj;
2889                 if (robj == NULL) {
2890                         DRM_ERROR("No texture bound to unit %u\n", u);
2891                         return -EINVAL;
2892                 }
2893                 size = 0;
2894                 for (i = 0; i <= track->textures[u].num_levels; i++) {
2895                         if (track->textures[u].use_pitch) {
2896                                 if (rdev->family < CHIP_R300)
2897                                         w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2898                                 else
2899                                         w = track->textures[u].pitch / (1 << i);
2900                         } else {
2901                                 w = track->textures[u].width;
2902                                 if (rdev->family >= CHIP_RV515)
2903                                         w |= track->textures[u].width_11;
2904                                 w = w / (1 << i);
2905                                 if (track->textures[u].roundup_w)
2906                                         w = roundup_pow_of_two(w);
2907                         }
2908                         h = track->textures[u].height;
2909                         if (rdev->family >= CHIP_RV515)
2910                                 h |= track->textures[u].height_11;
2911                         h = h / (1 << i);
2912                         if (track->textures[u].roundup_h)
2913                                 h = roundup_pow_of_two(h);
2914                         if (track->textures[u].compress_format) {
2915
2916                                 size += r100_track_compress_size(track->textures[u].compress_format, w, h);
2917                                 /* compressed textures are block based */
2918                         } else
2919                                 size += w * h;
2920                 }
2921                 size *= track->textures[u].cpp;
2922
2923                 switch (track->textures[u].tex_coord_type) {
2924                 case 0:
2925                         break;
2926                 case 1:
2927                         size *= (1 << track->textures[u].txdepth);
2928                         break;
2929                 case 2:
2930                         if (track->separate_cube) {
2931                                 ret = r100_cs_track_cube(rdev, track, u);
2932                                 if (ret)
2933                                         return ret;
2934                         } else
2935                                 size *= 6;
2936                         break;
2937                 default:
2938                         DRM_ERROR("Invalid texture coordinate type %u for unit "
2939                                   "%u\n", track->textures[u].tex_coord_type, u);
2940                         return -EINVAL;
2941                 }
2942                 if (size > radeon_bo_size(robj)) {
2943                         DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2944                                   "%lu\n", u, size, radeon_bo_size(robj));
2945                         r100_cs_track_texture_print(&track->textures[u]);
2946                         return -EINVAL;
2947                 }
2948         }
2949         return 0;
2950 }
2951
2952 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2953 {
2954         unsigned i;
2955         unsigned long size;
2956         unsigned prim_walk;
2957         unsigned nverts;
2958
2959         for (i = 0; i < track->num_cb; i++) {
2960                 if (track->cb[i].robj == NULL) {
2961                         if (!(track->fastfill || track->color_channel_mask ||
2962                               track->blend_read_enable)) {
2963                                 continue;
2964                         }
2965                         DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2966                         return -EINVAL;
2967                 }
2968                 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2969                 size += track->cb[i].offset;
2970                 if (size > radeon_bo_size(track->cb[i].robj)) {
2971                         DRM_ERROR("[drm] Buffer too small for color buffer %d "
2972                                   "(need %lu have %lu) !\n", i, size,
2973                                   radeon_bo_size(track->cb[i].robj));
2974                         DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2975                                   i, track->cb[i].pitch, track->cb[i].cpp,
2976                                   track->cb[i].offset, track->maxy);
2977                         return -EINVAL;
2978                 }
2979         }
2980         if (track->z_enabled) {
2981                 if (track->zb.robj == NULL) {
2982                         DRM_ERROR("[drm] No buffer for z buffer !\n");
2983                         return -EINVAL;
2984                 }
2985                 size = track->zb.pitch * track->zb.cpp * track->maxy;
2986                 size += track->zb.offset;
2987                 if (size > radeon_bo_size(track->zb.robj)) {
2988                         DRM_ERROR("[drm] Buffer too small for z buffer "
2989                                   "(need %lu have %lu) !\n", size,
2990                                   radeon_bo_size(track->zb.robj));
2991                         DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2992                                   track->zb.pitch, track->zb.cpp,
2993                                   track->zb.offset, track->maxy);
2994                         return -EINVAL;
2995                 }
2996         }
2997         prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2998         nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2999         switch (prim_walk) {
3000         case 1:
3001                 for (i = 0; i < track->num_arrays; i++) {
3002                         size = track->arrays[i].esize * track->max_indx * 4;
3003                         if (track->arrays[i].robj == NULL) {
3004                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3005                                           "bound\n", prim_walk, i);
3006                                 return -EINVAL;
3007                         }
3008                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3009                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3010                                         "need %lu dwords have %lu dwords\n",
3011                                         prim_walk, i, size >> 2,
3012                                         radeon_bo_size(track->arrays[i].robj)
3013                                         >> 2);
3014                                 DRM_ERROR("Max indices %u\n", track->max_indx);
3015                                 return -EINVAL;
3016                         }
3017                 }
3018                 break;
3019         case 2:
3020                 for (i = 0; i < track->num_arrays; i++) {
3021                         size = track->arrays[i].esize * (nverts - 1) * 4;
3022                         if (track->arrays[i].robj == NULL) {
3023                                 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3024                                           "bound\n", prim_walk, i);
3025                                 return -EINVAL;
3026                         }
3027                         if (size > radeon_bo_size(track->arrays[i].robj)) {
3028                                 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3029                                         "need %lu dwords have %lu dwords\n",
3030                                         prim_walk, i, size >> 2,
3031                                         radeon_bo_size(track->arrays[i].robj)
3032                                         >> 2);
3033                                 return -EINVAL;
3034                         }
3035                 }
3036                 break;
3037         case 3:
3038                 size = track->vtx_size * nverts;
3039                 if (size != track->immd_dwords) {
3040                         DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3041                                   track->immd_dwords, size);
3042                         DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3043                                   nverts, track->vtx_size);
3044                         return -EINVAL;
3045                 }
3046                 break;
3047         default:
3048                 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3049                           prim_walk);
3050                 return -EINVAL;
3051         }
3052         return r100_cs_track_texture_check(rdev, track);
3053 }
3054
3055 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3056 {
3057         unsigned i, face;
3058
3059         if (rdev->family < CHIP_R300) {
3060                 track->num_cb = 1;
3061                 if (rdev->family <= CHIP_RS200)
3062                         track->num_texture = 3;
3063                 else
3064                         track->num_texture = 6;
3065                 track->maxy = 2048;
3066                 track->separate_cube = 1;
3067         } else {
3068                 track->num_cb = 4;
3069                 track->num_texture = 16;
3070                 track->maxy = 4096;
3071                 track->separate_cube = 0;
3072         }
3073
3074         for (i = 0; i < track->num_cb; i++) {
3075                 track->cb[i].robj = NULL;
3076                 track->cb[i].pitch = 8192;
3077                 track->cb[i].cpp = 16;
3078                 track->cb[i].offset = 0;
3079         }
3080         track->z_enabled = true;
3081         track->zb.robj = NULL;
3082         track->zb.pitch = 8192;
3083         track->zb.cpp = 4;
3084         track->zb.offset = 0;
3085         track->vtx_size = 0x7F;
3086         track->immd_dwords = 0xFFFFFFFFUL;
3087         track->num_arrays = 11;
3088         track->max_indx = 0x00FFFFFFUL;
3089         for (i = 0; i < track->num_arrays; i++) {
3090                 track->arrays[i].robj = NULL;
3091                 track->arrays[i].esize = 0x7F;
3092         }
3093         for (i = 0; i < track->num_texture; i++) {
3094                 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
3095                 track->textures[i].pitch = 16536;
3096                 track->textures[i].width = 16536;
3097                 track->textures[i].height = 16536;
3098                 track->textures[i].width_11 = 1 << 11;
3099                 track->textures[i].height_11 = 1 << 11;
3100                 track->textures[i].num_levels = 12;
3101                 if (rdev->family <= CHIP_RS200) {
3102                         track->textures[i].tex_coord_type = 0;
3103                         track->textures[i].txdepth = 0;
3104                 } else {
3105                         track->textures[i].txdepth = 16;
3106                         track->textures[i].tex_coord_type = 1;
3107                 }
3108                 track->textures[i].cpp = 64;
3109                 track->textures[i].robj = NULL;
3110                 /* CS IB emission code makes sure texture unit are disabled */
3111                 track->textures[i].enabled = false;
3112                 track->textures[i].roundup_w = true;
3113                 track->textures[i].roundup_h = true;
3114                 if (track->separate_cube)
3115                         for (face = 0; face < 5; face++) {
3116                                 track->textures[i].cube_info[face].robj = NULL;
3117                                 track->textures[i].cube_info[face].width = 16536;
3118                                 track->textures[i].cube_info[face].height = 16536;
3119                                 track->textures[i].cube_info[face].offset = 0;
3120                         }
3121         }
3122 }
3123
3124 int r100_ring_test(struct radeon_device *rdev)
3125 {
3126         uint32_t scratch;
3127         uint32_t tmp = 0;
3128         unsigned i;
3129         int r;
3130
3131         r = radeon_scratch_get(rdev, &scratch);
3132         if (r) {
3133                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3134                 return r;
3135         }
3136         WREG32(scratch, 0xCAFEDEAD);
3137         r = radeon_ring_lock(rdev, 2);
3138         if (r) {
3139                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3140                 radeon_scratch_free(rdev, scratch);
3141                 return r;
3142         }
3143         radeon_ring_write(rdev, PACKET0(scratch, 0));
3144         radeon_ring_write(rdev, 0xDEADBEEF);
3145         radeon_ring_unlock_commit(rdev);
3146         for (i = 0; i < rdev->usec_timeout; i++) {
3147                 tmp = RREG32(scratch);
3148                 if (tmp == 0xDEADBEEF) {
3149                         break;
3150                 }
3151                 DRM_UDELAY(1);
3152         }
3153         if (i < rdev->usec_timeout) {
3154                 DRM_INFO("ring test succeeded in %d usecs\n", i);
3155         } else {
3156                 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
3157                           scratch, tmp);
3158                 r = -EINVAL;
3159         }
3160         radeon_scratch_free(rdev, scratch);
3161         return r;
3162 }
3163
3164 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3165 {
3166         radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3167         radeon_ring_write(rdev, ib->gpu_addr);
3168         radeon_ring_write(rdev, ib->length_dw);
3169 }
3170
3171 int r100_ib_test(struct radeon_device *rdev)
3172 {
3173         struct radeon_ib *ib;
3174         uint32_t scratch;
3175         uint32_t tmp = 0;
3176         unsigned i;
3177         int r;
3178
3179         r = radeon_scratch_get(rdev, &scratch);
3180         if (r) {
3181                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3182                 return r;
3183         }
3184         WREG32(scratch, 0xCAFEDEAD);
3185         r = radeon_ib_get(rdev, &ib);
3186         if (r) {
3187                 return r;
3188         }
3189         ib->ptr[0] = PACKET0(scratch, 0);
3190         ib->ptr[1] = 0xDEADBEEF;
3191         ib->ptr[2] = PACKET2(0);
3192         ib->ptr[3] = PACKET2(0);
3193         ib->ptr[4] = PACKET2(0);
3194         ib->ptr[5] = PACKET2(0);
3195         ib->ptr[6] = PACKET2(0);
3196         ib->ptr[7] = PACKET2(0);
3197         ib->length_dw = 8;
3198         r = radeon_ib_schedule(rdev, ib);
3199         if (r) {
3200                 radeon_scratch_free(rdev, scratch);
3201                 radeon_ib_free(rdev, &ib);
3202                 return r;
3203         }
3204         r = radeon_fence_wait(ib->fence, false);
3205         if (r) {
3206                 return r;
3207         }
3208         for (i = 0; i < rdev->usec_timeout; i++) {
3209                 tmp = RREG32(scratch);
3210                 if (tmp == 0xDEADBEEF) {
3211                         break;
3212                 }
3213                 DRM_UDELAY(1);
3214         }
3215         if (i < rdev->usec_timeout) {
3216                 DRM_INFO("ib test succeeded in %u usecs\n", i);
3217         } else {
3218                 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3219                           scratch, tmp);
3220                 r = -EINVAL;
3221         }
3222         radeon_scratch_free(rdev, scratch);
3223         radeon_ib_free(rdev, &ib);
3224         return r;
3225 }
3226
3227 void r100_ib_fini(struct radeon_device *rdev)
3228 {
3229         radeon_ib_pool_fini(rdev);
3230 }
3231
3232 int r100_ib_init(struct radeon_device *rdev)
3233 {
3234         int r;
3235
3236         r = radeon_ib_pool_init(rdev);
3237         if (r) {
3238                 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
3239                 r100_ib_fini(rdev);
3240                 return r;
3241         }
3242         r = r100_ib_test(rdev);
3243         if (r) {
3244                 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
3245                 r100_ib_fini(rdev);
3246                 return r;
3247         }
3248         return 0;
3249 }
3250
3251 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3252 {
3253         /* Shutdown CP we shouldn't need to do that but better be safe than
3254          * sorry
3255          */
3256         rdev->cp.ready = false;
3257         WREG32(R_000740_CP_CSQ_CNTL, 0);
3258
3259         /* Save few CRTC registers */
3260         save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3261         save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3262         save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3263         save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3264         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3265                 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3266                 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3267         }
3268
3269         /* Disable VGA aperture access */
3270         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3271         /* Disable cursor, overlay, crtc */
3272         WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3273         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3274                                         S_000054_CRTC_DISPLAY_DIS(1));
3275         WREG32(R_000050_CRTC_GEN_CNTL,
3276                         (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3277                         S_000050_CRTC_DISP_REQ_EN_B(1));
3278         WREG32(R_000420_OV0_SCALE_CNTL,
3279                 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3280         WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3281         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3282                 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3283                                                 S_000360_CUR2_LOCK(1));
3284                 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3285                         (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3286                         S_0003F8_CRTC2_DISPLAY_DIS(1) |
3287                         S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3288                 WREG32(R_000360_CUR2_OFFSET,
3289                         C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3290         }
3291 }
3292
3293 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3294 {
3295         /* Update base address for crtc */
3296         WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3297         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3298                 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3299         }
3300         /* Restore CRTC registers */
3301         WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3302         WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3303         WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3304         if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3305                 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3306         }
3307 }
3308
3309 void r100_vga_render_disable(struct radeon_device *rdev)
3310 {
3311         u32 tmp;
3312
3313         tmp = RREG8(R_0003C2_GENMO_WT);
3314         WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3315 }
3316
3317 static void r100_debugfs(struct radeon_device *rdev)
3318 {
3319         int r;
3320
3321         r = r100_debugfs_mc_info_init(rdev);
3322         if (r)
3323                 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3324 }
3325
3326 static void r100_mc_program(struct radeon_device *rdev)
3327 {
3328         struct r100_mc_save save;
3329
3330         /* Stops all mc clients */
3331         r100_mc_stop(rdev, &save);
3332         if (rdev->flags & RADEON_IS_AGP) {
3333                 WREG32(R_00014C_MC_AGP_LOCATION,
3334                         S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3335                         S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3336                 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3337                 if (rdev->family > CHIP_RV200)
3338                         WREG32(R_00015C_AGP_BASE_2,
3339                                 upper_32_bits(rdev->mc.agp_base) & 0xff);
3340         } else {
3341                 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3342                 WREG32(R_000170_AGP_BASE, 0);
3343                 if (rdev->family > CHIP_RV200)
3344                         WREG32(R_00015C_AGP_BASE_2, 0);
3345         }
3346         /* Wait for mc idle */
3347         if (r100_mc_wait_for_idle(rdev))
3348                 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3349         /* Program MC, should be a 32bits limited address space */
3350         WREG32(R_000148_MC_FB_LOCATION,
3351                 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3352                 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3353         r100_mc_resume(rdev, &save);
3354 }
3355
3356 void r100_clock_startup(struct radeon_device *rdev)
3357 {
3358         u32 tmp;
3359
3360         if (radeon_dynclks != -1 && radeon_dynclks)
3361                 radeon_legacy_set_clock_gating(rdev, 1);
3362         /* We need to force on some of the block */
3363         tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3364         tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3365         if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3366                 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3367         WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3368 }
3369
3370 static int r100_startup(struct radeon_device *rdev)
3371 {
3372         int r;
3373
3374         /* set common regs */
3375         r100_set_common_regs(rdev);
3376         /* program mc */
3377         r100_mc_program(rdev);
3378         /* Resume clock */
3379         r100_clock_startup(rdev);
3380         /* Initialize GPU configuration (# pipes, ...) */
3381         r100_gpu_init(rdev);
3382         /* Initialize GART (initialize after TTM so we can allocate
3383          * memory through TTM but finalize after TTM) */
3384         r100_enable_bm(rdev);
3385         if (rdev->flags & RADEON_IS_PCI) {
3386                 r = r100_pci_gart_enable(rdev);
3387                 if (r)
3388                         return r;
3389         }
3390         /* Enable IRQ */
3391         r100_irq_set(rdev);
3392         rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3393         /* 1M ring buffer */
3394         r = r100_cp_init(rdev, 1024 * 1024);
3395         if (r) {
3396                 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3397                 return r;
3398         }
3399         r = r100_wb_init(rdev);
3400         if (r)
3401                 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
3402         r = r100_ib_init(rdev);
3403         if (r) {
3404                 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
3405                 return r;
3406         }
3407         return 0;
3408 }
3409
3410 int r100_resume(struct radeon_device *rdev)
3411 {
3412         /* Make sur GART are not working */
3413         if (rdev->flags & RADEON_IS_PCI)
3414                 r100_pci_gart_disable(rdev);
3415         /* Resume clock before doing reset */
3416         r100_clock_startup(rdev);
3417         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3418         if (radeon_gpu_reset(rdev)) {
3419                 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3420                         RREG32(R_000E40_RBBM_STATUS),
3421                         RREG32(R_0007C0_CP_STAT));
3422         }
3423         /* post */
3424         radeon_combios_asic_init(rdev->ddev);
3425         /* Resume clock after posting */
3426         r100_clock_startup(rdev);
3427         /* Initialize surface registers */
3428         radeon_surface_init(rdev);
3429         return r100_startup(rdev);
3430 }
3431
3432 int r100_suspend(struct radeon_device *rdev)
3433 {
3434         r100_cp_disable(rdev);
3435         r100_wb_disable(rdev);
3436         r100_irq_disable(rdev);
3437         if (rdev->flags & RADEON_IS_PCI)
3438                 r100_pci_gart_disable(rdev);
3439         return 0;
3440 }
3441
3442 void r100_fini(struct radeon_device *rdev)
3443 {
3444         r100_cp_fini(rdev);
3445         r100_wb_fini(rdev);
3446         r100_ib_fini(rdev);
3447         radeon_gem_fini(rdev);
3448         if (rdev->flags & RADEON_IS_PCI)
3449                 r100_pci_gart_fini(rdev);
3450         radeon_agp_fini(rdev);
3451         radeon_irq_kms_fini(rdev);
3452         radeon_fence_driver_fini(rdev);
3453         radeon_bo_fini(rdev);
3454         radeon_atombios_fini(rdev);
3455         kfree(rdev->bios);
3456         rdev->bios = NULL;
3457 }
3458
3459 int r100_init(struct radeon_device *rdev)
3460 {
3461         int r;
3462
3463         /* Register debugfs file specific to this group of asics */
3464         r100_debugfs(rdev);
3465         /* Disable VGA */
3466         r100_vga_render_disable(rdev);
3467         /* Initialize scratch registers */
3468         radeon_scratch_init(rdev);
3469         /* Initialize surface registers */
3470         radeon_surface_init(rdev);
3471         /* TODO: disable VGA need to use VGA request */
3472         /* BIOS*/
3473         if (!radeon_get_bios(rdev)) {
3474                 if (ASIC_IS_AVIVO(rdev))
3475                         return -EINVAL;
3476         }
3477         if (rdev->is_atom_bios) {
3478                 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3479                 return -EINVAL;
3480         } else {
3481                 r = radeon_combios_init(rdev);
3482                 if (r)
3483                         return r;
3484         }
3485         /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3486         if (radeon_gpu_reset(rdev)) {
3487                 dev_warn(rdev->dev,
3488                         "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3489                         RREG32(R_000E40_RBBM_STATUS),
3490                         RREG32(R_0007C0_CP_STAT));
3491         }
3492         /* check if cards are posted or not */
3493         if (radeon_boot_test_post_card(rdev) == false)
3494                 return -EINVAL;
3495         /* Set asic errata */
3496         r100_errata(rdev);
3497         /* Initialize clocks */
3498         radeon_get_clock_info(rdev->ddev);
3499         /* Initialize power management */
3500         radeon_pm_init(rdev);
3501         /* initialize AGP */
3502         if (rdev->flags & RADEON_IS_AGP) {
3503                 r = radeon_agp_init(rdev);
3504                 if (r) {
3505                         radeon_agp_disable(rdev);
3506                 }
3507         }
3508         /* initialize VRAM */
3509         r100_mc_init(rdev);
3510         /* Fence driver */
3511         r = radeon_fence_driver_init(rdev);
3512         if (r)
3513                 return r;
3514         r = radeon_irq_kms_init(rdev);
3515         if (r)
3516                 return r;
3517         /* Memory manager */
3518         r = radeon_bo_init(rdev);
3519         if (r)
3520                 return r;
3521         if (rdev->flags & RADEON_IS_PCI) {
3522                 r = r100_pci_gart_init(rdev);
3523                 if (r)
3524                         return r;
3525         }
3526         r100_set_safe_registers(rdev);
3527         rdev->accel_working = true;
3528         r = r100_startup(rdev);
3529         if (r) {
3530                 /* Somethings want wront with the accel init stop accel */
3531                 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3532                 r100_cp_fini(rdev);
3533                 r100_wb_fini(rdev);
3534                 r100_ib_fini(rdev);
3535                 radeon_irq_kms_fini(rdev);
3536                 if (rdev->flags & RADEON_IS_PCI)
3537                         r100_pci_gart_fini(rdev);
3538                 rdev->accel_working = false;
3539         }
3540         return 0;
3541 }