drm/radeon/dce6: add missing display reg for tiling setup
[linux-2.6.git] / drivers / gpu / drm / radeon / nid.h
1 /*
2  * Copyright 2010 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Alex Deucher
23  */
24 #ifndef NI_H
25 #define NI_H
26
27 #define CAYMAN_MAX_SH_GPRS           256
28 #define CAYMAN_MAX_TEMP_GPRS         16
29 #define CAYMAN_MAX_SH_THREADS        256
30 #define CAYMAN_MAX_SH_STACK_ENTRIES  4096
31 #define CAYMAN_MAX_FRC_EOV_CNT       16384
32 #define CAYMAN_MAX_BACKENDS          8
33 #define CAYMAN_MAX_BACKENDS_MASK     0xFF
34 #define CAYMAN_MAX_BACKENDS_PER_SE_MASK 0xF
35 #define CAYMAN_MAX_SIMDS             16
36 #define CAYMAN_MAX_SIMDS_MASK        0xFFFF
37 #define CAYMAN_MAX_SIMDS_PER_SE_MASK 0xFFF
38 #define CAYMAN_MAX_PIPES             8
39 #define CAYMAN_MAX_PIPES_MASK        0xFF
40 #define CAYMAN_MAX_LDS_NUM           0xFFFF
41 #define CAYMAN_MAX_TCC               16
42 #define CAYMAN_MAX_TCC_MASK          0xFF
43
44 #define DMIF_ADDR_CONFIG                                0xBD4
45
46 /* DCE6 only */
47 #define DMIF_ADDR_CALC                                  0xC00
48
49 #define SRBM_GFX_CNTL                                   0x0E44
50 #define         RINGID(x)                                       (((x) & 0x3) << 0)
51 #define         VMID(x)                                         (((x) & 0x7) << 0)
52 #define SRBM_STATUS                                     0x0E50
53
54 #define VM_CONTEXT0_REQUEST_RESPONSE                    0x1470
55 #define         REQUEST_TYPE(x)                                 (((x) & 0xf) << 0)
56 #define         RESPONSE_TYPE_MASK                              0x000000F0
57 #define         RESPONSE_TYPE_SHIFT                             4
58 #define VM_L2_CNTL                                      0x1400
59 #define         ENABLE_L2_CACHE                                 (1 << 0)
60 #define         ENABLE_L2_FRAGMENT_PROCESSING                   (1 << 1)
61 #define         ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE         (1 << 9)
62 #define         ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE        (1 << 10)
63 #define         EFFECTIVE_L2_QUEUE_SIZE(x)                      (((x) & 7) << 14)
64 #define         CONTEXT1_IDENTITY_ACCESS_MODE(x)                (((x) & 3) << 18)
65 /* CONTEXT1_IDENTITY_ACCESS_MODE
66  * 0 physical = logical
67  * 1 logical via context1 page table
68  * 2 inside identity aperture use translation, outside physical = logical
69  * 3 inside identity aperture physical = logical, outside use translation
70  */
71 #define VM_L2_CNTL2                                     0x1404
72 #define         INVALIDATE_ALL_L1_TLBS                          (1 << 0)
73 #define         INVALIDATE_L2_CACHE                             (1 << 1)
74 #define VM_L2_CNTL3                                     0x1408
75 #define         BANK_SELECT(x)                                  ((x) << 0)
76 #define         CACHE_UPDATE_MODE(x)                            ((x) << 6)
77 #define         L2_CACHE_BIGK_ASSOCIATIVITY                     (1 << 20)
78 #define         L2_CACHE_BIGK_FRAGMENT_SIZE(x)                  ((x) << 15)
79 #define VM_L2_STATUS                                    0x140C
80 #define         L2_BUSY                                         (1 << 0)
81 #define VM_CONTEXT0_CNTL                                0x1410
82 #define         ENABLE_CONTEXT                                  (1 << 0)
83 #define         PAGE_TABLE_DEPTH(x)                             (((x) & 3) << 1)
84 #define         RANGE_PROTECTION_FAULT_ENABLE_DEFAULT           (1 << 4)
85 #define VM_CONTEXT1_CNTL                                0x1414
86 #define VM_CONTEXT0_CNTL2                               0x1430
87 #define VM_CONTEXT1_CNTL2                               0x1434
88 #define VM_INVALIDATE_REQUEST                           0x1478
89 #define VM_INVALIDATE_RESPONSE                          0x147c
90 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR       0x1518
91 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR       0x151c
92 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR                0x153C
93 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR               0x155C
94 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR                 0x157C
95
96 #define MC_SHARED_CHMAP                                         0x2004
97 #define         NOOFCHAN_SHIFT                                  12
98 #define         NOOFCHAN_MASK                                   0x00003000
99 #define MC_SHARED_CHREMAP                                       0x2008
100
101 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR                  0x2034
102 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR                 0x2038
103 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR              0x203C
104 #define MC_VM_MX_L1_TLB_CNTL                            0x2064
105 #define         ENABLE_L1_TLB                                   (1 << 0)
106 #define         ENABLE_L1_FRAGMENT_PROCESSING                   (1 << 1)
107 #define         SYSTEM_ACCESS_MODE_PA_ONLY                      (0 << 3)
108 #define         SYSTEM_ACCESS_MODE_USE_SYS_MAP                  (1 << 3)
109 #define         SYSTEM_ACCESS_MODE_IN_SYS                       (2 << 3)
110 #define         SYSTEM_ACCESS_MODE_NOT_IN_SYS                   (3 << 3)
111 #define         SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU       (0 << 5)
112 #define         ENABLE_ADVANCED_DRIVER_MODEL                    (1 << 6)
113 #define FUS_MC_VM_FB_OFFSET                             0x2068
114
115 #define MC_SHARED_BLACKOUT_CNTL                         0x20ac
116 #define MC_ARB_RAMCFG                                   0x2760
117 #define         NOOFBANK_SHIFT                                  0
118 #define         NOOFBANK_MASK                                   0x00000003
119 #define         NOOFRANK_SHIFT                                  2
120 #define         NOOFRANK_MASK                                   0x00000004
121 #define         NOOFROWS_SHIFT                                  3
122 #define         NOOFROWS_MASK                                   0x00000038
123 #define         NOOFCOLS_SHIFT                                  6
124 #define         NOOFCOLS_MASK                                   0x000000C0
125 #define         CHANSIZE_SHIFT                                  8
126 #define         CHANSIZE_MASK                                   0x00000100
127 #define         BURSTLENGTH_SHIFT                               9
128 #define         BURSTLENGTH_MASK                                0x00000200
129 #define         CHANSIZE_OVERRIDE                               (1 << 11)
130 #define MC_SEQ_SUP_CNTL                                 0x28c8
131 #define         RUN_MASK                                (1 << 0)
132 #define MC_SEQ_SUP_PGM                                  0x28cc
133 #define MC_IO_PAD_CNTL_D0                               0x29d0
134 #define         MEM_FALL_OUT_CMD                        (1 << 8)
135 #define MC_SEQ_MISC0                                    0x2a00
136 #define         MC_SEQ_MISC0_GDDR5_SHIFT                28
137 #define         MC_SEQ_MISC0_GDDR5_MASK                 0xf0000000
138 #define         MC_SEQ_MISC0_GDDR5_VALUE                5
139 #define MC_SEQ_IO_DEBUG_INDEX                           0x2a44
140 #define MC_SEQ_IO_DEBUG_DATA                            0x2a48
141
142 #define HDP_HOST_PATH_CNTL                              0x2C00
143 #define HDP_NONSURFACE_BASE                             0x2C04
144 #define HDP_NONSURFACE_INFO                             0x2C08
145 #define HDP_NONSURFACE_SIZE                             0x2C0C
146 #define HDP_ADDR_CONFIG                                 0x2F48
147 #define HDP_MISC_CNTL                                   0x2F4C
148 #define         HDP_FLUSH_INVALIDATE_CACHE                      (1 << 0)
149
150 #define CC_SYS_RB_BACKEND_DISABLE                       0x3F88
151 #define GC_USER_SYS_RB_BACKEND_DISABLE                  0x3F8C
152 #define CGTS_SYS_TCC_DISABLE                            0x3F90
153 #define CGTS_USER_SYS_TCC_DISABLE                       0x3F94
154
155 #define CONFIG_MEMSIZE                                  0x5428
156
157 #define HDP_MEM_COHERENCY_FLUSH_CNTL                    0x5480
158 #define HDP_REG_COHERENCY_FLUSH_CNTL                    0x54A0
159
160 #define GRBM_CNTL                                       0x8000
161 #define         GRBM_READ_TIMEOUT(x)                            ((x) << 0)
162 #define GRBM_STATUS                                     0x8010
163 #define         CMDFIFO_AVAIL_MASK                              0x0000000F
164 #define         RING2_RQ_PENDING                                (1 << 4)
165 #define         SRBM_RQ_PENDING                                 (1 << 5)
166 #define         RING1_RQ_PENDING                                (1 << 6)
167 #define         CF_RQ_PENDING                                   (1 << 7)
168 #define         PF_RQ_PENDING                                   (1 << 8)
169 #define         GDS_DMA_RQ_PENDING                              (1 << 9)
170 #define         GRBM_EE_BUSY                                    (1 << 10)
171 #define         SX_CLEAN                                        (1 << 11)
172 #define         DB_CLEAN                                        (1 << 12)
173 #define         CB_CLEAN                                        (1 << 13)
174 #define         TA_BUSY                                         (1 << 14)
175 #define         GDS_BUSY                                        (1 << 15)
176 #define         VGT_BUSY_NO_DMA                                 (1 << 16)
177 #define         VGT_BUSY                                        (1 << 17)
178 #define         IA_BUSY_NO_DMA                                  (1 << 18)
179 #define         IA_BUSY                                         (1 << 19)
180 #define         SX_BUSY                                         (1 << 20)
181 #define         SH_BUSY                                         (1 << 21)
182 #define         SPI_BUSY                                        (1 << 22)
183 #define         SC_BUSY                                         (1 << 24)
184 #define         PA_BUSY                                         (1 << 25)
185 #define         DB_BUSY                                         (1 << 26)
186 #define         CP_COHERENCY_BUSY                               (1 << 28)
187 #define         CP_BUSY                                         (1 << 29)
188 #define         CB_BUSY                                         (1 << 30)
189 #define         GUI_ACTIVE                                      (1 << 31)
190 #define GRBM_STATUS_SE0                                 0x8014
191 #define GRBM_STATUS_SE1                                 0x8018
192 #define         SE_SX_CLEAN                                     (1 << 0)
193 #define         SE_DB_CLEAN                                     (1 << 1)
194 #define         SE_CB_CLEAN                                     (1 << 2)
195 #define         SE_VGT_BUSY                                     (1 << 23)
196 #define         SE_PA_BUSY                                      (1 << 24)
197 #define         SE_TA_BUSY                                      (1 << 25)
198 #define         SE_SX_BUSY                                      (1 << 26)
199 #define         SE_SPI_BUSY                                     (1 << 27)
200 #define         SE_SH_BUSY                                      (1 << 28)
201 #define         SE_SC_BUSY                                      (1 << 29)
202 #define         SE_DB_BUSY                                      (1 << 30)
203 #define         SE_CB_BUSY                                      (1 << 31)
204 #define GRBM_SOFT_RESET                                 0x8020
205 #define         SOFT_RESET_CP                                   (1 << 0)
206 #define         SOFT_RESET_CB                                   (1 << 1)
207 #define         SOFT_RESET_DB                                   (1 << 3)
208 #define         SOFT_RESET_GDS                                  (1 << 4)
209 #define         SOFT_RESET_PA                                   (1 << 5)
210 #define         SOFT_RESET_SC                                   (1 << 6)
211 #define         SOFT_RESET_SPI                                  (1 << 8)
212 #define         SOFT_RESET_SH                                   (1 << 9)
213 #define         SOFT_RESET_SX                                   (1 << 10)
214 #define         SOFT_RESET_TC                                   (1 << 11)
215 #define         SOFT_RESET_TA                                   (1 << 12)
216 #define         SOFT_RESET_VGT                                  (1 << 14)
217 #define         SOFT_RESET_IA                                   (1 << 15)
218
219 #define SCRATCH_REG0                                    0x8500
220 #define SCRATCH_REG1                                    0x8504
221 #define SCRATCH_REG2                                    0x8508
222 #define SCRATCH_REG3                                    0x850C
223 #define SCRATCH_REG4                                    0x8510
224 #define SCRATCH_REG5                                    0x8514
225 #define SCRATCH_REG6                                    0x8518
226 #define SCRATCH_REG7                                    0x851C
227 #define SCRATCH_UMSK                                    0x8540
228 #define SCRATCH_ADDR                                    0x8544
229 #define CP_SEM_WAIT_TIMER                               0x85BC
230 #define CP_SEM_INCOMPLETE_TIMER_CNTL                    0x85C8
231 #define CP_COHER_CNTL2                                  0x85E8
232 #define CP_ME_CNTL                                      0x86D8
233 #define         CP_ME_HALT                                      (1 << 28)
234 #define         CP_PFP_HALT                                     (1 << 26)
235 #define CP_RB2_RPTR                                     0x86f8
236 #define CP_RB1_RPTR                                     0x86fc
237 #define CP_RB0_RPTR                                     0x8700
238 #define CP_RB_WPTR_DELAY                                0x8704
239 #define CP_MEQ_THRESHOLDS                               0x8764
240 #define         MEQ1_START(x)                           ((x) << 0)
241 #define         MEQ2_START(x)                           ((x) << 8)
242 #define CP_PERFMON_CNTL                                 0x87FC
243
244 #define VGT_CACHE_INVALIDATION                          0x88C4
245 #define         CACHE_INVALIDATION(x)                           ((x) << 0)
246 #define                 VC_ONLY                                         0
247 #define                 TC_ONLY                                         1
248 #define                 VC_AND_TC                                       2
249 #define         AUTO_INVLD_EN(x)                                ((x) << 6)
250 #define                 NO_AUTO                                         0
251 #define                 ES_AUTO                                         1
252 #define                 GS_AUTO                                         2
253 #define                 ES_AND_GS_AUTO                                  3
254 #define VGT_GS_VERTEX_REUSE                             0x88D4
255
256 #define CC_GC_SHADER_PIPE_CONFIG                        0x8950
257 #define GC_USER_SHADER_PIPE_CONFIG                      0x8954
258 #define         INACTIVE_QD_PIPES(x)                            ((x) << 8)
259 #define         INACTIVE_QD_PIPES_MASK                          0x0000FF00
260 #define         INACTIVE_QD_PIPES_SHIFT                         8
261 #define         INACTIVE_SIMDS(x)                               ((x) << 16)
262 #define         INACTIVE_SIMDS_MASK                             0xFFFF0000
263 #define         INACTIVE_SIMDS_SHIFT                            16
264
265 #define VGT_PRIMITIVE_TYPE                              0x8958
266 #define VGT_NUM_INSTANCES                               0x8974
267 #define VGT_TF_RING_SIZE                                0x8988
268 #define VGT_OFFCHIP_LDS_BASE                            0x89b4
269
270 #define PA_SC_LINE_STIPPLE_STATE                        0x8B10
271 #define PA_CL_ENHANCE                                   0x8A14
272 #define         CLIP_VTX_REORDER_ENA                            (1 << 0)
273 #define         NUM_CLIP_SEQ(x)                                 ((x) << 1)
274 #define PA_SC_FIFO_SIZE                                 0x8BCC
275 #define         SC_PRIM_FIFO_SIZE(x)                            ((x) << 0)
276 #define         SC_HIZ_TILE_FIFO_SIZE(x)                        ((x) << 12)
277 #define         SC_EARLYZ_TILE_FIFO_SIZE(x)                     ((x) << 20)
278 #define PA_SC_FORCE_EOV_MAX_CNTS                        0x8B24
279 #define         FORCE_EOV_MAX_CLK_CNT(x)                        ((x) << 0)
280 #define         FORCE_EOV_MAX_REZ_CNT(x)                        ((x) << 16)
281
282 #define SQ_CONFIG                                       0x8C00
283 #define         VC_ENABLE                                       (1 << 0)
284 #define         EXPORT_SRC_C                                    (1 << 1)
285 #define         GFX_PRIO(x)                                     ((x) << 2)
286 #define         CS1_PRIO(x)                                     ((x) << 4)
287 #define         CS2_PRIO(x)                                     ((x) << 6)
288 #define SQ_GPR_RESOURCE_MGMT_1                          0x8C04
289 #define         NUM_PS_GPRS(x)                                  ((x) << 0)
290 #define         NUM_VS_GPRS(x)                                  ((x) << 16)
291 #define         NUM_CLAUSE_TEMP_GPRS(x)                         ((x) << 28)
292 #define SQ_ESGS_RING_SIZE                               0x8c44
293 #define SQ_GSVS_RING_SIZE                               0x8c4c
294 #define SQ_ESTMP_RING_BASE                              0x8c50
295 #define SQ_ESTMP_RING_SIZE                              0x8c54
296 #define SQ_GSTMP_RING_BASE                              0x8c58
297 #define SQ_GSTMP_RING_SIZE                              0x8c5c
298 #define SQ_VSTMP_RING_BASE                              0x8c60
299 #define SQ_VSTMP_RING_SIZE                              0x8c64
300 #define SQ_PSTMP_RING_BASE                              0x8c68
301 #define SQ_PSTMP_RING_SIZE                              0x8c6c
302 #define SQ_MS_FIFO_SIZES                                0x8CF0
303 #define         CACHE_FIFO_SIZE(x)                              ((x) << 0)
304 #define         FETCH_FIFO_HIWATER(x)                           ((x) << 8)
305 #define         DONE_FIFO_HIWATER(x)                            ((x) << 16)
306 #define         ALU_UPDATE_FIFO_HIWATER(x)                      ((x) << 24)
307 #define SQ_LSTMP_RING_BASE                              0x8e10
308 #define SQ_LSTMP_RING_SIZE                              0x8e14
309 #define SQ_HSTMP_RING_BASE                              0x8e18
310 #define SQ_HSTMP_RING_SIZE                              0x8e1c
311 #define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ                    0x8D8C
312 #define         DYN_GPR_ENABLE                                  (1 << 8)
313 #define SQ_CONST_MEM_BASE                               0x8df8
314
315 #define SX_EXPORT_BUFFER_SIZES                          0x900C
316 #define         COLOR_BUFFER_SIZE(x)                            ((x) << 0)
317 #define         POSITION_BUFFER_SIZE(x)                         ((x) << 8)
318 #define         SMX_BUFFER_SIZE(x)                              ((x) << 16)
319 #define SX_DEBUG_1                                      0x9058
320 #define         ENABLE_NEW_SMX_ADDRESS                          (1 << 16)
321
322 #define SPI_CONFIG_CNTL                                 0x9100
323 #define         GPR_WRITE_PRIORITY(x)                           ((x) << 0)
324 #define SPI_CONFIG_CNTL_1                               0x913C
325 #define         VTX_DONE_DELAY(x)                               ((x) << 0)
326 #define         INTERP_ONE_PRIM_PER_ROW                         (1 << 4)
327 #define         CRC_SIMD_ID_WADDR_DISABLE                       (1 << 8)
328
329 #define CGTS_TCC_DISABLE                                0x9148
330 #define CGTS_USER_TCC_DISABLE                           0x914C
331 #define         TCC_DISABLE_MASK                                0xFFFF0000
332 #define         TCC_DISABLE_SHIFT                               16
333 #define CGTS_SM_CTRL_REG                                0x9150
334 #define         OVERRIDE                                (1 << 21)
335
336 #define TA_CNTL_AUX                                     0x9508
337 #define         DISABLE_CUBE_WRAP                               (1 << 0)
338 #define         DISABLE_CUBE_ANISO                              (1 << 1)
339
340 #define TCP_CHAN_STEER_LO                               0x960c
341 #define TCP_CHAN_STEER_HI                               0x9610
342
343 #define CC_RB_BACKEND_DISABLE                           0x98F4
344 #define         BACKEND_DISABLE(x)                      ((x) << 16)
345 #define GB_ADDR_CONFIG                                  0x98F8
346 #define         NUM_PIPES(x)                            ((x) << 0)
347 #define         NUM_PIPES_MASK                          0x00000007
348 #define         NUM_PIPES_SHIFT                         0
349 #define         PIPE_INTERLEAVE_SIZE(x)                 ((x) << 4)
350 #define         PIPE_INTERLEAVE_SIZE_MASK               0x00000070
351 #define         PIPE_INTERLEAVE_SIZE_SHIFT              4
352 #define         BANK_INTERLEAVE_SIZE(x)                 ((x) << 8)
353 #define         NUM_SHADER_ENGINES(x)                   ((x) << 12)
354 #define         NUM_SHADER_ENGINES_MASK                 0x00003000
355 #define         NUM_SHADER_ENGINES_SHIFT                12
356 #define         SHADER_ENGINE_TILE_SIZE(x)              ((x) << 16)
357 #define         SHADER_ENGINE_TILE_SIZE_MASK            0x00070000
358 #define         SHADER_ENGINE_TILE_SIZE_SHIFT           16
359 #define         NUM_GPUS(x)                             ((x) << 20)
360 #define         NUM_GPUS_MASK                           0x00700000
361 #define         NUM_GPUS_SHIFT                          20
362 #define         MULTI_GPU_TILE_SIZE(x)                  ((x) << 24)
363 #define         MULTI_GPU_TILE_SIZE_MASK                0x03000000
364 #define         MULTI_GPU_TILE_SIZE_SHIFT               24
365 #define         ROW_SIZE(x)                             ((x) << 28)
366 #define         ROW_SIZE_MASK                           0x30000000
367 #define         ROW_SIZE_SHIFT                          28
368 #define         NUM_LOWER_PIPES(x)                      ((x) << 30)
369 #define         NUM_LOWER_PIPES_MASK                    0x40000000
370 #define         NUM_LOWER_PIPES_SHIFT                   30
371 #define GB_BACKEND_MAP                                  0x98FC
372
373 #define CB_PERF_CTR0_SEL_0                              0x9A20
374 #define CB_PERF_CTR0_SEL_1                              0x9A24
375 #define CB_PERF_CTR1_SEL_0                              0x9A28
376 #define CB_PERF_CTR1_SEL_1                              0x9A2C
377 #define CB_PERF_CTR2_SEL_0                              0x9A30
378 #define CB_PERF_CTR2_SEL_1                              0x9A34
379 #define CB_PERF_CTR3_SEL_0                              0x9A38
380 #define CB_PERF_CTR3_SEL_1                              0x9A3C
381
382 #define GC_USER_RB_BACKEND_DISABLE                      0x9B7C
383 #define         BACKEND_DISABLE_MASK                    0x00FF0000
384 #define         BACKEND_DISABLE_SHIFT                   16
385
386 #define SMX_DC_CTL0                                     0xA020
387 #define         USE_HASH_FUNCTION                               (1 << 0)
388 #define         NUMBER_OF_SETS(x)                               ((x) << 1)
389 #define         FLUSH_ALL_ON_EVENT                              (1 << 10)
390 #define         STALL_ON_EVENT                                  (1 << 11)
391 #define SMX_EVENT_CTL                                   0xA02C
392 #define         ES_FLUSH_CTL(x)                                 ((x) << 0)
393 #define         GS_FLUSH_CTL(x)                                 ((x) << 3)
394 #define         ACK_FLUSH_CTL(x)                                ((x) << 6)
395 #define         SYNC_FLUSH_CTL                                  (1 << 8)
396
397 #define CP_RB0_BASE                                     0xC100
398 #define CP_RB0_CNTL                                     0xC104
399 #define         RB_BUFSZ(x)                                     ((x) << 0)
400 #define         RB_BLKSZ(x)                                     ((x) << 8)
401 #define         RB_NO_UPDATE                                    (1 << 27)
402 #define         RB_RPTR_WR_ENA                                  (1 << 31)
403 #define         BUF_SWAP_32BIT                                  (2 << 16)
404 #define CP_RB0_RPTR_ADDR                                0xC10C
405 #define CP_RB0_RPTR_ADDR_HI                             0xC110
406 #define CP_RB0_WPTR                                     0xC114
407
408 #define CP_INT_CNTL                                     0xC124
409 #       define CNTX_BUSY_INT_ENABLE                     (1 << 19)
410 #       define CNTX_EMPTY_INT_ENABLE                    (1 << 20)
411 #       define TIME_STAMP_INT_ENABLE                    (1 << 26)
412
413 #define CP_RB1_BASE                                     0xC180
414 #define CP_RB1_CNTL                                     0xC184
415 #define CP_RB1_RPTR_ADDR                                0xC188
416 #define CP_RB1_RPTR_ADDR_HI                             0xC18C
417 #define CP_RB1_WPTR                                     0xC190
418 #define CP_RB2_BASE                                     0xC194
419 #define CP_RB2_CNTL                                     0xC198
420 #define CP_RB2_RPTR_ADDR                                0xC19C
421 #define CP_RB2_RPTR_ADDR_HI                             0xC1A0
422 #define CP_RB2_WPTR                                     0xC1A4
423 #define CP_PFP_UCODE_ADDR                               0xC150
424 #define CP_PFP_UCODE_DATA                               0xC154
425 #define CP_ME_RAM_RADDR                                 0xC158
426 #define CP_ME_RAM_WADDR                                 0xC15C
427 #define CP_ME_RAM_DATA                                  0xC160
428 #define CP_DEBUG                                        0xC1FC
429
430 #define VGT_EVENT_INITIATOR                             0x28a90
431 #       define CACHE_FLUSH_AND_INV_EVENT_TS                     (0x14 << 0)
432 #       define CACHE_FLUSH_AND_INV_EVENT                        (0x16 << 0)
433
434 /*
435  * PM4
436  */
437 #define PACKET_TYPE0    0
438 #define PACKET_TYPE1    1
439 #define PACKET_TYPE2    2
440 #define PACKET_TYPE3    3
441
442 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
443 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
444 #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
445 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
446 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) |                         \
447                          (((reg) >> 2) & 0xFFFF) |                      \
448                          ((n) & 0x3FFF) << 16)
449 #define CP_PACKET2                      0x80000000
450 #define         PACKET2_PAD_SHIFT               0
451 #define         PACKET2_PAD_MASK                (0x3fffffff << 0)
452
453 #define PACKET2(v)      (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
454
455 #define PACKET3(op, n)  ((PACKET_TYPE3 << 30) |                         \
456                          (((op) & 0xFF) << 8) |                         \
457                          ((n) & 0x3FFF) << 16)
458
459 /* Packet 3 types */
460 #define PACKET3_NOP                                     0x10
461 #define PACKET3_SET_BASE                                0x11
462 #define PACKET3_CLEAR_STATE                             0x12
463 #define PACKET3_INDEX_BUFFER_SIZE                       0x13
464 #define PACKET3_DEALLOC_STATE                           0x14
465 #define PACKET3_DISPATCH_DIRECT                         0x15
466 #define PACKET3_DISPATCH_INDIRECT                       0x16
467 #define PACKET3_INDIRECT_BUFFER_END                     0x17
468 #define PACKET3_MODE_CONTROL                            0x18
469 #define PACKET3_SET_PREDICATION                         0x20
470 #define PACKET3_REG_RMW                                 0x21
471 #define PACKET3_COND_EXEC                               0x22
472 #define PACKET3_PRED_EXEC                               0x23
473 #define PACKET3_DRAW_INDIRECT                           0x24
474 #define PACKET3_DRAW_INDEX_INDIRECT                     0x25
475 #define PACKET3_INDEX_BASE                              0x26
476 #define PACKET3_DRAW_INDEX_2                            0x27
477 #define PACKET3_CONTEXT_CONTROL                         0x28
478 #define PACKET3_DRAW_INDEX_OFFSET                       0x29
479 #define PACKET3_INDEX_TYPE                              0x2A
480 #define PACKET3_DRAW_INDEX                              0x2B
481 #define PACKET3_DRAW_INDEX_AUTO                         0x2D
482 #define PACKET3_DRAW_INDEX_IMMD                         0x2E
483 #define PACKET3_NUM_INSTANCES                           0x2F
484 #define PACKET3_DRAW_INDEX_MULTI_AUTO                   0x30
485 #define PACKET3_INDIRECT_BUFFER                         0x32
486 #define PACKET3_STRMOUT_BUFFER_UPDATE                   0x34
487 #define PACKET3_DRAW_INDEX_OFFSET_2                     0x35
488 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT                0x36
489 #define PACKET3_WRITE_DATA                              0x37
490 #define PACKET3_MEM_SEMAPHORE                           0x39
491 #define PACKET3_MPEG_INDEX                              0x3A
492 #define PACKET3_WAIT_REG_MEM                            0x3C
493 #define PACKET3_MEM_WRITE                               0x3D
494 #define PACKET3_SURFACE_SYNC                            0x43
495 #              define PACKET3_CB0_DEST_BASE_ENA    (1 << 6)
496 #              define PACKET3_CB1_DEST_BASE_ENA    (1 << 7)
497 #              define PACKET3_CB2_DEST_BASE_ENA    (1 << 8)
498 #              define PACKET3_CB3_DEST_BASE_ENA    (1 << 9)
499 #              define PACKET3_CB4_DEST_BASE_ENA    (1 << 10)
500 #              define PACKET3_CB5_DEST_BASE_ENA    (1 << 11)
501 #              define PACKET3_CB6_DEST_BASE_ENA    (1 << 12)
502 #              define PACKET3_CB7_DEST_BASE_ENA    (1 << 13)
503 #              define PACKET3_DB_DEST_BASE_ENA     (1 << 14)
504 #              define PACKET3_CB8_DEST_BASE_ENA    (1 << 15)
505 #              define PACKET3_CB9_DEST_BASE_ENA    (1 << 16)
506 #              define PACKET3_CB10_DEST_BASE_ENA   (1 << 17)
507 #              define PACKET3_CB11_DEST_BASE_ENA   (1 << 18)
508 #              define PACKET3_FULL_CACHE_ENA       (1 << 20)
509 #              define PACKET3_TC_ACTION_ENA        (1 << 23)
510 #              define PACKET3_CB_ACTION_ENA        (1 << 25)
511 #              define PACKET3_DB_ACTION_ENA        (1 << 26)
512 #              define PACKET3_SH_ACTION_ENA        (1 << 27)
513 #              define PACKET3_SX_ACTION_ENA        (1 << 28)
514 #define PACKET3_ME_INITIALIZE                           0x44
515 #define         PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
516 #define PACKET3_COND_WRITE                              0x45
517 #define PACKET3_EVENT_WRITE                             0x46
518 #define         EVENT_TYPE(x)                           ((x) << 0)
519 #define         EVENT_INDEX(x)                          ((x) << 8)
520                 /* 0 - any non-TS event
521                  * 1 - ZPASS_DONE
522                  * 2 - SAMPLE_PIPELINESTAT
523                  * 3 - SAMPLE_STREAMOUTSTAT*
524                  * 4 - *S_PARTIAL_FLUSH
525                  * 5 - TS events
526                  */
527 #define PACKET3_EVENT_WRITE_EOP                         0x47
528 #define         DATA_SEL(x)                             ((x) << 29)
529                 /* 0 - discard
530                  * 1 - send low 32bit data
531                  * 2 - send 64bit data
532                  * 3 - send 64bit counter value
533                  */
534 #define         INT_SEL(x)                              ((x) << 24)
535                 /* 0 - none
536                  * 1 - interrupt only (DATA_SEL = 0)
537                  * 2 - interrupt when data write is confirmed
538                  */
539 #define PACKET3_EVENT_WRITE_EOS                         0x48
540 #define PACKET3_PREAMBLE_CNTL                           0x4A
541 #              define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE     (2 << 28)
542 #              define PACKET3_PREAMBLE_END_CLEAR_STATE       (3 << 28)
543 #define PACKET3_ALU_PS_CONST_BUFFER_COPY                0x4C
544 #define PACKET3_ALU_VS_CONST_BUFFER_COPY                0x4D
545 #define PACKET3_ALU_PS_CONST_UPDATE                     0x4E
546 #define PACKET3_ALU_VS_CONST_UPDATE                     0x4F
547 #define PACKET3_ONE_REG_WRITE                           0x57
548 #define PACKET3_SET_CONFIG_REG                          0x68
549 #define         PACKET3_SET_CONFIG_REG_START                    0x00008000
550 #define         PACKET3_SET_CONFIG_REG_END                      0x0000ac00
551 #define PACKET3_SET_CONTEXT_REG                         0x69
552 #define         PACKET3_SET_CONTEXT_REG_START                   0x00028000
553 #define         PACKET3_SET_CONTEXT_REG_END                     0x00029000
554 #define PACKET3_SET_ALU_CONST                           0x6A
555 /* alu const buffers only; no reg file */
556 #define PACKET3_SET_BOOL_CONST                          0x6B
557 #define         PACKET3_SET_BOOL_CONST_START                    0x0003a500
558 #define         PACKET3_SET_BOOL_CONST_END                      0x0003a518
559 #define PACKET3_SET_LOOP_CONST                          0x6C
560 #define         PACKET3_SET_LOOP_CONST_START                    0x0003a200
561 #define         PACKET3_SET_LOOP_CONST_END                      0x0003a500
562 #define PACKET3_SET_RESOURCE                            0x6D
563 #define         PACKET3_SET_RESOURCE_START                      0x00030000
564 #define         PACKET3_SET_RESOURCE_END                        0x00038000
565 #define PACKET3_SET_SAMPLER                             0x6E
566 #define         PACKET3_SET_SAMPLER_START                       0x0003c000
567 #define         PACKET3_SET_SAMPLER_END                         0x0003c600
568 #define PACKET3_SET_CTL_CONST                           0x6F
569 #define         PACKET3_SET_CTL_CONST_START                     0x0003cff0
570 #define         PACKET3_SET_CTL_CONST_END                       0x0003ff0c
571 #define PACKET3_SET_RESOURCE_OFFSET                     0x70
572 #define PACKET3_SET_ALU_CONST_VS                        0x71
573 #define PACKET3_SET_ALU_CONST_DI                        0x72
574 #define PACKET3_SET_CONTEXT_REG_INDIRECT                0x73
575 #define PACKET3_SET_RESOURCE_INDIRECT                   0x74
576 #define PACKET3_SET_APPEND_CNT                          0x75
577
578 #endif
579