2 * Copyright 2010 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
22 * Authors: Alex Deucher
27 #define EVERGREEN_MAX_SH_GPRS 256
28 #define EVERGREEN_MAX_TEMP_GPRS 16
29 #define EVERGREEN_MAX_SH_THREADS 256
30 #define EVERGREEN_MAX_SH_STACK_ENTRIES 4096
31 #define EVERGREEN_MAX_FRC_EOV_CNT 16384
32 #define EVERGREEN_MAX_BACKENDS 8
33 #define EVERGREEN_MAX_BACKENDS_MASK 0xFF
34 #define EVERGREEN_MAX_SIMDS 16
35 #define EVERGREEN_MAX_SIMDS_MASK 0xFFFF
36 #define EVERGREEN_MAX_PIPES 8
37 #define EVERGREEN_MAX_PIPES_MASK 0xFF
38 #define EVERGREEN_MAX_LDS_NUM 0xFFFF
42 #define RCU_IND_INDEX 0x100
43 #define RCU_IND_DATA 0x104
45 #define GRBM_GFX_INDEX 0x802C
46 #define INSTANCE_INDEX(x) ((x) << 0)
47 #define SE_INDEX(x) ((x) << 16)
48 #define INSTANCE_BROADCAST_WRITES (1 << 30)
49 #define SE_BROADCAST_WRITES (1 << 31)
50 #define RLC_GFX_INDEX 0x3fC4
51 #define CC_GC_SHADER_PIPE_CONFIG 0x8950
52 #define WRITE_DIS (1 << 0)
53 #define CC_RB_BACKEND_DISABLE 0x98F4
54 #define BACKEND_DISABLE(x) ((x) << 16)
55 #define GB_ADDR_CONFIG 0x98F8
56 #define NUM_PIPES(x) ((x) << 0)
57 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4)
58 #define BANK_INTERLEAVE_SIZE(x) ((x) << 8)
59 #define NUM_SHADER_ENGINES(x) ((x) << 12)
60 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16)
61 #define NUM_GPUS(x) ((x) << 20)
62 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24)
63 #define ROW_SIZE(x) ((x) << 28)
64 #define GB_BACKEND_MAP 0x98FC
65 #define DMIF_ADDR_CONFIG 0xBD4
66 #define HDP_ADDR_CONFIG 0x2F48
68 #define CC_SYS_RB_BACKEND_DISABLE 0x3F88
69 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C
71 #define CGTS_SYS_TCC_DISABLE 0x3F90
72 #define CGTS_TCC_DISABLE 0x9148
73 #define CGTS_USER_SYS_TCC_DISABLE 0x3F94
74 #define CGTS_USER_TCC_DISABLE 0x914C
76 #define CONFIG_MEMSIZE 0x5428
78 #define CP_ME_CNTL 0x86D8
79 #define CP_ME_HALT (1 << 28)
80 #define CP_PFP_HALT (1 << 26)
81 #define CP_ME_RAM_DATA 0xC160
82 #define CP_ME_RAM_RADDR 0xC158
83 #define CP_ME_RAM_WADDR 0xC15C
84 #define CP_MEQ_THRESHOLDS 0x8764
85 #define STQ_SPLIT(x) ((x) << 0)
86 #define CP_PERFMON_CNTL 0x87FC
87 #define CP_PFP_UCODE_ADDR 0xC150
88 #define CP_PFP_UCODE_DATA 0xC154
89 #define CP_QUEUE_THRESHOLDS 0x8760
90 #define ROQ_IB1_START(x) ((x) << 0)
91 #define ROQ_IB2_START(x) ((x) << 8)
92 #define CP_RB_BASE 0xC100
93 #define CP_RB_CNTL 0xC104
94 #define RB_BUFSZ(x) ((x) << 0)
95 #define RB_BLKSZ(x) ((x) << 8)
96 #define RB_NO_UPDATE (1 << 27)
97 #define RB_RPTR_WR_ENA (1 << 31)
98 #define BUF_SWAP_32BIT (2 << 16)
99 #define CP_RB_RPTR 0x8700
100 #define CP_RB_RPTR_ADDR 0xC10C
101 #define RB_RPTR_SWAP(x) ((x) << 0)
102 #define CP_RB_RPTR_ADDR_HI 0xC110
103 #define CP_RB_RPTR_WR 0xC108
104 #define CP_RB_WPTR 0xC114
105 #define CP_RB_WPTR_ADDR 0xC118
106 #define CP_RB_WPTR_ADDR_HI 0xC11C
107 #define CP_RB_WPTR_DELAY 0x8704
108 #define CP_SEM_WAIT_TIMER 0x85BC
109 #define CP_DEBUG 0xC1FC
112 #define GC_USER_SHADER_PIPE_CONFIG 0x8954
113 #define INACTIVE_QD_PIPES(x) ((x) << 8)
114 #define INACTIVE_QD_PIPES_MASK 0x0000FF00
115 #define INACTIVE_SIMDS(x) ((x) << 16)
116 #define INACTIVE_SIMDS_MASK 0x00FF0000
118 #define GRBM_CNTL 0x8000
119 #define GRBM_READ_TIMEOUT(x) ((x) << 0)
120 #define GRBM_SOFT_RESET 0x8020
121 #define SOFT_RESET_CP (1 << 0)
122 #define SOFT_RESET_CB (1 << 1)
123 #define SOFT_RESET_DB (1 << 3)
124 #define SOFT_RESET_PA (1 << 5)
125 #define SOFT_RESET_SC (1 << 6)
126 #define SOFT_RESET_SPI (1 << 8)
127 #define SOFT_RESET_SH (1 << 9)
128 #define SOFT_RESET_SX (1 << 10)
129 #define SOFT_RESET_TC (1 << 11)
130 #define SOFT_RESET_TA (1 << 12)
131 #define SOFT_RESET_VC (1 << 13)
132 #define SOFT_RESET_VGT (1 << 14)
134 #define GRBM_STATUS 0x8010
135 #define CMDFIFO_AVAIL_MASK 0x0000000F
136 #define SRBM_RQ_PENDING (1 << 5)
137 #define CF_RQ_PENDING (1 << 7)
138 #define PF_RQ_PENDING (1 << 8)
139 #define GRBM_EE_BUSY (1 << 10)
140 #define SX_CLEAN (1 << 11)
141 #define DB_CLEAN (1 << 12)
142 #define CB_CLEAN (1 << 13)
143 #define TA_BUSY (1 << 14)
144 #define VGT_BUSY_NO_DMA (1 << 16)
145 #define VGT_BUSY (1 << 17)
146 #define SX_BUSY (1 << 20)
147 #define SH_BUSY (1 << 21)
148 #define SPI_BUSY (1 << 22)
149 #define SC_BUSY (1 << 24)
150 #define PA_BUSY (1 << 25)
151 #define DB_BUSY (1 << 26)
152 #define CP_COHERENCY_BUSY (1 << 28)
153 #define CP_BUSY (1 << 29)
154 #define CB_BUSY (1 << 30)
155 #define GUI_ACTIVE (1 << 31)
156 #define GRBM_STATUS_SE0 0x8014
157 #define GRBM_STATUS_SE1 0x8018
158 #define SE_SX_CLEAN (1 << 0)
159 #define SE_DB_CLEAN (1 << 1)
160 #define SE_CB_CLEAN (1 << 2)
161 #define SE_TA_BUSY (1 << 25)
162 #define SE_SX_BUSY (1 << 26)
163 #define SE_SPI_BUSY (1 << 27)
164 #define SE_SH_BUSY (1 << 28)
165 #define SE_SC_BUSY (1 << 29)
166 #define SE_DB_BUSY (1 << 30)
167 #define SE_CB_BUSY (1 << 31)
169 #define CG_MULT_THERMAL_STATUS 0x740
170 #define ASIC_T(x) ((x) << 16)
171 #define ASIC_T_MASK 0x7FF0000
172 #define ASIC_T_SHIFT 16
174 #define CG_THERMAL_STATUS 0x678
176 #define HDP_HOST_PATH_CNTL 0x2C00
177 #define HDP_NONSURFACE_BASE 0x2C04
178 #define HDP_NONSURFACE_INFO 0x2C08
179 #define HDP_NONSURFACE_SIZE 0x2C0C
180 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480
181 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
182 #define HDP_TILING_CONFIG 0x2F3C
184 #define MC_SHARED_CHMAP 0x2004
185 #define NOOFCHAN_SHIFT 12
186 #define NOOFCHAN_MASK 0x00003000
187 #define MC_SHARED_CHREMAP 0x2008
189 #define MC_ARB_RAMCFG 0x2760
190 #define NOOFBANK_SHIFT 0
191 #define NOOFBANK_MASK 0x00000003
192 #define NOOFRANK_SHIFT 2
193 #define NOOFRANK_MASK 0x00000004
194 #define NOOFROWS_SHIFT 3
195 #define NOOFROWS_MASK 0x00000038
196 #define NOOFCOLS_SHIFT 6
197 #define NOOFCOLS_MASK 0x000000C0
198 #define CHANSIZE_SHIFT 8
199 #define CHANSIZE_MASK 0x00000100
200 #define BURSTLENGTH_SHIFT 9
201 #define BURSTLENGTH_MASK 0x00000200
202 #define CHANSIZE_OVERRIDE (1 << 11)
203 #define FUS_MC_ARB_RAMCFG 0x2768
204 #define MC_VM_AGP_TOP 0x2028
205 #define MC_VM_AGP_BOT 0x202C
206 #define MC_VM_AGP_BASE 0x2030
207 #define MC_VM_FB_LOCATION 0x2024
208 #define MC_FUS_VM_FB_OFFSET 0x2898
209 #define MC_VM_MB_L1_TLB0_CNTL 0x2234
210 #define MC_VM_MB_L1_TLB1_CNTL 0x2238
211 #define MC_VM_MB_L1_TLB2_CNTL 0x223C
212 #define MC_VM_MB_L1_TLB3_CNTL 0x2240
213 #define ENABLE_L1_TLB (1 << 0)
214 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
215 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
216 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
217 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
218 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
219 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
220 #define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15)
221 #define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18)
222 #define MC_VM_MD_L1_TLB0_CNTL 0x2654
223 #define MC_VM_MD_L1_TLB1_CNTL 0x2658
224 #define MC_VM_MD_L1_TLB2_CNTL 0x265C
226 #define FUS_MC_VM_MD_L1_TLB0_CNTL 0x265C
227 #define FUS_MC_VM_MD_L1_TLB1_CNTL 0x2660
228 #define FUS_MC_VM_MD_L1_TLB2_CNTL 0x2664
230 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
231 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
232 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
234 #define PA_CL_ENHANCE 0x8A14
235 #define CLIP_VTX_REORDER_ENA (1 << 0)
236 #define NUM_CLIP_SEQ(x) ((x) << 1)
237 #define PA_SC_AA_CONFIG 0x28C04
238 #define MSAA_NUM_SAMPLES_SHIFT 0
239 #define MSAA_NUM_SAMPLES_MASK 0x3
240 #define PA_SC_CLIPRECT_RULE 0x2820C
241 #define PA_SC_EDGERULE 0x28230
242 #define PA_SC_FIFO_SIZE 0x8BCC
243 #define SC_PRIM_FIFO_SIZE(x) ((x) << 0)
244 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
245 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
246 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
247 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0)
248 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16)
249 #define PA_SC_LINE_STIPPLE 0x28A0C
250 #define PA_SU_LINE_STIPPLE_VALUE 0x8A60
251 #define PA_SC_LINE_STIPPLE_STATE 0x8B10
253 #define SCRATCH_REG0 0x8500
254 #define SCRATCH_REG1 0x8504
255 #define SCRATCH_REG2 0x8508
256 #define SCRATCH_REG3 0x850C
257 #define SCRATCH_REG4 0x8510
258 #define SCRATCH_REG5 0x8514
259 #define SCRATCH_REG6 0x8518
260 #define SCRATCH_REG7 0x851C
261 #define SCRATCH_UMSK 0x8540
262 #define SCRATCH_ADDR 0x8544
264 #define SMX_DC_CTL0 0xA020
265 #define USE_HASH_FUNCTION (1 << 0)
266 #define NUMBER_OF_SETS(x) ((x) << 1)
267 #define FLUSH_ALL_ON_EVENT (1 << 10)
268 #define STALL_ON_EVENT (1 << 11)
269 #define SMX_EVENT_CTL 0xA02C
270 #define ES_FLUSH_CTL(x) ((x) << 0)
271 #define GS_FLUSH_CTL(x) ((x) << 3)
272 #define ACK_FLUSH_CTL(x) ((x) << 6)
273 #define SYNC_FLUSH_CTL (1 << 8)
275 #define SPI_CONFIG_CNTL 0x9100
276 #define GPR_WRITE_PRIORITY(x) ((x) << 0)
277 #define SPI_CONFIG_CNTL_1 0x913C
278 #define VTX_DONE_DELAY(x) ((x) << 0)
279 #define INTERP_ONE_PRIM_PER_ROW (1 << 4)
280 #define SPI_INPUT_Z 0x286D8
281 #define SPI_PS_IN_CONTROL_0 0x286CC
282 #define NUM_INTERP(x) ((x)<<0)
283 #define POSITION_ENA (1<<8)
284 #define POSITION_CENTROID (1<<9)
285 #define POSITION_ADDR(x) ((x)<<10)
286 #define PARAM_GEN(x) ((x)<<15)
287 #define PARAM_GEN_ADDR(x) ((x)<<19)
288 #define BARYC_SAMPLE_CNTL(x) ((x)<<26)
289 #define PERSP_GRADIENT_ENA (1<<28)
290 #define LINEAR_GRADIENT_ENA (1<<29)
291 #define POSITION_SAMPLE (1<<30)
292 #define BARYC_AT_SAMPLE_ENA (1<<31)
294 #define SQ_CONFIG 0x8C00
295 #define VC_ENABLE (1 << 0)
296 #define EXPORT_SRC_C (1 << 1)
297 #define CS_PRIO(x) ((x) << 18)
298 #define LS_PRIO(x) ((x) << 20)
299 #define HS_PRIO(x) ((x) << 22)
300 #define PS_PRIO(x) ((x) << 24)
301 #define VS_PRIO(x) ((x) << 26)
302 #define GS_PRIO(x) ((x) << 28)
303 #define ES_PRIO(x) ((x) << 30)
304 #define SQ_GPR_RESOURCE_MGMT_1 0x8C04
305 #define NUM_PS_GPRS(x) ((x) << 0)
306 #define NUM_VS_GPRS(x) ((x) << 16)
307 #define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
308 #define SQ_GPR_RESOURCE_MGMT_2 0x8C08
309 #define NUM_GS_GPRS(x) ((x) << 0)
310 #define NUM_ES_GPRS(x) ((x) << 16)
311 #define SQ_GPR_RESOURCE_MGMT_3 0x8C0C
312 #define NUM_HS_GPRS(x) ((x) << 0)
313 #define NUM_LS_GPRS(x) ((x) << 16)
314 #define SQ_THREAD_RESOURCE_MGMT 0x8C18
315 #define NUM_PS_THREADS(x) ((x) << 0)
316 #define NUM_VS_THREADS(x) ((x) << 8)
317 #define NUM_GS_THREADS(x) ((x) << 16)
318 #define NUM_ES_THREADS(x) ((x) << 24)
319 #define SQ_THREAD_RESOURCE_MGMT_2 0x8C1C
320 #define NUM_HS_THREADS(x) ((x) << 0)
321 #define NUM_LS_THREADS(x) ((x) << 8)
322 #define SQ_STACK_RESOURCE_MGMT_1 0x8C20
323 #define NUM_PS_STACK_ENTRIES(x) ((x) << 0)
324 #define NUM_VS_STACK_ENTRIES(x) ((x) << 16)
325 #define SQ_STACK_RESOURCE_MGMT_2 0x8C24
326 #define NUM_GS_STACK_ENTRIES(x) ((x) << 0)
327 #define NUM_ES_STACK_ENTRIES(x) ((x) << 16)
328 #define SQ_STACK_RESOURCE_MGMT_3 0x8C28
329 #define NUM_HS_STACK_ENTRIES(x) ((x) << 0)
330 #define NUM_LS_STACK_ENTRIES(x) ((x) << 16)
331 #define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C
332 #define SQ_LDS_RESOURCE_MGMT 0x8E2C
334 #define SQ_MS_FIFO_SIZES 0x8CF0
335 #define CACHE_FIFO_SIZE(x) ((x) << 0)
336 #define FETCH_FIFO_HIWATER(x) ((x) << 8)
337 #define DONE_FIFO_HIWATER(x) ((x) << 16)
338 #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
340 #define SX_DEBUG_1 0x9058
341 #define ENABLE_NEW_SMX_ADDRESS (1 << 16)
342 #define SX_EXPORT_BUFFER_SIZES 0x900C
343 #define COLOR_BUFFER_SIZE(x) ((x) << 0)
344 #define POSITION_BUFFER_SIZE(x) ((x) << 8)
345 #define SMX_BUFFER_SIZE(x) ((x) << 16)
346 #define SX_MISC 0x28350
348 #define CB_PERF_CTR0_SEL_0 0x9A20
349 #define CB_PERF_CTR0_SEL_1 0x9A24
350 #define CB_PERF_CTR1_SEL_0 0x9A28
351 #define CB_PERF_CTR1_SEL_1 0x9A2C
352 #define CB_PERF_CTR2_SEL_0 0x9A30
353 #define CB_PERF_CTR2_SEL_1 0x9A34
354 #define CB_PERF_CTR3_SEL_0 0x9A38
355 #define CB_PERF_CTR3_SEL_1 0x9A3C
357 #define TA_CNTL_AUX 0x9508
358 #define DISABLE_CUBE_WRAP (1 << 0)
359 #define DISABLE_CUBE_ANISO (1 << 1)
360 #define SYNC_GRADIENT (1 << 24)
361 #define SYNC_WALKER (1 << 25)
362 #define SYNC_ALIGNER (1 << 26)
364 #define TCP_CHAN_STEER_LO 0x960c
365 #define TCP_CHAN_STEER_HI 0x9610
367 #define VGT_CACHE_INVALIDATION 0x88C4
368 #define CACHE_INVALIDATION(x) ((x) << 0)
372 #define AUTO_INVLD_EN(x) ((x) << 6)
376 #define ES_AND_GS_AUTO 3
377 #define VGT_GS_VERTEX_REUSE 0x88D4
378 #define VGT_NUM_INSTANCES 0x8974
379 #define VGT_OUT_DEALLOC_CNTL 0x28C5C
380 #define DEALLOC_DIST_MASK 0x0000007F
381 #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58
382 #define VTX_REUSE_DEPTH_MASK 0x000000FF
384 #define VM_CONTEXT0_CNTL 0x1410
385 #define ENABLE_CONTEXT (1 << 0)
386 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
387 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
388 #define VM_CONTEXT1_CNTL 0x1414
389 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C
390 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
391 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C
392 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
393 #define VM_CONTEXT0_REQUEST_RESPONSE 0x1470
394 #define REQUEST_TYPE(x) (((x) & 0xf) << 0)
395 #define RESPONSE_TYPE_MASK 0x000000F0
396 #define RESPONSE_TYPE_SHIFT 4
397 #define VM_L2_CNTL 0x1400
398 #define ENABLE_L2_CACHE (1 << 0)
399 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
400 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
401 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14)
402 #define VM_L2_CNTL2 0x1404
403 #define INVALIDATE_ALL_L1_TLBS (1 << 0)
404 #define INVALIDATE_L2_CACHE (1 << 1)
405 #define VM_L2_CNTL3 0x1408
406 #define BANK_SELECT(x) ((x) << 0)
407 #define CACHE_UPDATE_MODE(x) ((x) << 6)
408 #define VM_L2_STATUS 0x140C
409 #define L2_BUSY (1 << 0)
411 #define WAIT_UNTIL 0x8040
413 #define SRBM_STATUS 0x0E50
414 #define SRBM_SOFT_RESET 0x0E60
415 #define SRBM_SOFT_RESET_ALL_MASK 0x00FEEFA6
416 #define SOFT_RESET_BIF (1 << 1)
417 #define SOFT_RESET_CG (1 << 2)
418 #define SOFT_RESET_DC (1 << 5)
419 #define SOFT_RESET_GRBM (1 << 8)
420 #define SOFT_RESET_HDP (1 << 9)
421 #define SOFT_RESET_IH (1 << 10)
422 #define SOFT_RESET_MC (1 << 11)
423 #define SOFT_RESET_RLC (1 << 13)
424 #define SOFT_RESET_ROM (1 << 14)
425 #define SOFT_RESET_SEM (1 << 15)
426 #define SOFT_RESET_VMC (1 << 17)
427 #define SOFT_RESET_TST (1 << 21)
428 #define SOFT_RESET_REGBB (1 << 22)
429 #define SOFT_RESET_ORB (1 << 23)
431 /* display watermarks */
432 #define DC_LB_MEMORY_SPLIT 0x6b0c
433 #define PRIORITY_A_CNT 0x6b18
434 #define PRIORITY_MARK_MASK 0x7fff
435 #define PRIORITY_OFF (1 << 16)
436 #define PRIORITY_ALWAYS_ON (1 << 20)
437 #define PRIORITY_B_CNT 0x6b1c
438 #define PIPE0_ARBITRATION_CONTROL3 0x0bf0
439 # define LATENCY_WATERMARK_MASK(x) ((x) << 16)
440 #define PIPE0_LATENCY_CONTROL 0x0bf4
441 # define LATENCY_LOW_WATERMARK(x) ((x) << 0)
442 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16)
444 #define IH_RB_CNTL 0x3e00
445 # define IH_RB_ENABLE (1 << 0)
446 # define IH_IB_SIZE(x) ((x) << 1) /* log2 */
447 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6)
448 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8)
449 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */
450 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16)
451 # define IH_WPTR_OVERFLOW_CLEAR (1 << 31)
452 #define IH_RB_BASE 0x3e04
453 #define IH_RB_RPTR 0x3e08
454 #define IH_RB_WPTR 0x3e0c
455 # define RB_OVERFLOW (1 << 0)
456 # define WPTR_OFFSET_MASK 0x3fffc
457 #define IH_RB_WPTR_ADDR_HI 0x3e10
458 #define IH_RB_WPTR_ADDR_LO 0x3e14
459 #define IH_CNTL 0x3e18
460 # define ENABLE_INTR (1 << 0)
461 # define IH_MC_SWAP(x) ((x) << 2)
462 # define IH_MC_SWAP_NONE 0
463 # define IH_MC_SWAP_16BIT 1
464 # define IH_MC_SWAP_32BIT 2
465 # define IH_MC_SWAP_64BIT 3
466 # define RPTR_REARM (1 << 4)
467 # define MC_WRREQ_CREDIT(x) ((x) << 15)
468 # define MC_WR_CLEAN_CNT(x) ((x) << 20)
470 #define CP_INT_CNTL 0xc124
471 # define CNTX_BUSY_INT_ENABLE (1 << 19)
472 # define CNTX_EMPTY_INT_ENABLE (1 << 20)
473 # define SCRATCH_INT_ENABLE (1 << 25)
474 # define TIME_STAMP_INT_ENABLE (1 << 26)
475 # define IB2_INT_ENABLE (1 << 29)
476 # define IB1_INT_ENABLE (1 << 30)
477 # define RB_INT_ENABLE (1 << 31)
478 #define CP_INT_STATUS 0xc128
479 # define SCRATCH_INT_STAT (1 << 25)
480 # define TIME_STAMP_INT_STAT (1 << 26)
481 # define IB2_INT_STAT (1 << 29)
482 # define IB1_INT_STAT (1 << 30)
483 # define RB_INT_STAT (1 << 31)
485 #define GRBM_INT_CNTL 0x8060
486 # define RDERR_INT_ENABLE (1 << 0)
487 # define GUI_IDLE_INT_ENABLE (1 << 19)
489 /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */
490 #define CRTC_STATUS_FRAME_COUNT 0x6e98
492 /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */
493 #define VLINE_STATUS 0x6bb8
494 # define VLINE_OCCURRED (1 << 0)
495 # define VLINE_ACK (1 << 4)
496 # define VLINE_STAT (1 << 12)
497 # define VLINE_INTERRUPT (1 << 16)
498 # define VLINE_INTERRUPT_TYPE (1 << 17)
499 /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */
500 #define VBLANK_STATUS 0x6bbc
501 # define VBLANK_OCCURRED (1 << 0)
502 # define VBLANK_ACK (1 << 4)
503 # define VBLANK_STAT (1 << 12)
504 # define VBLANK_INTERRUPT (1 << 16)
505 # define VBLANK_INTERRUPT_TYPE (1 << 17)
507 /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */
508 #define INT_MASK 0x6b40
509 # define VBLANK_INT_MASK (1 << 0)
510 # define VLINE_INT_MASK (1 << 4)
512 #define DISP_INTERRUPT_STATUS 0x60f4
513 # define LB_D1_VLINE_INTERRUPT (1 << 2)
514 # define LB_D1_VBLANK_INTERRUPT (1 << 3)
515 # define DC_HPD1_INTERRUPT (1 << 17)
516 # define DC_HPD1_RX_INTERRUPT (1 << 18)
517 # define DACA_AUTODETECT_INTERRUPT (1 << 22)
518 # define DACB_AUTODETECT_INTERRUPT (1 << 23)
519 # define DC_I2C_SW_DONE_INTERRUPT (1 << 24)
520 # define DC_I2C_HW_DONE_INTERRUPT (1 << 25)
521 #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8
522 # define LB_D2_VLINE_INTERRUPT (1 << 2)
523 # define LB_D2_VBLANK_INTERRUPT (1 << 3)
524 # define DC_HPD2_INTERRUPT (1 << 17)
525 # define DC_HPD2_RX_INTERRUPT (1 << 18)
526 # define DISP_TIMER_INTERRUPT (1 << 24)
527 #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc
528 # define LB_D3_VLINE_INTERRUPT (1 << 2)
529 # define LB_D3_VBLANK_INTERRUPT (1 << 3)
530 # define DC_HPD3_INTERRUPT (1 << 17)
531 # define DC_HPD3_RX_INTERRUPT (1 << 18)
532 #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100
533 # define LB_D4_VLINE_INTERRUPT (1 << 2)
534 # define LB_D4_VBLANK_INTERRUPT (1 << 3)
535 # define DC_HPD4_INTERRUPT (1 << 17)
536 # define DC_HPD4_RX_INTERRUPT (1 << 18)
537 #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c
538 # define LB_D5_VLINE_INTERRUPT (1 << 2)
539 # define LB_D5_VBLANK_INTERRUPT (1 << 3)
540 # define DC_HPD5_INTERRUPT (1 << 17)
541 # define DC_HPD5_RX_INTERRUPT (1 << 18)
542 #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6050
543 # define LB_D6_VLINE_INTERRUPT (1 << 2)
544 # define LB_D6_VBLANK_INTERRUPT (1 << 3)
545 # define DC_HPD6_INTERRUPT (1 << 17)
546 # define DC_HPD6_RX_INTERRUPT (1 << 18)
548 /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
549 #define GRPH_INT_STATUS 0x6858
550 # define GRPH_PFLIP_INT_OCCURRED (1 << 0)
551 # define GRPH_PFLIP_INT_CLEAR (1 << 8)
552 /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
553 #define GRPH_INT_CONTROL 0x685c
554 # define GRPH_PFLIP_INT_MASK (1 << 0)
555 # define GRPH_PFLIP_INT_TYPE (1 << 8)
557 #define DACA_AUTODETECT_INT_CONTROL 0x66c8
558 #define DACB_AUTODETECT_INT_CONTROL 0x67c8
560 #define DC_HPD1_INT_STATUS 0x601c
561 #define DC_HPD2_INT_STATUS 0x6028
562 #define DC_HPD3_INT_STATUS 0x6034
563 #define DC_HPD4_INT_STATUS 0x6040
564 #define DC_HPD5_INT_STATUS 0x604c
565 #define DC_HPD6_INT_STATUS 0x6058
566 # define DC_HPDx_INT_STATUS (1 << 0)
567 # define DC_HPDx_SENSE (1 << 1)
568 # define DC_HPDx_RX_INT_STATUS (1 << 8)
570 #define DC_HPD1_INT_CONTROL 0x6020
571 #define DC_HPD2_INT_CONTROL 0x602c
572 #define DC_HPD3_INT_CONTROL 0x6038
573 #define DC_HPD4_INT_CONTROL 0x6044
574 #define DC_HPD5_INT_CONTROL 0x6050
575 #define DC_HPD6_INT_CONTROL 0x605c
576 # define DC_HPDx_INT_ACK (1 << 0)
577 # define DC_HPDx_INT_POLARITY (1 << 8)
578 # define DC_HPDx_INT_EN (1 << 16)
579 # define DC_HPDx_RX_INT_ACK (1 << 20)
580 # define DC_HPDx_RX_INT_EN (1 << 24)
582 #define DC_HPD1_CONTROL 0x6024
583 #define DC_HPD2_CONTROL 0x6030
584 #define DC_HPD3_CONTROL 0x603c
585 #define DC_HPD4_CONTROL 0x6048
586 #define DC_HPD5_CONTROL 0x6054
587 #define DC_HPD6_CONTROL 0x6060
588 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0)
589 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16)
590 # define DC_HPDx_EN (1 << 28)
592 /* PCIE link stuff */
593 #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */
594 #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
595 # define LC_LINK_WIDTH_SHIFT 0
596 # define LC_LINK_WIDTH_MASK 0x7
597 # define LC_LINK_WIDTH_X0 0
598 # define LC_LINK_WIDTH_X1 1
599 # define LC_LINK_WIDTH_X2 2
600 # define LC_LINK_WIDTH_X4 3
601 # define LC_LINK_WIDTH_X8 4
602 # define LC_LINK_WIDTH_X16 6
603 # define LC_LINK_WIDTH_RD_SHIFT 4
604 # define LC_LINK_WIDTH_RD_MASK 0x70
605 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
606 # define LC_RECONFIG_NOW (1 << 8)
607 # define LC_RENEGOTIATION_SUPPORT (1 << 9)
608 # define LC_RENEGOTIATE_EN (1 << 10)
609 # define LC_SHORT_RECONFIG_EN (1 << 11)
610 # define LC_UPCONFIGURE_SUPPORT (1 << 12)
611 # define LC_UPCONFIGURE_DIS (1 << 13)
612 #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
613 # define LC_GEN2_EN_STRAP (1 << 0)
614 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)
615 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)
616 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)
617 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)
618 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3
619 # define LC_CURRENT_DATA_RATE (1 << 11)
620 # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)
621 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)
622 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)
623 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)
624 #define MM_CFGREGS_CNTL 0x544c
625 # define MM_WR_TO_CFG_EN (1 << 3)
626 #define LINK_CNTL2 0x88 /* F0 */
627 # define TARGET_LINK_SPEED_MASK (0xf << 0)
628 # define SELECTABLE_DEEMPHASIS (1 << 6)
633 #define PACKET_TYPE0 0
634 #define PACKET_TYPE1 1
635 #define PACKET_TYPE2 2
636 #define PACKET_TYPE3 3
638 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
639 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
640 #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
641 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
642 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) | \
643 (((reg) >> 2) & 0xFFFF) | \
644 ((n) & 0x3FFF) << 16)
645 #define CP_PACKET2 0x80000000
646 #define PACKET2_PAD_SHIFT 0
647 #define PACKET2_PAD_MASK (0x3fffffff << 0)
649 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
651 #define PACKET3(op, n) ((PACKET_TYPE3 << 30) | \
652 (((op) & 0xFF) << 8) | \
653 ((n) & 0x3FFF) << 16)
656 #define PACKET3_NOP 0x10
657 #define PACKET3_SET_BASE 0x11
658 #define PACKET3_CLEAR_STATE 0x12
659 #define PACKET3_INDEX_BUFFER_SIZE 0x13
660 #define PACKET3_DISPATCH_DIRECT 0x15
661 #define PACKET3_DISPATCH_INDIRECT 0x16
662 #define PACKET3_INDIRECT_BUFFER_END 0x17
663 #define PACKET3_MODE_CONTROL 0x18
664 #define PACKET3_SET_PREDICATION 0x20
665 #define PACKET3_REG_RMW 0x21
666 #define PACKET3_COND_EXEC 0x22
667 #define PACKET3_PRED_EXEC 0x23
668 #define PACKET3_DRAW_INDIRECT 0x24
669 #define PACKET3_DRAW_INDEX_INDIRECT 0x25
670 #define PACKET3_INDEX_BASE 0x26
671 #define PACKET3_DRAW_INDEX_2 0x27
672 #define PACKET3_CONTEXT_CONTROL 0x28
673 #define PACKET3_DRAW_INDEX_OFFSET 0x29
674 #define PACKET3_INDEX_TYPE 0x2A
675 #define PACKET3_DRAW_INDEX 0x2B
676 #define PACKET3_DRAW_INDEX_AUTO 0x2D
677 #define PACKET3_DRAW_INDEX_IMMD 0x2E
678 #define PACKET3_NUM_INSTANCES 0x2F
679 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
680 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
681 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35
682 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36
683 #define PACKET3_MEM_SEMAPHORE 0x39
684 #define PACKET3_MPEG_INDEX 0x3A
685 #define PACKET3_WAIT_REG_MEM 0x3C
686 #define PACKET3_MEM_WRITE 0x3D
687 #define PACKET3_INDIRECT_BUFFER 0x32
688 #define PACKET3_SURFACE_SYNC 0x43
689 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
690 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
691 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
692 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
693 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
694 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
695 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
696 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
697 # define PACKET3_DB_DEST_BASE_ENA (1 << 14)
698 # define PACKET3_CB8_DEST_BASE_ENA (1 << 15)
699 # define PACKET3_CB9_DEST_BASE_ENA (1 << 16)
700 # define PACKET3_CB10_DEST_BASE_ENA (1 << 17)
701 # define PACKET3_CB11_DEST_BASE_ENA (1 << 18)
702 # define PACKET3_FULL_CACHE_ENA (1 << 20)
703 # define PACKET3_TC_ACTION_ENA (1 << 23)
704 # define PACKET3_VC_ACTION_ENA (1 << 24)
705 # define PACKET3_CB_ACTION_ENA (1 << 25)
706 # define PACKET3_DB_ACTION_ENA (1 << 26)
707 # define PACKET3_SH_ACTION_ENA (1 << 27)
708 # define PACKET3_SX_ACTION_ENA (1 << 28)
709 #define PACKET3_ME_INITIALIZE 0x44
710 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
711 #define PACKET3_COND_WRITE 0x45
712 #define PACKET3_EVENT_WRITE 0x46
713 #define PACKET3_EVENT_WRITE_EOP 0x47
714 #define PACKET3_EVENT_WRITE_EOS 0x48
715 #define PACKET3_PREAMBLE_CNTL 0x4A
716 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
717 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
718 #define PACKET3_RB_OFFSET 0x4B
719 #define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C
720 #define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D
721 #define PACKET3_ALU_PS_CONST_UPDATE 0x4E
722 #define PACKET3_ALU_VS_CONST_UPDATE 0x4F
723 #define PACKET3_ONE_REG_WRITE 0x57
724 #define PACKET3_SET_CONFIG_REG 0x68
725 #define PACKET3_SET_CONFIG_REG_START 0x00008000
726 #define PACKET3_SET_CONFIG_REG_END 0x0000ac00
727 #define PACKET3_SET_CONTEXT_REG 0x69
728 #define PACKET3_SET_CONTEXT_REG_START 0x00028000
729 #define PACKET3_SET_CONTEXT_REG_END 0x00029000
730 #define PACKET3_SET_ALU_CONST 0x6A
731 /* alu const buffers only; no reg file */
732 #define PACKET3_SET_BOOL_CONST 0x6B
733 #define PACKET3_SET_BOOL_CONST_START 0x0003a500
734 #define PACKET3_SET_BOOL_CONST_END 0x0003a518
735 #define PACKET3_SET_LOOP_CONST 0x6C
736 #define PACKET3_SET_LOOP_CONST_START 0x0003a200
737 #define PACKET3_SET_LOOP_CONST_END 0x0003a500
738 #define PACKET3_SET_RESOURCE 0x6D
739 #define PACKET3_SET_RESOURCE_START 0x00030000
740 #define PACKET3_SET_RESOURCE_END 0x00038000
741 #define PACKET3_SET_SAMPLER 0x6E
742 #define PACKET3_SET_SAMPLER_START 0x0003c000
743 #define PACKET3_SET_SAMPLER_END 0x0003c600
744 #define PACKET3_SET_CTL_CONST 0x6F
745 #define PACKET3_SET_CTL_CONST_START 0x0003cff0
746 #define PACKET3_SET_CTL_CONST_END 0x0003ff0c
747 #define PACKET3_SET_RESOURCE_OFFSET 0x70
748 #define PACKET3_SET_ALU_CONST_VS 0x71
749 #define PACKET3_SET_ALU_CONST_DI 0x72
750 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
751 #define PACKET3_SET_RESOURCE_INDIRECT 0x74
752 #define PACKET3_SET_APPEND_CNT 0x75
754 #define SQ_RESOURCE_CONSTANT_WORD7_0 0x3001c
755 #define S__SQ_CONSTANT_TYPE(x) (((x) & 3) << 30)
756 #define G__SQ_CONSTANT_TYPE(x) (((x) >> 30) & 3)
757 #define SQ_TEX_VTX_INVALID_TEXTURE 0x0
758 #define SQ_TEX_VTX_INVALID_BUFFER 0x1
759 #define SQ_TEX_VTX_VALID_TEXTURE 0x2
760 #define SQ_TEX_VTX_VALID_BUFFER 0x3
762 #define SQ_CONST_MEM_BASE 0x8df8
764 #define SQ_ESGS_RING_BASE 0x8c40
765 #define SQ_ESGS_RING_SIZE 0x8c44
766 #define SQ_GSVS_RING_BASE 0x8c48
767 #define SQ_GSVS_RING_SIZE 0x8c4c
768 #define SQ_ESTMP_RING_BASE 0x8c50
769 #define SQ_ESTMP_RING_SIZE 0x8c54
770 #define SQ_GSTMP_RING_BASE 0x8c58
771 #define SQ_GSTMP_RING_SIZE 0x8c5c
772 #define SQ_VSTMP_RING_BASE 0x8c60
773 #define SQ_VSTMP_RING_SIZE 0x8c64
774 #define SQ_PSTMP_RING_BASE 0x8c68
775 #define SQ_PSTMP_RING_SIZE 0x8c6c
776 #define SQ_LSTMP_RING_BASE 0x8e10
777 #define SQ_LSTMP_RING_SIZE 0x8e14
778 #define SQ_HSTMP_RING_BASE 0x8e18
779 #define SQ_HSTMP_RING_SIZE 0x8e1c
780 #define VGT_TF_RING_SIZE 0x8988
782 #define SQ_ESGS_RING_ITEMSIZE 0x28900
783 #define SQ_GSVS_RING_ITEMSIZE 0x28904
784 #define SQ_ESTMP_RING_ITEMSIZE 0x28908
785 #define SQ_GSTMP_RING_ITEMSIZE 0x2890c
786 #define SQ_VSTMP_RING_ITEMSIZE 0x28910
787 #define SQ_PSTMP_RING_ITEMSIZE 0x28914
788 #define SQ_LSTMP_RING_ITEMSIZE 0x28830
789 #define SQ_HSTMP_RING_ITEMSIZE 0x28834
791 #define SQ_GS_VERT_ITEMSIZE 0x2891c
792 #define SQ_GS_VERT_ITEMSIZE_1 0x28920
793 #define SQ_GS_VERT_ITEMSIZE_2 0x28924
794 #define SQ_GS_VERT_ITEMSIZE_3 0x28928
795 #define SQ_GSVS_RING_OFFSET_1 0x2892c
796 #define SQ_GSVS_RING_OFFSET_2 0x28930
797 #define SQ_GSVS_RING_OFFSET_3 0x28934
799 #define SQ_ALU_CONST_BUFFER_SIZE_PS_0 0x28140
800 #define SQ_ALU_CONST_BUFFER_SIZE_HS_0 0x28f80
802 #define SQ_ALU_CONST_CACHE_PS_0 0x28940
803 #define SQ_ALU_CONST_CACHE_PS_1 0x28944
804 #define SQ_ALU_CONST_CACHE_PS_2 0x28948
805 #define SQ_ALU_CONST_CACHE_PS_3 0x2894c
806 #define SQ_ALU_CONST_CACHE_PS_4 0x28950
807 #define SQ_ALU_CONST_CACHE_PS_5 0x28954
808 #define SQ_ALU_CONST_CACHE_PS_6 0x28958
809 #define SQ_ALU_CONST_CACHE_PS_7 0x2895c
810 #define SQ_ALU_CONST_CACHE_PS_8 0x28960
811 #define SQ_ALU_CONST_CACHE_PS_9 0x28964
812 #define SQ_ALU_CONST_CACHE_PS_10 0x28968
813 #define SQ_ALU_CONST_CACHE_PS_11 0x2896c
814 #define SQ_ALU_CONST_CACHE_PS_12 0x28970
815 #define SQ_ALU_CONST_CACHE_PS_13 0x28974
816 #define SQ_ALU_CONST_CACHE_PS_14 0x28978
817 #define SQ_ALU_CONST_CACHE_PS_15 0x2897c
818 #define SQ_ALU_CONST_CACHE_VS_0 0x28980
819 #define SQ_ALU_CONST_CACHE_VS_1 0x28984
820 #define SQ_ALU_CONST_CACHE_VS_2 0x28988
821 #define SQ_ALU_CONST_CACHE_VS_3 0x2898c
822 #define SQ_ALU_CONST_CACHE_VS_4 0x28990
823 #define SQ_ALU_CONST_CACHE_VS_5 0x28994
824 #define SQ_ALU_CONST_CACHE_VS_6 0x28998
825 #define SQ_ALU_CONST_CACHE_VS_7 0x2899c
826 #define SQ_ALU_CONST_CACHE_VS_8 0x289a0
827 #define SQ_ALU_CONST_CACHE_VS_9 0x289a4
828 #define SQ_ALU_CONST_CACHE_VS_10 0x289a8
829 #define SQ_ALU_CONST_CACHE_VS_11 0x289ac
830 #define SQ_ALU_CONST_CACHE_VS_12 0x289b0
831 #define SQ_ALU_CONST_CACHE_VS_13 0x289b4
832 #define SQ_ALU_CONST_CACHE_VS_14 0x289b8
833 #define SQ_ALU_CONST_CACHE_VS_15 0x289bc
834 #define SQ_ALU_CONST_CACHE_GS_0 0x289c0
835 #define SQ_ALU_CONST_CACHE_GS_1 0x289c4
836 #define SQ_ALU_CONST_CACHE_GS_2 0x289c8
837 #define SQ_ALU_CONST_CACHE_GS_3 0x289cc
838 #define SQ_ALU_CONST_CACHE_GS_4 0x289d0
839 #define SQ_ALU_CONST_CACHE_GS_5 0x289d4
840 #define SQ_ALU_CONST_CACHE_GS_6 0x289d8
841 #define SQ_ALU_CONST_CACHE_GS_7 0x289dc
842 #define SQ_ALU_CONST_CACHE_GS_8 0x289e0
843 #define SQ_ALU_CONST_CACHE_GS_9 0x289e4
844 #define SQ_ALU_CONST_CACHE_GS_10 0x289e8
845 #define SQ_ALU_CONST_CACHE_GS_11 0x289ec
846 #define SQ_ALU_CONST_CACHE_GS_12 0x289f0
847 #define SQ_ALU_CONST_CACHE_GS_13 0x289f4
848 #define SQ_ALU_CONST_CACHE_GS_14 0x289f8
849 #define SQ_ALU_CONST_CACHE_GS_15 0x289fc
850 #define SQ_ALU_CONST_CACHE_HS_0 0x28f00
851 #define SQ_ALU_CONST_CACHE_HS_1 0x28f04
852 #define SQ_ALU_CONST_CACHE_HS_2 0x28f08
853 #define SQ_ALU_CONST_CACHE_HS_3 0x28f0c
854 #define SQ_ALU_CONST_CACHE_HS_4 0x28f10
855 #define SQ_ALU_CONST_CACHE_HS_5 0x28f14
856 #define SQ_ALU_CONST_CACHE_HS_6 0x28f18
857 #define SQ_ALU_CONST_CACHE_HS_7 0x28f1c
858 #define SQ_ALU_CONST_CACHE_HS_8 0x28f20
859 #define SQ_ALU_CONST_CACHE_HS_9 0x28f24
860 #define SQ_ALU_CONST_CACHE_HS_10 0x28f28
861 #define SQ_ALU_CONST_CACHE_HS_11 0x28f2c
862 #define SQ_ALU_CONST_CACHE_HS_12 0x28f30
863 #define SQ_ALU_CONST_CACHE_HS_13 0x28f34
864 #define SQ_ALU_CONST_CACHE_HS_14 0x28f38
865 #define SQ_ALU_CONST_CACHE_HS_15 0x28f3c
866 #define SQ_ALU_CONST_CACHE_LS_0 0x28f40
867 #define SQ_ALU_CONST_CACHE_LS_1 0x28f44
868 #define SQ_ALU_CONST_CACHE_LS_2 0x28f48
869 #define SQ_ALU_CONST_CACHE_LS_3 0x28f4c
870 #define SQ_ALU_CONST_CACHE_LS_4 0x28f50
871 #define SQ_ALU_CONST_CACHE_LS_5 0x28f54
872 #define SQ_ALU_CONST_CACHE_LS_6 0x28f58
873 #define SQ_ALU_CONST_CACHE_LS_7 0x28f5c
874 #define SQ_ALU_CONST_CACHE_LS_8 0x28f60
875 #define SQ_ALU_CONST_CACHE_LS_9 0x28f64
876 #define SQ_ALU_CONST_CACHE_LS_10 0x28f68
877 #define SQ_ALU_CONST_CACHE_LS_11 0x28f6c
878 #define SQ_ALU_CONST_CACHE_LS_12 0x28f70
879 #define SQ_ALU_CONST_CACHE_LS_13 0x28f74
880 #define SQ_ALU_CONST_CACHE_LS_14 0x28f78
881 #define SQ_ALU_CONST_CACHE_LS_15 0x28f7c
883 #define PA_SC_SCREEN_SCISSOR_TL 0x28030
884 #define PA_SC_GENERIC_SCISSOR_TL 0x28240
885 #define PA_SC_WINDOW_SCISSOR_TL 0x28204
886 #define VGT_PRIMITIVE_TYPE 0x8958
888 #define DB_DEPTH_CONTROL 0x28800
889 #define DB_DEPTH_VIEW 0x28008
890 #define DB_HTILE_DATA_BASE 0x28014
891 #define DB_Z_INFO 0x28040
892 # define Z_ARRAY_MODE(x) ((x) << 4)
893 #define DB_STENCIL_INFO 0x28044
894 #define DB_Z_READ_BASE 0x28048
895 #define DB_STENCIL_READ_BASE 0x2804c
896 #define DB_Z_WRITE_BASE 0x28050
897 #define DB_STENCIL_WRITE_BASE 0x28054
898 #define DB_DEPTH_SIZE 0x28058
900 #define SQ_PGM_START_PS 0x28840
901 #define SQ_PGM_START_VS 0x2885c
902 #define SQ_PGM_START_GS 0x28874
903 #define SQ_PGM_START_ES 0x2888c
904 #define SQ_PGM_START_FS 0x288a4
905 #define SQ_PGM_START_HS 0x288b8
906 #define SQ_PGM_START_LS 0x288d0
908 #define VGT_STRMOUT_CONFIG 0x28b94
909 #define VGT_STRMOUT_BUFFER_CONFIG 0x28b98
911 #define CB_TARGET_MASK 0x28238
912 #define CB_SHADER_MASK 0x2823c
914 #define GDS_ADDR_BASE 0x28720
916 #define CB_IMMED0_BASE 0x28b9c
917 #define CB_IMMED1_BASE 0x28ba0
918 #define CB_IMMED2_BASE 0x28ba4
919 #define CB_IMMED3_BASE 0x28ba8
920 #define CB_IMMED4_BASE 0x28bac
921 #define CB_IMMED5_BASE 0x28bb0
922 #define CB_IMMED6_BASE 0x28bb4
923 #define CB_IMMED7_BASE 0x28bb8
924 #define CB_IMMED8_BASE 0x28bbc
925 #define CB_IMMED9_BASE 0x28bc0
926 #define CB_IMMED10_BASE 0x28bc4
927 #define CB_IMMED11_BASE 0x28bc8
929 /* all 12 CB blocks have these regs */
930 #define CB_COLOR0_BASE 0x28c60
931 #define CB_COLOR0_PITCH 0x28c64
932 #define CB_COLOR0_SLICE 0x28c68
933 #define CB_COLOR0_VIEW 0x28c6c
934 #define CB_COLOR0_INFO 0x28c70
935 # define CB_ARRAY_MODE(x) ((x) << 8)
936 # define ARRAY_LINEAR_GENERAL 0
937 # define ARRAY_LINEAR_ALIGNED 1
938 # define ARRAY_1D_TILED_THIN1 2
939 # define ARRAY_2D_TILED_THIN1 4
940 #define CB_COLOR0_ATTRIB 0x28c74
941 #define CB_COLOR0_DIM 0x28c78
942 /* only CB0-7 blocks have these regs */
943 #define CB_COLOR0_CMASK 0x28c7c
944 #define CB_COLOR0_CMASK_SLICE 0x28c80
945 #define CB_COLOR0_FMASK 0x28c84
946 #define CB_COLOR0_FMASK_SLICE 0x28c88
947 #define CB_COLOR0_CLEAR_WORD0 0x28c8c
948 #define CB_COLOR0_CLEAR_WORD1 0x28c90
949 #define CB_COLOR0_CLEAR_WORD2 0x28c94
950 #define CB_COLOR0_CLEAR_WORD3 0x28c98
952 #define CB_COLOR1_BASE 0x28c9c
953 #define CB_COLOR2_BASE 0x28cd8
954 #define CB_COLOR3_BASE 0x28d14
955 #define CB_COLOR4_BASE 0x28d50
956 #define CB_COLOR5_BASE 0x28d8c
957 #define CB_COLOR6_BASE 0x28dc8
958 #define CB_COLOR7_BASE 0x28e04
959 #define CB_COLOR8_BASE 0x28e40
960 #define CB_COLOR9_BASE 0x28e5c
961 #define CB_COLOR10_BASE 0x28e78
962 #define CB_COLOR11_BASE 0x28e94
964 #define CB_COLOR1_PITCH 0x28ca0
965 #define CB_COLOR2_PITCH 0x28cdc
966 #define CB_COLOR3_PITCH 0x28d18
967 #define CB_COLOR4_PITCH 0x28d54
968 #define CB_COLOR5_PITCH 0x28d90
969 #define CB_COLOR6_PITCH 0x28dcc
970 #define CB_COLOR7_PITCH 0x28e08
971 #define CB_COLOR8_PITCH 0x28e44
972 #define CB_COLOR9_PITCH 0x28e60
973 #define CB_COLOR10_PITCH 0x28e7c
974 #define CB_COLOR11_PITCH 0x28e98
976 #define CB_COLOR1_SLICE 0x28ca4
977 #define CB_COLOR2_SLICE 0x28ce0
978 #define CB_COLOR3_SLICE 0x28d1c
979 #define CB_COLOR4_SLICE 0x28d58
980 #define CB_COLOR5_SLICE 0x28d94
981 #define CB_COLOR6_SLICE 0x28dd0
982 #define CB_COLOR7_SLICE 0x28e0c
983 #define CB_COLOR8_SLICE 0x28e48
984 #define CB_COLOR9_SLICE 0x28e64
985 #define CB_COLOR10_SLICE 0x28e80
986 #define CB_COLOR11_SLICE 0x28e9c
988 #define CB_COLOR1_VIEW 0x28ca8
989 #define CB_COLOR2_VIEW 0x28ce4
990 #define CB_COLOR3_VIEW 0x28d20
991 #define CB_COLOR4_VIEW 0x28d5c
992 #define CB_COLOR5_VIEW 0x28d98
993 #define CB_COLOR6_VIEW 0x28dd4
994 #define CB_COLOR7_VIEW 0x28e10
995 #define CB_COLOR8_VIEW 0x28e4c
996 #define CB_COLOR9_VIEW 0x28e68
997 #define CB_COLOR10_VIEW 0x28e84
998 #define CB_COLOR11_VIEW 0x28ea0
1000 #define CB_COLOR1_INFO 0x28cac
1001 #define CB_COLOR2_INFO 0x28ce8
1002 #define CB_COLOR3_INFO 0x28d24
1003 #define CB_COLOR4_INFO 0x28d60
1004 #define CB_COLOR5_INFO 0x28d9c
1005 #define CB_COLOR6_INFO 0x28dd8
1006 #define CB_COLOR7_INFO 0x28e14
1007 #define CB_COLOR8_INFO 0x28e50
1008 #define CB_COLOR9_INFO 0x28e6c
1009 #define CB_COLOR10_INFO 0x28e88
1010 #define CB_COLOR11_INFO 0x28ea4
1012 #define CB_COLOR1_ATTRIB 0x28cb0
1013 #define CB_COLOR2_ATTRIB 0x28cec
1014 #define CB_COLOR3_ATTRIB 0x28d28
1015 #define CB_COLOR4_ATTRIB 0x28d64
1016 #define CB_COLOR5_ATTRIB 0x28da0
1017 #define CB_COLOR6_ATTRIB 0x28ddc
1018 #define CB_COLOR7_ATTRIB 0x28e18
1019 #define CB_COLOR8_ATTRIB 0x28e54
1020 #define CB_COLOR9_ATTRIB 0x28e70
1021 #define CB_COLOR10_ATTRIB 0x28e8c
1022 #define CB_COLOR11_ATTRIB 0x28ea8
1024 #define CB_COLOR1_DIM 0x28cb4
1025 #define CB_COLOR2_DIM 0x28cf0
1026 #define CB_COLOR3_DIM 0x28d2c
1027 #define CB_COLOR4_DIM 0x28d68
1028 #define CB_COLOR5_DIM 0x28da4
1029 #define CB_COLOR6_DIM 0x28de0
1030 #define CB_COLOR7_DIM 0x28e1c
1031 #define CB_COLOR8_DIM 0x28e58
1032 #define CB_COLOR9_DIM 0x28e74
1033 #define CB_COLOR10_DIM 0x28e90
1034 #define CB_COLOR11_DIM 0x28eac
1036 #define CB_COLOR1_CMASK 0x28cb8
1037 #define CB_COLOR2_CMASK 0x28cf4
1038 #define CB_COLOR3_CMASK 0x28d30
1039 #define CB_COLOR4_CMASK 0x28d6c
1040 #define CB_COLOR5_CMASK 0x28da8
1041 #define CB_COLOR6_CMASK 0x28de4
1042 #define CB_COLOR7_CMASK 0x28e20
1044 #define CB_COLOR1_CMASK_SLICE 0x28cbc
1045 #define CB_COLOR2_CMASK_SLICE 0x28cf8
1046 #define CB_COLOR3_CMASK_SLICE 0x28d34
1047 #define CB_COLOR4_CMASK_SLICE 0x28d70
1048 #define CB_COLOR5_CMASK_SLICE 0x28dac
1049 #define CB_COLOR6_CMASK_SLICE 0x28de8
1050 #define CB_COLOR7_CMASK_SLICE 0x28e24
1052 #define CB_COLOR1_FMASK 0x28cc0
1053 #define CB_COLOR2_FMASK 0x28cfc
1054 #define CB_COLOR3_FMASK 0x28d38
1055 #define CB_COLOR4_FMASK 0x28d74
1056 #define CB_COLOR5_FMASK 0x28db0
1057 #define CB_COLOR6_FMASK 0x28dec
1058 #define CB_COLOR7_FMASK 0x28e28
1060 #define CB_COLOR1_FMASK_SLICE 0x28cc4
1061 #define CB_COLOR2_FMASK_SLICE 0x28d00
1062 #define CB_COLOR3_FMASK_SLICE 0x28d3c
1063 #define CB_COLOR4_FMASK_SLICE 0x28d78
1064 #define CB_COLOR5_FMASK_SLICE 0x28db4
1065 #define CB_COLOR6_FMASK_SLICE 0x28df0
1066 #define CB_COLOR7_FMASK_SLICE 0x28e2c
1068 #define CB_COLOR1_CLEAR_WORD0 0x28cc8
1069 #define CB_COLOR2_CLEAR_WORD0 0x28d04
1070 #define CB_COLOR3_CLEAR_WORD0 0x28d40
1071 #define CB_COLOR4_CLEAR_WORD0 0x28d7c
1072 #define CB_COLOR5_CLEAR_WORD0 0x28db8
1073 #define CB_COLOR6_CLEAR_WORD0 0x28df4
1074 #define CB_COLOR7_CLEAR_WORD0 0x28e30
1076 #define CB_COLOR1_CLEAR_WORD1 0x28ccc
1077 #define CB_COLOR2_CLEAR_WORD1 0x28d08
1078 #define CB_COLOR3_CLEAR_WORD1 0x28d44
1079 #define CB_COLOR4_CLEAR_WORD1 0x28d80
1080 #define CB_COLOR5_CLEAR_WORD1 0x28dbc
1081 #define CB_COLOR6_CLEAR_WORD1 0x28df8
1082 #define CB_COLOR7_CLEAR_WORD1 0x28e34
1084 #define CB_COLOR1_CLEAR_WORD2 0x28cd0
1085 #define CB_COLOR2_CLEAR_WORD2 0x28d0c
1086 #define CB_COLOR3_CLEAR_WORD2 0x28d48
1087 #define CB_COLOR4_CLEAR_WORD2 0x28d84
1088 #define CB_COLOR5_CLEAR_WORD2 0x28dc0
1089 #define CB_COLOR6_CLEAR_WORD2 0x28dfc
1090 #define CB_COLOR7_CLEAR_WORD2 0x28e38
1092 #define CB_COLOR1_CLEAR_WORD3 0x28cd4
1093 #define CB_COLOR2_CLEAR_WORD3 0x28d10
1094 #define CB_COLOR3_CLEAR_WORD3 0x28d4c
1095 #define CB_COLOR4_CLEAR_WORD3 0x28d88
1096 #define CB_COLOR5_CLEAR_WORD3 0x28dc4
1097 #define CB_COLOR6_CLEAR_WORD3 0x28e00
1098 #define CB_COLOR7_CLEAR_WORD3 0x28e3c
1100 #define SQ_TEX_RESOURCE_WORD0_0 0x30000
1101 #define SQ_TEX_RESOURCE_WORD1_0 0x30004
1102 # define TEX_ARRAY_MODE(x) ((x) << 28)
1103 #define SQ_TEX_RESOURCE_WORD2_0 0x30008
1104 #define SQ_TEX_RESOURCE_WORD3_0 0x3000C
1105 #define SQ_TEX_RESOURCE_WORD4_0 0x30010
1106 #define SQ_TEX_RESOURCE_WORD5_0 0x30014
1107 #define SQ_TEX_RESOURCE_WORD6_0 0x30018
1108 #define SQ_TEX_RESOURCE_WORD7_0 0x3001c
1110 /* cayman 3D regs */
1111 #define CAYMAN_VGT_OFFCHIP_LDS_BASE 0x89B0
1112 #define CAYMAN_DB_EQAA 0x28804
1113 #define CAYMAN_DB_DEPTH_INFO 0x2803C
1114 #define CAYMAN_PA_SC_AA_CONFIG 0x28BE0
1115 #define CAYMAN_MSAA_NUM_SAMPLES_SHIFT 0
1116 #define CAYMAN_MSAA_NUM_SAMPLES_MASK 0x7
1117 /* cayman packet3 addition */
1118 #define CAYMAN_PACKET3_DEALLOC_STATE 0x14
Code Review / linux-2.6.git / blob