drm/radeon: add support for evergreen/ni tiling informations v11
[linux-2.6.git] / drivers / gpu / drm / radeon / evergreend.h
1 /*
2  * Copyright 2010 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Alex Deucher
23  */
24 #ifndef EVERGREEND_H
25 #define EVERGREEND_H
26
27 #define EVERGREEN_MAX_SH_GPRS           256
28 #define EVERGREEN_MAX_TEMP_GPRS         16
29 #define EVERGREEN_MAX_SH_THREADS        256
30 #define EVERGREEN_MAX_SH_STACK_ENTRIES  4096
31 #define EVERGREEN_MAX_FRC_EOV_CNT       16384
32 #define EVERGREEN_MAX_BACKENDS          8
33 #define EVERGREEN_MAX_BACKENDS_MASK     0xFF
34 #define EVERGREEN_MAX_SIMDS             16
35 #define EVERGREEN_MAX_SIMDS_MASK        0xFFFF
36 #define EVERGREEN_MAX_PIPES             8
37 #define EVERGREEN_MAX_PIPES_MASK        0xFF
38 #define EVERGREEN_MAX_LDS_NUM           0xFFFF
39
40 /* Registers */
41
42 #define RCU_IND_INDEX                                   0x100
43 #define RCU_IND_DATA                                    0x104
44
45 #define GRBM_GFX_INDEX                                  0x802C
46 #define         INSTANCE_INDEX(x)                       ((x) << 0)
47 #define         SE_INDEX(x)                             ((x) << 16)
48 #define         INSTANCE_BROADCAST_WRITES               (1 << 30)
49 #define         SE_BROADCAST_WRITES                     (1 << 31)
50 #define RLC_GFX_INDEX                                   0x3fC4
51 #define CC_GC_SHADER_PIPE_CONFIG                        0x8950
52 #define         WRITE_DIS                               (1 << 0)
53 #define CC_RB_BACKEND_DISABLE                           0x98F4
54 #define         BACKEND_DISABLE(x)                      ((x) << 16)
55 #define GB_ADDR_CONFIG                                  0x98F8
56 #define         NUM_PIPES(x)                            ((x) << 0)
57 #define         PIPE_INTERLEAVE_SIZE(x)                 ((x) << 4)
58 #define         BANK_INTERLEAVE_SIZE(x)                 ((x) << 8)
59 #define         NUM_SHADER_ENGINES(x)                   ((x) << 12)
60 #define         SHADER_ENGINE_TILE_SIZE(x)              ((x) << 16)
61 #define         NUM_GPUS(x)                             ((x) << 20)
62 #define         MULTI_GPU_TILE_SIZE(x)                  ((x) << 24)
63 #define         ROW_SIZE(x)                             ((x) << 28)
64 #define GB_BACKEND_MAP                                  0x98FC
65 #define DMIF_ADDR_CONFIG                                0xBD4
66 #define HDP_ADDR_CONFIG                                 0x2F48
67 #define HDP_MISC_CNTL                                   0x2F4C
68 #define         HDP_FLUSH_INVALIDATE_CACHE              (1 << 0)
69
70 #define CC_SYS_RB_BACKEND_DISABLE                       0x3F88
71 #define GC_USER_RB_BACKEND_DISABLE                      0x9B7C
72
73 #define CGTS_SYS_TCC_DISABLE                            0x3F90
74 #define CGTS_TCC_DISABLE                                0x9148
75 #define CGTS_USER_SYS_TCC_DISABLE                       0x3F94
76 #define CGTS_USER_TCC_DISABLE                           0x914C
77
78 #define CONFIG_MEMSIZE                                  0x5428
79
80 #define CP_COHER_BASE                                   0x85F8
81 #define CP_ME_CNTL                                      0x86D8
82 #define         CP_ME_HALT                                      (1 << 28)
83 #define         CP_PFP_HALT                                     (1 << 26)
84 #define CP_ME_RAM_DATA                                  0xC160
85 #define CP_ME_RAM_RADDR                                 0xC158
86 #define CP_ME_RAM_WADDR                                 0xC15C
87 #define CP_MEQ_THRESHOLDS                               0x8764
88 #define         STQ_SPLIT(x)                                    ((x) << 0)
89 #define CP_PERFMON_CNTL                                 0x87FC
90 #define CP_PFP_UCODE_ADDR                               0xC150
91 #define CP_PFP_UCODE_DATA                               0xC154
92 #define CP_QUEUE_THRESHOLDS                             0x8760
93 #define         ROQ_IB1_START(x)                                ((x) << 0)
94 #define         ROQ_IB2_START(x)                                ((x) << 8)
95 #define CP_RB_BASE                                      0xC100
96 #define CP_RB_CNTL                                      0xC104
97 #define         RB_BUFSZ(x)                                     ((x) << 0)
98 #define         RB_BLKSZ(x)                                     ((x) << 8)
99 #define         RB_NO_UPDATE                                    (1 << 27)
100 #define         RB_RPTR_WR_ENA                                  (1 << 31)
101 #define         BUF_SWAP_32BIT                                  (2 << 16)
102 #define CP_RB_RPTR                                      0x8700
103 #define CP_RB_RPTR_ADDR                                 0xC10C
104 #define         RB_RPTR_SWAP(x)                                 ((x) << 0)
105 #define CP_RB_RPTR_ADDR_HI                              0xC110
106 #define CP_RB_RPTR_WR                                   0xC108
107 #define CP_RB_WPTR                                      0xC114
108 #define CP_RB_WPTR_ADDR                                 0xC118
109 #define CP_RB_WPTR_ADDR_HI                              0xC11C
110 #define CP_RB_WPTR_DELAY                                0x8704
111 #define CP_SEM_WAIT_TIMER                               0x85BC
112 #define CP_SEM_INCOMPLETE_TIMER_CNTL                    0x85C8
113 #define CP_DEBUG                                        0xC1FC
114
115
116 #define GC_USER_SHADER_PIPE_CONFIG                      0x8954
117 #define         INACTIVE_QD_PIPES(x)                            ((x) << 8)
118 #define         INACTIVE_QD_PIPES_MASK                          0x0000FF00
119 #define         INACTIVE_SIMDS(x)                               ((x) << 16)
120 #define         INACTIVE_SIMDS_MASK                             0x00FF0000
121
122 #define GRBM_CNTL                                       0x8000
123 #define         GRBM_READ_TIMEOUT(x)                            ((x) << 0)
124 #define GRBM_SOFT_RESET                                 0x8020
125 #define         SOFT_RESET_CP                                   (1 << 0)
126 #define         SOFT_RESET_CB                                   (1 << 1)
127 #define         SOFT_RESET_DB                                   (1 << 3)
128 #define         SOFT_RESET_PA                                   (1 << 5)
129 #define         SOFT_RESET_SC                                   (1 << 6)
130 #define         SOFT_RESET_SPI                                  (1 << 8)
131 #define         SOFT_RESET_SH                                   (1 << 9)
132 #define         SOFT_RESET_SX                                   (1 << 10)
133 #define         SOFT_RESET_TC                                   (1 << 11)
134 #define         SOFT_RESET_TA                                   (1 << 12)
135 #define         SOFT_RESET_VC                                   (1 << 13)
136 #define         SOFT_RESET_VGT                                  (1 << 14)
137
138 #define GRBM_STATUS                                     0x8010
139 #define         CMDFIFO_AVAIL_MASK                              0x0000000F
140 #define         SRBM_RQ_PENDING                                 (1 << 5)
141 #define         CF_RQ_PENDING                                   (1 << 7)
142 #define         PF_RQ_PENDING                                   (1 << 8)
143 #define         GRBM_EE_BUSY                                    (1 << 10)
144 #define         SX_CLEAN                                        (1 << 11)
145 #define         DB_CLEAN                                        (1 << 12)
146 #define         CB_CLEAN                                        (1 << 13)
147 #define         TA_BUSY                                         (1 << 14)
148 #define         VGT_BUSY_NO_DMA                                 (1 << 16)
149 #define         VGT_BUSY                                        (1 << 17)
150 #define         SX_BUSY                                         (1 << 20)
151 #define         SH_BUSY                                         (1 << 21)
152 #define         SPI_BUSY                                        (1 << 22)
153 #define         SC_BUSY                                         (1 << 24)
154 #define         PA_BUSY                                         (1 << 25)
155 #define         DB_BUSY                                         (1 << 26)
156 #define         CP_COHERENCY_BUSY                               (1 << 28)
157 #define         CP_BUSY                                         (1 << 29)
158 #define         CB_BUSY                                         (1 << 30)
159 #define         GUI_ACTIVE                                      (1 << 31)
160 #define GRBM_STATUS_SE0                                 0x8014
161 #define GRBM_STATUS_SE1                                 0x8018
162 #define         SE_SX_CLEAN                                     (1 << 0)
163 #define         SE_DB_CLEAN                                     (1 << 1)
164 #define         SE_CB_CLEAN                                     (1 << 2)
165 #define         SE_TA_BUSY                                      (1 << 25)
166 #define         SE_SX_BUSY                                      (1 << 26)
167 #define         SE_SPI_BUSY                                     (1 << 27)
168 #define         SE_SH_BUSY                                      (1 << 28)
169 #define         SE_SC_BUSY                                      (1 << 29)
170 #define         SE_DB_BUSY                                      (1 << 30)
171 #define         SE_CB_BUSY                                      (1 << 31)
172 /* evergreen */
173 #define CG_THERMAL_CTRL                                 0x72c
174 #define         TOFFSET_MASK                            0x00003FE0
175 #define         TOFFSET_SHIFT                           5
176 #define CG_MULT_THERMAL_STATUS                          0x740
177 #define         ASIC_T(x)                               ((x) << 16)
178 #define         ASIC_T_MASK                             0x07FF0000
179 #define         ASIC_T_SHIFT                            16
180 #define CG_TS0_STATUS                                   0x760
181 #define         TS0_ADC_DOUT_MASK                       0x000003FF
182 #define         TS0_ADC_DOUT_SHIFT                      0
183 /* APU */
184 #define CG_THERMAL_STATUS                               0x678
185
186 #define HDP_HOST_PATH_CNTL                              0x2C00
187 #define HDP_NONSURFACE_BASE                             0x2C04
188 #define HDP_NONSURFACE_INFO                             0x2C08
189 #define HDP_NONSURFACE_SIZE                             0x2C0C
190 #define HDP_MEM_COHERENCY_FLUSH_CNTL                    0x5480
191 #define HDP_REG_COHERENCY_FLUSH_CNTL                    0x54A0
192 #define HDP_TILING_CONFIG                               0x2F3C
193
194 #define MC_SHARED_CHMAP                                         0x2004
195 #define         NOOFCHAN_SHIFT                                  12
196 #define         NOOFCHAN_MASK                                   0x00003000
197 #define MC_SHARED_CHREMAP                                       0x2008
198
199 #define MC_ARB_RAMCFG                                   0x2760
200 #define         NOOFBANK_SHIFT                                  0
201 #define         NOOFBANK_MASK                                   0x00000003
202 #define         NOOFRANK_SHIFT                                  2
203 #define         NOOFRANK_MASK                                   0x00000004
204 #define         NOOFROWS_SHIFT                                  3
205 #define         NOOFROWS_MASK                                   0x00000038
206 #define         NOOFCOLS_SHIFT                                  6
207 #define         NOOFCOLS_MASK                                   0x000000C0
208 #define         CHANSIZE_SHIFT                                  8
209 #define         CHANSIZE_MASK                                   0x00000100
210 #define         BURSTLENGTH_SHIFT                               9
211 #define         BURSTLENGTH_MASK                                0x00000200
212 #define         CHANSIZE_OVERRIDE                               (1 << 11)
213 #define FUS_MC_ARB_RAMCFG                               0x2768
214 #define MC_VM_AGP_TOP                                   0x2028
215 #define MC_VM_AGP_BOT                                   0x202C
216 #define MC_VM_AGP_BASE                                  0x2030
217 #define MC_VM_FB_LOCATION                               0x2024
218 #define MC_FUS_VM_FB_OFFSET                             0x2898
219 #define MC_VM_MB_L1_TLB0_CNTL                           0x2234
220 #define MC_VM_MB_L1_TLB1_CNTL                           0x2238
221 #define MC_VM_MB_L1_TLB2_CNTL                           0x223C
222 #define MC_VM_MB_L1_TLB3_CNTL                           0x2240
223 #define         ENABLE_L1_TLB                                   (1 << 0)
224 #define         ENABLE_L1_FRAGMENT_PROCESSING                   (1 << 1)
225 #define         SYSTEM_ACCESS_MODE_PA_ONLY                      (0 << 3)
226 #define         SYSTEM_ACCESS_MODE_USE_SYS_MAP                  (1 << 3)
227 #define         SYSTEM_ACCESS_MODE_IN_SYS                       (2 << 3)
228 #define         SYSTEM_ACCESS_MODE_NOT_IN_SYS                   (3 << 3)
229 #define         SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU       (0 << 5)
230 #define         EFFECTIVE_L1_TLB_SIZE(x)                        ((x)<<15)
231 #define         EFFECTIVE_L1_QUEUE_SIZE(x)                      ((x)<<18)
232 #define MC_VM_MD_L1_TLB0_CNTL                           0x2654
233 #define MC_VM_MD_L1_TLB1_CNTL                           0x2658
234 #define MC_VM_MD_L1_TLB2_CNTL                           0x265C
235
236 #define FUS_MC_VM_MD_L1_TLB0_CNTL                       0x265C
237 #define FUS_MC_VM_MD_L1_TLB1_CNTL                       0x2660
238 #define FUS_MC_VM_MD_L1_TLB2_CNTL                       0x2664
239
240 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR              0x203C
241 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR                 0x2038
242 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR                  0x2034
243
244 #define PA_CL_ENHANCE                                   0x8A14
245 #define         CLIP_VTX_REORDER_ENA                            (1 << 0)
246 #define         NUM_CLIP_SEQ(x)                                 ((x) << 1)
247 #define PA_SC_ENHANCE                                   0x8BF0
248 #define PA_SC_AA_CONFIG                                 0x28C04
249 #define         MSAA_NUM_SAMPLES_SHIFT                  0
250 #define         MSAA_NUM_SAMPLES_MASK                   0x3
251 #define PA_SC_CLIPRECT_RULE                             0x2820C
252 #define PA_SC_EDGERULE                                  0x28230
253 #define PA_SC_FIFO_SIZE                                 0x8BCC
254 #define         SC_PRIM_FIFO_SIZE(x)                            ((x) << 0)
255 #define         SC_HIZ_TILE_FIFO_SIZE(x)                        ((x) << 12)
256 #define         SC_EARLYZ_TILE_FIFO_SIZE(x)                     ((x) << 20)
257 #define PA_SC_FORCE_EOV_MAX_CNTS                        0x8B24
258 #define         FORCE_EOV_MAX_CLK_CNT(x)                        ((x) << 0)
259 #define         FORCE_EOV_MAX_REZ_CNT(x)                        ((x) << 16)
260 #define PA_SC_LINE_STIPPLE                              0x28A0C
261 #define PA_SU_LINE_STIPPLE_VALUE                        0x8A60
262 #define PA_SC_LINE_STIPPLE_STATE                        0x8B10
263
264 #define SCRATCH_REG0                                    0x8500
265 #define SCRATCH_REG1                                    0x8504
266 #define SCRATCH_REG2                                    0x8508
267 #define SCRATCH_REG3                                    0x850C
268 #define SCRATCH_REG4                                    0x8510
269 #define SCRATCH_REG5                                    0x8514
270 #define SCRATCH_REG6                                    0x8518
271 #define SCRATCH_REG7                                    0x851C
272 #define SCRATCH_UMSK                                    0x8540
273 #define SCRATCH_ADDR                                    0x8544
274
275 #define SMX_DC_CTL0                                     0xA020
276 #define         USE_HASH_FUNCTION                               (1 << 0)
277 #define         NUMBER_OF_SETS(x)                               ((x) << 1)
278 #define         FLUSH_ALL_ON_EVENT                              (1 << 10)
279 #define         STALL_ON_EVENT                                  (1 << 11)
280 #define SMX_EVENT_CTL                                   0xA02C
281 #define         ES_FLUSH_CTL(x)                                 ((x) << 0)
282 #define         GS_FLUSH_CTL(x)                                 ((x) << 3)
283 #define         ACK_FLUSH_CTL(x)                                ((x) << 6)
284 #define         SYNC_FLUSH_CTL                                  (1 << 8)
285
286 #define SPI_CONFIG_CNTL                                 0x9100
287 #define         GPR_WRITE_PRIORITY(x)                           ((x) << 0)
288 #define SPI_CONFIG_CNTL_1                               0x913C
289 #define         VTX_DONE_DELAY(x)                               ((x) << 0)
290 #define         INTERP_ONE_PRIM_PER_ROW                         (1 << 4)
291 #define SPI_INPUT_Z                                     0x286D8
292 #define SPI_PS_IN_CONTROL_0                             0x286CC
293 #define         NUM_INTERP(x)                                   ((x)<<0)
294 #define         POSITION_ENA                                    (1<<8)
295 #define         POSITION_CENTROID                               (1<<9)
296 #define         POSITION_ADDR(x)                                ((x)<<10)
297 #define         PARAM_GEN(x)                                    ((x)<<15)
298 #define         PARAM_GEN_ADDR(x)                               ((x)<<19)
299 #define         BARYC_SAMPLE_CNTL(x)                            ((x)<<26)
300 #define         PERSP_GRADIENT_ENA                              (1<<28)
301 #define         LINEAR_GRADIENT_ENA                             (1<<29)
302 #define         POSITION_SAMPLE                                 (1<<30)
303 #define         BARYC_AT_SAMPLE_ENA                             (1<<31)
304
305 #define SQ_CONFIG                                       0x8C00
306 #define         VC_ENABLE                                       (1 << 0)
307 #define         EXPORT_SRC_C                                    (1 << 1)
308 #define         CS_PRIO(x)                                      ((x) << 18)
309 #define         LS_PRIO(x)                                      ((x) << 20)
310 #define         HS_PRIO(x)                                      ((x) << 22)
311 #define         PS_PRIO(x)                                      ((x) << 24)
312 #define         VS_PRIO(x)                                      ((x) << 26)
313 #define         GS_PRIO(x)                                      ((x) << 28)
314 #define         ES_PRIO(x)                                      ((x) << 30)
315 #define SQ_GPR_RESOURCE_MGMT_1                          0x8C04
316 #define         NUM_PS_GPRS(x)                                  ((x) << 0)
317 #define         NUM_VS_GPRS(x)                                  ((x) << 16)
318 #define         NUM_CLAUSE_TEMP_GPRS(x)                         ((x) << 28)
319 #define SQ_GPR_RESOURCE_MGMT_2                          0x8C08
320 #define         NUM_GS_GPRS(x)                                  ((x) << 0)
321 #define         NUM_ES_GPRS(x)                                  ((x) << 16)
322 #define SQ_GPR_RESOURCE_MGMT_3                          0x8C0C
323 #define         NUM_HS_GPRS(x)                                  ((x) << 0)
324 #define         NUM_LS_GPRS(x)                                  ((x) << 16)
325 #define SQ_GLOBAL_GPR_RESOURCE_MGMT_1                   0x8C10
326 #define SQ_GLOBAL_GPR_RESOURCE_MGMT_2                   0x8C14
327 #define SQ_THREAD_RESOURCE_MGMT                         0x8C18
328 #define         NUM_PS_THREADS(x)                               ((x) << 0)
329 #define         NUM_VS_THREADS(x)                               ((x) << 8)
330 #define         NUM_GS_THREADS(x)                               ((x) << 16)
331 #define         NUM_ES_THREADS(x)                               ((x) << 24)
332 #define SQ_THREAD_RESOURCE_MGMT_2                       0x8C1C
333 #define         NUM_HS_THREADS(x)                               ((x) << 0)
334 #define         NUM_LS_THREADS(x)                               ((x) << 8)
335 #define SQ_STACK_RESOURCE_MGMT_1                        0x8C20
336 #define         NUM_PS_STACK_ENTRIES(x)                         ((x) << 0)
337 #define         NUM_VS_STACK_ENTRIES(x)                         ((x) << 16)
338 #define SQ_STACK_RESOURCE_MGMT_2                        0x8C24
339 #define         NUM_GS_STACK_ENTRIES(x)                         ((x) << 0)
340 #define         NUM_ES_STACK_ENTRIES(x)                         ((x) << 16)
341 #define SQ_STACK_RESOURCE_MGMT_3                        0x8C28
342 #define         NUM_HS_STACK_ENTRIES(x)                         ((x) << 0)
343 #define         NUM_LS_STACK_ENTRIES(x)                         ((x) << 16)
344 #define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ                    0x8D8C
345 #define SQ_DYN_GPR_SIMD_LOCK_EN                         0x8D94
346 #define SQ_STATIC_THREAD_MGMT_1                         0x8E20
347 #define SQ_STATIC_THREAD_MGMT_2                         0x8E24
348 #define SQ_STATIC_THREAD_MGMT_3                         0x8E28
349 #define SQ_LDS_RESOURCE_MGMT                            0x8E2C
350
351 #define SQ_MS_FIFO_SIZES                                0x8CF0
352 #define         CACHE_FIFO_SIZE(x)                              ((x) << 0)
353 #define         FETCH_FIFO_HIWATER(x)                           ((x) << 8)
354 #define         DONE_FIFO_HIWATER(x)                            ((x) << 16)
355 #define         ALU_UPDATE_FIFO_HIWATER(x)                      ((x) << 24)
356
357 #define SX_DEBUG_1                                      0x9058
358 #define         ENABLE_NEW_SMX_ADDRESS                          (1 << 16)
359 #define SX_EXPORT_BUFFER_SIZES                          0x900C
360 #define         COLOR_BUFFER_SIZE(x)                            ((x) << 0)
361 #define         POSITION_BUFFER_SIZE(x)                         ((x) << 8)
362 #define         SMX_BUFFER_SIZE(x)                              ((x) << 16)
363 #define SX_MEMORY_EXPORT_BASE                           0x9010
364 #define SX_MISC                                         0x28350
365
366 #define CB_PERF_CTR0_SEL_0                              0x9A20
367 #define CB_PERF_CTR0_SEL_1                              0x9A24
368 #define CB_PERF_CTR1_SEL_0                              0x9A28
369 #define CB_PERF_CTR1_SEL_1                              0x9A2C
370 #define CB_PERF_CTR2_SEL_0                              0x9A30
371 #define CB_PERF_CTR2_SEL_1                              0x9A34
372 #define CB_PERF_CTR3_SEL_0                              0x9A38
373 #define CB_PERF_CTR3_SEL_1                              0x9A3C
374
375 #define TA_CNTL_AUX                                     0x9508
376 #define         DISABLE_CUBE_WRAP                               (1 << 0)
377 #define         DISABLE_CUBE_ANISO                              (1 << 1)
378 #define         SYNC_GRADIENT                                   (1 << 24)
379 #define         SYNC_WALKER                                     (1 << 25)
380 #define         SYNC_ALIGNER                                    (1 << 26)
381
382 #define TCP_CHAN_STEER_LO                               0x960c
383 #define TCP_CHAN_STEER_HI                               0x9610
384
385 #define VGT_CACHE_INVALIDATION                          0x88C4
386 #define         CACHE_INVALIDATION(x)                           ((x) << 0)
387 #define                 VC_ONLY                                         0
388 #define                 TC_ONLY                                         1
389 #define                 VC_AND_TC                                       2
390 #define         AUTO_INVLD_EN(x)                                ((x) << 6)
391 #define                 NO_AUTO                                         0
392 #define                 ES_AUTO                                         1
393 #define                 GS_AUTO                                         2
394 #define                 ES_AND_GS_AUTO                                  3
395 #define VGT_GS_VERTEX_REUSE                             0x88D4
396 #define VGT_NUM_INSTANCES                               0x8974
397 #define VGT_OUT_DEALLOC_CNTL                            0x28C5C
398 #define         DEALLOC_DIST_MASK                               0x0000007F
399 #define VGT_VERTEX_REUSE_BLOCK_CNTL                     0x28C58
400 #define         VTX_REUSE_DEPTH_MASK                            0x000000FF
401
402 #define VM_CONTEXT0_CNTL                                0x1410
403 #define         ENABLE_CONTEXT                                  (1 << 0)
404 #define         PAGE_TABLE_DEPTH(x)                             (((x) & 3) << 1)
405 #define         RANGE_PROTECTION_FAULT_ENABLE_DEFAULT           (1 << 4)
406 #define VM_CONTEXT1_CNTL                                0x1414
407 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR                0x153C
408 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR                 0x157C
409 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR               0x155C
410 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR       0x1518
411 #define VM_CONTEXT0_REQUEST_RESPONSE                    0x1470
412 #define         REQUEST_TYPE(x)                                 (((x) & 0xf) << 0)
413 #define         RESPONSE_TYPE_MASK                              0x000000F0
414 #define         RESPONSE_TYPE_SHIFT                             4
415 #define VM_L2_CNTL                                      0x1400
416 #define         ENABLE_L2_CACHE                                 (1 << 0)
417 #define         ENABLE_L2_FRAGMENT_PROCESSING                   (1 << 1)
418 #define         ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE         (1 << 9)
419 #define         EFFECTIVE_L2_QUEUE_SIZE(x)                      (((x) & 7) << 14)
420 #define VM_L2_CNTL2                                     0x1404
421 #define         INVALIDATE_ALL_L1_TLBS                          (1 << 0)
422 #define         INVALIDATE_L2_CACHE                             (1 << 1)
423 #define VM_L2_CNTL3                                     0x1408
424 #define         BANK_SELECT(x)                                  ((x) << 0)
425 #define         CACHE_UPDATE_MODE(x)                            ((x) << 6)
426 #define VM_L2_STATUS                                    0x140C
427 #define         L2_BUSY                                         (1 << 0)
428
429 #define WAIT_UNTIL                                      0x8040
430
431 #define SRBM_STATUS                                     0x0E50
432 #define SRBM_SOFT_RESET                                 0x0E60
433 #define         SRBM_SOFT_RESET_ALL_MASK                0x00FEEFA6
434 #define         SOFT_RESET_BIF                          (1 << 1)
435 #define         SOFT_RESET_CG                           (1 << 2)
436 #define         SOFT_RESET_DC                           (1 << 5)
437 #define         SOFT_RESET_GRBM                         (1 << 8)
438 #define         SOFT_RESET_HDP                          (1 << 9)
439 #define         SOFT_RESET_IH                           (1 << 10)
440 #define         SOFT_RESET_MC                           (1 << 11)
441 #define         SOFT_RESET_RLC                          (1 << 13)
442 #define         SOFT_RESET_ROM                          (1 << 14)
443 #define         SOFT_RESET_SEM                          (1 << 15)
444 #define         SOFT_RESET_VMC                          (1 << 17)
445 #define         SOFT_RESET_TST                          (1 << 21)
446 #define         SOFT_RESET_REGBB                        (1 << 22)
447 #define         SOFT_RESET_ORB                          (1 << 23)
448
449 /* display watermarks */
450 #define DC_LB_MEMORY_SPLIT                                0x6b0c
451 #define PRIORITY_A_CNT                                    0x6b18
452 #define         PRIORITY_MARK_MASK                        0x7fff
453 #define         PRIORITY_OFF                              (1 << 16)
454 #define         PRIORITY_ALWAYS_ON                        (1 << 20)
455 #define PRIORITY_B_CNT                                    0x6b1c
456 #define PIPE0_ARBITRATION_CONTROL3                        0x0bf0
457 #       define LATENCY_WATERMARK_MASK(x)                  ((x) << 16)
458 #define PIPE0_LATENCY_CONTROL                             0x0bf4
459 #       define LATENCY_LOW_WATERMARK(x)                   ((x) << 0)
460 #       define LATENCY_HIGH_WATERMARK(x)                  ((x) << 16)
461
462 #define IH_RB_CNTL                                        0x3e00
463 #       define IH_RB_ENABLE                               (1 << 0)
464 #       define IH_IB_SIZE(x)                              ((x) << 1) /* log2 */
465 #       define IH_RB_FULL_DRAIN_ENABLE                    (1 << 6)
466 #       define IH_WPTR_WRITEBACK_ENABLE                   (1 << 8)
467 #       define IH_WPTR_WRITEBACK_TIMER(x)                 ((x) << 9) /* log2 */
468 #       define IH_WPTR_OVERFLOW_ENABLE                    (1 << 16)
469 #       define IH_WPTR_OVERFLOW_CLEAR                     (1 << 31)
470 #define IH_RB_BASE                                        0x3e04
471 #define IH_RB_RPTR                                        0x3e08
472 #define IH_RB_WPTR                                        0x3e0c
473 #       define RB_OVERFLOW                                (1 << 0)
474 #       define WPTR_OFFSET_MASK                           0x3fffc
475 #define IH_RB_WPTR_ADDR_HI                                0x3e10
476 #define IH_RB_WPTR_ADDR_LO                                0x3e14
477 #define IH_CNTL                                           0x3e18
478 #       define ENABLE_INTR                                (1 << 0)
479 #       define IH_MC_SWAP(x)                              ((x) << 1)
480 #       define IH_MC_SWAP_NONE                            0
481 #       define IH_MC_SWAP_16BIT                           1
482 #       define IH_MC_SWAP_32BIT                           2
483 #       define IH_MC_SWAP_64BIT                           3
484 #       define RPTR_REARM                                 (1 << 4)
485 #       define MC_WRREQ_CREDIT(x)                         ((x) << 15)
486 #       define MC_WR_CLEAN_CNT(x)                         ((x) << 20)
487
488 #define CP_INT_CNTL                                     0xc124
489 #       define CNTX_BUSY_INT_ENABLE                     (1 << 19)
490 #       define CNTX_EMPTY_INT_ENABLE                    (1 << 20)
491 #       define SCRATCH_INT_ENABLE                       (1 << 25)
492 #       define TIME_STAMP_INT_ENABLE                    (1 << 26)
493 #       define IB2_INT_ENABLE                           (1 << 29)
494 #       define IB1_INT_ENABLE                           (1 << 30)
495 #       define RB_INT_ENABLE                            (1 << 31)
496 #define CP_INT_STATUS                                   0xc128
497 #       define SCRATCH_INT_STAT                         (1 << 25)
498 #       define TIME_STAMP_INT_STAT                      (1 << 26)
499 #       define IB2_INT_STAT                             (1 << 29)
500 #       define IB1_INT_STAT                             (1 << 30)
501 #       define RB_INT_STAT                              (1 << 31)
502
503 #define GRBM_INT_CNTL                                   0x8060
504 #       define RDERR_INT_ENABLE                         (1 << 0)
505 #       define GUI_IDLE_INT_ENABLE                      (1 << 19)
506
507 /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */
508 #define CRTC_STATUS_FRAME_COUNT                         0x6e98
509
510 /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */
511 #define VLINE_STATUS                                    0x6bb8
512 #       define VLINE_OCCURRED                           (1 << 0)
513 #       define VLINE_ACK                                (1 << 4)
514 #       define VLINE_STAT                               (1 << 12)
515 #       define VLINE_INTERRUPT                          (1 << 16)
516 #       define VLINE_INTERRUPT_TYPE                     (1 << 17)
517 /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */
518 #define VBLANK_STATUS                                   0x6bbc
519 #       define VBLANK_OCCURRED                          (1 << 0)
520 #       define VBLANK_ACK                               (1 << 4)
521 #       define VBLANK_STAT                              (1 << 12)
522 #       define VBLANK_INTERRUPT                         (1 << 16)
523 #       define VBLANK_INTERRUPT_TYPE                    (1 << 17)
524
525 /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */
526 #define INT_MASK                                        0x6b40
527 #       define VBLANK_INT_MASK                          (1 << 0)
528 #       define VLINE_INT_MASK                           (1 << 4)
529
530 #define DISP_INTERRUPT_STATUS                           0x60f4
531 #       define LB_D1_VLINE_INTERRUPT                    (1 << 2)
532 #       define LB_D1_VBLANK_INTERRUPT                   (1 << 3)
533 #       define DC_HPD1_INTERRUPT                        (1 << 17)
534 #       define DC_HPD1_RX_INTERRUPT                     (1 << 18)
535 #       define DACA_AUTODETECT_INTERRUPT                (1 << 22)
536 #       define DACB_AUTODETECT_INTERRUPT                (1 << 23)
537 #       define DC_I2C_SW_DONE_INTERRUPT                 (1 << 24)
538 #       define DC_I2C_HW_DONE_INTERRUPT                 (1 << 25)
539 #define DISP_INTERRUPT_STATUS_CONTINUE                  0x60f8
540 #       define LB_D2_VLINE_INTERRUPT                    (1 << 2)
541 #       define LB_D2_VBLANK_INTERRUPT                   (1 << 3)
542 #       define DC_HPD2_INTERRUPT                        (1 << 17)
543 #       define DC_HPD2_RX_INTERRUPT                     (1 << 18)
544 #       define DISP_TIMER_INTERRUPT                     (1 << 24)
545 #define DISP_INTERRUPT_STATUS_CONTINUE2                 0x60fc
546 #       define LB_D3_VLINE_INTERRUPT                    (1 << 2)
547 #       define LB_D3_VBLANK_INTERRUPT                   (1 << 3)
548 #       define DC_HPD3_INTERRUPT                        (1 << 17)
549 #       define DC_HPD3_RX_INTERRUPT                     (1 << 18)
550 #define DISP_INTERRUPT_STATUS_CONTINUE3                 0x6100
551 #       define LB_D4_VLINE_INTERRUPT                    (1 << 2)
552 #       define LB_D4_VBLANK_INTERRUPT                   (1 << 3)
553 #       define DC_HPD4_INTERRUPT                        (1 << 17)
554 #       define DC_HPD4_RX_INTERRUPT                     (1 << 18)
555 #define DISP_INTERRUPT_STATUS_CONTINUE4                 0x614c
556 #       define LB_D5_VLINE_INTERRUPT                    (1 << 2)
557 #       define LB_D5_VBLANK_INTERRUPT                   (1 << 3)
558 #       define DC_HPD5_INTERRUPT                        (1 << 17)
559 #       define DC_HPD5_RX_INTERRUPT                     (1 << 18)
560 #define DISP_INTERRUPT_STATUS_CONTINUE5                 0x6150
561 #       define LB_D6_VLINE_INTERRUPT                    (1 << 2)
562 #       define LB_D6_VBLANK_INTERRUPT                   (1 << 3)
563 #       define DC_HPD6_INTERRUPT                        (1 << 17)
564 #       define DC_HPD6_RX_INTERRUPT                     (1 << 18)
565
566 /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */
567 #define GRPH_INT_STATUS                                 0x6858
568 #       define GRPH_PFLIP_INT_OCCURRED                  (1 << 0)
569 #       define GRPH_PFLIP_INT_CLEAR                     (1 << 8)
570 /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */
571 #define GRPH_INT_CONTROL                                0x685c
572 #       define GRPH_PFLIP_INT_MASK                      (1 << 0)
573 #       define GRPH_PFLIP_INT_TYPE                      (1 << 8)
574
575 #define DACA_AUTODETECT_INT_CONTROL                     0x66c8
576 #define DACB_AUTODETECT_INT_CONTROL                     0x67c8
577
578 #define DC_HPD1_INT_STATUS                              0x601c
579 #define DC_HPD2_INT_STATUS                              0x6028
580 #define DC_HPD3_INT_STATUS                              0x6034
581 #define DC_HPD4_INT_STATUS                              0x6040
582 #define DC_HPD5_INT_STATUS                              0x604c
583 #define DC_HPD6_INT_STATUS                              0x6058
584 #       define DC_HPDx_INT_STATUS                       (1 << 0)
585 #       define DC_HPDx_SENSE                            (1 << 1)
586 #       define DC_HPDx_RX_INT_STATUS                    (1 << 8)
587
588 #define DC_HPD1_INT_CONTROL                             0x6020
589 #define DC_HPD2_INT_CONTROL                             0x602c
590 #define DC_HPD3_INT_CONTROL                             0x6038
591 #define DC_HPD4_INT_CONTROL                             0x6044
592 #define DC_HPD5_INT_CONTROL                             0x6050
593 #define DC_HPD6_INT_CONTROL                             0x605c
594 #       define DC_HPDx_INT_ACK                          (1 << 0)
595 #       define DC_HPDx_INT_POLARITY                     (1 << 8)
596 #       define DC_HPDx_INT_EN                           (1 << 16)
597 #       define DC_HPDx_RX_INT_ACK                       (1 << 20)
598 #       define DC_HPDx_RX_INT_EN                        (1 << 24)
599
600 #define DC_HPD1_CONTROL                                   0x6024
601 #define DC_HPD2_CONTROL                                   0x6030
602 #define DC_HPD3_CONTROL                                   0x603c
603 #define DC_HPD4_CONTROL                                   0x6048
604 #define DC_HPD5_CONTROL                                   0x6054
605 #define DC_HPD6_CONTROL                                   0x6060
606 #       define DC_HPDx_CONNECTION_TIMER(x)                ((x) << 0)
607 #       define DC_HPDx_RX_INT_TIMER(x)                    ((x) << 16)
608 #       define DC_HPDx_EN                                 (1 << 28)
609
610 /* PCIE link stuff */
611 #define PCIE_LC_TRAINING_CNTL                             0xa1 /* PCIE_P */
612 #define PCIE_LC_LINK_WIDTH_CNTL                           0xa2 /* PCIE_P */
613 #       define LC_LINK_WIDTH_SHIFT                        0
614 #       define LC_LINK_WIDTH_MASK                         0x7
615 #       define LC_LINK_WIDTH_X0                           0
616 #       define LC_LINK_WIDTH_X1                           1
617 #       define LC_LINK_WIDTH_X2                           2
618 #       define LC_LINK_WIDTH_X4                           3
619 #       define LC_LINK_WIDTH_X8                           4
620 #       define LC_LINK_WIDTH_X16                          6
621 #       define LC_LINK_WIDTH_RD_SHIFT                     4
622 #       define LC_LINK_WIDTH_RD_MASK                      0x70
623 #       define LC_RECONFIG_ARC_MISSING_ESCAPE             (1 << 7)
624 #       define LC_RECONFIG_NOW                            (1 << 8)
625 #       define LC_RENEGOTIATION_SUPPORT                   (1 << 9)
626 #       define LC_RENEGOTIATE_EN                          (1 << 10)
627 #       define LC_SHORT_RECONFIG_EN                       (1 << 11)
628 #       define LC_UPCONFIGURE_SUPPORT                     (1 << 12)
629 #       define LC_UPCONFIGURE_DIS                         (1 << 13)
630 #define PCIE_LC_SPEED_CNTL                                0xa4 /* PCIE_P */
631 #       define LC_GEN2_EN_STRAP                           (1 << 0)
632 #       define LC_TARGET_LINK_SPEED_OVERRIDE_EN           (1 << 1)
633 #       define LC_FORCE_EN_HW_SPEED_CHANGE                (1 << 5)
634 #       define LC_FORCE_DIS_HW_SPEED_CHANGE               (1 << 6)
635 #       define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK      (0x3 << 8)
636 #       define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT     3
637 #       define LC_CURRENT_DATA_RATE                       (1 << 11)
638 #       define LC_VOLTAGE_TIMER_SEL_MASK                  (0xf << 14)
639 #       define LC_CLR_FAILED_SPD_CHANGE_CNT               (1 << 21)
640 #       define LC_OTHER_SIDE_EVER_SENT_GEN2               (1 << 23)
641 #       define LC_OTHER_SIDE_SUPPORTS_GEN2                (1 << 24)
642 #define MM_CFGREGS_CNTL                                   0x544c
643 #       define MM_WR_TO_CFG_EN                            (1 << 3)
644 #define LINK_CNTL2                                        0x88 /* F0 */
645 #       define TARGET_LINK_SPEED_MASK                     (0xf << 0)
646 #       define SELECTABLE_DEEMPHASIS                      (1 << 6)
647
648 /*
649  * PM4
650  */
651 #define PACKET_TYPE0    0
652 #define PACKET_TYPE1    1
653 #define PACKET_TYPE2    2
654 #define PACKET_TYPE3    3
655
656 #define CP_PACKET_GET_TYPE(h) (((h) >> 30) & 3)
657 #define CP_PACKET_GET_COUNT(h) (((h) >> 16) & 0x3FFF)
658 #define CP_PACKET0_GET_REG(h) (((h) & 0xFFFF) << 2)
659 #define CP_PACKET3_GET_OPCODE(h) (((h) >> 8) & 0xFF)
660 #define PACKET0(reg, n) ((PACKET_TYPE0 << 30) |                         \
661                          (((reg) >> 2) & 0xFFFF) |                      \
662                          ((n) & 0x3FFF) << 16)
663 #define CP_PACKET2                      0x80000000
664 #define         PACKET2_PAD_SHIFT               0
665 #define         PACKET2_PAD_MASK                (0x3fffffff << 0)
666
667 #define PACKET2(v)      (CP_PACKET2 | REG_SET(PACKET2_PAD, (v)))
668
669 #define PACKET3(op, n)  ((PACKET_TYPE3 << 30) |                         \
670                          (((op) & 0xFF) << 8) |                         \
671                          ((n) & 0x3FFF) << 16)
672
673 /* Packet 3 types */
674 #define PACKET3_NOP                                     0x10
675 #define PACKET3_SET_BASE                                0x11
676 #define PACKET3_CLEAR_STATE                             0x12
677 #define PACKET3_INDEX_BUFFER_SIZE                       0x13
678 #define PACKET3_DISPATCH_DIRECT                         0x15
679 #define PACKET3_DISPATCH_INDIRECT                       0x16
680 #define PACKET3_INDIRECT_BUFFER_END                     0x17
681 #define PACKET3_MODE_CONTROL                            0x18
682 #define PACKET3_SET_PREDICATION                         0x20
683 #define PACKET3_REG_RMW                                 0x21
684 #define PACKET3_COND_EXEC                               0x22
685 #define PACKET3_PRED_EXEC                               0x23
686 #define PACKET3_DRAW_INDIRECT                           0x24
687 #define PACKET3_DRAW_INDEX_INDIRECT                     0x25
688 #define PACKET3_INDEX_BASE                              0x26
689 #define PACKET3_DRAW_INDEX_2                            0x27
690 #define PACKET3_CONTEXT_CONTROL                         0x28
691 #define PACKET3_DRAW_INDEX_OFFSET                       0x29
692 #define PACKET3_INDEX_TYPE                              0x2A
693 #define PACKET3_DRAW_INDEX                              0x2B
694 #define PACKET3_DRAW_INDEX_AUTO                         0x2D
695 #define PACKET3_DRAW_INDEX_IMMD                         0x2E
696 #define PACKET3_NUM_INSTANCES                           0x2F
697 #define PACKET3_DRAW_INDEX_MULTI_AUTO                   0x30
698 #define PACKET3_STRMOUT_BUFFER_UPDATE                   0x34
699 #define PACKET3_DRAW_INDEX_OFFSET_2                     0x35
700 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT                0x36
701 #define PACKET3_MEM_SEMAPHORE                           0x39
702 #define PACKET3_MPEG_INDEX                              0x3A
703 #define PACKET3_COPY_DW                                 0x3B
704 #define PACKET3_WAIT_REG_MEM                            0x3C
705 #define PACKET3_MEM_WRITE                               0x3D
706 #define PACKET3_INDIRECT_BUFFER                         0x32
707 #define PACKET3_SURFACE_SYNC                            0x43
708 #              define PACKET3_CB0_DEST_BASE_ENA    (1 << 6)
709 #              define PACKET3_CB1_DEST_BASE_ENA    (1 << 7)
710 #              define PACKET3_CB2_DEST_BASE_ENA    (1 << 8)
711 #              define PACKET3_CB3_DEST_BASE_ENA    (1 << 9)
712 #              define PACKET3_CB4_DEST_BASE_ENA    (1 << 10)
713 #              define PACKET3_CB5_DEST_BASE_ENA    (1 << 11)
714 #              define PACKET3_CB6_DEST_BASE_ENA    (1 << 12)
715 #              define PACKET3_CB7_DEST_BASE_ENA    (1 << 13)
716 #              define PACKET3_DB_DEST_BASE_ENA     (1 << 14)
717 #              define PACKET3_CB8_DEST_BASE_ENA    (1 << 15)
718 #              define PACKET3_CB9_DEST_BASE_ENA    (1 << 16)
719 #              define PACKET3_CB10_DEST_BASE_ENA   (1 << 17)
720 #              define PACKET3_CB11_DEST_BASE_ENA   (1 << 18)
721 #              define PACKET3_FULL_CACHE_ENA       (1 << 20)
722 #              define PACKET3_TC_ACTION_ENA        (1 << 23)
723 #              define PACKET3_VC_ACTION_ENA        (1 << 24)
724 #              define PACKET3_CB_ACTION_ENA        (1 << 25)
725 #              define PACKET3_DB_ACTION_ENA        (1 << 26)
726 #              define PACKET3_SH_ACTION_ENA        (1 << 27)
727 #              define PACKET3_SX_ACTION_ENA        (1 << 28)
728 #define PACKET3_ME_INITIALIZE                           0x44
729 #define         PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
730 #define PACKET3_COND_WRITE                              0x45
731 #define PACKET3_EVENT_WRITE                             0x46
732 #define PACKET3_EVENT_WRITE_EOP                         0x47
733 #define PACKET3_EVENT_WRITE_EOS                         0x48
734 #define PACKET3_PREAMBLE_CNTL                           0x4A
735 #              define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE     (2 << 28)
736 #              define PACKET3_PREAMBLE_END_CLEAR_STATE       (3 << 28)
737 #define PACKET3_RB_OFFSET                               0x4B
738 #define PACKET3_ALU_PS_CONST_BUFFER_COPY                0x4C
739 #define PACKET3_ALU_VS_CONST_BUFFER_COPY                0x4D
740 #define PACKET3_ALU_PS_CONST_UPDATE                     0x4E
741 #define PACKET3_ALU_VS_CONST_UPDATE                     0x4F
742 #define PACKET3_ONE_REG_WRITE                           0x57
743 #define PACKET3_SET_CONFIG_REG                          0x68
744 #define         PACKET3_SET_CONFIG_REG_START                    0x00008000
745 #define         PACKET3_SET_CONFIG_REG_END                      0x0000ac00
746 #define PACKET3_SET_CONTEXT_REG                         0x69
747 #define         PACKET3_SET_CONTEXT_REG_START                   0x00028000
748 #define         PACKET3_SET_CONTEXT_REG_END                     0x00029000
749 #define PACKET3_SET_ALU_CONST                           0x6A
750 /* alu const buffers only; no reg file */
751 #define PACKET3_SET_BOOL_CONST                          0x6B
752 #define         PACKET3_SET_BOOL_CONST_START                    0x0003a500
753 #define         PACKET3_SET_BOOL_CONST_END                      0x0003a518
754 #define PACKET3_SET_LOOP_CONST                          0x6C
755 #define         PACKET3_SET_LOOP_CONST_START                    0x0003a200
756 #define         PACKET3_SET_LOOP_CONST_END                      0x0003a500
757 #define PACKET3_SET_RESOURCE                            0x6D
758 #define         PACKET3_SET_RESOURCE_START                      0x00030000
759 #define         PACKET3_SET_RESOURCE_END                        0x00038000
760 #define PACKET3_SET_SAMPLER                             0x6E
761 #define         PACKET3_SET_SAMPLER_START                       0x0003c000
762 #define         PACKET3_SET_SAMPLER_END                         0x0003c600
763 #define PACKET3_SET_CTL_CONST                           0x6F
764 #define         PACKET3_SET_CTL_CONST_START                     0x0003cff0
765 #define         PACKET3_SET_CTL_CONST_END                       0x0003ff0c
766 #define PACKET3_SET_RESOURCE_OFFSET                     0x70
767 #define PACKET3_SET_ALU_CONST_VS                        0x71
768 #define PACKET3_SET_ALU_CONST_DI                        0x72
769 #define PACKET3_SET_CONTEXT_REG_INDIRECT                0x73
770 #define PACKET3_SET_RESOURCE_INDIRECT                   0x74
771 #define PACKET3_SET_APPEND_CNT                          0x75
772
773 #define SQ_RESOURCE_CONSTANT_WORD7_0                            0x3001c
774 #define         S__SQ_CONSTANT_TYPE(x)                  (((x) & 3) << 30)
775 #define         G__SQ_CONSTANT_TYPE(x)                  (((x) >> 30) & 3)
776 #define                 SQ_TEX_VTX_INVALID_TEXTURE                      0x0
777 #define                 SQ_TEX_VTX_INVALID_BUFFER                       0x1
778 #define                 SQ_TEX_VTX_VALID_TEXTURE                        0x2
779 #define                 SQ_TEX_VTX_VALID_BUFFER                         0x3
780
781 #define VGT_VTX_VECT_EJECT_REG                          0x88b0
782
783 #define SQ_CONST_MEM_BASE                               0x8df8
784
785 #define SQ_ESGS_RING_BASE                               0x8c40
786 #define SQ_ESGS_RING_SIZE                               0x8c44
787 #define SQ_GSVS_RING_BASE                               0x8c48
788 #define SQ_GSVS_RING_SIZE                               0x8c4c
789 #define SQ_ESTMP_RING_BASE                              0x8c50
790 #define SQ_ESTMP_RING_SIZE                              0x8c54
791 #define SQ_GSTMP_RING_BASE                              0x8c58
792 #define SQ_GSTMP_RING_SIZE                              0x8c5c
793 #define SQ_VSTMP_RING_BASE                              0x8c60
794 #define SQ_VSTMP_RING_SIZE                              0x8c64
795 #define SQ_PSTMP_RING_BASE                              0x8c68
796 #define SQ_PSTMP_RING_SIZE                              0x8c6c
797 #define SQ_LSTMP_RING_BASE                              0x8e10
798 #define SQ_LSTMP_RING_SIZE                              0x8e14
799 #define SQ_HSTMP_RING_BASE                              0x8e18
800 #define SQ_HSTMP_RING_SIZE                              0x8e1c
801 #define VGT_TF_RING_SIZE                                0x8988
802
803 #define SQ_ESGS_RING_ITEMSIZE                           0x28900
804 #define SQ_GSVS_RING_ITEMSIZE                           0x28904
805 #define SQ_ESTMP_RING_ITEMSIZE                          0x28908
806 #define SQ_GSTMP_RING_ITEMSIZE                          0x2890c
807 #define SQ_VSTMP_RING_ITEMSIZE                          0x28910
808 #define SQ_PSTMP_RING_ITEMSIZE                          0x28914
809 #define SQ_LSTMP_RING_ITEMSIZE                          0x28830
810 #define SQ_HSTMP_RING_ITEMSIZE                          0x28834
811
812 #define SQ_GS_VERT_ITEMSIZE                             0x2891c
813 #define SQ_GS_VERT_ITEMSIZE_1                           0x28920
814 #define SQ_GS_VERT_ITEMSIZE_2                           0x28924
815 #define SQ_GS_VERT_ITEMSIZE_3                           0x28928
816 #define SQ_GSVS_RING_OFFSET_1                           0x2892c
817 #define SQ_GSVS_RING_OFFSET_2                           0x28930
818 #define SQ_GSVS_RING_OFFSET_3                           0x28934
819
820 #define SQ_ALU_CONST_BUFFER_SIZE_PS_0                   0x28140
821 #define SQ_ALU_CONST_BUFFER_SIZE_HS_0                   0x28f80
822
823 #define SQ_ALU_CONST_CACHE_PS_0                         0x28940
824 #define SQ_ALU_CONST_CACHE_PS_1                         0x28944
825 #define SQ_ALU_CONST_CACHE_PS_2                         0x28948
826 #define SQ_ALU_CONST_CACHE_PS_3                         0x2894c
827 #define SQ_ALU_CONST_CACHE_PS_4                         0x28950
828 #define SQ_ALU_CONST_CACHE_PS_5                         0x28954
829 #define SQ_ALU_CONST_CACHE_PS_6                         0x28958
830 #define SQ_ALU_CONST_CACHE_PS_7                         0x2895c
831 #define SQ_ALU_CONST_CACHE_PS_8                         0x28960
832 #define SQ_ALU_CONST_CACHE_PS_9                         0x28964
833 #define SQ_ALU_CONST_CACHE_PS_10                        0x28968
834 #define SQ_ALU_CONST_CACHE_PS_11                        0x2896c
835 #define SQ_ALU_CONST_CACHE_PS_12                        0x28970
836 #define SQ_ALU_CONST_CACHE_PS_13                        0x28974
837 #define SQ_ALU_CONST_CACHE_PS_14                        0x28978
838 #define SQ_ALU_CONST_CACHE_PS_15                        0x2897c
839 #define SQ_ALU_CONST_CACHE_VS_0                         0x28980
840 #define SQ_ALU_CONST_CACHE_VS_1                         0x28984
841 #define SQ_ALU_CONST_CACHE_VS_2                         0x28988
842 #define SQ_ALU_CONST_CACHE_VS_3                         0x2898c
843 #define SQ_ALU_CONST_CACHE_VS_4                         0x28990
844 #define SQ_ALU_CONST_CACHE_VS_5                         0x28994
845 #define SQ_ALU_CONST_CACHE_VS_6                         0x28998
846 #define SQ_ALU_CONST_CACHE_VS_7                         0x2899c
847 #define SQ_ALU_CONST_CACHE_VS_8                         0x289a0
848 #define SQ_ALU_CONST_CACHE_VS_9                         0x289a4
849 #define SQ_ALU_CONST_CACHE_VS_10                        0x289a8
850 #define SQ_ALU_CONST_CACHE_VS_11                        0x289ac
851 #define SQ_ALU_CONST_CACHE_VS_12                        0x289b0
852 #define SQ_ALU_CONST_CACHE_VS_13                        0x289b4
853 #define SQ_ALU_CONST_CACHE_VS_14                        0x289b8
854 #define SQ_ALU_CONST_CACHE_VS_15                        0x289bc
855 #define SQ_ALU_CONST_CACHE_GS_0                         0x289c0
856 #define SQ_ALU_CONST_CACHE_GS_1                         0x289c4
857 #define SQ_ALU_CONST_CACHE_GS_2                         0x289c8
858 #define SQ_ALU_CONST_CACHE_GS_3                         0x289cc
859 #define SQ_ALU_CONST_CACHE_GS_4                         0x289d0
860 #define SQ_ALU_CONST_CACHE_GS_5                         0x289d4
861 #define SQ_ALU_CONST_CACHE_GS_6                         0x289d8
862 #define SQ_ALU_CONST_CACHE_GS_7                         0x289dc
863 #define SQ_ALU_CONST_CACHE_GS_8                         0x289e0
864 #define SQ_ALU_CONST_CACHE_GS_9                         0x289e4
865 #define SQ_ALU_CONST_CACHE_GS_10                        0x289e8
866 #define SQ_ALU_CONST_CACHE_GS_11                        0x289ec
867 #define SQ_ALU_CONST_CACHE_GS_12                        0x289f0
868 #define SQ_ALU_CONST_CACHE_GS_13                        0x289f4
869 #define SQ_ALU_CONST_CACHE_GS_14                        0x289f8
870 #define SQ_ALU_CONST_CACHE_GS_15                        0x289fc
871 #define SQ_ALU_CONST_CACHE_HS_0                         0x28f00
872 #define SQ_ALU_CONST_CACHE_HS_1                         0x28f04
873 #define SQ_ALU_CONST_CACHE_HS_2                         0x28f08
874 #define SQ_ALU_CONST_CACHE_HS_3                         0x28f0c
875 #define SQ_ALU_CONST_CACHE_HS_4                         0x28f10
876 #define SQ_ALU_CONST_CACHE_HS_5                         0x28f14
877 #define SQ_ALU_CONST_CACHE_HS_6                         0x28f18
878 #define SQ_ALU_CONST_CACHE_HS_7                         0x28f1c
879 #define SQ_ALU_CONST_CACHE_HS_8                         0x28f20
880 #define SQ_ALU_CONST_CACHE_HS_9                         0x28f24
881 #define SQ_ALU_CONST_CACHE_HS_10                        0x28f28
882 #define SQ_ALU_CONST_CACHE_HS_11                        0x28f2c
883 #define SQ_ALU_CONST_CACHE_HS_12                        0x28f30
884 #define SQ_ALU_CONST_CACHE_HS_13                        0x28f34
885 #define SQ_ALU_CONST_CACHE_HS_14                        0x28f38
886 #define SQ_ALU_CONST_CACHE_HS_15                        0x28f3c
887 #define SQ_ALU_CONST_CACHE_LS_0                         0x28f40
888 #define SQ_ALU_CONST_CACHE_LS_1                         0x28f44
889 #define SQ_ALU_CONST_CACHE_LS_2                         0x28f48
890 #define SQ_ALU_CONST_CACHE_LS_3                         0x28f4c
891 #define SQ_ALU_CONST_CACHE_LS_4                         0x28f50
892 #define SQ_ALU_CONST_CACHE_LS_5                         0x28f54
893 #define SQ_ALU_CONST_CACHE_LS_6                         0x28f58
894 #define SQ_ALU_CONST_CACHE_LS_7                         0x28f5c
895 #define SQ_ALU_CONST_CACHE_LS_8                         0x28f60
896 #define SQ_ALU_CONST_CACHE_LS_9                         0x28f64
897 #define SQ_ALU_CONST_CACHE_LS_10                        0x28f68
898 #define SQ_ALU_CONST_CACHE_LS_11                        0x28f6c
899 #define SQ_ALU_CONST_CACHE_LS_12                        0x28f70
900 #define SQ_ALU_CONST_CACHE_LS_13                        0x28f74
901 #define SQ_ALU_CONST_CACHE_LS_14                        0x28f78
902 #define SQ_ALU_CONST_CACHE_LS_15                        0x28f7c
903
904 #define PA_SC_SCREEN_SCISSOR_TL                         0x28030
905 #define PA_SC_GENERIC_SCISSOR_TL                        0x28240
906 #define PA_SC_WINDOW_SCISSOR_TL                         0x28204
907
908 #define VGT_PRIMITIVE_TYPE                              0x8958
909 #define VGT_INDEX_TYPE                                  0x895C
910
911 #define VGT_NUM_INDICES                                 0x8970
912
913 #define VGT_COMPUTE_DIM_X                               0x8990
914 #define VGT_COMPUTE_DIM_Y                               0x8994
915 #define VGT_COMPUTE_DIM_Z                               0x8998
916 #define VGT_COMPUTE_START_X                             0x899C
917 #define VGT_COMPUTE_START_Y                             0x89A0
918 #define VGT_COMPUTE_START_Z                             0x89A4
919 #define VGT_COMPUTE_INDEX                               0x89A8
920 #define VGT_COMPUTE_THREAD_GROUP_SIZE                   0x89AC
921 #define VGT_HS_OFFCHIP_PARAM                            0x89B0
922
923 #define DB_DEBUG                                        0x9830
924 #define DB_DEBUG2                                       0x9834
925 #define DB_DEBUG3                                       0x9838
926 #define DB_DEBUG4                                       0x983C
927 #define DB_WATERMARKS                                   0x9854
928 #define DB_DEPTH_CONTROL                                0x28800
929 #define R_028800_DB_DEPTH_CONTROL                    0x028800
930 #define   S_028800_STENCIL_ENABLE(x)                   (((x) & 0x1) << 0)
931 #define   G_028800_STENCIL_ENABLE(x)                   (((x) >> 0) & 0x1)
932 #define   C_028800_STENCIL_ENABLE                      0xFFFFFFFE
933 #define   S_028800_Z_ENABLE(x)                         (((x) & 0x1) << 1)
934 #define   G_028800_Z_ENABLE(x)                         (((x) >> 1) & 0x1)
935 #define   C_028800_Z_ENABLE                            0xFFFFFFFD
936 #define   S_028800_Z_WRITE_ENABLE(x)                   (((x) & 0x1) << 2)
937 #define   G_028800_Z_WRITE_ENABLE(x)                   (((x) >> 2) & 0x1)
938 #define   C_028800_Z_WRITE_ENABLE                      0xFFFFFFFB
939 #define   S_028800_ZFUNC(x)                            (((x) & 0x7) << 4)
940 #define   G_028800_ZFUNC(x)                            (((x) >> 4) & 0x7)
941 #define   C_028800_ZFUNC                               0xFFFFFF8F
942 #define   S_028800_BACKFACE_ENABLE(x)                  (((x) & 0x1) << 7)
943 #define   G_028800_BACKFACE_ENABLE(x)                  (((x) >> 7) & 0x1)
944 #define   C_028800_BACKFACE_ENABLE                     0xFFFFFF7F
945 #define   S_028800_STENCILFUNC(x)                      (((x) & 0x7) << 8)
946 #define   G_028800_STENCILFUNC(x)                      (((x) >> 8) & 0x7)
947 #define   C_028800_STENCILFUNC                         0xFFFFF8FF
948 #define     V_028800_STENCILFUNC_NEVER                 0x00000000
949 #define     V_028800_STENCILFUNC_LESS                  0x00000001
950 #define     V_028800_STENCILFUNC_EQUAL                 0x00000002
951 #define     V_028800_STENCILFUNC_LEQUAL                0x00000003
952 #define     V_028800_STENCILFUNC_GREATER               0x00000004
953 #define     V_028800_STENCILFUNC_NOTEQUAL              0x00000005
954 #define     V_028800_STENCILFUNC_GEQUAL                0x00000006
955 #define     V_028800_STENCILFUNC_ALWAYS                0x00000007
956 #define   S_028800_STENCILFAIL(x)                      (((x) & 0x7) << 11)
957 #define   G_028800_STENCILFAIL(x)                      (((x) >> 11) & 0x7)
958 #define   C_028800_STENCILFAIL                         0xFFFFC7FF
959 #define     V_028800_STENCIL_KEEP                      0x00000000
960 #define     V_028800_STENCIL_ZERO                      0x00000001
961 #define     V_028800_STENCIL_REPLACE                   0x00000002
962 #define     V_028800_STENCIL_INCR                      0x00000003
963 #define     V_028800_STENCIL_DECR                      0x00000004
964 #define     V_028800_STENCIL_INVERT                    0x00000005
965 #define     V_028800_STENCIL_INCR_WRAP                 0x00000006
966 #define     V_028800_STENCIL_DECR_WRAP                 0x00000007
967 #define   S_028800_STENCILZPASS(x)                     (((x) & 0x7) << 14)
968 #define   G_028800_STENCILZPASS(x)                     (((x) >> 14) & 0x7)
969 #define   C_028800_STENCILZPASS                        0xFFFE3FFF
970 #define   S_028800_STENCILZFAIL(x)                     (((x) & 0x7) << 17)
971 #define   G_028800_STENCILZFAIL(x)                     (((x) >> 17) & 0x7)
972 #define   C_028800_STENCILZFAIL                        0xFFF1FFFF
973 #define   S_028800_STENCILFUNC_BF(x)                   (((x) & 0x7) << 20)
974 #define   G_028800_STENCILFUNC_BF(x)                   (((x) >> 20) & 0x7)
975 #define   C_028800_STENCILFUNC_BF                      0xFF8FFFFF
976 #define   S_028800_STENCILFAIL_BF(x)                   (((x) & 0x7) << 23)
977 #define   G_028800_STENCILFAIL_BF(x)                   (((x) >> 23) & 0x7)
978 #define   C_028800_STENCILFAIL_BF                      0xFC7FFFFF
979 #define   S_028800_STENCILZPASS_BF(x)                  (((x) & 0x7) << 26)
980 #define   G_028800_STENCILZPASS_BF(x)                  (((x) >> 26) & 0x7)
981 #define   C_028800_STENCILZPASS_BF                     0xE3FFFFFF
982 #define   S_028800_STENCILZFAIL_BF(x)                  (((x) & 0x7) << 29)
983 #define   G_028800_STENCILZFAIL_BF(x)                  (((x) >> 29) & 0x7)
984 #define   C_028800_STENCILZFAIL_BF                     0x1FFFFFFF
985 #define DB_DEPTH_VIEW                                   0x28008
986 #define R_028008_DB_DEPTH_VIEW                       0x00028008
987 #define   S_028008_SLICE_START(x)                      (((x) & 0x7FF) << 0)
988 #define   G_028008_SLICE_START(x)                      (((x) >> 0) & 0x7FF)
989 #define   C_028008_SLICE_START                         0xFFFFF800
990 #define   S_028008_SLICE_MAX(x)                        (((x) & 0x7FF) << 13)
991 #define   G_028008_SLICE_MAX(x)                        (((x) >> 13) & 0x7FF)
992 #define   C_028008_SLICE_MAX                           0xFF001FFF
993 #define DB_HTILE_DATA_BASE                              0x28014
994 #define DB_Z_INFO                                       0x28040
995 #       define Z_ARRAY_MODE(x)                          ((x) << 4)
996 #       define DB_TILE_SPLIT(x)                         (((x) & 0x7) << 8)
997 #       define DB_NUM_BANKS(x)                          (((x) & 0x3) << 12)
998 #       define DB_BANK_WIDTH(x)                         (((x) & 0x3) << 16)
999 #       define DB_BANK_HEIGHT(x)                        (((x) & 0x3) << 20)
1000 #       define DB_MACRO_TILE_ASPECT(x)                  (((x) & 0x3) << 24)
1001 #define R_028040_DB_Z_INFO                       0x028040
1002 #define   S_028040_FORMAT(x)                           (((x) & 0x3) << 0)
1003 #define   G_028040_FORMAT(x)                           (((x) >> 0) & 0x3)
1004 #define   C_028040_FORMAT                              0xFFFFFFFC
1005 #define     V_028040_Z_INVALID                     0x00000000
1006 #define     V_028040_Z_16                          0x00000001
1007 #define     V_028040_Z_24                          0x00000002
1008 #define     V_028040_Z_32_FLOAT                    0x00000003
1009 #define   S_028040_ARRAY_MODE(x)                       (((x) & 0xF) << 4)
1010 #define   G_028040_ARRAY_MODE(x)                       (((x) >> 4) & 0xF)
1011 #define   C_028040_ARRAY_MODE                          0xFFFFFF0F
1012 #define   S_028040_READ_SIZE(x)                        (((x) & 0x1) << 28)
1013 #define   G_028040_READ_SIZE(x)                        (((x) >> 28) & 0x1)
1014 #define   C_028040_READ_SIZE                           0xEFFFFFFF
1015 #define   S_028040_TILE_SURFACE_ENABLE(x)              (((x) & 0x1) << 29)
1016 #define   G_028040_TILE_SURFACE_ENABLE(x)              (((x) >> 29) & 0x1)
1017 #define   C_028040_TILE_SURFACE_ENABLE                 0xDFFFFFFF
1018 #define   S_028040_ZRANGE_PRECISION(x)                 (((x) & 0x1) << 31)
1019 #define   G_028040_ZRANGE_PRECISION(x)                 (((x) >> 31) & 0x1)
1020 #define   C_028040_ZRANGE_PRECISION                    0x7FFFFFFF
1021 #define   S_028040_TILE_SPLIT(x)                       (((x) & 0x7) << 8)
1022 #define   G_028040_TILE_SPLIT(x)                       (((x) >> 8) & 0x7)
1023 #define   S_028040_NUM_BANKS(x)                        (((x) & 0x3) << 12)
1024 #define   G_028040_NUM_BANKS(x)                        (((x) >> 12) & 0x3)
1025 #define   S_028040_BANK_WIDTH(x)                       (((x) & 0x3) << 16)
1026 #define   G_028040_BANK_WIDTH(x)                       (((x) >> 16) & 0x3)
1027 #define   S_028040_BANK_HEIGHT(x)                      (((x) & 0x3) << 20)
1028 #define   G_028040_BANK_HEIGHT(x)                      (((x) >> 20) & 0x3)
1029 #define   S_028040_MACRO_TILE_ASPECT(x)                (((x) & 0x3) << 24)
1030 #define   G_028040_MACRO_TILE_ASPECT(x)                (((x) >> 24) & 0x3)
1031 #define DB_STENCIL_INFO                                 0x28044
1032 #define R_028044_DB_STENCIL_INFO                     0x028044
1033 #define   S_028044_FORMAT(x)                           (((x) & 0x1) << 0)
1034 #define   G_028044_FORMAT(x)                           (((x) >> 0) & 0x1)
1035 #define   C_028044_FORMAT                              0xFFFFFFFE
1036 #define   G_028044_TILE_SPLIT(x)                       (((x) >> 8) & 0x7)
1037 #define DB_Z_READ_BASE                                  0x28048
1038 #define DB_STENCIL_READ_BASE                            0x2804c
1039 #define DB_Z_WRITE_BASE                                 0x28050
1040 #define DB_STENCIL_WRITE_BASE                           0x28054
1041 #define DB_DEPTH_SIZE                                   0x28058
1042 #define R_028058_DB_DEPTH_SIZE                       0x028058
1043 #define   S_028058_PITCH_TILE_MAX(x)                   (((x) & 0x7FF) << 0)
1044 #define   G_028058_PITCH_TILE_MAX(x)                   (((x) >> 0) & 0x7FF)
1045 #define   C_028058_PITCH_TILE_MAX                      0xFFFFF800
1046 #define   S_028058_HEIGHT_TILE_MAX(x)                   (((x) & 0x7FF) << 11)
1047 #define   G_028058_HEIGHT_TILE_MAX(x)                   (((x) >> 11) & 0x7FF)
1048 #define   C_028058_HEIGHT_TILE_MAX                      0xFFC007FF
1049 #define R_02805C_DB_DEPTH_SLICE                      0x02805C
1050 #define   S_02805C_SLICE_TILE_MAX(x)                   (((x) & 0x3FFFFF) << 0)
1051 #define   G_02805C_SLICE_TILE_MAX(x)                   (((x) >> 0) & 0x3FFFFF)
1052 #define   C_02805C_SLICE_TILE_MAX                      0xFFC00000
1053
1054 #define SQ_PGM_START_PS                                 0x28840
1055 #define SQ_PGM_START_VS                                 0x2885c
1056 #define SQ_PGM_START_GS                                 0x28874
1057 #define SQ_PGM_START_ES                                 0x2888c
1058 #define SQ_PGM_START_FS                                 0x288a4
1059 #define SQ_PGM_START_HS                                 0x288b8
1060 #define SQ_PGM_START_LS                                 0x288d0
1061
1062 #define VGT_STRMOUT_BUFFER_BASE_0                       0x28AD8
1063 #define VGT_STRMOUT_BUFFER_BASE_1                       0x28AE8
1064 #define VGT_STRMOUT_BUFFER_BASE_2                       0x28AF8
1065 #define VGT_STRMOUT_BUFFER_BASE_3                       0x28B08
1066 #define VGT_STRMOUT_BUFFER_SIZE_0                       0x28AD0
1067 #define VGT_STRMOUT_BUFFER_SIZE_1                       0x28AE0
1068 #define VGT_STRMOUT_BUFFER_SIZE_2                       0x28AF0
1069 #define VGT_STRMOUT_BUFFER_SIZE_3                       0x28B00
1070 #define VGT_STRMOUT_CONFIG                              0x28b94
1071 #define VGT_STRMOUT_BUFFER_CONFIG                       0x28b98
1072
1073 #define CB_TARGET_MASK                                  0x28238
1074 #define CB_SHADER_MASK                                  0x2823c
1075
1076 #define GDS_ADDR_BASE                                   0x28720
1077
1078 #define CB_IMMED0_BASE                                  0x28b9c
1079 #define CB_IMMED1_BASE                                  0x28ba0
1080 #define CB_IMMED2_BASE                                  0x28ba4
1081 #define CB_IMMED3_BASE                                  0x28ba8
1082 #define CB_IMMED4_BASE                                  0x28bac
1083 #define CB_IMMED5_BASE                                  0x28bb0
1084 #define CB_IMMED6_BASE                                  0x28bb4
1085 #define CB_IMMED7_BASE                                  0x28bb8
1086 #define CB_IMMED8_BASE                                  0x28bbc
1087 #define CB_IMMED9_BASE                                  0x28bc0
1088 #define CB_IMMED10_BASE                                 0x28bc4
1089 #define CB_IMMED11_BASE                                 0x28bc8
1090
1091 /* all 12 CB blocks have these regs */
1092 #define CB_COLOR0_BASE                                  0x28c60
1093 #define CB_COLOR0_PITCH                                 0x28c64
1094 #define CB_COLOR0_SLICE                                 0x28c68
1095 #define CB_COLOR0_VIEW                                  0x28c6c
1096 #define R_028C6C_CB_COLOR0_VIEW                      0x00028C6C
1097 #define   S_028C6C_SLICE_START(x)                      (((x) & 0x7FF) << 0)
1098 #define   G_028C6C_SLICE_START(x)                      (((x) >> 0) & 0x7FF)
1099 #define   C_028C6C_SLICE_START                         0xFFFFF800
1100 #define   S_028C6C_SLICE_MAX(x)                        (((x) & 0x7FF) << 13)
1101 #define   G_028C6C_SLICE_MAX(x)                        (((x) >> 13) & 0x7FF)
1102 #define   C_028C6C_SLICE_MAX                           0xFF001FFF
1103 #define R_028C70_CB_COLOR0_INFO                      0x028C70
1104 #define   S_028C70_ENDIAN(x)                           (((x) & 0x3) << 0)
1105 #define   G_028C70_ENDIAN(x)                           (((x) >> 0) & 0x3)
1106 #define   C_028C70_ENDIAN                              0xFFFFFFFC
1107 #define   S_028C70_FORMAT(x)                           (((x) & 0x3F) << 2)
1108 #define   G_028C70_FORMAT(x)                           (((x) >> 2) & 0x3F)
1109 #define   C_028C70_FORMAT                              0xFFFFFF03
1110 #define     V_028C70_COLOR_INVALID                     0x00000000
1111 #define     V_028C70_COLOR_8                           0x00000001
1112 #define     V_028C70_COLOR_4_4                         0x00000002
1113 #define     V_028C70_COLOR_3_3_2                       0x00000003
1114 #define     V_028C70_COLOR_16                          0x00000005
1115 #define     V_028C70_COLOR_16_FLOAT                    0x00000006
1116 #define     V_028C70_COLOR_8_8                         0x00000007
1117 #define     V_028C70_COLOR_5_6_5                       0x00000008
1118 #define     V_028C70_COLOR_6_5_5                       0x00000009
1119 #define     V_028C70_COLOR_1_5_5_5                     0x0000000A
1120 #define     V_028C70_COLOR_4_4_4_4                     0x0000000B
1121 #define     V_028C70_COLOR_5_5_5_1                     0x0000000C
1122 #define     V_028C70_COLOR_32                          0x0000000D
1123 #define     V_028C70_COLOR_32_FLOAT                    0x0000000E
1124 #define     V_028C70_COLOR_16_16                       0x0000000F
1125 #define     V_028C70_COLOR_16_16_FLOAT                 0x00000010
1126 #define     V_028C70_COLOR_8_24                        0x00000011
1127 #define     V_028C70_COLOR_8_24_FLOAT                  0x00000012
1128 #define     V_028C70_COLOR_24_8                        0x00000013
1129 #define     V_028C70_COLOR_24_8_FLOAT                  0x00000014
1130 #define     V_028C70_COLOR_10_11_11                    0x00000015
1131 #define     V_028C70_COLOR_10_11_11_FLOAT              0x00000016
1132 #define     V_028C70_COLOR_11_11_10                    0x00000017
1133 #define     V_028C70_COLOR_11_11_10_FLOAT              0x00000018
1134 #define     V_028C70_COLOR_2_10_10_10                  0x00000019
1135 #define     V_028C70_COLOR_8_8_8_8                     0x0000001A
1136 #define     V_028C70_COLOR_10_10_10_2                  0x0000001B
1137 #define     V_028C70_COLOR_X24_8_32_FLOAT              0x0000001C
1138 #define     V_028C70_COLOR_32_32                       0x0000001D
1139 #define     V_028C70_COLOR_32_32_FLOAT                 0x0000001E
1140 #define     V_028C70_COLOR_16_16_16_16                 0x0000001F
1141 #define     V_028C70_COLOR_16_16_16_16_FLOAT           0x00000020
1142 #define     V_028C70_COLOR_32_32_32_32                 0x00000022
1143 #define     V_028C70_COLOR_32_32_32_32_FLOAT           0x00000023
1144 #define     V_028C70_COLOR_32_32_32_FLOAT              0x00000030
1145 #define   S_028C70_ARRAY_MODE(x)                       (((x) & 0xF) << 8)
1146 #define   G_028C70_ARRAY_MODE(x)                       (((x) >> 8) & 0xF)
1147 #define   C_028C70_ARRAY_MODE                          0xFFFFF0FF
1148 #define     V_028C70_ARRAY_LINEAR_GENERAL              0x00000000
1149 #define     V_028C70_ARRAY_LINEAR_ALIGNED              0x00000001
1150 #define     V_028C70_ARRAY_1D_TILED_THIN1              0x00000002
1151 #define     V_028C70_ARRAY_2D_TILED_THIN1              0x00000004
1152 #define   S_028C70_NUMBER_TYPE(x)                      (((x) & 0x7) << 12)
1153 #define   G_028C70_NUMBER_TYPE(x)                      (((x) >> 12) & 0x7)
1154 #define   C_028C70_NUMBER_TYPE                         0xFFFF8FFF
1155 #define     V_028C70_NUMBER_UNORM                      0x00000000
1156 #define     V_028C70_NUMBER_SNORM                      0x00000001
1157 #define     V_028C70_NUMBER_USCALED                    0x00000002
1158 #define     V_028C70_NUMBER_SSCALED                    0x00000003
1159 #define     V_028C70_NUMBER_UINT                       0x00000004
1160 #define     V_028C70_NUMBER_SINT                       0x00000005
1161 #define     V_028C70_NUMBER_SRGB                       0x00000006
1162 #define     V_028C70_NUMBER_FLOAT                      0x00000007
1163 #define   S_028C70_COMP_SWAP(x)                        (((x) & 0x3) << 15)
1164 #define   G_028C70_COMP_SWAP(x)                        (((x) >> 15) & 0x3)
1165 #define   C_028C70_COMP_SWAP                           0xFFFE7FFF
1166 #define     V_028C70_SWAP_STD                          0x00000000
1167 #define     V_028C70_SWAP_ALT                          0x00000001
1168 #define     V_028C70_SWAP_STD_REV                      0x00000002
1169 #define     V_028C70_SWAP_ALT_REV                      0x00000003
1170 #define   S_028C70_FAST_CLEAR(x)                       (((x) & 0x1) << 17)
1171 #define   G_028C70_FAST_CLEAR(x)                       (((x) >> 17) & 0x1)
1172 #define   C_028C70_FAST_CLEAR                          0xFFFDFFFF
1173 #define   S_028C70_COMPRESSION(x)                      (((x) & 0x3) << 18)
1174 #define   G_028C70_COMPRESSION(x)                      (((x) >> 18) & 0x3)
1175 #define   C_028C70_COMPRESSION                         0xFFF3FFFF
1176 #define   S_028C70_BLEND_CLAMP(x)                      (((x) & 0x1) << 19)
1177 #define   G_028C70_BLEND_CLAMP(x)                      (((x) >> 19) & 0x1)
1178 #define   C_028C70_BLEND_CLAMP                         0xFFF7FFFF
1179 #define   S_028C70_BLEND_BYPASS(x)                     (((x) & 0x1) << 20)
1180 #define   G_028C70_BLEND_BYPASS(x)                     (((x) >> 20) & 0x1)
1181 #define   C_028C70_BLEND_BYPASS                        0xFFEFFFFF
1182 #define   S_028C70_SIMPLE_FLOAT(x)                     (((x) & 0x1) << 21)
1183 #define   G_028C70_SIMPLE_FLOAT(x)                     (((x) >> 21) & 0x1)
1184 #define   C_028C70_SIMPLE_FLOAT                        0xFFDFFFFF
1185 #define   S_028C70_ROUND_MODE(x)                       (((x) & 0x1) << 22)
1186 #define   G_028C70_ROUND_MODE(x)                       (((x) >> 22) & 0x1)
1187 #define   C_028C70_ROUND_MODE                          0xFFBFFFFF
1188 #define   S_028C70_TILE_COMPACT(x)                     (((x) & 0x1) << 23)
1189 #define   G_028C70_TILE_COMPACT(x)                     (((x) >> 23) & 0x1)
1190 #define   C_028C70_TILE_COMPACT                        0xFF7FFFFF
1191 #define   S_028C70_SOURCE_FORMAT(x)                    (((x) & 0x3) << 24)
1192 #define   G_028C70_SOURCE_FORMAT(x)                    (((x) >> 24) & 0x3)
1193 #define   C_028C70_SOURCE_FORMAT                       0xFCFFFFFF
1194 #define     V_028C70_EXPORT_4C_32BPC                   0x0
1195 #define     V_028C70_EXPORT_4C_16BPC                   0x1
1196 #define     V_028C70_EXPORT_2C_32BPC                   0x2 /* Do not use */
1197 #define   S_028C70_RAT(x)                              (((x) & 0x1) << 26)
1198 #define   G_028C70_RAT(x)                              (((x) >> 26) & 0x1)
1199 #define   C_028C70_RAT                                 0xFBFFFFFF
1200 #define   S_028C70_RESOURCE_TYPE(x)                    (((x) & 0x7) << 27)
1201 #define   G_028C70_RESOURCE_TYPE(x)                    (((x) >> 27) & 0x7)
1202 #define   C_028C70_RESOURCE_TYPE                       0xC7FFFFFF
1203
1204 #define CB_COLOR0_INFO                                  0x28c70
1205 #       define CB_FORMAT(x)                             ((x) << 2)
1206 #       define CB_ARRAY_MODE(x)                         ((x) << 8)
1207 #       define ARRAY_LINEAR_GENERAL                     0
1208 #       define ARRAY_LINEAR_ALIGNED                     1
1209 #       define ARRAY_1D_TILED_THIN1                     2
1210 #       define ARRAY_2D_TILED_THIN1                     4
1211 #       define CB_SOURCE_FORMAT(x)                      ((x) << 24)
1212 #       define CB_SF_EXPORT_FULL                        0
1213 #       define CB_SF_EXPORT_NORM                        1
1214 #define R_028C74_CB_COLOR0_ATTRIB                      0x028C74
1215 #define   S_028C74_NON_DISP_TILING_ORDER(x)            (((x) & 0x1) << 4)
1216 #define   G_028C74_NON_DISP_TILING_ORDER(x)            (((x) >> 4) & 0x1)
1217 #define   C_028C74_NON_DISP_TILING_ORDER               0xFFFFFFEF
1218 #define   S_028C74_TILE_SPLIT(x)                       (((x) & 0xf) << 5)
1219 #define   G_028C74_TILE_SPLIT(x)                       (((x) >> 5) & 0xf)
1220 #define   S_028C74_NUM_BANKS(x)                        (((x) & 0x3) << 10)
1221 #define   G_028C74_NUM_BANKS(x)                        (((x) >> 10) & 0x3)
1222 #define   S_028C74_BANK_WIDTH(x)                       (((x) & 0x3) << 13)
1223 #define   G_028C74_BANK_WIDTH(x)                       (((x) >> 13) & 0x3)
1224 #define   S_028C74_BANK_HEIGHT(x)                      (((x) & 0x3) << 16)
1225 #define   G_028C74_BANK_HEIGHT(x)                      (((x) >> 16) & 0x3)
1226 #define   S_028C74_MACRO_TILE_ASPECT(x)                (((x) & 0x3) << 19)
1227 #define   G_028C74_MACRO_TILE_ASPECT(x)                (((x) >> 19) & 0x3)
1228 #define CB_COLOR0_ATTRIB                                0x28c74
1229 #       define CB_TILE_SPLIT(x)                         (((x) & 0x7) << 5)
1230 #       define ADDR_SURF_TILE_SPLIT_64B                 0
1231 #       define ADDR_SURF_TILE_SPLIT_128B                1
1232 #       define ADDR_SURF_TILE_SPLIT_256B                2
1233 #       define ADDR_SURF_TILE_SPLIT_512B                3
1234 #       define ADDR_SURF_TILE_SPLIT_1KB                 4
1235 #       define ADDR_SURF_TILE_SPLIT_2KB                 5
1236 #       define ADDR_SURF_TILE_SPLIT_4KB                 6
1237 #       define CB_NUM_BANKS(x)                          (((x) & 0x3) << 10)
1238 #       define ADDR_SURF_2_BANK                         0
1239 #       define ADDR_SURF_4_BANK                         1
1240 #       define ADDR_SURF_8_BANK                         2
1241 #       define ADDR_SURF_16_BANK                        3
1242 #       define CB_BANK_WIDTH(x)                         (((x) & 0x3) << 13)
1243 #       define ADDR_SURF_BANK_WIDTH_1                   0
1244 #       define ADDR_SURF_BANK_WIDTH_2                   1
1245 #       define ADDR_SURF_BANK_WIDTH_4                   2
1246 #       define ADDR_SURF_BANK_WIDTH_8                   3
1247 #       define CB_BANK_HEIGHT(x)                        (((x) & 0x3) << 16)
1248 #       define ADDR_SURF_BANK_HEIGHT_1                  0
1249 #       define ADDR_SURF_BANK_HEIGHT_2                  1
1250 #       define ADDR_SURF_BANK_HEIGHT_4                  2
1251 #       define ADDR_SURF_BANK_HEIGHT_8                  3
1252 #       define CB_MACRO_TILE_ASPECT(x)                  (((x) & 0x3) << 19)
1253 #define CB_COLOR0_DIM                                   0x28c78
1254 /* only CB0-7 blocks have these regs */
1255 #define CB_COLOR0_CMASK                                 0x28c7c
1256 #define CB_COLOR0_CMASK_SLICE                           0x28c80
1257 #define CB_COLOR0_FMASK                                 0x28c84
1258 #define CB_COLOR0_FMASK_SLICE                           0x28c88
1259 #define CB_COLOR0_CLEAR_WORD0                           0x28c8c
1260 #define CB_COLOR0_CLEAR_WORD1                           0x28c90
1261 #define CB_COLOR0_CLEAR_WORD2                           0x28c94
1262 #define CB_COLOR0_CLEAR_WORD3                           0x28c98
1263
1264 #define CB_COLOR1_BASE                                  0x28c9c
1265 #define CB_COLOR2_BASE                                  0x28cd8
1266 #define CB_COLOR3_BASE                                  0x28d14
1267 #define CB_COLOR4_BASE                                  0x28d50
1268 #define CB_COLOR5_BASE                                  0x28d8c
1269 #define CB_COLOR6_BASE                                  0x28dc8
1270 #define CB_COLOR7_BASE                                  0x28e04
1271 #define CB_COLOR8_BASE                                  0x28e40
1272 #define CB_COLOR9_BASE                                  0x28e5c
1273 #define CB_COLOR10_BASE                                 0x28e78
1274 #define CB_COLOR11_BASE                                 0x28e94
1275
1276 #define CB_COLOR1_PITCH                                 0x28ca0
1277 #define CB_COLOR2_PITCH                                 0x28cdc
1278 #define CB_COLOR3_PITCH                                 0x28d18
1279 #define CB_COLOR4_PITCH                                 0x28d54
1280 #define CB_COLOR5_PITCH                                 0x28d90
1281 #define CB_COLOR6_PITCH                                 0x28dcc
1282 #define CB_COLOR7_PITCH                                 0x28e08
1283 #define CB_COLOR8_PITCH                                 0x28e44
1284 #define CB_COLOR9_PITCH                                 0x28e60
1285 #define CB_COLOR10_PITCH                                0x28e7c
1286 #define CB_COLOR11_PITCH                                0x28e98
1287
1288 #define CB_COLOR1_SLICE                                 0x28ca4
1289 #define CB_COLOR2_SLICE                                 0x28ce0
1290 #define CB_COLOR3_SLICE                                 0x28d1c
1291 #define CB_COLOR4_SLICE                                 0x28d58
1292 #define CB_COLOR5_SLICE                                 0x28d94
1293 #define CB_COLOR6_SLICE                                 0x28dd0
1294 #define CB_COLOR7_SLICE                                 0x28e0c
1295 #define CB_COLOR8_SLICE                                 0x28e48
1296 #define CB_COLOR9_SLICE                                 0x28e64
1297 #define CB_COLOR10_SLICE                                0x28e80
1298 #define CB_COLOR11_SLICE                                0x28e9c
1299
1300 #define CB_COLOR1_VIEW                                  0x28ca8
1301 #define CB_COLOR2_VIEW                                  0x28ce4
1302 #define CB_COLOR3_VIEW                                  0x28d20
1303 #define CB_COLOR4_VIEW                                  0x28d5c
1304 #define CB_COLOR5_VIEW                                  0x28d98
1305 #define CB_COLOR6_VIEW                                  0x28dd4
1306 #define CB_COLOR7_VIEW                                  0x28e10
1307 #define CB_COLOR8_VIEW                                  0x28e4c
1308 #define CB_COLOR9_VIEW                                  0x28e68
1309 #define CB_COLOR10_VIEW                                 0x28e84
1310 #define CB_COLOR11_VIEW                                 0x28ea0
1311
1312 #define CB_COLOR1_INFO                                  0x28cac
1313 #define CB_COLOR2_INFO                                  0x28ce8
1314 #define CB_COLOR3_INFO                                  0x28d24
1315 #define CB_COLOR4_INFO                                  0x28d60
1316 #define CB_COLOR5_INFO                                  0x28d9c
1317 #define CB_COLOR6_INFO                                  0x28dd8
1318 #define CB_COLOR7_INFO                                  0x28e14
1319 #define CB_COLOR8_INFO                                  0x28e50
1320 #define CB_COLOR9_INFO                                  0x28e6c
1321 #define CB_COLOR10_INFO                                 0x28e88
1322 #define CB_COLOR11_INFO                                 0x28ea4
1323
1324 #define CB_COLOR1_ATTRIB                                0x28cb0
1325 #define CB_COLOR2_ATTRIB                                0x28cec
1326 #define CB_COLOR3_ATTRIB                                0x28d28
1327 #define CB_COLOR4_ATTRIB                                0x28d64
1328 #define CB_COLOR5_ATTRIB                                0x28da0
1329 #define CB_COLOR6_ATTRIB                                0x28ddc
1330 #define CB_COLOR7_ATTRIB                                0x28e18
1331 #define CB_COLOR8_ATTRIB                                0x28e54
1332 #define CB_COLOR9_ATTRIB                                0x28e70
1333 #define CB_COLOR10_ATTRIB                               0x28e8c
1334 #define CB_COLOR11_ATTRIB                               0x28ea8
1335
1336 #define CB_COLOR1_DIM                                   0x28cb4
1337 #define CB_COLOR2_DIM                                   0x28cf0
1338 #define CB_COLOR3_DIM                                   0x28d2c
1339 #define CB_COLOR4_DIM                                   0x28d68
1340 #define CB_COLOR5_DIM                                   0x28da4
1341 #define CB_COLOR6_DIM                                   0x28de0
1342 #define CB_COLOR7_DIM                                   0x28e1c
1343 #define CB_COLOR8_DIM                                   0x28e58
1344 #define CB_COLOR9_DIM                                   0x28e74
1345 #define CB_COLOR10_DIM                                  0x28e90
1346 #define CB_COLOR11_DIM                                  0x28eac
1347
1348 #define CB_COLOR1_CMASK                                 0x28cb8
1349 #define CB_COLOR2_CMASK                                 0x28cf4
1350 #define CB_COLOR3_CMASK                                 0x28d30
1351 #define CB_COLOR4_CMASK                                 0x28d6c
1352 #define CB_COLOR5_CMASK                                 0x28da8
1353 #define CB_COLOR6_CMASK                                 0x28de4
1354 #define CB_COLOR7_CMASK                                 0x28e20
1355
1356 #define CB_COLOR1_CMASK_SLICE                           0x28cbc
1357 #define CB_COLOR2_CMASK_SLICE                           0x28cf8
1358 #define CB_COLOR3_CMASK_SLICE                           0x28d34
1359 #define CB_COLOR4_CMASK_SLICE                           0x28d70
1360 #define CB_COLOR5_CMASK_SLICE                           0x28dac
1361 #define CB_COLOR6_CMASK_SLICE                           0x28de8
1362 #define CB_COLOR7_CMASK_SLICE                           0x28e24
1363
1364 #define CB_COLOR1_FMASK                                 0x28cc0
1365 #define CB_COLOR2_FMASK                                 0x28cfc
1366 #define CB_COLOR3_FMASK                                 0x28d38
1367 #define CB_COLOR4_FMASK                                 0x28d74
1368 #define CB_COLOR5_FMASK                                 0x28db0
1369 #define CB_COLOR6_FMASK                                 0x28dec
1370 #define CB_COLOR7_FMASK                                 0x28e28
1371
1372 #define CB_COLOR1_FMASK_SLICE                           0x28cc4
1373 #define CB_COLOR2_FMASK_SLICE                           0x28d00
1374 #define CB_COLOR3_FMASK_SLICE                           0x28d3c
1375 #define CB_COLOR4_FMASK_SLICE                           0x28d78
1376 #define CB_COLOR5_FMASK_SLICE                           0x28db4
1377 #define CB_COLOR6_FMASK_SLICE                           0x28df0
1378 #define CB_COLOR7_FMASK_SLICE                           0x28e2c
1379
1380 #define CB_COLOR1_CLEAR_WORD0                           0x28cc8
1381 #define CB_COLOR2_CLEAR_WORD0                           0x28d04
1382 #define CB_COLOR3_CLEAR_WORD0                           0x28d40
1383 #define CB_COLOR4_CLEAR_WORD0                           0x28d7c
1384 #define CB_COLOR5_CLEAR_WORD0                           0x28db8
1385 #define CB_COLOR6_CLEAR_WORD0                           0x28df4
1386 #define CB_COLOR7_CLEAR_WORD0                           0x28e30
1387
1388 #define CB_COLOR1_CLEAR_WORD1                           0x28ccc
1389 #define CB_COLOR2_CLEAR_WORD1                           0x28d08
1390 #define CB_COLOR3_CLEAR_WORD1                           0x28d44
1391 #define CB_COLOR4_CLEAR_WORD1                           0x28d80
1392 #define CB_COLOR5_CLEAR_WORD1                           0x28dbc
1393 #define CB_COLOR6_CLEAR_WORD1                           0x28df8
1394 #define CB_COLOR7_CLEAR_WORD1                           0x28e34
1395
1396 #define CB_COLOR1_CLEAR_WORD2                           0x28cd0
1397 #define CB_COLOR2_CLEAR_WORD2                           0x28d0c
1398 #define CB_COLOR3_CLEAR_WORD2                           0x28d48
1399 #define CB_COLOR4_CLEAR_WORD2                           0x28d84
1400 #define CB_COLOR5_CLEAR_WORD2                           0x28dc0
1401 #define CB_COLOR6_CLEAR_WORD2                           0x28dfc
1402 #define CB_COLOR7_CLEAR_WORD2                           0x28e38
1403
1404 #define CB_COLOR1_CLEAR_WORD3                           0x28cd4
1405 #define CB_COLOR2_CLEAR_WORD3                           0x28d10
1406 #define CB_COLOR3_CLEAR_WORD3                           0x28d4c
1407 #define CB_COLOR4_CLEAR_WORD3                           0x28d88
1408 #define CB_COLOR5_CLEAR_WORD3                           0x28dc4
1409 #define CB_COLOR6_CLEAR_WORD3                           0x28e00
1410 #define CB_COLOR7_CLEAR_WORD3                           0x28e3c
1411
1412 #define SQ_TEX_RESOURCE_WORD0_0                         0x30000
1413 #       define TEX_DIM(x)                               ((x) << 0)
1414 #       define SQ_TEX_DIM_1D                            0
1415 #       define SQ_TEX_DIM_2D                            1
1416 #       define SQ_TEX_DIM_3D                            2
1417 #       define SQ_TEX_DIM_CUBEMAP                       3
1418 #       define SQ_TEX_DIM_1D_ARRAY                      4
1419 #       define SQ_TEX_DIM_2D_ARRAY                      5
1420 #       define SQ_TEX_DIM_2D_MSAA                       6
1421 #       define SQ_TEX_DIM_2D_ARRAY_MSAA                 7
1422 #define SQ_TEX_RESOURCE_WORD1_0                         0x30004
1423 #       define TEX_ARRAY_MODE(x)                        ((x) << 28)
1424 #define SQ_TEX_RESOURCE_WORD2_0                         0x30008
1425 #define SQ_TEX_RESOURCE_WORD3_0                         0x3000C
1426 #define SQ_TEX_RESOURCE_WORD4_0                         0x30010
1427 #       define TEX_DST_SEL_X(x)                         ((x) << 16)
1428 #       define TEX_DST_SEL_Y(x)                         ((x) << 19)
1429 #       define TEX_DST_SEL_Z(x)                         ((x) << 22)
1430 #       define TEX_DST_SEL_W(x)                         ((x) << 25)
1431 #       define SQ_SEL_X                                 0
1432 #       define SQ_SEL_Y                                 1
1433 #       define SQ_SEL_Z                                 2
1434 #       define SQ_SEL_W                                 3
1435 #       define SQ_SEL_0                                 4
1436 #       define SQ_SEL_1                                 5
1437 #define SQ_TEX_RESOURCE_WORD5_0                         0x30014
1438 #define SQ_TEX_RESOURCE_WORD6_0                         0x30018
1439 #       define TEX_TILE_SPLIT(x)                        (((x) & 0x7) << 29)
1440 #define SQ_TEX_RESOURCE_WORD7_0                         0x3001c
1441 #       define MACRO_TILE_ASPECT(x)                     (((x) & 0x3) << 6)
1442 #       define TEX_BANK_WIDTH(x)                        (((x) & 0x3) << 8)
1443 #       define TEX_BANK_HEIGHT(x)                       (((x) & 0x3) << 10)
1444 #       define TEX_NUM_BANKS(x)                         (((x) & 0x3) << 16)
1445 #define R_030000_SQ_TEX_RESOURCE_WORD0_0             0x030000
1446 #define   S_030000_DIM(x)                              (((x) & 0x7) << 0)
1447 #define   G_030000_DIM(x)                              (((x) >> 0) & 0x7)
1448 #define   C_030000_DIM                                 0xFFFFFFF8
1449 #define     V_030000_SQ_TEX_DIM_1D                     0x00000000
1450 #define     V_030000_SQ_TEX_DIM_2D                     0x00000001
1451 #define     V_030000_SQ_TEX_DIM_3D                     0x00000002
1452 #define     V_030000_SQ_TEX_DIM_CUBEMAP                0x00000003
1453 #define     V_030000_SQ_TEX_DIM_1D_ARRAY               0x00000004
1454 #define     V_030000_SQ_TEX_DIM_2D_ARRAY               0x00000005
1455 #define     V_030000_SQ_TEX_DIM_2D_MSAA                0x00000006
1456 #define     V_030000_SQ_TEX_DIM_2D_ARRAY_MSAA          0x00000007
1457 #define   S_030000_NON_DISP_TILING_ORDER(x)            (((x) & 0x1) << 5)
1458 #define   G_030000_NON_DISP_TILING_ORDER(x)            (((x) >> 5) & 0x1)
1459 #define   C_030000_NON_DISP_TILING_ORDER               0xFFFFFFDF
1460 #define   S_030000_PITCH(x)                            (((x) & 0xFFF) << 6)
1461 #define   G_030000_PITCH(x)                            (((x) >> 6) & 0xFFF)
1462 #define   C_030000_PITCH                               0xFFFC003F
1463 #define   S_030000_TEX_WIDTH(x)                        (((x) & 0x3FFF) << 18)
1464 #define   G_030000_TEX_WIDTH(x)                        (((x) >> 18) & 0x3FFF)
1465 #define   C_030000_TEX_WIDTH                           0x0003FFFF
1466 #define R_030004_SQ_TEX_RESOURCE_WORD1_0             0x030004
1467 #define   S_030004_TEX_HEIGHT(x)                       (((x) & 0x3FFF) << 0)
1468 #define   G_030004_TEX_HEIGHT(x)                       (((x) >> 0) & 0x3FFF)
1469 #define   C_030004_TEX_HEIGHT                          0xFFFFC000
1470 #define   S_030004_TEX_DEPTH(x)                        (((x) & 0x1FFF) << 14)
1471 #define   G_030004_TEX_DEPTH(x)                        (((x) >> 14) & 0x1FFF)
1472 #define   C_030004_TEX_DEPTH                           0xF8003FFF
1473 #define   S_030004_ARRAY_MODE(x)                       (((x) & 0xF) << 28)
1474 #define   G_030004_ARRAY_MODE(x)                       (((x) >> 28) & 0xF)
1475 #define   C_030004_ARRAY_MODE                          0x0FFFFFFF
1476 #define R_030008_SQ_TEX_RESOURCE_WORD2_0             0x030008
1477 #define   S_030008_BASE_ADDRESS(x)                     (((x) & 0xFFFFFFFF) << 0)
1478 #define   G_030008_BASE_ADDRESS(x)                     (((x) >> 0) & 0xFFFFFFFF)
1479 #define   C_030008_BASE_ADDRESS                        0x00000000
1480 #define R_03000C_SQ_TEX_RESOURCE_WORD3_0             0x03000C
1481 #define   S_03000C_MIP_ADDRESS(x)                      (((x) & 0xFFFFFFFF) << 0)
1482 #define   G_03000C_MIP_ADDRESS(x)                      (((x) >> 0) & 0xFFFFFFFF)
1483 #define   C_03000C_MIP_ADDRESS                         0x00000000
1484 #define R_030010_SQ_TEX_RESOURCE_WORD4_0             0x030010
1485 #define   S_030010_FORMAT_COMP_X(x)                    (((x) & 0x3) << 0)
1486 #define   G_030010_FORMAT_COMP_X(x)                    (((x) >> 0) & 0x3)
1487 #define   C_030010_FORMAT_COMP_X                       0xFFFFFFFC
1488 #define     V_030010_SQ_FORMAT_COMP_UNSIGNED           0x00000000
1489 #define     V_030010_SQ_FORMAT_COMP_SIGNED             0x00000001
1490 #define     V_030010_SQ_FORMAT_COMP_UNSIGNED_BIASED    0x00000002
1491 #define   S_030010_FORMAT_COMP_Y(x)                    (((x) & 0x3) << 2)
1492 #define   G_030010_FORMAT_COMP_Y(x)                    (((x) >> 2) & 0x3)
1493 #define   C_030010_FORMAT_COMP_Y                       0xFFFFFFF3
1494 #define   S_030010_FORMAT_COMP_Z(x)                    (((x) & 0x3) << 4)
1495 #define   G_030010_FORMAT_COMP_Z(x)                    (((x) >> 4) & 0x3)
1496 #define   C_030010_FORMAT_COMP_Z                       0xFFFFFFCF
1497 #define   S_030010_FORMAT_COMP_W(x)                    (((x) & 0x3) << 6)
1498 #define   G_030010_FORMAT_COMP_W(x)                    (((x) >> 6) & 0x3)
1499 #define   C_030010_FORMAT_COMP_W                       0xFFFFFF3F
1500 #define   S_030010_NUM_FORMAT_ALL(x)                   (((x) & 0x3) << 8)
1501 #define   G_030010_NUM_FORMAT_ALL(x)                   (((x) >> 8) & 0x3)
1502 #define   C_030010_NUM_FORMAT_ALL                      0xFFFFFCFF
1503 #define     V_030010_SQ_NUM_FORMAT_NORM                0x00000000
1504 #define     V_030010_SQ_NUM_FORMAT_INT                 0x00000001
1505 #define     V_030010_SQ_NUM_FORMAT_SCALED              0x00000002
1506 #define   S_030010_SRF_MODE_ALL(x)                     (((x) & 0x1) << 10)
1507 #define   G_030010_SRF_MODE_ALL(x)                     (((x) >> 10) & 0x1)
1508 #define   C_030010_SRF_MODE_ALL                        0xFFFFFBFF
1509 #define     V_030010_SRF_MODE_ZERO_CLAMP_MINUS_ONE     0x00000000
1510 #define     V_030010_SRF_MODE_NO_ZERO                  0x00000001
1511 #define   S_030010_FORCE_DEGAMMA(x)                    (((x) & 0x1) << 11)
1512 #define   G_030010_FORCE_DEGAMMA(x)                    (((x) >> 11) & 0x1)
1513 #define   C_030010_FORCE_DEGAMMA                       0xFFFFF7FF
1514 #define   S_030010_ENDIAN_SWAP(x)                      (((x) & 0x3) << 12)
1515 #define   G_030010_ENDIAN_SWAP(x)                      (((x) >> 12) & 0x3)
1516 #define   C_030010_ENDIAN_SWAP                         0xFFFFCFFF
1517 #define   S_030010_DST_SEL_X(x)                        (((x) & 0x7) << 16)
1518 #define   G_030010_DST_SEL_X(x)                        (((x) >> 16) & 0x7)
1519 #define   C_030010_DST_SEL_X                           0xFFF8FFFF
1520 #define     V_030010_SQ_SEL_X                          0x00000000
1521 #define     V_030010_SQ_SEL_Y                          0x00000001
1522 #define     V_030010_SQ_SEL_Z                          0x00000002
1523 #define     V_030010_SQ_SEL_W                          0x00000003
1524 #define     V_030010_SQ_SEL_0                          0x00000004
1525 #define     V_030010_SQ_SEL_1                          0x00000005
1526 #define   S_030010_DST_SEL_Y(x)                        (((x) & 0x7) << 19)
1527 #define   G_030010_DST_SEL_Y(x)                        (((x) >> 19) & 0x7)
1528 #define   C_030010_DST_SEL_Y                           0xFFC7FFFF
1529 #define   S_030010_DST_SEL_Z(x)                        (((x) & 0x7) << 22)
1530 #define   G_030010_DST_SEL_Z(x)                        (((x) >> 22) & 0x7)
1531 #define   C_030010_DST_SEL_Z                           0xFE3FFFFF
1532 #define   S_030010_DST_SEL_W(x)                        (((x) & 0x7) << 25)
1533 #define   G_030010_DST_SEL_W(x)                        (((x) >> 25) & 0x7)
1534 #define   C_030010_DST_SEL_W                           0xF1FFFFFF
1535 #define   S_030010_BASE_LEVEL(x)                       (((x) & 0xF) << 28)
1536 #define   G_030010_BASE_LEVEL(x)                       (((x) >> 28) & 0xF)
1537 #define   C_030010_BASE_LEVEL                          0x0FFFFFFF
1538 #define R_030014_SQ_TEX_RESOURCE_WORD5_0             0x030014
1539 #define   S_030014_LAST_LEVEL(x)                       (((x) & 0xF) << 0)
1540 #define   G_030014_LAST_LEVEL(x)                       (((x) >> 0) & 0xF)
1541 #define   C_030014_LAST_LEVEL                          0xFFFFFFF0
1542 #define   S_030014_BASE_ARRAY(x)                       (((x) & 0x1FFF) << 4)
1543 #define   G_030014_BASE_ARRAY(x)                       (((x) >> 4) & 0x1FFF)
1544 #define   C_030014_BASE_ARRAY                          0xFFFE000F
1545 #define   S_030014_LAST_ARRAY(x)                       (((x) & 0x1FFF) << 17)
1546 #define   G_030014_LAST_ARRAY(x)                       (((x) >> 17) & 0x1FFF)
1547 #define   C_030014_LAST_ARRAY                          0xC001FFFF
1548 #define R_030018_SQ_TEX_RESOURCE_WORD6_0             0x030018
1549 #define   S_030018_MAX_ANISO(x)                        (((x) & 0x7) << 0)
1550 #define   G_030018_MAX_ANISO(x)                        (((x) >> 0) & 0x7)
1551 #define   C_030018_MAX_ANISO                           0xFFFFFFF8
1552 #define   S_030018_PERF_MODULATION(x)                  (((x) & 0x7) << 3)
1553 #define   G_030018_PERF_MODULATION(x)                  (((x) >> 3) & 0x7)
1554 #define   C_030018_PERF_MODULATION                     0xFFFFFFC7
1555 #define   S_030018_INTERLACED(x)                       (((x) & 0x1) << 6)
1556 #define   G_030018_INTERLACED(x)                       (((x) >> 6) & 0x1)
1557 #define   C_030018_INTERLACED                          0xFFFFFFBF
1558 #define   S_030018_TILE_SPLIT(x)                       (((x) & 0x7) << 29)
1559 #define   G_030018_TILE_SPLIT(x)                       (((x) >> 29) & 0x7)
1560 #define R_03001C_SQ_TEX_RESOURCE_WORD7_0             0x03001C
1561 #define   S_03001C_MACRO_TILE_ASPECT(x)                (((x) & 0x3) << 6)
1562 #define   G_03001C_MACRO_TILE_ASPECT(x)                (((x) >> 6) & 0x3)
1563 #define   S_03001C_BANK_WIDTH(x)                       (((x) & 0x3) << 8)
1564 #define   G_03001C_BANK_WIDTH(x)                       (((x) >> 8) & 0x3)
1565 #define   S_03001C_BANK_HEIGHT(x)                      (((x) & 0x3) << 10)
1566 #define   G_03001C_BANK_HEIGHT(x)                      (((x) >> 10) & 0x3)
1567 #define   S_03001C_NUM_BANKS(x)                        (((x) & 0x3) << 16)
1568 #define   G_03001C_NUM_BANKS(x)                        (((x) >> 16) & 0x3)
1569 #define   S_03001C_TYPE(x)                             (((x) & 0x3) << 30)
1570 #define   G_03001C_TYPE(x)                             (((x) >> 30) & 0x3)
1571 #define   C_03001C_TYPE                                0x3FFFFFFF
1572 #define     V_03001C_SQ_TEX_VTX_INVALID_TEXTURE        0x00000000
1573 #define     V_03001C_SQ_TEX_VTX_INVALID_BUFFER         0x00000001
1574 #define     V_03001C_SQ_TEX_VTX_VALID_TEXTURE          0x00000002
1575 #define     V_03001C_SQ_TEX_VTX_VALID_BUFFER           0x00000003
1576 #define   S_03001C_DATA_FORMAT(x)                      (((x) & 0x3F) << 0)
1577 #define   G_03001C_DATA_FORMAT(x)                      (((x) >> 0) & 0x3F)
1578 #define   C_03001C_DATA_FORMAT                         0xFFFFFFC0
1579
1580 #define SQ_VTX_CONSTANT_WORD0_0                         0x30000
1581 #define SQ_VTX_CONSTANT_WORD1_0                         0x30004
1582 #define SQ_VTX_CONSTANT_WORD2_0                         0x30008
1583 #       define SQ_VTXC_BASE_ADDR_HI(x)                  ((x) << 0)
1584 #       define SQ_VTXC_STRIDE(x)                        ((x) << 8)
1585 #       define SQ_VTXC_ENDIAN_SWAP(x)                   ((x) << 30)
1586 #       define SQ_ENDIAN_NONE                           0
1587 #       define SQ_ENDIAN_8IN16                          1
1588 #       define SQ_ENDIAN_8IN32                          2
1589 #define SQ_VTX_CONSTANT_WORD3_0                         0x3000C
1590 #       define SQ_VTCX_SEL_X(x)                         ((x) << 3)
1591 #       define SQ_VTCX_SEL_Y(x)                         ((x) << 6)
1592 #       define SQ_VTCX_SEL_Z(x)                         ((x) << 9)
1593 #       define SQ_VTCX_SEL_W(x)                         ((x) << 12)
1594 #define SQ_VTX_CONSTANT_WORD4_0                         0x30010
1595 #define SQ_VTX_CONSTANT_WORD5_0                         0x30014
1596 #define SQ_VTX_CONSTANT_WORD6_0                         0x30018
1597 #define SQ_VTX_CONSTANT_WORD7_0                         0x3001c
1598
1599 #define TD_PS_BORDER_COLOR_INDEX                        0xA400
1600 #define TD_PS_BORDER_COLOR_RED                          0xA404
1601 #define TD_PS_BORDER_COLOR_GREEN                        0xA408
1602 #define TD_PS_BORDER_COLOR_BLUE                         0xA40C
1603 #define TD_PS_BORDER_COLOR_ALPHA                        0xA410
1604 #define TD_VS_BORDER_COLOR_INDEX                        0xA414
1605 #define TD_VS_BORDER_COLOR_RED                          0xA418
1606 #define TD_VS_BORDER_COLOR_GREEN                        0xA41C
1607 #define TD_VS_BORDER_COLOR_BLUE                         0xA420
1608 #define TD_VS_BORDER_COLOR_ALPHA                        0xA424
1609 #define TD_GS_BORDER_COLOR_INDEX                        0xA428
1610 #define TD_GS_BORDER_COLOR_RED                          0xA42C
1611 #define TD_GS_BORDER_COLOR_GREEN                        0xA430
1612 #define TD_GS_BORDER_COLOR_BLUE                         0xA434
1613 #define TD_GS_BORDER_COLOR_ALPHA                        0xA438
1614 #define TD_HS_BORDER_COLOR_INDEX                        0xA43C
1615 #define TD_HS_BORDER_COLOR_RED                          0xA440
1616 #define TD_HS_BORDER_COLOR_GREEN                        0xA444
1617 #define TD_HS_BORDER_COLOR_BLUE                         0xA448
1618 #define TD_HS_BORDER_COLOR_ALPHA                        0xA44C
1619 #define TD_LS_BORDER_COLOR_INDEX                        0xA450
1620 #define TD_LS_BORDER_COLOR_RED                          0xA454
1621 #define TD_LS_BORDER_COLOR_GREEN                        0xA458
1622 #define TD_LS_BORDER_COLOR_BLUE                         0xA45C
1623 #define TD_LS_BORDER_COLOR_ALPHA                        0xA460
1624 #define TD_CS_BORDER_COLOR_INDEX                        0xA464
1625 #define TD_CS_BORDER_COLOR_RED                          0xA468
1626 #define TD_CS_BORDER_COLOR_GREEN                        0xA46C
1627 #define TD_CS_BORDER_COLOR_BLUE                         0xA470
1628 #define TD_CS_BORDER_COLOR_ALPHA                        0xA474
1629
1630 /* cayman 3D regs */
1631 #define CAYMAN_VGT_OFFCHIP_LDS_BASE                     0x89B4
1632 #define CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS                  0x8E48
1633 #define CAYMAN_DB_EQAA                                  0x28804
1634 #define CAYMAN_DB_DEPTH_INFO                            0x2803C
1635 #define CAYMAN_PA_SC_AA_CONFIG                          0x28BE0
1636 #define         CAYMAN_MSAA_NUM_SAMPLES_SHIFT           0
1637 #define         CAYMAN_MSAA_NUM_SAMPLES_MASK            0x7
1638 #define CAYMAN_SX_SCATTER_EXPORT_BASE                   0x28358
1639 /* cayman packet3 addition */
1640 #define CAYMAN_PACKET3_DEALLOC_STATE                    0x14
1641
1642 #endif