drm/radeon/kms: implement display watermark support for evergreen
[linux-2.6.git] / drivers / gpu / drm / radeon / evergreen.c
1 /*
2  * Copyright 2010 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Alex Deucher
23  */
24 #include <linux/firmware.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
27 #include "drmP.h"
28 #include "radeon.h"
29 #include "radeon_asic.h"
30 #include "radeon_drm.h"
31 #include "evergreend.h"
32 #include "atom.h"
33 #include "avivod.h"
34 #include "evergreen_reg.h"
35
36 #define EVERGREEN_PFP_UCODE_SIZE 1120
37 #define EVERGREEN_PM4_UCODE_SIZE 1376
38
39 static void evergreen_gpu_init(struct radeon_device *rdev);
40 void evergreen_fini(struct radeon_device *rdev);
41
42 /* get temperature in millidegrees */
43 u32 evergreen_get_temp(struct radeon_device *rdev)
44 {
45         u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
46                 ASIC_T_SHIFT;
47         u32 actual_temp = 0;
48
49         if ((temp >> 10) & 1)
50                 actual_temp = 0;
51         else if ((temp >> 9) & 1)
52                 actual_temp = 255;
53         else
54                 actual_temp = (temp >> 1) & 0xff;
55
56         return actual_temp * 1000;
57 }
58
59 void evergreen_pm_misc(struct radeon_device *rdev)
60 {
61         int req_ps_idx = rdev->pm.requested_power_state_index;
62         int req_cm_idx = rdev->pm.requested_clock_mode_index;
63         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
64         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
65
66         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
67                 if (voltage->voltage != rdev->pm.current_vddc) {
68                         radeon_atom_set_voltage(rdev, voltage->voltage);
69                         rdev->pm.current_vddc = voltage->voltage;
70                         DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
71                 }
72         }
73 }
74
75 void evergreen_pm_prepare(struct radeon_device *rdev)
76 {
77         struct drm_device *ddev = rdev->ddev;
78         struct drm_crtc *crtc;
79         struct radeon_crtc *radeon_crtc;
80         u32 tmp;
81
82         /* disable any active CRTCs */
83         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
84                 radeon_crtc = to_radeon_crtc(crtc);
85                 if (radeon_crtc->enabled) {
86                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
87                         tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
88                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
89                 }
90         }
91 }
92
93 void evergreen_pm_finish(struct radeon_device *rdev)
94 {
95         struct drm_device *ddev = rdev->ddev;
96         struct drm_crtc *crtc;
97         struct radeon_crtc *radeon_crtc;
98         u32 tmp;
99
100         /* enable any active CRTCs */
101         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
102                 radeon_crtc = to_radeon_crtc(crtc);
103                 if (radeon_crtc->enabled) {
104                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
105                         tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
106                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
107                 }
108         }
109 }
110
111 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
112 {
113         bool connected = false;
114
115         switch (hpd) {
116         case RADEON_HPD_1:
117                 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
118                         connected = true;
119                 break;
120         case RADEON_HPD_2:
121                 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
122                         connected = true;
123                 break;
124         case RADEON_HPD_3:
125                 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
126                         connected = true;
127                 break;
128         case RADEON_HPD_4:
129                 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
130                         connected = true;
131                 break;
132         case RADEON_HPD_5:
133                 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
134                         connected = true;
135                 break;
136         case RADEON_HPD_6:
137                 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
138                         connected = true;
139                         break;
140         default:
141                 break;
142         }
143
144         return connected;
145 }
146
147 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
148                                 enum radeon_hpd_id hpd)
149 {
150         u32 tmp;
151         bool connected = evergreen_hpd_sense(rdev, hpd);
152
153         switch (hpd) {
154         case RADEON_HPD_1:
155                 tmp = RREG32(DC_HPD1_INT_CONTROL);
156                 if (connected)
157                         tmp &= ~DC_HPDx_INT_POLARITY;
158                 else
159                         tmp |= DC_HPDx_INT_POLARITY;
160                 WREG32(DC_HPD1_INT_CONTROL, tmp);
161                 break;
162         case RADEON_HPD_2:
163                 tmp = RREG32(DC_HPD2_INT_CONTROL);
164                 if (connected)
165                         tmp &= ~DC_HPDx_INT_POLARITY;
166                 else
167                         tmp |= DC_HPDx_INT_POLARITY;
168                 WREG32(DC_HPD2_INT_CONTROL, tmp);
169                 break;
170         case RADEON_HPD_3:
171                 tmp = RREG32(DC_HPD3_INT_CONTROL);
172                 if (connected)
173                         tmp &= ~DC_HPDx_INT_POLARITY;
174                 else
175                         tmp |= DC_HPDx_INT_POLARITY;
176                 WREG32(DC_HPD3_INT_CONTROL, tmp);
177                 break;
178         case RADEON_HPD_4:
179                 tmp = RREG32(DC_HPD4_INT_CONTROL);
180                 if (connected)
181                         tmp &= ~DC_HPDx_INT_POLARITY;
182                 else
183                         tmp |= DC_HPDx_INT_POLARITY;
184                 WREG32(DC_HPD4_INT_CONTROL, tmp);
185                 break;
186         case RADEON_HPD_5:
187                 tmp = RREG32(DC_HPD5_INT_CONTROL);
188                 if (connected)
189                         tmp &= ~DC_HPDx_INT_POLARITY;
190                 else
191                         tmp |= DC_HPDx_INT_POLARITY;
192                 WREG32(DC_HPD5_INT_CONTROL, tmp);
193                         break;
194         case RADEON_HPD_6:
195                 tmp = RREG32(DC_HPD6_INT_CONTROL);
196                 if (connected)
197                         tmp &= ~DC_HPDx_INT_POLARITY;
198                 else
199                         tmp |= DC_HPDx_INT_POLARITY;
200                 WREG32(DC_HPD6_INT_CONTROL, tmp);
201                 break;
202         default:
203                 break;
204         }
205 }
206
207 void evergreen_hpd_init(struct radeon_device *rdev)
208 {
209         struct drm_device *dev = rdev->ddev;
210         struct drm_connector *connector;
211         u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
212                 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
213
214         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
215                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
216                 switch (radeon_connector->hpd.hpd) {
217                 case RADEON_HPD_1:
218                         WREG32(DC_HPD1_CONTROL, tmp);
219                         rdev->irq.hpd[0] = true;
220                         break;
221                 case RADEON_HPD_2:
222                         WREG32(DC_HPD2_CONTROL, tmp);
223                         rdev->irq.hpd[1] = true;
224                         break;
225                 case RADEON_HPD_3:
226                         WREG32(DC_HPD3_CONTROL, tmp);
227                         rdev->irq.hpd[2] = true;
228                         break;
229                 case RADEON_HPD_4:
230                         WREG32(DC_HPD4_CONTROL, tmp);
231                         rdev->irq.hpd[3] = true;
232                         break;
233                 case RADEON_HPD_5:
234                         WREG32(DC_HPD5_CONTROL, tmp);
235                         rdev->irq.hpd[4] = true;
236                         break;
237                 case RADEON_HPD_6:
238                         WREG32(DC_HPD6_CONTROL, tmp);
239                         rdev->irq.hpd[5] = true;
240                         break;
241                 default:
242                         break;
243                 }
244         }
245         if (rdev->irq.installed)
246                 evergreen_irq_set(rdev);
247 }
248
249 void evergreen_hpd_fini(struct radeon_device *rdev)
250 {
251         struct drm_device *dev = rdev->ddev;
252         struct drm_connector *connector;
253
254         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
255                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
256                 switch (radeon_connector->hpd.hpd) {
257                 case RADEON_HPD_1:
258                         WREG32(DC_HPD1_CONTROL, 0);
259                         rdev->irq.hpd[0] = false;
260                         break;
261                 case RADEON_HPD_2:
262                         WREG32(DC_HPD2_CONTROL, 0);
263                         rdev->irq.hpd[1] = false;
264                         break;
265                 case RADEON_HPD_3:
266                         WREG32(DC_HPD3_CONTROL, 0);
267                         rdev->irq.hpd[2] = false;
268                         break;
269                 case RADEON_HPD_4:
270                         WREG32(DC_HPD4_CONTROL, 0);
271                         rdev->irq.hpd[3] = false;
272                         break;
273                 case RADEON_HPD_5:
274                         WREG32(DC_HPD5_CONTROL, 0);
275                         rdev->irq.hpd[4] = false;
276                         break;
277                 case RADEON_HPD_6:
278                         WREG32(DC_HPD6_CONTROL, 0);
279                         rdev->irq.hpd[5] = false;
280                         break;
281                 default:
282                         break;
283                 }
284         }
285 }
286
287 /* watermark setup */
288
289 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
290                                         struct radeon_crtc *radeon_crtc,
291                                         struct drm_display_mode *mode,
292                                         struct drm_display_mode *other_mode)
293 {
294         u32 tmp = 0;
295         /*
296          * Line Buffer Setup
297          * There are 3 line buffers, each one shared by 2 display controllers.
298          * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
299          * the display controllers.  The paritioning is done via one of four
300          * preset allocations specified in bits 2:0:
301          * first display controller
302          *  0 - first half of lb (3840 * 2)
303          *  1 - first 3/4 of lb (5760 * 2)
304          *  2 - whole lb (7680 * 2)
305          *  3 - first 1/4 of lb (1920 * 2)
306          * second display controller
307          *  4 - second half of lb (3840 * 2)
308          *  5 - second 3/4 of lb (5760 * 2)
309          *  6 - whole lb (7680 * 2)
310          *  7 - last 1/4 of lb (1920 * 2)
311          */
312         if (mode && other_mode) {
313                 if (mode->hdisplay > other_mode->hdisplay) {
314                         if (mode->hdisplay > 2560)
315                                 tmp = 1; /* 3/4 */
316                         else
317                                 tmp = 0; /* 1/2 */
318                 } else if (other_mode->hdisplay > mode->hdisplay) {
319                         if (other_mode->hdisplay > 2560)
320                                 tmp = 3; /* 1/4 */
321                         else
322                                 tmp = 0; /* 1/2 */
323                 } else
324                         tmp = 0; /* 1/2 */
325         } else if (mode)
326                 tmp = 2; /* whole */
327         else if (other_mode)
328                 tmp = 3; /* 1/4 */
329
330         /* second controller of the pair uses second half of the lb */
331         if (radeon_crtc->crtc_id % 2)
332                 tmp += 4;
333         WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
334
335         switch (tmp) {
336         case 0:
337         case 4:
338         default:
339                 return 3840 * 2;
340         case 1:
341         case 5:
342                 return 5760 * 2;
343         case 2:
344         case 6:
345                 return 7680 * 2;
346         case 3:
347         case 7:
348                 return 1920 * 2;
349         }
350 }
351
352 static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
353 {
354         u32 tmp = RREG32(MC_SHARED_CHMAP);
355
356         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
357         case 0:
358         default:
359                 return 1;
360         case 1:
361                 return 2;
362         case 2:
363                 return 4;
364         case 3:
365                 return 8;
366         }
367 }
368
369 struct evergreen_wm_params {
370         u32 dram_channels; /* number of dram channels */
371         u32 yclk;          /* bandwidth per dram data pin in kHz */
372         u32 sclk;          /* engine clock in kHz */
373         u32 disp_clk;      /* display clock in kHz */
374         u32 src_width;     /* viewport width */
375         u32 active_time;   /* active display time in ns */
376         u32 blank_time;    /* blank time in ns */
377         bool interlaced;    /* mode is interlaced */
378         fixed20_12 vsc;    /* vertical scale ratio */
379         u32 num_heads;     /* number of active crtcs */
380         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
381         u32 lb_size;       /* line buffer allocated to pipe */
382         u32 vtaps;         /* vertical scaler taps */
383 };
384
385 static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
386 {
387         /* Calculate DRAM Bandwidth and the part allocated to display. */
388         fixed20_12 dram_efficiency; /* 0.7 */
389         fixed20_12 yclk, dram_channels, bandwidth;
390         fixed20_12 a;
391
392         a.full = dfixed_const(1000);
393         yclk.full = dfixed_const(wm->yclk);
394         yclk.full = dfixed_div(yclk, a);
395         dram_channels.full = dfixed_const(wm->dram_channels * 4);
396         a.full = dfixed_const(10);
397         dram_efficiency.full = dfixed_const(7);
398         dram_efficiency.full = dfixed_div(dram_efficiency, a);
399         bandwidth.full = dfixed_mul(dram_channels, yclk);
400         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
401
402         return dfixed_trunc(bandwidth);
403 }
404
405 static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
406 {
407         /* Calculate DRAM Bandwidth and the part allocated to display. */
408         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
409         fixed20_12 yclk, dram_channels, bandwidth;
410         fixed20_12 a;
411
412         a.full = dfixed_const(1000);
413         yclk.full = dfixed_const(wm->yclk);
414         yclk.full = dfixed_div(yclk, a);
415         dram_channels.full = dfixed_const(wm->dram_channels * 4);
416         a.full = dfixed_const(10);
417         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
418         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
419         bandwidth.full = dfixed_mul(dram_channels, yclk);
420         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
421
422         return dfixed_trunc(bandwidth);
423 }
424
425 static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
426 {
427         /* Calculate the display Data return Bandwidth */
428         fixed20_12 return_efficiency; /* 0.8 */
429         fixed20_12 sclk, bandwidth;
430         fixed20_12 a;
431
432         a.full = dfixed_const(1000);
433         sclk.full = dfixed_const(wm->sclk);
434         sclk.full = dfixed_div(sclk, a);
435         a.full = dfixed_const(10);
436         return_efficiency.full = dfixed_const(8);
437         return_efficiency.full = dfixed_div(return_efficiency, a);
438         a.full = dfixed_const(32);
439         bandwidth.full = dfixed_mul(a, sclk);
440         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
441
442         return dfixed_trunc(bandwidth);
443 }
444
445 static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
446 {
447         /* Calculate the DMIF Request Bandwidth */
448         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
449         fixed20_12 disp_clk, bandwidth;
450         fixed20_12 a;
451
452         a.full = dfixed_const(1000);
453         disp_clk.full = dfixed_const(wm->disp_clk);
454         disp_clk.full = dfixed_div(disp_clk, a);
455         a.full = dfixed_const(10);
456         disp_clk_request_efficiency.full = dfixed_const(8);
457         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
458         a.full = dfixed_const(32);
459         bandwidth.full = dfixed_mul(a, disp_clk);
460         bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
461
462         return dfixed_trunc(bandwidth);
463 }
464
465 static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
466 {
467         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
468         u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
469         u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
470         u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
471
472         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
473 }
474
475 static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
476 {
477         /* Calculate the display mode Average Bandwidth
478          * DisplayMode should contain the source and destination dimensions,
479          * timing, etc.
480          */
481         fixed20_12 bpp;
482         fixed20_12 line_time;
483         fixed20_12 src_width;
484         fixed20_12 bandwidth;
485         fixed20_12 a;
486
487         a.full = dfixed_const(1000);
488         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
489         line_time.full = dfixed_div(line_time, a);
490         bpp.full = dfixed_const(wm->bytes_per_pixel);
491         src_width.full = dfixed_const(wm->src_width);
492         bandwidth.full = dfixed_mul(src_width, bpp);
493         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
494         bandwidth.full = dfixed_div(bandwidth, line_time);
495
496         return dfixed_trunc(bandwidth);
497 }
498
499 static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
500 {
501         /* First calcualte the latency in ns */
502         u32 mc_latency = 2000; /* 2000 ns. */
503         u32 available_bandwidth = evergreen_available_bandwidth(wm);
504         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
505         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
506         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
507         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
508                 (wm->num_heads * cursor_line_pair_return_time);
509         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
510         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
511         fixed20_12 a, b, c;
512
513         if (wm->num_heads == 0)
514                 return 0;
515
516         a.full = dfixed_const(2);
517         b.full = dfixed_const(1);
518         if ((wm->vsc.full > a.full) ||
519             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
520             (wm->vtaps >= 5) ||
521             ((wm->vsc.full >= a.full) && wm->interlaced))
522                 max_src_lines_per_dst_line = 4;
523         else
524                 max_src_lines_per_dst_line = 2;
525
526         a.full = dfixed_const(available_bandwidth);
527         b.full = dfixed_const(wm->num_heads);
528         a.full = dfixed_div(a, b);
529
530         b.full = dfixed_const(1000);
531         c.full = dfixed_const(wm->disp_clk);
532         b.full = dfixed_div(c, b);
533         c.full = dfixed_const(wm->bytes_per_pixel);
534         b.full = dfixed_mul(b, c);
535
536         lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
537
538         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
539         b.full = dfixed_const(1000);
540         c.full = dfixed_const(lb_fill_bw);
541         b.full = dfixed_div(c, b);
542         a.full = dfixed_div(a, b);
543         line_fill_time = dfixed_trunc(a);
544
545         if (line_fill_time < wm->active_time)
546                 return latency;
547         else
548                 return latency + (line_fill_time - wm->active_time);
549
550 }
551
552 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
553 {
554         if (evergreen_average_bandwidth(wm) <=
555             (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
556                 return true;
557         else
558                 return false;
559 };
560
561 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
562 {
563         if (evergreen_average_bandwidth(wm) <=
564             (evergreen_available_bandwidth(wm) / wm->num_heads))
565                 return true;
566         else
567                 return false;
568 };
569
570 static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
571 {
572         u32 lb_partitions = wm->lb_size / wm->src_width;
573         u32 line_time = wm->active_time + wm->blank_time;
574         u32 latency_tolerant_lines;
575         u32 latency_hiding;
576         fixed20_12 a;
577
578         a.full = dfixed_const(1);
579         if (wm->vsc.full > a.full)
580                 latency_tolerant_lines = 1;
581         else {
582                 if (lb_partitions <= (wm->vtaps + 1))
583                         latency_tolerant_lines = 1;
584                 else
585                         latency_tolerant_lines = 2;
586         }
587
588         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
589
590         if (evergreen_latency_watermark(wm) <= latency_hiding)
591                 return true;
592         else
593                 return false;
594 }
595
596 static void evergreen_program_watermarks(struct radeon_device *rdev,
597                                          struct radeon_crtc *radeon_crtc,
598                                          u32 lb_size, u32 num_heads)
599 {
600         struct drm_display_mode *mode = &radeon_crtc->base.mode;
601         struct evergreen_wm_params wm;
602         u32 pixel_period;
603         u32 line_time = 0;
604         u32 latency_watermark_a = 0, latency_watermark_b = 0;
605         u32 priority_a_mark = 0, priority_b_mark = 0;
606         u32 priority_a_cnt = PRIORITY_OFF;
607         u32 priority_b_cnt = PRIORITY_OFF;
608         u32 pipe_offset = radeon_crtc->crtc_id * 16;
609         u32 tmp, arb_control3;
610         fixed20_12 a, b, c;
611
612         if (radeon_crtc->base.enabled && num_heads && mode) {
613                 pixel_period = 1000000 / (u32)mode->clock;
614                 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
615                 priority_a_cnt = 0;
616                 priority_b_cnt = 0;
617
618                 wm.yclk = rdev->pm.current_mclk * 10;
619                 wm.sclk = rdev->pm.current_sclk * 10;
620                 wm.disp_clk = mode->clock;
621                 wm.src_width = mode->crtc_hdisplay;
622                 wm.active_time = mode->crtc_hdisplay * pixel_period;
623                 wm.blank_time = line_time - wm.active_time;
624                 wm.interlaced = false;
625                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
626                         wm.interlaced = true;
627                 wm.vsc = radeon_crtc->vsc;
628                 wm.vtaps = 1;
629                 if (radeon_crtc->rmx_type != RMX_OFF)
630                         wm.vtaps = 2;
631                 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
632                 wm.lb_size = lb_size;
633                 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
634                 wm.num_heads = num_heads;
635
636                 /* set for high clocks */
637                 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
638                 /* set for low clocks */
639                 /* wm.yclk = low clk; wm.sclk = low clk */
640                 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
641
642                 /* possibly force display priority to high */
643                 /* should really do this at mode validation time... */
644                 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
645                     !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
646                     !evergreen_check_latency_hiding(&wm) ||
647                     (rdev->disp_priority == 2)) {
648                         DRM_INFO("force priority to high\n");
649                         priority_a_cnt |= PRIORITY_ALWAYS_ON;
650                         priority_b_cnt |= PRIORITY_ALWAYS_ON;
651                 }
652
653                 a.full = dfixed_const(1000);
654                 b.full = dfixed_const(mode->clock);
655                 b.full = dfixed_div(b, a);
656                 c.full = dfixed_const(latency_watermark_a);
657                 c.full = dfixed_mul(c, b);
658                 c.full = dfixed_mul(c, radeon_crtc->hsc);
659                 c.full = dfixed_div(c, a);
660                 a.full = dfixed_const(16);
661                 c.full = dfixed_div(c, a);
662                 priority_a_mark = dfixed_trunc(c);
663                 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
664
665                 a.full = dfixed_const(1000);
666                 b.full = dfixed_const(mode->clock);
667                 b.full = dfixed_div(b, a);
668                 c.full = dfixed_const(latency_watermark_b);
669                 c.full = dfixed_mul(c, b);
670                 c.full = dfixed_mul(c, radeon_crtc->hsc);
671                 c.full = dfixed_div(c, a);
672                 a.full = dfixed_const(16);
673                 c.full = dfixed_div(c, a);
674                 priority_b_mark = dfixed_trunc(c);
675                 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
676         }
677
678         /* select wm A */
679         arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
680         tmp = arb_control3;
681         tmp &= ~LATENCY_WATERMARK_MASK(3);
682         tmp |= LATENCY_WATERMARK_MASK(1);
683         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
684         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
685                (LATENCY_LOW_WATERMARK(latency_watermark_a) |
686                 LATENCY_HIGH_WATERMARK(line_time)));
687         /* select wm B */
688         tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
689         tmp &= ~LATENCY_WATERMARK_MASK(3);
690         tmp |= LATENCY_WATERMARK_MASK(2);
691         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
692         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
693                (LATENCY_LOW_WATERMARK(latency_watermark_b) |
694                 LATENCY_HIGH_WATERMARK(line_time)));
695         /* restore original selection */
696         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
697
698         /* write the priority marks */
699         WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
700         WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
701
702 }
703
704 void evergreen_bandwidth_update(struct radeon_device *rdev)
705 {
706         struct drm_display_mode *mode0 = NULL;
707         struct drm_display_mode *mode1 = NULL;
708         u32 num_heads = 0, lb_size;
709         int i;
710
711         radeon_update_display_priority(rdev);
712
713         for (i = 0; i < rdev->num_crtc; i++) {
714                 if (rdev->mode_info.crtcs[i]->base.enabled)
715                         num_heads++;
716         }
717         for (i = 0; i < rdev->num_crtc; i += 2) {
718                 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
719                 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
720                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
721                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
722                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
723                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
724         }
725 }
726
727 static int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
728 {
729         unsigned i;
730         u32 tmp;
731
732         for (i = 0; i < rdev->usec_timeout; i++) {
733                 /* read MC_STATUS */
734                 tmp = RREG32(SRBM_STATUS) & 0x1F00;
735                 if (!tmp)
736                         return 0;
737                 udelay(1);
738         }
739         return -1;
740 }
741
742 /*
743  * GART
744  */
745 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
746 {
747         unsigned i;
748         u32 tmp;
749
750         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
751         for (i = 0; i < rdev->usec_timeout; i++) {
752                 /* read MC_STATUS */
753                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
754                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
755                 if (tmp == 2) {
756                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
757                         return;
758                 }
759                 if (tmp) {
760                         return;
761                 }
762                 udelay(1);
763         }
764 }
765
766 int evergreen_pcie_gart_enable(struct radeon_device *rdev)
767 {
768         u32 tmp;
769         int r;
770
771         if (rdev->gart.table.vram.robj == NULL) {
772                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
773                 return -EINVAL;
774         }
775         r = radeon_gart_table_vram_pin(rdev);
776         if (r)
777                 return r;
778         radeon_gart_restore(rdev);
779         /* Setup L2 cache */
780         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
781                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
782                                 EFFECTIVE_L2_QUEUE_SIZE(7));
783         WREG32(VM_L2_CNTL2, 0);
784         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
785         /* Setup TLB control */
786         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
787                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
788                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
789                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
790         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
791         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
792         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
793         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
794         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
795         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
796         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
797         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
798         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
799         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
800         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
801                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
802         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
803                         (u32)(rdev->dummy_page.addr >> 12));
804         WREG32(VM_CONTEXT1_CNTL, 0);
805
806         evergreen_pcie_gart_tlb_flush(rdev);
807         rdev->gart.ready = true;
808         return 0;
809 }
810
811 void evergreen_pcie_gart_disable(struct radeon_device *rdev)
812 {
813         u32 tmp;
814         int r;
815
816         /* Disable all tables */
817         WREG32(VM_CONTEXT0_CNTL, 0);
818         WREG32(VM_CONTEXT1_CNTL, 0);
819
820         /* Setup L2 cache */
821         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
822                                 EFFECTIVE_L2_QUEUE_SIZE(7));
823         WREG32(VM_L2_CNTL2, 0);
824         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
825         /* Setup TLB control */
826         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
827         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
828         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
829         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
830         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
831         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
832         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
833         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
834         if (rdev->gart.table.vram.robj) {
835                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
836                 if (likely(r == 0)) {
837                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
838                         radeon_bo_unpin(rdev->gart.table.vram.robj);
839                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
840                 }
841         }
842 }
843
844 void evergreen_pcie_gart_fini(struct radeon_device *rdev)
845 {
846         evergreen_pcie_gart_disable(rdev);
847         radeon_gart_table_vram_free(rdev);
848         radeon_gart_fini(rdev);
849 }
850
851
852 void evergreen_agp_enable(struct radeon_device *rdev)
853 {
854         u32 tmp;
855
856         /* Setup L2 cache */
857         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
858                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
859                                 EFFECTIVE_L2_QUEUE_SIZE(7));
860         WREG32(VM_L2_CNTL2, 0);
861         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
862         /* Setup TLB control */
863         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
864                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
865                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
866                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
867         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
868         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
869         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
870         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
871         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
872         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
873         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
874         WREG32(VM_CONTEXT0_CNTL, 0);
875         WREG32(VM_CONTEXT1_CNTL, 0);
876 }
877
878 static void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
879 {
880         save->vga_control[0] = RREG32(D1VGA_CONTROL);
881         save->vga_control[1] = RREG32(D2VGA_CONTROL);
882         save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
883         save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
884         save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
885         save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
886         save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
887         save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
888         save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
889         save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
890         save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
891         save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
892         save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
893         save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
894
895         /* Stop all video */
896         WREG32(VGA_RENDER_CONTROL, 0);
897         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
898         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
899         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
900         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
901         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
902         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
903         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
904         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
905         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
906         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
907         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
908         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
909         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
910         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
911         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
912         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
913         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
914         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
915
916         WREG32(D1VGA_CONTROL, 0);
917         WREG32(D2VGA_CONTROL, 0);
918         WREG32(EVERGREEN_D3VGA_CONTROL, 0);
919         WREG32(EVERGREEN_D4VGA_CONTROL, 0);
920         WREG32(EVERGREEN_D5VGA_CONTROL, 0);
921         WREG32(EVERGREEN_D6VGA_CONTROL, 0);
922 }
923
924 static void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
925 {
926         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
927                upper_32_bits(rdev->mc.vram_start));
928         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
929                upper_32_bits(rdev->mc.vram_start));
930         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
931                (u32)rdev->mc.vram_start);
932         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
933                (u32)rdev->mc.vram_start);
934
935         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
936                upper_32_bits(rdev->mc.vram_start));
937         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
938                upper_32_bits(rdev->mc.vram_start));
939         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
940                (u32)rdev->mc.vram_start);
941         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
942                (u32)rdev->mc.vram_start);
943
944         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
945                upper_32_bits(rdev->mc.vram_start));
946         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
947                upper_32_bits(rdev->mc.vram_start));
948         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
949                (u32)rdev->mc.vram_start);
950         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
951                (u32)rdev->mc.vram_start);
952
953         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
954                upper_32_bits(rdev->mc.vram_start));
955         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
956                upper_32_bits(rdev->mc.vram_start));
957         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
958                (u32)rdev->mc.vram_start);
959         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
960                (u32)rdev->mc.vram_start);
961
962         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
963                upper_32_bits(rdev->mc.vram_start));
964         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
965                upper_32_bits(rdev->mc.vram_start));
966         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
967                (u32)rdev->mc.vram_start);
968         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
969                (u32)rdev->mc.vram_start);
970
971         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
972                upper_32_bits(rdev->mc.vram_start));
973         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
974                upper_32_bits(rdev->mc.vram_start));
975         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
976                (u32)rdev->mc.vram_start);
977         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
978                (u32)rdev->mc.vram_start);
979
980         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
981         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
982         /* Unlock host access */
983         WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
984         mdelay(1);
985         /* Restore video state */
986         WREG32(D1VGA_CONTROL, save->vga_control[0]);
987         WREG32(D2VGA_CONTROL, save->vga_control[1]);
988         WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
989         WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
990         WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
991         WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
992         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
993         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
994         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
995         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
996         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
997         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
998         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
999         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
1000         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1001         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
1002         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1003         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1004         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1005         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1006         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1007         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1008         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1009         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1010         WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1011 }
1012
1013 static void evergreen_mc_program(struct radeon_device *rdev)
1014 {
1015         struct evergreen_mc_save save;
1016         u32 tmp;
1017         int i, j;
1018
1019         /* Initialize HDP */
1020         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1021                 WREG32((0x2c14 + j), 0x00000000);
1022                 WREG32((0x2c18 + j), 0x00000000);
1023                 WREG32((0x2c1c + j), 0x00000000);
1024                 WREG32((0x2c20 + j), 0x00000000);
1025                 WREG32((0x2c24 + j), 0x00000000);
1026         }
1027         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1028
1029         evergreen_mc_stop(rdev, &save);
1030         if (evergreen_mc_wait_for_idle(rdev)) {
1031                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1032         }
1033         /* Lockout access through VGA aperture*/
1034         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1035         /* Update configuration */
1036         if (rdev->flags & RADEON_IS_AGP) {
1037                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1038                         /* VRAM before AGP */
1039                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1040                                 rdev->mc.vram_start >> 12);
1041                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1042                                 rdev->mc.gtt_end >> 12);
1043                 } else {
1044                         /* VRAM after AGP */
1045                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1046                                 rdev->mc.gtt_start >> 12);
1047                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1048                                 rdev->mc.vram_end >> 12);
1049                 }
1050         } else {
1051                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1052                         rdev->mc.vram_start >> 12);
1053                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1054                         rdev->mc.vram_end >> 12);
1055         }
1056         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1057         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1058         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1059         WREG32(MC_VM_FB_LOCATION, tmp);
1060         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1061         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1062         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1063         if (rdev->flags & RADEON_IS_AGP) {
1064                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1065                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1066                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1067         } else {
1068                 WREG32(MC_VM_AGP_BASE, 0);
1069                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1070                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1071         }
1072         if (evergreen_mc_wait_for_idle(rdev)) {
1073                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1074         }
1075         evergreen_mc_resume(rdev, &save);
1076         /* we need to own VRAM, so turn off the VGA renderer here
1077          * to stop it overwriting our objects */
1078         rv515_vga_render_disable(rdev);
1079 }
1080
1081 /*
1082  * CP.
1083  */
1084
1085 static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1086 {
1087         const __be32 *fw_data;
1088         int i;
1089
1090         if (!rdev->me_fw || !rdev->pfp_fw)
1091                 return -EINVAL;
1092
1093         r700_cp_stop(rdev);
1094         WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
1095
1096         fw_data = (const __be32 *)rdev->pfp_fw->data;
1097         WREG32(CP_PFP_UCODE_ADDR, 0);
1098         for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1099                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1100         WREG32(CP_PFP_UCODE_ADDR, 0);
1101
1102         fw_data = (const __be32 *)rdev->me_fw->data;
1103         WREG32(CP_ME_RAM_WADDR, 0);
1104         for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1105                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1106
1107         WREG32(CP_PFP_UCODE_ADDR, 0);
1108         WREG32(CP_ME_RAM_WADDR, 0);
1109         WREG32(CP_ME_RAM_RADDR, 0);
1110         return 0;
1111 }
1112
1113 static int evergreen_cp_start(struct radeon_device *rdev)
1114 {
1115         int r;
1116         uint32_t cp_me;
1117
1118         r = radeon_ring_lock(rdev, 7);
1119         if (r) {
1120                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1121                 return r;
1122         }
1123         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1124         radeon_ring_write(rdev, 0x1);
1125         radeon_ring_write(rdev, 0x0);
1126         radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
1127         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1128         radeon_ring_write(rdev, 0);
1129         radeon_ring_write(rdev, 0);
1130         radeon_ring_unlock_commit(rdev);
1131
1132         cp_me = 0xff;
1133         WREG32(CP_ME_CNTL, cp_me);
1134
1135         r = radeon_ring_lock(rdev, 4);
1136         if (r) {
1137                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1138                 return r;
1139         }
1140         /* init some VGT regs */
1141         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2));
1142         radeon_ring_write(rdev, (VGT_VERTEX_REUSE_BLOCK_CNTL - PACKET3_SET_CONTEXT_REG_START) >> 2);
1143         radeon_ring_write(rdev, 0xe);
1144         radeon_ring_write(rdev, 0x10);
1145         radeon_ring_unlock_commit(rdev);
1146
1147         return 0;
1148 }
1149
1150 int evergreen_cp_resume(struct radeon_device *rdev)
1151 {
1152         u32 tmp;
1153         u32 rb_bufsz;
1154         int r;
1155
1156         /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1157         WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1158                                  SOFT_RESET_PA |
1159                                  SOFT_RESET_SH |
1160                                  SOFT_RESET_VGT |
1161                                  SOFT_RESET_SX));
1162         RREG32(GRBM_SOFT_RESET);
1163         mdelay(15);
1164         WREG32(GRBM_SOFT_RESET, 0);
1165         RREG32(GRBM_SOFT_RESET);
1166
1167         /* Set ring buffer size */
1168         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1169         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1170 #ifdef __BIG_ENDIAN
1171         tmp |= BUF_SWAP_32BIT;
1172 #endif
1173         WREG32(CP_RB_CNTL, tmp);
1174         WREG32(CP_SEM_WAIT_TIMER, 0x4);
1175
1176         /* Set the write pointer delay */
1177         WREG32(CP_RB_WPTR_DELAY, 0);
1178
1179         /* Initialize the ring buffer's read and write pointers */
1180         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1181         WREG32(CP_RB_RPTR_WR, 0);
1182         WREG32(CP_RB_WPTR, 0);
1183
1184         /* set the wb address wether it's enabled or not */
1185         WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
1186         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1187         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1188
1189         if (rdev->wb.enabled)
1190                 WREG32(SCRATCH_UMSK, 0xff);
1191         else {
1192                 tmp |= RB_NO_UPDATE;
1193                 WREG32(SCRATCH_UMSK, 0);
1194         }
1195
1196         mdelay(1);
1197         WREG32(CP_RB_CNTL, tmp);
1198
1199         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1200         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1201
1202         rdev->cp.rptr = RREG32(CP_RB_RPTR);
1203         rdev->cp.wptr = RREG32(CP_RB_WPTR);
1204
1205         evergreen_cp_start(rdev);
1206         rdev->cp.ready = true;
1207         r = radeon_ring_test(rdev);
1208         if (r) {
1209                 rdev->cp.ready = false;
1210                 return r;
1211         }
1212         return 0;
1213 }
1214
1215 /*
1216  * Core functions
1217  */
1218 static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1219                                                   u32 num_tile_pipes,
1220                                                   u32 num_backends,
1221                                                   u32 backend_disable_mask)
1222 {
1223         u32 backend_map = 0;
1224         u32 enabled_backends_mask = 0;
1225         u32 enabled_backends_count = 0;
1226         u32 cur_pipe;
1227         u32 swizzle_pipe[EVERGREEN_MAX_PIPES];
1228         u32 cur_backend = 0;
1229         u32 i;
1230         bool force_no_swizzle;
1231
1232         if (num_tile_pipes > EVERGREEN_MAX_PIPES)
1233                 num_tile_pipes = EVERGREEN_MAX_PIPES;
1234         if (num_tile_pipes < 1)
1235                 num_tile_pipes = 1;
1236         if (num_backends > EVERGREEN_MAX_BACKENDS)
1237                 num_backends = EVERGREEN_MAX_BACKENDS;
1238         if (num_backends < 1)
1239                 num_backends = 1;
1240
1241         for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1242                 if (((backend_disable_mask >> i) & 1) == 0) {
1243                         enabled_backends_mask |= (1 << i);
1244                         ++enabled_backends_count;
1245                 }
1246                 if (enabled_backends_count == num_backends)
1247                         break;
1248         }
1249
1250         if (enabled_backends_count == 0) {
1251                 enabled_backends_mask = 1;
1252                 enabled_backends_count = 1;
1253         }
1254
1255         if (enabled_backends_count != num_backends)
1256                 num_backends = enabled_backends_count;
1257
1258         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES);
1259         switch (rdev->family) {
1260         case CHIP_CEDAR:
1261         case CHIP_REDWOOD:
1262                 force_no_swizzle = false;
1263                 break;
1264         case CHIP_CYPRESS:
1265         case CHIP_HEMLOCK:
1266         case CHIP_JUNIPER:
1267         default:
1268                 force_no_swizzle = true;
1269                 break;
1270         }
1271         if (force_no_swizzle) {
1272                 bool last_backend_enabled = false;
1273
1274                 force_no_swizzle = false;
1275                 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1276                         if (((enabled_backends_mask >> i) & 1) == 1) {
1277                                 if (last_backend_enabled)
1278                                         force_no_swizzle = true;
1279                                 last_backend_enabled = true;
1280                         } else
1281                                 last_backend_enabled = false;
1282                 }
1283         }
1284
1285         switch (num_tile_pipes) {
1286         case 1:
1287         case 3:
1288         case 5:
1289         case 7:
1290                 DRM_ERROR("odd number of pipes!\n");
1291                 break;
1292         case 2:
1293                 swizzle_pipe[0] = 0;
1294                 swizzle_pipe[1] = 1;
1295                 break;
1296         case 4:
1297                 if (force_no_swizzle) {
1298                         swizzle_pipe[0] = 0;
1299                         swizzle_pipe[1] = 1;
1300                         swizzle_pipe[2] = 2;
1301                         swizzle_pipe[3] = 3;
1302                 } else {
1303                         swizzle_pipe[0] = 0;
1304                         swizzle_pipe[1] = 2;
1305                         swizzle_pipe[2] = 1;
1306                         swizzle_pipe[3] = 3;
1307                 }
1308                 break;
1309         case 6:
1310                 if (force_no_swizzle) {
1311                         swizzle_pipe[0] = 0;
1312                         swizzle_pipe[1] = 1;
1313                         swizzle_pipe[2] = 2;
1314                         swizzle_pipe[3] = 3;
1315                         swizzle_pipe[4] = 4;
1316                         swizzle_pipe[5] = 5;
1317                 } else {
1318                         swizzle_pipe[0] = 0;
1319                         swizzle_pipe[1] = 2;
1320                         swizzle_pipe[2] = 4;
1321                         swizzle_pipe[3] = 1;
1322                         swizzle_pipe[4] = 3;
1323                         swizzle_pipe[5] = 5;
1324                 }
1325                 break;
1326         case 8:
1327                 if (force_no_swizzle) {
1328                         swizzle_pipe[0] = 0;
1329                         swizzle_pipe[1] = 1;
1330                         swizzle_pipe[2] = 2;
1331                         swizzle_pipe[3] = 3;
1332                         swizzle_pipe[4] = 4;
1333                         swizzle_pipe[5] = 5;
1334                         swizzle_pipe[6] = 6;
1335                         swizzle_pipe[7] = 7;
1336                 } else {
1337                         swizzle_pipe[0] = 0;
1338                         swizzle_pipe[1] = 2;
1339                         swizzle_pipe[2] = 4;
1340                         swizzle_pipe[3] = 6;
1341                         swizzle_pipe[4] = 1;
1342                         swizzle_pipe[5] = 3;
1343                         swizzle_pipe[6] = 5;
1344                         swizzle_pipe[7] = 7;
1345                 }
1346                 break;
1347         }
1348
1349         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1350                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1351                         cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1352
1353                 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
1354
1355                 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1356         }
1357
1358         return backend_map;
1359 }
1360
1361 static void evergreen_gpu_init(struct radeon_device *rdev)
1362 {
1363         u32 cc_rb_backend_disable = 0;
1364         u32 cc_gc_shader_pipe_config;
1365         u32 gb_addr_config = 0;
1366         u32 mc_shared_chmap, mc_arb_ramcfg;
1367         u32 gb_backend_map;
1368         u32 grbm_gfx_index;
1369         u32 sx_debug_1;
1370         u32 smx_dc_ctl0;
1371         u32 sq_config;
1372         u32 sq_lds_resource_mgmt;
1373         u32 sq_gpr_resource_mgmt_1;
1374         u32 sq_gpr_resource_mgmt_2;
1375         u32 sq_gpr_resource_mgmt_3;
1376         u32 sq_thread_resource_mgmt;
1377         u32 sq_thread_resource_mgmt_2;
1378         u32 sq_stack_resource_mgmt_1;
1379         u32 sq_stack_resource_mgmt_2;
1380         u32 sq_stack_resource_mgmt_3;
1381         u32 vgt_cache_invalidation;
1382         u32 hdp_host_path_cntl;
1383         int i, j, num_shader_engines, ps_thread_count;
1384
1385         switch (rdev->family) {
1386         case CHIP_CYPRESS:
1387         case CHIP_HEMLOCK:
1388                 rdev->config.evergreen.num_ses = 2;
1389                 rdev->config.evergreen.max_pipes = 4;
1390                 rdev->config.evergreen.max_tile_pipes = 8;
1391                 rdev->config.evergreen.max_simds = 10;
1392                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1393                 rdev->config.evergreen.max_gprs = 256;
1394                 rdev->config.evergreen.max_threads = 248;
1395                 rdev->config.evergreen.max_gs_threads = 32;
1396                 rdev->config.evergreen.max_stack_entries = 512;
1397                 rdev->config.evergreen.sx_num_of_sets = 4;
1398                 rdev->config.evergreen.sx_max_export_size = 256;
1399                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1400                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1401                 rdev->config.evergreen.max_hw_contexts = 8;
1402                 rdev->config.evergreen.sq_num_cf_insts = 2;
1403
1404                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1405                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1406                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1407                 break;
1408         case CHIP_JUNIPER:
1409                 rdev->config.evergreen.num_ses = 1;
1410                 rdev->config.evergreen.max_pipes = 4;
1411                 rdev->config.evergreen.max_tile_pipes = 4;
1412                 rdev->config.evergreen.max_simds = 10;
1413                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1414                 rdev->config.evergreen.max_gprs = 256;
1415                 rdev->config.evergreen.max_threads = 248;
1416                 rdev->config.evergreen.max_gs_threads = 32;
1417                 rdev->config.evergreen.max_stack_entries = 512;
1418                 rdev->config.evergreen.sx_num_of_sets = 4;
1419                 rdev->config.evergreen.sx_max_export_size = 256;
1420                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1421                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1422                 rdev->config.evergreen.max_hw_contexts = 8;
1423                 rdev->config.evergreen.sq_num_cf_insts = 2;
1424
1425                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1426                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1427                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1428                 break;
1429         case CHIP_REDWOOD:
1430                 rdev->config.evergreen.num_ses = 1;
1431                 rdev->config.evergreen.max_pipes = 4;
1432                 rdev->config.evergreen.max_tile_pipes = 4;
1433                 rdev->config.evergreen.max_simds = 5;
1434                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1435                 rdev->config.evergreen.max_gprs = 256;
1436                 rdev->config.evergreen.max_threads = 248;
1437                 rdev->config.evergreen.max_gs_threads = 32;
1438                 rdev->config.evergreen.max_stack_entries = 256;
1439                 rdev->config.evergreen.sx_num_of_sets = 4;
1440                 rdev->config.evergreen.sx_max_export_size = 256;
1441                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1442                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1443                 rdev->config.evergreen.max_hw_contexts = 8;
1444                 rdev->config.evergreen.sq_num_cf_insts = 2;
1445
1446                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1447                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1448                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1449                 break;
1450         case CHIP_CEDAR:
1451         default:
1452                 rdev->config.evergreen.num_ses = 1;
1453                 rdev->config.evergreen.max_pipes = 2;
1454                 rdev->config.evergreen.max_tile_pipes = 2;
1455                 rdev->config.evergreen.max_simds = 2;
1456                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1457                 rdev->config.evergreen.max_gprs = 256;
1458                 rdev->config.evergreen.max_threads = 192;
1459                 rdev->config.evergreen.max_gs_threads = 16;
1460                 rdev->config.evergreen.max_stack_entries = 256;
1461                 rdev->config.evergreen.sx_num_of_sets = 4;
1462                 rdev->config.evergreen.sx_max_export_size = 128;
1463                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1464                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1465                 rdev->config.evergreen.max_hw_contexts = 4;
1466                 rdev->config.evergreen.sq_num_cf_insts = 1;
1467
1468                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1469                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1470                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1471                 break;
1472         }
1473
1474         /* Initialize HDP */
1475         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1476                 WREG32((0x2c14 + j), 0x00000000);
1477                 WREG32((0x2c18 + j), 0x00000000);
1478                 WREG32((0x2c1c + j), 0x00000000);
1479                 WREG32((0x2c20 + j), 0x00000000);
1480                 WREG32((0x2c24 + j), 0x00000000);
1481         }
1482
1483         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1484
1485         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
1486
1487         cc_gc_shader_pipe_config |=
1488                 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
1489                                   & EVERGREEN_MAX_PIPES_MASK);
1490         cc_gc_shader_pipe_config |=
1491                 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
1492                                & EVERGREEN_MAX_SIMDS_MASK);
1493
1494         cc_rb_backend_disable =
1495                 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
1496                                 & EVERGREEN_MAX_BACKENDS_MASK);
1497
1498
1499         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1500         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1501
1502         switch (rdev->config.evergreen.max_tile_pipes) {
1503         case 1:
1504         default:
1505                 gb_addr_config |= NUM_PIPES(0);
1506                 break;
1507         case 2:
1508                 gb_addr_config |= NUM_PIPES(1);
1509                 break;
1510         case 4:
1511                 gb_addr_config |= NUM_PIPES(2);
1512                 break;
1513         case 8:
1514                 gb_addr_config |= NUM_PIPES(3);
1515                 break;
1516         }
1517
1518         gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1519         gb_addr_config |= BANK_INTERLEAVE_SIZE(0);
1520         gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1);
1521         gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1);
1522         gb_addr_config |= NUM_GPUS(0); /* Hemlock? */
1523         gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
1524
1525         if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2)
1526                 gb_addr_config |= ROW_SIZE(2);
1527         else
1528                 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
1529
1530         if (rdev->ddev->pdev->device == 0x689e) {
1531                 u32 efuse_straps_4;
1532                 u32 efuse_straps_3;
1533                 u8 efuse_box_bit_131_124;
1534
1535                 WREG32(RCU_IND_INDEX, 0x204);
1536                 efuse_straps_4 = RREG32(RCU_IND_DATA);
1537                 WREG32(RCU_IND_INDEX, 0x203);
1538                 efuse_straps_3 = RREG32(RCU_IND_DATA);
1539                 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
1540
1541                 switch(efuse_box_bit_131_124) {
1542                 case 0x00:
1543                         gb_backend_map = 0x76543210;
1544                         break;
1545                 case 0x55:
1546                         gb_backend_map = 0x77553311;
1547                         break;
1548                 case 0x56:
1549                         gb_backend_map = 0x77553300;
1550                         break;
1551                 case 0x59:
1552                         gb_backend_map = 0x77552211;
1553                         break;
1554                 case 0x66:
1555                         gb_backend_map = 0x77443300;
1556                         break;
1557                 case 0x99:
1558                         gb_backend_map = 0x66552211;
1559                         break;
1560                 case 0x5a:
1561                         gb_backend_map = 0x77552200;
1562                         break;
1563                 case 0xaa:
1564                         gb_backend_map = 0x66442200;
1565                         break;
1566                 case 0x95:
1567                         gb_backend_map = 0x66553311;
1568                         break;
1569                 default:
1570                         DRM_ERROR("bad backend map, using default\n");
1571                         gb_backend_map =
1572                                 evergreen_get_tile_pipe_to_backend_map(rdev,
1573                                                                        rdev->config.evergreen.max_tile_pipes,
1574                                                                        rdev->config.evergreen.max_backends,
1575                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
1576                                                                    rdev->config.evergreen.max_backends) &
1577                                                                         EVERGREEN_MAX_BACKENDS_MASK));
1578                         break;
1579                 }
1580         } else if (rdev->ddev->pdev->device == 0x68b9) {
1581                 u32 efuse_straps_3;
1582                 u8 efuse_box_bit_127_124;
1583
1584                 WREG32(RCU_IND_INDEX, 0x203);
1585                 efuse_straps_3 = RREG32(RCU_IND_DATA);
1586                 efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28);
1587
1588                 switch(efuse_box_bit_127_124) {
1589                 case 0x0:
1590                         gb_backend_map = 0x00003210;
1591                         break;
1592                 case 0x5:
1593                 case 0x6:
1594                 case 0x9:
1595                 case 0xa:
1596                         gb_backend_map = 0x00003311;
1597                         break;
1598                 default:
1599                         DRM_ERROR("bad backend map, using default\n");
1600                         gb_backend_map =
1601                                 evergreen_get_tile_pipe_to_backend_map(rdev,
1602                                                                        rdev->config.evergreen.max_tile_pipes,
1603                                                                        rdev->config.evergreen.max_backends,
1604                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
1605                                                                    rdev->config.evergreen.max_backends) &
1606                                                                         EVERGREEN_MAX_BACKENDS_MASK));
1607                         break;
1608                 }
1609         } else {
1610                 switch (rdev->family) {
1611                 case CHIP_CYPRESS:
1612                 case CHIP_HEMLOCK:
1613                         gb_backend_map = 0x66442200;
1614                         break;
1615                 case CHIP_JUNIPER:
1616                         gb_backend_map = 0x00006420;
1617                         break;
1618                 default:
1619                         gb_backend_map =
1620                                 evergreen_get_tile_pipe_to_backend_map(rdev,
1621                                                                        rdev->config.evergreen.max_tile_pipes,
1622                                                                        rdev->config.evergreen.max_backends,
1623                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
1624                                                                          rdev->config.evergreen.max_backends) &
1625                                                                         EVERGREEN_MAX_BACKENDS_MASK));
1626                 }
1627         }
1628
1629         rdev->config.evergreen.tile_config = gb_addr_config;
1630         WREG32(GB_BACKEND_MAP, gb_backend_map);
1631         WREG32(GB_ADDR_CONFIG, gb_addr_config);
1632         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1633         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1634
1635         num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
1636         grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
1637
1638         for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
1639                 u32 rb = cc_rb_backend_disable | (0xf0 << 16);
1640                 u32 sp = cc_gc_shader_pipe_config;
1641                 u32 gfx = grbm_gfx_index | SE_INDEX(i);
1642
1643                 if (i == num_shader_engines) {
1644                         rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
1645                         sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
1646                 }
1647
1648                 WREG32(GRBM_GFX_INDEX, gfx);
1649                 WREG32(RLC_GFX_INDEX, gfx);
1650
1651                 WREG32(CC_RB_BACKEND_DISABLE, rb);
1652                 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
1653                 WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
1654                 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
1655         }
1656
1657         grbm_gfx_index |= SE_BROADCAST_WRITES;
1658         WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
1659         WREG32(RLC_GFX_INDEX, grbm_gfx_index);
1660
1661         WREG32(CGTS_SYS_TCC_DISABLE, 0);
1662         WREG32(CGTS_TCC_DISABLE, 0);
1663         WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
1664         WREG32(CGTS_USER_TCC_DISABLE, 0);
1665
1666         /* set HW defaults for 3D engine */
1667         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1668                                      ROQ_IB2_START(0x2b)));
1669
1670         WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
1671
1672         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
1673                              SYNC_GRADIENT |
1674                              SYNC_WALKER |
1675                              SYNC_ALIGNER));
1676
1677         sx_debug_1 = RREG32(SX_DEBUG_1);
1678         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
1679         WREG32(SX_DEBUG_1, sx_debug_1);
1680
1681
1682         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
1683         smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
1684         smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
1685         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1686
1687         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
1688                                         POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
1689                                         SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
1690
1691         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
1692                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
1693                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
1694
1695         WREG32(VGT_NUM_INSTANCES, 1);
1696         WREG32(SPI_CONFIG_CNTL, 0);
1697         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1698         WREG32(CP_PERFMON_CNTL, 0);
1699
1700         WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
1701                                   FETCH_FIFO_HIWATER(0x4) |
1702                                   DONE_FIFO_HIWATER(0xe0) |
1703                                   ALU_UPDATE_FIFO_HIWATER(0x8)));
1704
1705         sq_config = RREG32(SQ_CONFIG);
1706         sq_config &= ~(PS_PRIO(3) |
1707                        VS_PRIO(3) |
1708                        GS_PRIO(3) |
1709                        ES_PRIO(3));
1710         sq_config |= (VC_ENABLE |
1711                       EXPORT_SRC_C |
1712                       PS_PRIO(0) |
1713                       VS_PRIO(1) |
1714                       GS_PRIO(2) |
1715                       ES_PRIO(3));
1716
1717         if (rdev->family == CHIP_CEDAR)
1718                 /* no vertex cache */
1719                 sq_config &= ~VC_ENABLE;
1720
1721         sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
1722
1723         sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
1724         sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
1725         sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
1726         sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
1727         sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
1728         sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
1729         sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
1730
1731         if (rdev->family == CHIP_CEDAR)
1732                 ps_thread_count = 96;
1733         else
1734                 ps_thread_count = 128;
1735
1736         sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
1737         sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1738         sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1739         sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1740         sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1741         sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1742
1743         sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1744         sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1745         sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1746         sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1747         sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1748         sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1749
1750         WREG32(SQ_CONFIG, sq_config);
1751         WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1752         WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1753         WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
1754         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1755         WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
1756         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1757         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1758         WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
1759         WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
1760         WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
1761
1762         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1763                                           FORCE_EOV_MAX_REZ_CNT(255)));
1764
1765         if (rdev->family == CHIP_CEDAR)
1766                 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
1767         else
1768                 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
1769         vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
1770         WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
1771
1772         WREG32(VGT_GS_VERTEX_REUSE, 16);
1773         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1774
1775         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
1776         WREG32(VGT_OUT_DEALLOC_CNTL, 16);
1777
1778         WREG32(CB_PERF_CTR0_SEL_0, 0);
1779         WREG32(CB_PERF_CTR0_SEL_1, 0);
1780         WREG32(CB_PERF_CTR1_SEL_0, 0);
1781         WREG32(CB_PERF_CTR1_SEL_1, 0);
1782         WREG32(CB_PERF_CTR2_SEL_0, 0);
1783         WREG32(CB_PERF_CTR2_SEL_1, 0);
1784         WREG32(CB_PERF_CTR3_SEL_0, 0);
1785         WREG32(CB_PERF_CTR3_SEL_1, 0);
1786
1787         /* clear render buffer base addresses */
1788         WREG32(CB_COLOR0_BASE, 0);
1789         WREG32(CB_COLOR1_BASE, 0);
1790         WREG32(CB_COLOR2_BASE, 0);
1791         WREG32(CB_COLOR3_BASE, 0);
1792         WREG32(CB_COLOR4_BASE, 0);
1793         WREG32(CB_COLOR5_BASE, 0);
1794         WREG32(CB_COLOR6_BASE, 0);
1795         WREG32(CB_COLOR7_BASE, 0);
1796         WREG32(CB_COLOR8_BASE, 0);
1797         WREG32(CB_COLOR9_BASE, 0);
1798         WREG32(CB_COLOR10_BASE, 0);
1799         WREG32(CB_COLOR11_BASE, 0);
1800
1801         /* set the shader const cache sizes to 0 */
1802         for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
1803                 WREG32(i, 0);
1804         for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
1805                 WREG32(i, 0);
1806
1807         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1808         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1809
1810         WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1811
1812         udelay(50);
1813
1814 }
1815
1816 int evergreen_mc_init(struct radeon_device *rdev)
1817 {
1818         u32 tmp;
1819         int chansize, numchan;
1820
1821         /* Get VRAM informations */
1822         rdev->mc.vram_is_ddr = true;
1823         tmp = RREG32(MC_ARB_RAMCFG);
1824         if (tmp & CHANSIZE_OVERRIDE) {
1825                 chansize = 16;
1826         } else if (tmp & CHANSIZE_MASK) {
1827                 chansize = 64;
1828         } else {
1829                 chansize = 32;
1830         }
1831         tmp = RREG32(MC_SHARED_CHMAP);
1832         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1833         case 0:
1834         default:
1835                 numchan = 1;
1836                 break;
1837         case 1:
1838                 numchan = 2;
1839                 break;
1840         case 2:
1841                 numchan = 4;
1842                 break;
1843         case 3:
1844                 numchan = 8;
1845                 break;
1846         }
1847         rdev->mc.vram_width = numchan * chansize;
1848         /* Could aper size report 0 ? */
1849         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1850         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1851         /* Setup GPU memory space */
1852         /* size in MB on evergreen */
1853         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
1854         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
1855         rdev->mc.visible_vram_size = rdev->mc.aper_size;
1856         rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
1857         r600_vram_gtt_location(rdev, &rdev->mc);
1858         radeon_update_bandwidth_info(rdev);
1859
1860         return 0;
1861 }
1862
1863 bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
1864 {
1865         /* FIXME: implement for evergreen */
1866         return false;
1867 }
1868
1869 static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
1870 {
1871         struct evergreen_mc_save save;
1872         u32 srbm_reset = 0;
1873         u32 grbm_reset = 0;
1874
1875         dev_info(rdev->dev, "GPU softreset \n");
1876         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
1877                 RREG32(GRBM_STATUS));
1878         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
1879                 RREG32(GRBM_STATUS_SE0));
1880         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
1881                 RREG32(GRBM_STATUS_SE1));
1882         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
1883                 RREG32(SRBM_STATUS));
1884         evergreen_mc_stop(rdev, &save);
1885         if (evergreen_mc_wait_for_idle(rdev)) {
1886                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1887         }
1888         /* Disable CP parsing/prefetching */
1889         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1890
1891         /* reset all the gfx blocks */
1892         grbm_reset = (SOFT_RESET_CP |
1893                       SOFT_RESET_CB |
1894                       SOFT_RESET_DB |
1895                       SOFT_RESET_PA |
1896                       SOFT_RESET_SC |
1897                       SOFT_RESET_SPI |
1898                       SOFT_RESET_SH |
1899                       SOFT_RESET_SX |
1900                       SOFT_RESET_TC |
1901                       SOFT_RESET_TA |
1902                       SOFT_RESET_VC |
1903                       SOFT_RESET_VGT);
1904
1905         dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
1906         WREG32(GRBM_SOFT_RESET, grbm_reset);
1907         (void)RREG32(GRBM_SOFT_RESET);
1908         udelay(50);
1909         WREG32(GRBM_SOFT_RESET, 0);
1910         (void)RREG32(GRBM_SOFT_RESET);
1911
1912         /* reset all the system blocks */
1913         srbm_reset = SRBM_SOFT_RESET_ALL_MASK;
1914
1915         dev_info(rdev->dev, "  SRBM_SOFT_RESET=0x%08X\n", srbm_reset);
1916         WREG32(SRBM_SOFT_RESET, srbm_reset);
1917         (void)RREG32(SRBM_SOFT_RESET);
1918         udelay(50);
1919         WREG32(SRBM_SOFT_RESET, 0);
1920         (void)RREG32(SRBM_SOFT_RESET);
1921         /* Wait a little for things to settle down */
1922         udelay(50);
1923         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
1924                 RREG32(GRBM_STATUS));
1925         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
1926                 RREG32(GRBM_STATUS_SE0));
1927         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
1928                 RREG32(GRBM_STATUS_SE1));
1929         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
1930                 RREG32(SRBM_STATUS));
1931         /* After reset we need to reinit the asic as GPU often endup in an
1932          * incoherent state.
1933          */
1934         atom_asic_init(rdev->mode_info.atom_context);
1935         evergreen_mc_resume(rdev, &save);
1936         return 0;
1937 }
1938
1939 int evergreen_asic_reset(struct radeon_device *rdev)
1940 {
1941         return evergreen_gpu_soft_reset(rdev);
1942 }
1943
1944 /* Interrupts */
1945
1946 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
1947 {
1948         switch (crtc) {
1949         case 0:
1950                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
1951         case 1:
1952                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
1953         case 2:
1954                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
1955         case 3:
1956                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
1957         case 4:
1958                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
1959         case 5:
1960                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
1961         default:
1962                 return 0;
1963         }
1964 }
1965
1966 void evergreen_disable_interrupt_state(struct radeon_device *rdev)
1967 {
1968         u32 tmp;
1969
1970         WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
1971         WREG32(GRBM_INT_CNTL, 0);
1972         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1973         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1974         WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1975         WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1976         WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1977         WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1978
1979         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1980         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1981         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1982         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1983         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1984         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1985
1986         WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
1987         WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
1988
1989         tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1990         WREG32(DC_HPD1_INT_CONTROL, tmp);
1991         tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1992         WREG32(DC_HPD2_INT_CONTROL, tmp);
1993         tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1994         WREG32(DC_HPD3_INT_CONTROL, tmp);
1995         tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1996         WREG32(DC_HPD4_INT_CONTROL, tmp);
1997         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1998         WREG32(DC_HPD5_INT_CONTROL, tmp);
1999         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2000         WREG32(DC_HPD6_INT_CONTROL, tmp);
2001
2002 }
2003
2004 int evergreen_irq_set(struct radeon_device *rdev)
2005 {
2006         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2007         u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2008         u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2009         u32 grbm_int_cntl = 0;
2010
2011         if (!rdev->irq.installed) {
2012                 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
2013                 return -EINVAL;
2014         }
2015         /* don't enable anything if the ih is disabled */
2016         if (!rdev->ih.enabled) {
2017                 r600_disable_interrupts(rdev);
2018                 /* force the active interrupt state to all disabled */
2019                 evergreen_disable_interrupt_state(rdev);
2020                 return 0;
2021         }
2022
2023         hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2024         hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2025         hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2026         hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2027         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2028         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2029
2030         if (rdev->irq.sw_int) {
2031                 DRM_DEBUG("evergreen_irq_set: sw int\n");
2032                 cp_int_cntl |= RB_INT_ENABLE;
2033                 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2034         }
2035         if (rdev->irq.crtc_vblank_int[0]) {
2036                 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2037                 crtc1 |= VBLANK_INT_MASK;
2038         }
2039         if (rdev->irq.crtc_vblank_int[1]) {
2040                 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2041                 crtc2 |= VBLANK_INT_MASK;
2042         }
2043         if (rdev->irq.crtc_vblank_int[2]) {
2044                 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2045                 crtc3 |= VBLANK_INT_MASK;
2046         }
2047         if (rdev->irq.crtc_vblank_int[3]) {
2048                 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2049                 crtc4 |= VBLANK_INT_MASK;
2050         }
2051         if (rdev->irq.crtc_vblank_int[4]) {
2052                 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2053                 crtc5 |= VBLANK_INT_MASK;
2054         }
2055         if (rdev->irq.crtc_vblank_int[5]) {
2056                 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2057                 crtc6 |= VBLANK_INT_MASK;
2058         }
2059         if (rdev->irq.hpd[0]) {
2060                 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2061                 hpd1 |= DC_HPDx_INT_EN;
2062         }
2063         if (rdev->irq.hpd[1]) {
2064                 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2065                 hpd2 |= DC_HPDx_INT_EN;
2066         }
2067         if (rdev->irq.hpd[2]) {
2068                 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2069                 hpd3 |= DC_HPDx_INT_EN;
2070         }
2071         if (rdev->irq.hpd[3]) {
2072                 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2073                 hpd4 |= DC_HPDx_INT_EN;
2074         }
2075         if (rdev->irq.hpd[4]) {
2076                 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2077                 hpd5 |= DC_HPDx_INT_EN;
2078         }
2079         if (rdev->irq.hpd[5]) {
2080                 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2081                 hpd6 |= DC_HPDx_INT_EN;
2082         }
2083         if (rdev->irq.gui_idle) {
2084                 DRM_DEBUG("gui idle\n");
2085                 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2086         }
2087
2088         WREG32(CP_INT_CNTL, cp_int_cntl);
2089         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
2090
2091         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2092         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2093         WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2094         WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2095         WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2096         WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2097
2098         WREG32(DC_HPD1_INT_CONTROL, hpd1);
2099         WREG32(DC_HPD2_INT_CONTROL, hpd2);
2100         WREG32(DC_HPD3_INT_CONTROL, hpd3);
2101         WREG32(DC_HPD4_INT_CONTROL, hpd4);
2102         WREG32(DC_HPD5_INT_CONTROL, hpd5);
2103         WREG32(DC_HPD6_INT_CONTROL, hpd6);
2104
2105         return 0;
2106 }
2107
2108 static inline void evergreen_irq_ack(struct radeon_device *rdev,
2109                                      u32 *disp_int,
2110                                      u32 *disp_int_cont,
2111                                      u32 *disp_int_cont2,
2112                                      u32 *disp_int_cont3,
2113                                      u32 *disp_int_cont4,
2114                                      u32 *disp_int_cont5)
2115 {
2116         u32 tmp;
2117
2118         *disp_int = RREG32(DISP_INTERRUPT_STATUS);
2119         *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2120         *disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2121         *disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2122         *disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2123         *disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2124
2125         if (*disp_int & LB_D1_VBLANK_INTERRUPT)
2126                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
2127         if (*disp_int & LB_D1_VLINE_INTERRUPT)
2128                 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2129
2130         if (*disp_int_cont & LB_D2_VBLANK_INTERRUPT)
2131                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
2132         if (*disp_int_cont & LB_D2_VLINE_INTERRUPT)
2133                 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2134
2135         if (*disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2136                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2137         if (*disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2138                 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2139
2140         if (*disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2141                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2142         if (*disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2143                 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2144
2145         if (*disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2146                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2147         if (*disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2148                 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2149
2150         if (*disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2151                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2152         if (*disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2153                 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2154
2155         if (*disp_int & DC_HPD1_INTERRUPT) {
2156                 tmp = RREG32(DC_HPD1_INT_CONTROL);
2157                 tmp |= DC_HPDx_INT_ACK;
2158                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2159         }
2160         if (*disp_int_cont & DC_HPD2_INTERRUPT) {
2161                 tmp = RREG32(DC_HPD2_INT_CONTROL);
2162                 tmp |= DC_HPDx_INT_ACK;
2163                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2164         }
2165         if (*disp_int_cont2 & DC_HPD3_INTERRUPT) {
2166                 tmp = RREG32(DC_HPD3_INT_CONTROL);
2167                 tmp |= DC_HPDx_INT_ACK;
2168                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2169         }
2170         if (*disp_int_cont3 & DC_HPD4_INTERRUPT) {
2171                 tmp = RREG32(DC_HPD4_INT_CONTROL);
2172                 tmp |= DC_HPDx_INT_ACK;
2173                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2174         }
2175         if (*disp_int_cont4 & DC_HPD5_INTERRUPT) {
2176                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2177                 tmp |= DC_HPDx_INT_ACK;
2178                 WREG32(DC_HPD5_INT_CONTROL, tmp);
2179         }
2180         if (*disp_int_cont5 & DC_HPD6_INTERRUPT) {
2181                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2182                 tmp |= DC_HPDx_INT_ACK;
2183                 WREG32(DC_HPD6_INT_CONTROL, tmp);
2184         }
2185 }
2186
2187 void evergreen_irq_disable(struct radeon_device *rdev)
2188 {
2189         u32 disp_int, disp_int_cont, disp_int_cont2;
2190         u32 disp_int_cont3, disp_int_cont4, disp_int_cont5;
2191
2192         r600_disable_interrupts(rdev);
2193         /* Wait and acknowledge irq */
2194         mdelay(1);
2195         evergreen_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2,
2196                           &disp_int_cont3, &disp_int_cont4, &disp_int_cont5);
2197         evergreen_disable_interrupt_state(rdev);
2198 }
2199
2200 static void evergreen_irq_suspend(struct radeon_device *rdev)
2201 {
2202         evergreen_irq_disable(rdev);
2203         r600_rlc_stop(rdev);
2204 }
2205
2206 static inline u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2207 {
2208         u32 wptr, tmp;
2209
2210         if (rdev->wb.enabled)
2211                 wptr = rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4];
2212         else
2213                 wptr = RREG32(IH_RB_WPTR);
2214
2215         if (wptr & RB_OVERFLOW) {
2216                 /* When a ring buffer overflow happen start parsing interrupt
2217                  * from the last not overwritten vector (wptr + 16). Hopefully
2218                  * this should allow us to catchup.
2219                  */
2220                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2221                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2222                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2223                 tmp = RREG32(IH_RB_CNTL);
2224                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2225                 WREG32(IH_RB_CNTL, tmp);
2226         }
2227         return (wptr & rdev->ih.ptr_mask);
2228 }
2229
2230 int evergreen_irq_process(struct radeon_device *rdev)
2231 {
2232         u32 wptr = evergreen_get_ih_wptr(rdev);
2233         u32 rptr = rdev->ih.rptr;
2234         u32 src_id, src_data;
2235         u32 ring_index;
2236         u32 disp_int, disp_int_cont, disp_int_cont2;
2237         u32 disp_int_cont3, disp_int_cont4, disp_int_cont5;
2238         unsigned long flags;
2239         bool queue_hotplug = false;
2240
2241         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2242         if (!rdev->ih.enabled)
2243                 return IRQ_NONE;
2244
2245         spin_lock_irqsave(&rdev->ih.lock, flags);
2246
2247         if (rptr == wptr) {
2248                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2249                 return IRQ_NONE;
2250         }
2251         if (rdev->shutdown) {
2252                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2253                 return IRQ_NONE;
2254         }
2255
2256 restart_ih:
2257         /* display interrupts */
2258         evergreen_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2,
2259                           &disp_int_cont3, &disp_int_cont4, &disp_int_cont5);
2260
2261         rdev->ih.wptr = wptr;
2262         while (rptr != wptr) {
2263                 /* wptr/rptr are in bytes! */
2264                 ring_index = rptr / 4;
2265                 src_id =  rdev->ih.ring[ring_index] & 0xff;
2266                 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
2267
2268                 switch (src_id) {
2269                 case 1: /* D1 vblank/vline */
2270                         switch (src_data) {
2271                         case 0: /* D1 vblank */
2272                                 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
2273                                         drm_handle_vblank(rdev->ddev, 0);
2274                                         wake_up(&rdev->irq.vblank_queue);
2275                                         disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2276                                         DRM_DEBUG("IH: D1 vblank\n");
2277                                 }
2278                                 break;
2279                         case 1: /* D1 vline */
2280                                 if (disp_int & LB_D1_VLINE_INTERRUPT) {
2281                                         disp_int &= ~LB_D1_VLINE_INTERRUPT;
2282                                         DRM_DEBUG("IH: D1 vline\n");
2283                                 }
2284                                 break;
2285                         default:
2286                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2287                                 break;
2288                         }
2289                         break;
2290                 case 2: /* D2 vblank/vline */
2291                         switch (src_data) {
2292                         case 0: /* D2 vblank */
2293                                 if (disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
2294                                         drm_handle_vblank(rdev->ddev, 1);
2295                                         wake_up(&rdev->irq.vblank_queue);
2296                                         disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
2297                                         DRM_DEBUG("IH: D2 vblank\n");
2298                                 }
2299                                 break;
2300                         case 1: /* D2 vline */
2301                                 if (disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2302                                         disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
2303                                         DRM_DEBUG("IH: D2 vline\n");
2304                                 }
2305                                 break;
2306                         default:
2307                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2308                                 break;
2309                         }
2310                         break;
2311                 case 3: /* D3 vblank/vline */
2312                         switch (src_data) {
2313                         case 0: /* D3 vblank */
2314                                 if (disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2315                                         drm_handle_vblank(rdev->ddev, 2);
2316                                         wake_up(&rdev->irq.vblank_queue);
2317                                         disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
2318                                         DRM_DEBUG("IH: D3 vblank\n");
2319                                 }
2320                                 break;
2321                         case 1: /* D3 vline */
2322                                 if (disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
2323                                         disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
2324                                         DRM_DEBUG("IH: D3 vline\n");
2325                                 }
2326                                 break;
2327                         default:
2328                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2329                                 break;
2330                         }
2331                         break;
2332                 case 4: /* D4 vblank/vline */
2333                         switch (src_data) {
2334                         case 0: /* D4 vblank */
2335                                 if (disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
2336                                         drm_handle_vblank(rdev->ddev, 3);
2337                                         wake_up(&rdev->irq.vblank_queue);
2338                                         disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
2339                                         DRM_DEBUG("IH: D4 vblank\n");
2340                                 }
2341                                 break;
2342                         case 1: /* D4 vline */
2343                                 if (disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
2344                                         disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
2345                                         DRM_DEBUG("IH: D4 vline\n");
2346                                 }
2347                                 break;
2348                         default:
2349                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2350                                 break;
2351                         }
2352                         break;
2353                 case 5: /* D5 vblank/vline */
2354                         switch (src_data) {
2355                         case 0: /* D5 vblank */
2356                                 if (disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
2357                                         drm_handle_vblank(rdev->ddev, 4);
2358                                         wake_up(&rdev->irq.vblank_queue);
2359                                         disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
2360                                         DRM_DEBUG("IH: D5 vblank\n");
2361                                 }
2362                                 break;
2363                         case 1: /* D5 vline */
2364                                 if (disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
2365                                         disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
2366                                         DRM_DEBUG("IH: D5 vline\n");
2367                                 }
2368                                 break;
2369                         default:
2370                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2371                                 break;
2372                         }
2373                         break;
2374                 case 6: /* D6 vblank/vline */
2375                         switch (src_data) {
2376                         case 0: /* D6 vblank */
2377                                 if (disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
2378                                         drm_handle_vblank(rdev->ddev, 5);
2379                                         wake_up(&rdev->irq.vblank_queue);
2380                                         disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
2381                                         DRM_DEBUG("IH: D6 vblank\n");
2382                                 }
2383                                 break;
2384                         case 1: /* D6 vline */
2385                                 if (disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
2386                                         disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
2387                                         DRM_DEBUG("IH: D6 vline\n");
2388                                 }
2389                                 break;
2390                         default:
2391                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2392                                 break;
2393                         }
2394                         break;
2395                 case 42: /* HPD hotplug */
2396                         switch (src_data) {
2397                         case 0:
2398                                 if (disp_int & DC_HPD1_INTERRUPT) {
2399                                         disp_int &= ~DC_HPD1_INTERRUPT;
2400                                         queue_hotplug = true;
2401                                         DRM_DEBUG("IH: HPD1\n");
2402                                 }
2403                                 break;
2404                         case 1:
2405                                 if (disp_int_cont & DC_HPD2_INTERRUPT) {
2406                                         disp_int_cont &= ~DC_HPD2_INTERRUPT;
2407                                         queue_hotplug = true;
2408                                         DRM_DEBUG("IH: HPD2\n");
2409                                 }
2410                                 break;
2411                         case 2:
2412                                 if (disp_int_cont2 & DC_HPD3_INTERRUPT) {
2413                                         disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
2414                                         queue_hotplug = true;
2415                                         DRM_DEBUG("IH: HPD3\n");
2416                                 }
2417                                 break;
2418                         case 3:
2419                                 if (disp_int_cont3 & DC_HPD4_INTERRUPT) {
2420                                         disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
2421                                         queue_hotplug = true;
2422                                         DRM_DEBUG("IH: HPD4\n");
2423                                 }
2424                                 break;
2425                         case 4:
2426                                 if (disp_int_cont4 & DC_HPD5_INTERRUPT) {
2427                                         disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
2428                                         queue_hotplug = true;
2429                                         DRM_DEBUG("IH: HPD5\n");
2430                                 }
2431                                 break;
2432                         case 5:
2433                                 if (disp_int_cont5 & DC_HPD6_INTERRUPT) {
2434                                         disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
2435                                         queue_hotplug = true;
2436                                         DRM_DEBUG("IH: HPD6\n");
2437                                 }
2438                                 break;
2439                         default:
2440                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2441                                 break;
2442                         }
2443                         break;
2444                 case 176: /* CP_INT in ring buffer */
2445                 case 177: /* CP_INT in IB1 */
2446                 case 178: /* CP_INT in IB2 */
2447                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2448                         radeon_fence_process(rdev);
2449                         break;
2450                 case 181: /* CP EOP event */
2451                         DRM_DEBUG("IH: CP EOP\n");
2452                         radeon_fence_process(rdev);
2453                         break;
2454                 case 233: /* GUI IDLE */
2455                         DRM_DEBUG("IH: CP EOP\n");
2456                         rdev->pm.gui_idle = true;
2457                         wake_up(&rdev->irq.idle_queue);
2458                         break;
2459                 default:
2460                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2461                         break;
2462                 }
2463
2464                 /* wptr/rptr are in bytes! */
2465                 rptr += 16;
2466                 rptr &= rdev->ih.ptr_mask;
2467         }
2468         /* make sure wptr hasn't changed while processing */
2469         wptr = evergreen_get_ih_wptr(rdev);
2470         if (wptr != rdev->ih.wptr)
2471                 goto restart_ih;
2472         if (queue_hotplug)
2473                 queue_work(rdev->wq, &rdev->hotplug_work);
2474         rdev->ih.rptr = rptr;
2475         WREG32(IH_RB_RPTR, rdev->ih.rptr);
2476         spin_unlock_irqrestore(&rdev->ih.lock, flags);
2477         return IRQ_HANDLED;
2478 }
2479
2480 static int evergreen_startup(struct radeon_device *rdev)
2481 {
2482         int r;
2483
2484         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2485                 r = r600_init_microcode(rdev);
2486                 if (r) {
2487                         DRM_ERROR("Failed to load firmware!\n");
2488                         return r;
2489                 }
2490         }
2491
2492         evergreen_mc_program(rdev);
2493         if (rdev->flags & RADEON_IS_AGP) {
2494                 evergreen_agp_enable(rdev);
2495         } else {
2496                 r = evergreen_pcie_gart_enable(rdev);
2497                 if (r)
2498                         return r;
2499         }
2500         evergreen_gpu_init(rdev);
2501
2502         r = evergreen_blit_init(rdev);
2503         if (r) {
2504                 evergreen_blit_fini(rdev);
2505                 rdev->asic->copy = NULL;
2506                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2507         }
2508
2509         /* allocate wb buffer */
2510         r = radeon_wb_init(rdev);
2511         if (r)
2512                 return r;
2513
2514         /* Enable IRQ */
2515         r = r600_irq_init(rdev);
2516         if (r) {
2517                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2518                 radeon_irq_kms_fini(rdev);
2519                 return r;
2520         }
2521         evergreen_irq_set(rdev);
2522
2523         r = radeon_ring_init(rdev, rdev->cp.ring_size);
2524         if (r)
2525                 return r;
2526         r = evergreen_cp_load_microcode(rdev);
2527         if (r)
2528                 return r;
2529         r = evergreen_cp_resume(rdev);
2530         if (r)
2531                 return r;
2532
2533         return 0;
2534 }
2535
2536 int evergreen_resume(struct radeon_device *rdev)
2537 {
2538         int r;
2539
2540         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
2541          * posting will perform necessary task to bring back GPU into good
2542          * shape.
2543          */
2544         /* post card */
2545         atom_asic_init(rdev->mode_info.atom_context);
2546
2547         r = evergreen_startup(rdev);
2548         if (r) {
2549                 DRM_ERROR("r600 startup failed on resume\n");
2550                 return r;
2551         }
2552
2553         r = r600_ib_test(rdev);
2554         if (r) {
2555                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2556                 return r;
2557         }
2558
2559         return r;
2560
2561 }
2562
2563 int evergreen_suspend(struct radeon_device *rdev)
2564 {
2565         int r;
2566
2567         /* FIXME: we should wait for ring to be empty */
2568         r700_cp_stop(rdev);
2569         rdev->cp.ready = false;
2570         evergreen_irq_suspend(rdev);
2571         radeon_wb_disable(rdev);
2572         evergreen_pcie_gart_disable(rdev);
2573
2574         /* unpin shaders bo */
2575         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2576         if (likely(r == 0)) {
2577                 radeon_bo_unpin(rdev->r600_blit.shader_obj);
2578                 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2579         }
2580
2581         return 0;
2582 }
2583
2584 int evergreen_copy_blit(struct radeon_device *rdev,
2585                         uint64_t src_offset, uint64_t dst_offset,
2586                         unsigned num_pages, struct radeon_fence *fence)
2587 {
2588         int r;
2589
2590         mutex_lock(&rdev->r600_blit.mutex);
2591         rdev->r600_blit.vb_ib = NULL;
2592         r = evergreen_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
2593         if (r) {
2594                 if (rdev->r600_blit.vb_ib)
2595                         radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2596                 mutex_unlock(&rdev->r600_blit.mutex);
2597                 return r;
2598         }
2599         evergreen_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
2600         evergreen_blit_done_copy(rdev, fence);
2601         mutex_unlock(&rdev->r600_blit.mutex);
2602         return 0;
2603 }
2604
2605 static bool evergreen_card_posted(struct radeon_device *rdev)
2606 {
2607         u32 reg;
2608
2609         /* first check CRTCs */
2610         reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
2611                 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
2612                 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
2613                 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
2614                 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
2615                 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
2616         if (reg & EVERGREEN_CRTC_MASTER_EN)
2617                 return true;
2618
2619         /* then check MEM_SIZE, in case the crtcs are off */
2620         if (RREG32(CONFIG_MEMSIZE))
2621                 return true;
2622
2623         return false;
2624 }
2625
2626 /* Plan is to move initialization in that function and use
2627  * helper function so that radeon_device_init pretty much
2628  * do nothing more than calling asic specific function. This
2629  * should also allow to remove a bunch of callback function
2630  * like vram_info.
2631  */
2632 int evergreen_init(struct radeon_device *rdev)
2633 {
2634         int r;
2635
2636         r = radeon_dummy_page_init(rdev);
2637         if (r)
2638                 return r;
2639         /* This don't do much */
2640         r = radeon_gem_init(rdev);
2641         if (r)
2642                 return r;
2643         /* Read BIOS */
2644         if (!radeon_get_bios(rdev)) {
2645                 if (ASIC_IS_AVIVO(rdev))
2646                         return -EINVAL;
2647         }
2648         /* Must be an ATOMBIOS */
2649         if (!rdev->is_atom_bios) {
2650                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2651                 return -EINVAL;
2652         }
2653         r = radeon_atombios_init(rdev);
2654         if (r)
2655                 return r;
2656         /* Post card if necessary */
2657         if (!evergreen_card_posted(rdev)) {
2658                 if (!rdev->bios) {
2659                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2660                         return -EINVAL;
2661                 }
2662                 DRM_INFO("GPU not posted. posting now...\n");
2663                 atom_asic_init(rdev->mode_info.atom_context);
2664         }
2665         /* Initialize scratch registers */
2666         r600_scratch_init(rdev);
2667         /* Initialize surface registers */
2668         radeon_surface_init(rdev);
2669         /* Initialize clocks */
2670         radeon_get_clock_info(rdev->ddev);
2671         /* Fence driver */
2672         r = radeon_fence_driver_init(rdev);
2673         if (r)
2674                 return r;
2675         /* initialize AGP */
2676         if (rdev->flags & RADEON_IS_AGP) {
2677                 r = radeon_agp_init(rdev);
2678                 if (r)
2679                         radeon_agp_disable(rdev);
2680         }
2681         /* initialize memory controller */
2682         r = evergreen_mc_init(rdev);
2683         if (r)
2684                 return r;
2685         /* Memory manager */
2686         r = radeon_bo_init(rdev);
2687         if (r)
2688                 return r;
2689
2690         r = radeon_irq_kms_init(rdev);
2691         if (r)
2692                 return r;
2693
2694         rdev->cp.ring_obj = NULL;
2695         r600_ring_init(rdev, 1024 * 1024);
2696
2697         rdev->ih.ring_obj = NULL;
2698         r600_ih_ring_init(rdev, 64 * 1024);
2699
2700         r = r600_pcie_gart_init(rdev);
2701         if (r)
2702                 return r;
2703
2704         rdev->accel_working = true;
2705         r = evergreen_startup(rdev);
2706         if (r) {
2707                 dev_err(rdev->dev, "disabling GPU acceleration\n");
2708                 r700_cp_fini(rdev);
2709                 r600_irq_fini(rdev);
2710                 radeon_wb_fini(rdev);
2711                 radeon_irq_kms_fini(rdev);
2712                 evergreen_pcie_gart_fini(rdev);
2713                 rdev->accel_working = false;
2714         }
2715         if (rdev->accel_working) {
2716                 r = radeon_ib_pool_init(rdev);
2717                 if (r) {
2718                         DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
2719                         rdev->accel_working = false;
2720                 }
2721                 r = r600_ib_test(rdev);
2722                 if (r) {
2723                         DRM_ERROR("radeon: failed testing IB (%d).\n", r);
2724                         rdev->accel_working = false;
2725                 }
2726         }
2727         return 0;
2728 }
2729
2730 void evergreen_fini(struct radeon_device *rdev)
2731 {
2732         evergreen_blit_fini(rdev);
2733         r700_cp_fini(rdev);
2734         r600_irq_fini(rdev);
2735         radeon_wb_fini(rdev);
2736         radeon_irq_kms_fini(rdev);
2737         evergreen_pcie_gart_fini(rdev);
2738         radeon_gem_fini(rdev);
2739         radeon_fence_driver_fini(rdev);
2740         radeon_agp_fini(rdev);
2741         radeon_bo_fini(rdev);
2742         radeon_atombios_fini(rdev);
2743         kfree(rdev->bios);
2744         rdev->bios = NULL;
2745         radeon_dummy_page_fini(rdev);
2746 }