6ced1ba2bee85e68d32251dc6a9200af58b2bbc6
[linux-2.6.git] / drivers / gpu / drm / radeon / evergreen.c
1 /*
2  * Copyright 2010 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Alex Deucher
23  */
24 #include <linux/firmware.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
27 #include "drmP.h"
28 #include "radeon.h"
29 #include "radeon_asic.h"
30 #include "radeon_drm.h"
31 #include "evergreend.h"
32 #include "atom.h"
33 #include "avivod.h"
34 #include "evergreen_reg.h"
35 #include "evergreen_blit_shaders.h"
36
37 #define EVERGREEN_PFP_UCODE_SIZE 1120
38 #define EVERGREEN_PM4_UCODE_SIZE 1376
39
40 static void evergreen_gpu_init(struct radeon_device *rdev);
41 void evergreen_fini(struct radeon_device *rdev);
42
43 /* get temperature in millidegrees */
44 u32 evergreen_get_temp(struct radeon_device *rdev)
45 {
46         u32 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
47                 ASIC_T_SHIFT;
48         u32 actual_temp = 0;
49
50         if ((temp >> 10) & 1)
51                 actual_temp = 0;
52         else if ((temp >> 9) & 1)
53                 actual_temp = 255;
54         else
55                 actual_temp = (temp >> 1) & 0xff;
56
57         return actual_temp * 1000;
58 }
59
60 void evergreen_pm_misc(struct radeon_device *rdev)
61 {
62         int req_ps_idx = rdev->pm.requested_power_state_index;
63         int req_cm_idx = rdev->pm.requested_clock_mode_index;
64         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
65         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
66
67         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
68                 if (voltage->voltage != rdev->pm.current_vddc) {
69                         radeon_atom_set_voltage(rdev, voltage->voltage);
70                         rdev->pm.current_vddc = voltage->voltage;
71                         DRM_DEBUG("Setting: v: %d\n", voltage->voltage);
72                 }
73         }
74 }
75
76 void evergreen_pm_prepare(struct radeon_device *rdev)
77 {
78         struct drm_device *ddev = rdev->ddev;
79         struct drm_crtc *crtc;
80         struct radeon_crtc *radeon_crtc;
81         u32 tmp;
82
83         /* disable any active CRTCs */
84         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
85                 radeon_crtc = to_radeon_crtc(crtc);
86                 if (radeon_crtc->enabled) {
87                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
88                         tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
89                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
90                 }
91         }
92 }
93
94 void evergreen_pm_finish(struct radeon_device *rdev)
95 {
96         struct drm_device *ddev = rdev->ddev;
97         struct drm_crtc *crtc;
98         struct radeon_crtc *radeon_crtc;
99         u32 tmp;
100
101         /* enable any active CRTCs */
102         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
103                 radeon_crtc = to_radeon_crtc(crtc);
104                 if (radeon_crtc->enabled) {
105                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
106                         tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
107                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
108                 }
109         }
110 }
111
112 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
113 {
114         bool connected = false;
115
116         switch (hpd) {
117         case RADEON_HPD_1:
118                 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
119                         connected = true;
120                 break;
121         case RADEON_HPD_2:
122                 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
123                         connected = true;
124                 break;
125         case RADEON_HPD_3:
126                 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
127                         connected = true;
128                 break;
129         case RADEON_HPD_4:
130                 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
131                         connected = true;
132                 break;
133         case RADEON_HPD_5:
134                 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
135                         connected = true;
136                 break;
137         case RADEON_HPD_6:
138                 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
139                         connected = true;
140                         break;
141         default:
142                 break;
143         }
144
145         return connected;
146 }
147
148 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
149                                 enum radeon_hpd_id hpd)
150 {
151         u32 tmp;
152         bool connected = evergreen_hpd_sense(rdev, hpd);
153
154         switch (hpd) {
155         case RADEON_HPD_1:
156                 tmp = RREG32(DC_HPD1_INT_CONTROL);
157                 if (connected)
158                         tmp &= ~DC_HPDx_INT_POLARITY;
159                 else
160                         tmp |= DC_HPDx_INT_POLARITY;
161                 WREG32(DC_HPD1_INT_CONTROL, tmp);
162                 break;
163         case RADEON_HPD_2:
164                 tmp = RREG32(DC_HPD2_INT_CONTROL);
165                 if (connected)
166                         tmp &= ~DC_HPDx_INT_POLARITY;
167                 else
168                         tmp |= DC_HPDx_INT_POLARITY;
169                 WREG32(DC_HPD2_INT_CONTROL, tmp);
170                 break;
171         case RADEON_HPD_3:
172                 tmp = RREG32(DC_HPD3_INT_CONTROL);
173                 if (connected)
174                         tmp &= ~DC_HPDx_INT_POLARITY;
175                 else
176                         tmp |= DC_HPDx_INT_POLARITY;
177                 WREG32(DC_HPD3_INT_CONTROL, tmp);
178                 break;
179         case RADEON_HPD_4:
180                 tmp = RREG32(DC_HPD4_INT_CONTROL);
181                 if (connected)
182                         tmp &= ~DC_HPDx_INT_POLARITY;
183                 else
184                         tmp |= DC_HPDx_INT_POLARITY;
185                 WREG32(DC_HPD4_INT_CONTROL, tmp);
186                 break;
187         case RADEON_HPD_5:
188                 tmp = RREG32(DC_HPD5_INT_CONTROL);
189                 if (connected)
190                         tmp &= ~DC_HPDx_INT_POLARITY;
191                 else
192                         tmp |= DC_HPDx_INT_POLARITY;
193                 WREG32(DC_HPD5_INT_CONTROL, tmp);
194                         break;
195         case RADEON_HPD_6:
196                 tmp = RREG32(DC_HPD6_INT_CONTROL);
197                 if (connected)
198                         tmp &= ~DC_HPDx_INT_POLARITY;
199                 else
200                         tmp |= DC_HPDx_INT_POLARITY;
201                 WREG32(DC_HPD6_INT_CONTROL, tmp);
202                 break;
203         default:
204                 break;
205         }
206 }
207
208 void evergreen_hpd_init(struct radeon_device *rdev)
209 {
210         struct drm_device *dev = rdev->ddev;
211         struct drm_connector *connector;
212         u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
213                 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
214
215         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
216                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
217                 switch (radeon_connector->hpd.hpd) {
218                 case RADEON_HPD_1:
219                         WREG32(DC_HPD1_CONTROL, tmp);
220                         rdev->irq.hpd[0] = true;
221                         break;
222                 case RADEON_HPD_2:
223                         WREG32(DC_HPD2_CONTROL, tmp);
224                         rdev->irq.hpd[1] = true;
225                         break;
226                 case RADEON_HPD_3:
227                         WREG32(DC_HPD3_CONTROL, tmp);
228                         rdev->irq.hpd[2] = true;
229                         break;
230                 case RADEON_HPD_4:
231                         WREG32(DC_HPD4_CONTROL, tmp);
232                         rdev->irq.hpd[3] = true;
233                         break;
234                 case RADEON_HPD_5:
235                         WREG32(DC_HPD5_CONTROL, tmp);
236                         rdev->irq.hpd[4] = true;
237                         break;
238                 case RADEON_HPD_6:
239                         WREG32(DC_HPD6_CONTROL, tmp);
240                         rdev->irq.hpd[5] = true;
241                         break;
242                 default:
243                         break;
244                 }
245         }
246         if (rdev->irq.installed)
247                 evergreen_irq_set(rdev);
248 }
249
250 void evergreen_hpd_fini(struct radeon_device *rdev)
251 {
252         struct drm_device *dev = rdev->ddev;
253         struct drm_connector *connector;
254
255         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
256                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
257                 switch (radeon_connector->hpd.hpd) {
258                 case RADEON_HPD_1:
259                         WREG32(DC_HPD1_CONTROL, 0);
260                         rdev->irq.hpd[0] = false;
261                         break;
262                 case RADEON_HPD_2:
263                         WREG32(DC_HPD2_CONTROL, 0);
264                         rdev->irq.hpd[1] = false;
265                         break;
266                 case RADEON_HPD_3:
267                         WREG32(DC_HPD3_CONTROL, 0);
268                         rdev->irq.hpd[2] = false;
269                         break;
270                 case RADEON_HPD_4:
271                         WREG32(DC_HPD4_CONTROL, 0);
272                         rdev->irq.hpd[3] = false;
273                         break;
274                 case RADEON_HPD_5:
275                         WREG32(DC_HPD5_CONTROL, 0);
276                         rdev->irq.hpd[4] = false;
277                         break;
278                 case RADEON_HPD_6:
279                         WREG32(DC_HPD6_CONTROL, 0);
280                         rdev->irq.hpd[5] = false;
281                         break;
282                 default:
283                         break;
284                 }
285         }
286 }
287
288 /* watermark setup */
289
290 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
291                                         struct radeon_crtc *radeon_crtc,
292                                         struct drm_display_mode *mode,
293                                         struct drm_display_mode *other_mode)
294 {
295         u32 tmp = 0;
296         /*
297          * Line Buffer Setup
298          * There are 3 line buffers, each one shared by 2 display controllers.
299          * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
300          * the display controllers.  The paritioning is done via one of four
301          * preset allocations specified in bits 2:0:
302          * first display controller
303          *  0 - first half of lb (3840 * 2)
304          *  1 - first 3/4 of lb (5760 * 2)
305          *  2 - whole lb (7680 * 2)
306          *  3 - first 1/4 of lb (1920 * 2)
307          * second display controller
308          *  4 - second half of lb (3840 * 2)
309          *  5 - second 3/4 of lb (5760 * 2)
310          *  6 - whole lb (7680 * 2)
311          *  7 - last 1/4 of lb (1920 * 2)
312          */
313         if (mode && other_mode) {
314                 if (mode->hdisplay > other_mode->hdisplay) {
315                         if (mode->hdisplay > 2560)
316                                 tmp = 1; /* 3/4 */
317                         else
318                                 tmp = 0; /* 1/2 */
319                 } else if (other_mode->hdisplay > mode->hdisplay) {
320                         if (other_mode->hdisplay > 2560)
321                                 tmp = 3; /* 1/4 */
322                         else
323                                 tmp = 0; /* 1/2 */
324                 } else
325                         tmp = 0; /* 1/2 */
326         } else if (mode)
327                 tmp = 2; /* whole */
328         else if (other_mode)
329                 tmp = 3; /* 1/4 */
330
331         /* second controller of the pair uses second half of the lb */
332         if (radeon_crtc->crtc_id % 2)
333                 tmp += 4;
334         WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
335
336         switch (tmp) {
337         case 0:
338         case 4:
339         default:
340                 return 3840 * 2;
341         case 1:
342         case 5:
343                 return 5760 * 2;
344         case 2:
345         case 6:
346                 return 7680 * 2;
347         case 3:
348         case 7:
349                 return 1920 * 2;
350         }
351 }
352
353 static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
354 {
355         u32 tmp = RREG32(MC_SHARED_CHMAP);
356
357         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
358         case 0:
359         default:
360                 return 1;
361         case 1:
362                 return 2;
363         case 2:
364                 return 4;
365         case 3:
366                 return 8;
367         }
368 }
369
370 struct evergreen_wm_params {
371         u32 dram_channels; /* number of dram channels */
372         u32 yclk;          /* bandwidth per dram data pin in kHz */
373         u32 sclk;          /* engine clock in kHz */
374         u32 disp_clk;      /* display clock in kHz */
375         u32 src_width;     /* viewport width */
376         u32 active_time;   /* active display time in ns */
377         u32 blank_time;    /* blank time in ns */
378         bool interlaced;    /* mode is interlaced */
379         fixed20_12 vsc;    /* vertical scale ratio */
380         u32 num_heads;     /* number of active crtcs */
381         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
382         u32 lb_size;       /* line buffer allocated to pipe */
383         u32 vtaps;         /* vertical scaler taps */
384 };
385
386 static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
387 {
388         /* Calculate DRAM Bandwidth and the part allocated to display. */
389         fixed20_12 dram_efficiency; /* 0.7 */
390         fixed20_12 yclk, dram_channels, bandwidth;
391         fixed20_12 a;
392
393         a.full = dfixed_const(1000);
394         yclk.full = dfixed_const(wm->yclk);
395         yclk.full = dfixed_div(yclk, a);
396         dram_channels.full = dfixed_const(wm->dram_channels * 4);
397         a.full = dfixed_const(10);
398         dram_efficiency.full = dfixed_const(7);
399         dram_efficiency.full = dfixed_div(dram_efficiency, a);
400         bandwidth.full = dfixed_mul(dram_channels, yclk);
401         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
402
403         return dfixed_trunc(bandwidth);
404 }
405
406 static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
407 {
408         /* Calculate DRAM Bandwidth and the part allocated to display. */
409         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
410         fixed20_12 yclk, dram_channels, bandwidth;
411         fixed20_12 a;
412
413         a.full = dfixed_const(1000);
414         yclk.full = dfixed_const(wm->yclk);
415         yclk.full = dfixed_div(yclk, a);
416         dram_channels.full = dfixed_const(wm->dram_channels * 4);
417         a.full = dfixed_const(10);
418         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
419         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
420         bandwidth.full = dfixed_mul(dram_channels, yclk);
421         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
422
423         return dfixed_trunc(bandwidth);
424 }
425
426 static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
427 {
428         /* Calculate the display Data return Bandwidth */
429         fixed20_12 return_efficiency; /* 0.8 */
430         fixed20_12 sclk, bandwidth;
431         fixed20_12 a;
432
433         a.full = dfixed_const(1000);
434         sclk.full = dfixed_const(wm->sclk);
435         sclk.full = dfixed_div(sclk, a);
436         a.full = dfixed_const(10);
437         return_efficiency.full = dfixed_const(8);
438         return_efficiency.full = dfixed_div(return_efficiency, a);
439         a.full = dfixed_const(32);
440         bandwidth.full = dfixed_mul(a, sclk);
441         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
442
443         return dfixed_trunc(bandwidth);
444 }
445
446 static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
447 {
448         /* Calculate the DMIF Request Bandwidth */
449         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
450         fixed20_12 disp_clk, bandwidth;
451         fixed20_12 a;
452
453         a.full = dfixed_const(1000);
454         disp_clk.full = dfixed_const(wm->disp_clk);
455         disp_clk.full = dfixed_div(disp_clk, a);
456         a.full = dfixed_const(10);
457         disp_clk_request_efficiency.full = dfixed_const(8);
458         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
459         a.full = dfixed_const(32);
460         bandwidth.full = dfixed_mul(a, disp_clk);
461         bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
462
463         return dfixed_trunc(bandwidth);
464 }
465
466 static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
467 {
468         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
469         u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
470         u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
471         u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
472
473         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
474 }
475
476 static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
477 {
478         /* Calculate the display mode Average Bandwidth
479          * DisplayMode should contain the source and destination dimensions,
480          * timing, etc.
481          */
482         fixed20_12 bpp;
483         fixed20_12 line_time;
484         fixed20_12 src_width;
485         fixed20_12 bandwidth;
486         fixed20_12 a;
487
488         a.full = dfixed_const(1000);
489         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
490         line_time.full = dfixed_div(line_time, a);
491         bpp.full = dfixed_const(wm->bytes_per_pixel);
492         src_width.full = dfixed_const(wm->src_width);
493         bandwidth.full = dfixed_mul(src_width, bpp);
494         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
495         bandwidth.full = dfixed_div(bandwidth, line_time);
496
497         return dfixed_trunc(bandwidth);
498 }
499
500 static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
501 {
502         /* First calcualte the latency in ns */
503         u32 mc_latency = 2000; /* 2000 ns. */
504         u32 available_bandwidth = evergreen_available_bandwidth(wm);
505         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
506         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
507         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
508         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
509                 (wm->num_heads * cursor_line_pair_return_time);
510         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
511         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
512         fixed20_12 a, b, c;
513
514         if (wm->num_heads == 0)
515                 return 0;
516
517         a.full = dfixed_const(2);
518         b.full = dfixed_const(1);
519         if ((wm->vsc.full > a.full) ||
520             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
521             (wm->vtaps >= 5) ||
522             ((wm->vsc.full >= a.full) && wm->interlaced))
523                 max_src_lines_per_dst_line = 4;
524         else
525                 max_src_lines_per_dst_line = 2;
526
527         a.full = dfixed_const(available_bandwidth);
528         b.full = dfixed_const(wm->num_heads);
529         a.full = dfixed_div(a, b);
530
531         b.full = dfixed_const(1000);
532         c.full = dfixed_const(wm->disp_clk);
533         b.full = dfixed_div(c, b);
534         c.full = dfixed_const(wm->bytes_per_pixel);
535         b.full = dfixed_mul(b, c);
536
537         lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
538
539         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
540         b.full = dfixed_const(1000);
541         c.full = dfixed_const(lb_fill_bw);
542         b.full = dfixed_div(c, b);
543         a.full = dfixed_div(a, b);
544         line_fill_time = dfixed_trunc(a);
545
546         if (line_fill_time < wm->active_time)
547                 return latency;
548         else
549                 return latency + (line_fill_time - wm->active_time);
550
551 }
552
553 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
554 {
555         if (evergreen_average_bandwidth(wm) <=
556             (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
557                 return true;
558         else
559                 return false;
560 };
561
562 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
563 {
564         if (evergreen_average_bandwidth(wm) <=
565             (evergreen_available_bandwidth(wm) / wm->num_heads))
566                 return true;
567         else
568                 return false;
569 };
570
571 static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
572 {
573         u32 lb_partitions = wm->lb_size / wm->src_width;
574         u32 line_time = wm->active_time + wm->blank_time;
575         u32 latency_tolerant_lines;
576         u32 latency_hiding;
577         fixed20_12 a;
578
579         a.full = dfixed_const(1);
580         if (wm->vsc.full > a.full)
581                 latency_tolerant_lines = 1;
582         else {
583                 if (lb_partitions <= (wm->vtaps + 1))
584                         latency_tolerant_lines = 1;
585                 else
586                         latency_tolerant_lines = 2;
587         }
588
589         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
590
591         if (evergreen_latency_watermark(wm) <= latency_hiding)
592                 return true;
593         else
594                 return false;
595 }
596
597 static void evergreen_program_watermarks(struct radeon_device *rdev,
598                                          struct radeon_crtc *radeon_crtc,
599                                          u32 lb_size, u32 num_heads)
600 {
601         struct drm_display_mode *mode = &radeon_crtc->base.mode;
602         struct evergreen_wm_params wm;
603         u32 pixel_period;
604         u32 line_time = 0;
605         u32 latency_watermark_a = 0, latency_watermark_b = 0;
606         u32 priority_a_mark = 0, priority_b_mark = 0;
607         u32 priority_a_cnt = PRIORITY_OFF;
608         u32 priority_b_cnt = PRIORITY_OFF;
609         u32 pipe_offset = radeon_crtc->crtc_id * 16;
610         u32 tmp, arb_control3;
611         fixed20_12 a, b, c;
612
613         if (radeon_crtc->base.enabled && num_heads && mode) {
614                 pixel_period = 1000000 / (u32)mode->clock;
615                 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
616                 priority_a_cnt = 0;
617                 priority_b_cnt = 0;
618
619                 wm.yclk = rdev->pm.current_mclk * 10;
620                 wm.sclk = rdev->pm.current_sclk * 10;
621                 wm.disp_clk = mode->clock;
622                 wm.src_width = mode->crtc_hdisplay;
623                 wm.active_time = mode->crtc_hdisplay * pixel_period;
624                 wm.blank_time = line_time - wm.active_time;
625                 wm.interlaced = false;
626                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
627                         wm.interlaced = true;
628                 wm.vsc = radeon_crtc->vsc;
629                 wm.vtaps = 1;
630                 if (radeon_crtc->rmx_type != RMX_OFF)
631                         wm.vtaps = 2;
632                 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
633                 wm.lb_size = lb_size;
634                 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
635                 wm.num_heads = num_heads;
636
637                 /* set for high clocks */
638                 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
639                 /* set for low clocks */
640                 /* wm.yclk = low clk; wm.sclk = low clk */
641                 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
642
643                 /* possibly force display priority to high */
644                 /* should really do this at mode validation time... */
645                 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
646                     !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
647                     !evergreen_check_latency_hiding(&wm) ||
648                     (rdev->disp_priority == 2)) {
649                         DRM_INFO("force priority to high\n");
650                         priority_a_cnt |= PRIORITY_ALWAYS_ON;
651                         priority_b_cnt |= PRIORITY_ALWAYS_ON;
652                 }
653
654                 a.full = dfixed_const(1000);
655                 b.full = dfixed_const(mode->clock);
656                 b.full = dfixed_div(b, a);
657                 c.full = dfixed_const(latency_watermark_a);
658                 c.full = dfixed_mul(c, b);
659                 c.full = dfixed_mul(c, radeon_crtc->hsc);
660                 c.full = dfixed_div(c, a);
661                 a.full = dfixed_const(16);
662                 c.full = dfixed_div(c, a);
663                 priority_a_mark = dfixed_trunc(c);
664                 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
665
666                 a.full = dfixed_const(1000);
667                 b.full = dfixed_const(mode->clock);
668                 b.full = dfixed_div(b, a);
669                 c.full = dfixed_const(latency_watermark_b);
670                 c.full = dfixed_mul(c, b);
671                 c.full = dfixed_mul(c, radeon_crtc->hsc);
672                 c.full = dfixed_div(c, a);
673                 a.full = dfixed_const(16);
674                 c.full = dfixed_div(c, a);
675                 priority_b_mark = dfixed_trunc(c);
676                 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
677         }
678
679         /* select wm A */
680         arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
681         tmp = arb_control3;
682         tmp &= ~LATENCY_WATERMARK_MASK(3);
683         tmp |= LATENCY_WATERMARK_MASK(1);
684         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
685         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
686                (LATENCY_LOW_WATERMARK(latency_watermark_a) |
687                 LATENCY_HIGH_WATERMARK(line_time)));
688         /* select wm B */
689         tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
690         tmp &= ~LATENCY_WATERMARK_MASK(3);
691         tmp |= LATENCY_WATERMARK_MASK(2);
692         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
693         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
694                (LATENCY_LOW_WATERMARK(latency_watermark_b) |
695                 LATENCY_HIGH_WATERMARK(line_time)));
696         /* restore original selection */
697         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
698
699         /* write the priority marks */
700         WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
701         WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
702
703 }
704
705 void evergreen_bandwidth_update(struct radeon_device *rdev)
706 {
707         struct drm_display_mode *mode0 = NULL;
708         struct drm_display_mode *mode1 = NULL;
709         u32 num_heads = 0, lb_size;
710         int i;
711
712         radeon_update_display_priority(rdev);
713
714         for (i = 0; i < rdev->num_crtc; i++) {
715                 if (rdev->mode_info.crtcs[i]->base.enabled)
716                         num_heads++;
717         }
718         for (i = 0; i < rdev->num_crtc; i += 2) {
719                 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
720                 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
721                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
722                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
723                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
724                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
725         }
726 }
727
728 static int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
729 {
730         unsigned i;
731         u32 tmp;
732
733         for (i = 0; i < rdev->usec_timeout; i++) {
734                 /* read MC_STATUS */
735                 tmp = RREG32(SRBM_STATUS) & 0x1F00;
736                 if (!tmp)
737                         return 0;
738                 udelay(1);
739         }
740         return -1;
741 }
742
743 /*
744  * GART
745  */
746 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
747 {
748         unsigned i;
749         u32 tmp;
750
751         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
752
753         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
754         for (i = 0; i < rdev->usec_timeout; i++) {
755                 /* read MC_STATUS */
756                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
757                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
758                 if (tmp == 2) {
759                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
760                         return;
761                 }
762                 if (tmp) {
763                         return;
764                 }
765                 udelay(1);
766         }
767 }
768
769 int evergreen_pcie_gart_enable(struct radeon_device *rdev)
770 {
771         u32 tmp;
772         int r;
773
774         if (rdev->gart.table.vram.robj == NULL) {
775                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
776                 return -EINVAL;
777         }
778         r = radeon_gart_table_vram_pin(rdev);
779         if (r)
780                 return r;
781         radeon_gart_restore(rdev);
782         /* Setup L2 cache */
783         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
784                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
785                                 EFFECTIVE_L2_QUEUE_SIZE(7));
786         WREG32(VM_L2_CNTL2, 0);
787         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
788         /* Setup TLB control */
789         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
790                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
791                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
792                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
793         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
794         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
795         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
796         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
797         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
798         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
799         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
800         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
801         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
802         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
803         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
804                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
805         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
806                         (u32)(rdev->dummy_page.addr >> 12));
807         WREG32(VM_CONTEXT1_CNTL, 0);
808
809         evergreen_pcie_gart_tlb_flush(rdev);
810         rdev->gart.ready = true;
811         return 0;
812 }
813
814 void evergreen_pcie_gart_disable(struct radeon_device *rdev)
815 {
816         u32 tmp;
817         int r;
818
819         /* Disable all tables */
820         WREG32(VM_CONTEXT0_CNTL, 0);
821         WREG32(VM_CONTEXT1_CNTL, 0);
822
823         /* Setup L2 cache */
824         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
825                                 EFFECTIVE_L2_QUEUE_SIZE(7));
826         WREG32(VM_L2_CNTL2, 0);
827         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
828         /* Setup TLB control */
829         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
830         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
831         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
832         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
833         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
834         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
835         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
836         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
837         if (rdev->gart.table.vram.robj) {
838                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
839                 if (likely(r == 0)) {
840                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
841                         radeon_bo_unpin(rdev->gart.table.vram.robj);
842                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
843                 }
844         }
845 }
846
847 void evergreen_pcie_gart_fini(struct radeon_device *rdev)
848 {
849         evergreen_pcie_gart_disable(rdev);
850         radeon_gart_table_vram_free(rdev);
851         radeon_gart_fini(rdev);
852 }
853
854
855 void evergreen_agp_enable(struct radeon_device *rdev)
856 {
857         u32 tmp;
858
859         /* Setup L2 cache */
860         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
861                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
862                                 EFFECTIVE_L2_QUEUE_SIZE(7));
863         WREG32(VM_L2_CNTL2, 0);
864         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
865         /* Setup TLB control */
866         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
867                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
868                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
869                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
870         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
871         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
872         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
873         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
874         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
875         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
876         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
877         WREG32(VM_CONTEXT0_CNTL, 0);
878         WREG32(VM_CONTEXT1_CNTL, 0);
879 }
880
881 static void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
882 {
883         save->vga_control[0] = RREG32(D1VGA_CONTROL);
884         save->vga_control[1] = RREG32(D2VGA_CONTROL);
885         save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
886         save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
887         save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
888         save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
889         save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
890         save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
891         save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
892         save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
893         save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
894         save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
895         save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
896         save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
897
898         /* Stop all video */
899         WREG32(VGA_RENDER_CONTROL, 0);
900         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
901         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
902         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
903         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
904         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
905         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
906         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
907         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
908         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
909         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
910         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
911         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
912         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
913         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
914         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
915         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
916         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
917         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
918
919         WREG32(D1VGA_CONTROL, 0);
920         WREG32(D2VGA_CONTROL, 0);
921         WREG32(EVERGREEN_D3VGA_CONTROL, 0);
922         WREG32(EVERGREEN_D4VGA_CONTROL, 0);
923         WREG32(EVERGREEN_D5VGA_CONTROL, 0);
924         WREG32(EVERGREEN_D6VGA_CONTROL, 0);
925 }
926
927 static void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
928 {
929         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
930                upper_32_bits(rdev->mc.vram_start));
931         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
932                upper_32_bits(rdev->mc.vram_start));
933         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
934                (u32)rdev->mc.vram_start);
935         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
936                (u32)rdev->mc.vram_start);
937
938         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
939                upper_32_bits(rdev->mc.vram_start));
940         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
941                upper_32_bits(rdev->mc.vram_start));
942         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
943                (u32)rdev->mc.vram_start);
944         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
945                (u32)rdev->mc.vram_start);
946
947         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
948                upper_32_bits(rdev->mc.vram_start));
949         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
950                upper_32_bits(rdev->mc.vram_start));
951         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
952                (u32)rdev->mc.vram_start);
953         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
954                (u32)rdev->mc.vram_start);
955
956         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
957                upper_32_bits(rdev->mc.vram_start));
958         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
959                upper_32_bits(rdev->mc.vram_start));
960         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
961                (u32)rdev->mc.vram_start);
962         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
963                (u32)rdev->mc.vram_start);
964
965         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
966                upper_32_bits(rdev->mc.vram_start));
967         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
968                upper_32_bits(rdev->mc.vram_start));
969         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
970                (u32)rdev->mc.vram_start);
971         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
972                (u32)rdev->mc.vram_start);
973
974         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
975                upper_32_bits(rdev->mc.vram_start));
976         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
977                upper_32_bits(rdev->mc.vram_start));
978         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
979                (u32)rdev->mc.vram_start);
980         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
981                (u32)rdev->mc.vram_start);
982
983         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
984         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
985         /* Unlock host access */
986         WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
987         mdelay(1);
988         /* Restore video state */
989         WREG32(D1VGA_CONTROL, save->vga_control[0]);
990         WREG32(D2VGA_CONTROL, save->vga_control[1]);
991         WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
992         WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
993         WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
994         WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
995         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
996         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
997         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
998         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
999         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1000         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1001         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1002         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
1003         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1004         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
1005         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1006         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1007         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1008         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1009         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1010         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1011         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1012         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1013         WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1014 }
1015
1016 static void evergreen_mc_program(struct radeon_device *rdev)
1017 {
1018         struct evergreen_mc_save save;
1019         u32 tmp;
1020         int i, j;
1021
1022         /* Initialize HDP */
1023         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1024                 WREG32((0x2c14 + j), 0x00000000);
1025                 WREG32((0x2c18 + j), 0x00000000);
1026                 WREG32((0x2c1c + j), 0x00000000);
1027                 WREG32((0x2c20 + j), 0x00000000);
1028                 WREG32((0x2c24 + j), 0x00000000);
1029         }
1030         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1031
1032         evergreen_mc_stop(rdev, &save);
1033         if (evergreen_mc_wait_for_idle(rdev)) {
1034                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1035         }
1036         /* Lockout access through VGA aperture*/
1037         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1038         /* Update configuration */
1039         if (rdev->flags & RADEON_IS_AGP) {
1040                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1041                         /* VRAM before AGP */
1042                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1043                                 rdev->mc.vram_start >> 12);
1044                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1045                                 rdev->mc.gtt_end >> 12);
1046                 } else {
1047                         /* VRAM after AGP */
1048                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1049                                 rdev->mc.gtt_start >> 12);
1050                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1051                                 rdev->mc.vram_end >> 12);
1052                 }
1053         } else {
1054                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1055                         rdev->mc.vram_start >> 12);
1056                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1057                         rdev->mc.vram_end >> 12);
1058         }
1059         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1060         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1061         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1062         WREG32(MC_VM_FB_LOCATION, tmp);
1063         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1064         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1065         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1066         if (rdev->flags & RADEON_IS_AGP) {
1067                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1068                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1069                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1070         } else {
1071                 WREG32(MC_VM_AGP_BASE, 0);
1072                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1073                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1074         }
1075         if (evergreen_mc_wait_for_idle(rdev)) {
1076                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1077         }
1078         evergreen_mc_resume(rdev, &save);
1079         /* we need to own VRAM, so turn off the VGA renderer here
1080          * to stop it overwriting our objects */
1081         rv515_vga_render_disable(rdev);
1082 }
1083
1084 /*
1085  * CP.
1086  */
1087
1088 static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1089 {
1090         const __be32 *fw_data;
1091         int i;
1092
1093         if (!rdev->me_fw || !rdev->pfp_fw)
1094                 return -EINVAL;
1095
1096         r700_cp_stop(rdev);
1097         WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
1098
1099         fw_data = (const __be32 *)rdev->pfp_fw->data;
1100         WREG32(CP_PFP_UCODE_ADDR, 0);
1101         for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1102                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1103         WREG32(CP_PFP_UCODE_ADDR, 0);
1104
1105         fw_data = (const __be32 *)rdev->me_fw->data;
1106         WREG32(CP_ME_RAM_WADDR, 0);
1107         for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1108                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1109
1110         WREG32(CP_PFP_UCODE_ADDR, 0);
1111         WREG32(CP_ME_RAM_WADDR, 0);
1112         WREG32(CP_ME_RAM_RADDR, 0);
1113         return 0;
1114 }
1115
1116 static int evergreen_cp_start(struct radeon_device *rdev)
1117 {
1118         int r, i;
1119         uint32_t cp_me;
1120
1121         r = radeon_ring_lock(rdev, 7);
1122         if (r) {
1123                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1124                 return r;
1125         }
1126         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1127         radeon_ring_write(rdev, 0x1);
1128         radeon_ring_write(rdev, 0x0);
1129         radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
1130         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1131         radeon_ring_write(rdev, 0);
1132         radeon_ring_write(rdev, 0);
1133         radeon_ring_unlock_commit(rdev);
1134
1135         cp_me = 0xff;
1136         WREG32(CP_ME_CNTL, cp_me);
1137
1138         r = radeon_ring_lock(rdev, evergreen_default_size + 15);
1139         if (r) {
1140                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1141                 return r;
1142         }
1143
1144         /* setup clear context state */
1145         radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1146         radeon_ring_write(rdev, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1147
1148         for (i = 0; i < evergreen_default_size; i++)
1149                 radeon_ring_write(rdev, evergreen_default_state[i]);
1150
1151         radeon_ring_write(rdev, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1152         radeon_ring_write(rdev, PACKET3_PREAMBLE_END_CLEAR_STATE);
1153
1154         /* set clear context state */
1155         radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0));
1156         radeon_ring_write(rdev, 0);
1157
1158         /* SQ_VTX_BASE_VTX_LOC */
1159         radeon_ring_write(rdev, 0xc0026f00);
1160         radeon_ring_write(rdev, 0x00000000);
1161         radeon_ring_write(rdev, 0x00000000);
1162         radeon_ring_write(rdev, 0x00000000);
1163
1164         /* Clear consts */
1165         radeon_ring_write(rdev, 0xc0036f00);
1166         radeon_ring_write(rdev, 0x00000bc4);
1167         radeon_ring_write(rdev, 0xffffffff);
1168         radeon_ring_write(rdev, 0xffffffff);
1169         radeon_ring_write(rdev, 0xffffffff);
1170
1171         radeon_ring_unlock_commit(rdev);
1172
1173         return 0;
1174 }
1175
1176 int evergreen_cp_resume(struct radeon_device *rdev)
1177 {
1178         u32 tmp;
1179         u32 rb_bufsz;
1180         int r;
1181
1182         /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1183         WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1184                                  SOFT_RESET_PA |
1185                                  SOFT_RESET_SH |
1186                                  SOFT_RESET_VGT |
1187                                  SOFT_RESET_SX));
1188         RREG32(GRBM_SOFT_RESET);
1189         mdelay(15);
1190         WREG32(GRBM_SOFT_RESET, 0);
1191         RREG32(GRBM_SOFT_RESET);
1192
1193         /* Set ring buffer size */
1194         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1195         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1196 #ifdef __BIG_ENDIAN
1197         tmp |= BUF_SWAP_32BIT;
1198 #endif
1199         WREG32(CP_RB_CNTL, tmp);
1200         WREG32(CP_SEM_WAIT_TIMER, 0x4);
1201
1202         /* Set the write pointer delay */
1203         WREG32(CP_RB_WPTR_DELAY, 0);
1204
1205         /* Initialize the ring buffer's read and write pointers */
1206         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1207         WREG32(CP_RB_RPTR_WR, 0);
1208         WREG32(CP_RB_WPTR, 0);
1209
1210         /* set the wb address wether it's enabled or not */
1211         WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
1212         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1213         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1214
1215         if (rdev->wb.enabled)
1216                 WREG32(SCRATCH_UMSK, 0xff);
1217         else {
1218                 tmp |= RB_NO_UPDATE;
1219                 WREG32(SCRATCH_UMSK, 0);
1220         }
1221
1222         mdelay(1);
1223         WREG32(CP_RB_CNTL, tmp);
1224
1225         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1226         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1227
1228         rdev->cp.rptr = RREG32(CP_RB_RPTR);
1229         rdev->cp.wptr = RREG32(CP_RB_WPTR);
1230
1231         evergreen_cp_start(rdev);
1232         rdev->cp.ready = true;
1233         r = radeon_ring_test(rdev);
1234         if (r) {
1235                 rdev->cp.ready = false;
1236                 return r;
1237         }
1238         return 0;
1239 }
1240
1241 /*
1242  * Core functions
1243  */
1244 static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1245                                                   u32 num_tile_pipes,
1246                                                   u32 num_backends,
1247                                                   u32 backend_disable_mask)
1248 {
1249         u32 backend_map = 0;
1250         u32 enabled_backends_mask = 0;
1251         u32 enabled_backends_count = 0;
1252         u32 cur_pipe;
1253         u32 swizzle_pipe[EVERGREEN_MAX_PIPES];
1254         u32 cur_backend = 0;
1255         u32 i;
1256         bool force_no_swizzle;
1257
1258         if (num_tile_pipes > EVERGREEN_MAX_PIPES)
1259                 num_tile_pipes = EVERGREEN_MAX_PIPES;
1260         if (num_tile_pipes < 1)
1261                 num_tile_pipes = 1;
1262         if (num_backends > EVERGREEN_MAX_BACKENDS)
1263                 num_backends = EVERGREEN_MAX_BACKENDS;
1264         if (num_backends < 1)
1265                 num_backends = 1;
1266
1267         for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1268                 if (((backend_disable_mask >> i) & 1) == 0) {
1269                         enabled_backends_mask |= (1 << i);
1270                         ++enabled_backends_count;
1271                 }
1272                 if (enabled_backends_count == num_backends)
1273                         break;
1274         }
1275
1276         if (enabled_backends_count == 0) {
1277                 enabled_backends_mask = 1;
1278                 enabled_backends_count = 1;
1279         }
1280
1281         if (enabled_backends_count != num_backends)
1282                 num_backends = enabled_backends_count;
1283
1284         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES);
1285         switch (rdev->family) {
1286         case CHIP_CEDAR:
1287         case CHIP_REDWOOD:
1288                 force_no_swizzle = false;
1289                 break;
1290         case CHIP_CYPRESS:
1291         case CHIP_HEMLOCK:
1292         case CHIP_JUNIPER:
1293         default:
1294                 force_no_swizzle = true;
1295                 break;
1296         }
1297         if (force_no_swizzle) {
1298                 bool last_backend_enabled = false;
1299
1300                 force_no_swizzle = false;
1301                 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1302                         if (((enabled_backends_mask >> i) & 1) == 1) {
1303                                 if (last_backend_enabled)
1304                                         force_no_swizzle = true;
1305                                 last_backend_enabled = true;
1306                         } else
1307                                 last_backend_enabled = false;
1308                 }
1309         }
1310
1311         switch (num_tile_pipes) {
1312         case 1:
1313         case 3:
1314         case 5:
1315         case 7:
1316                 DRM_ERROR("odd number of pipes!\n");
1317                 break;
1318         case 2:
1319                 swizzle_pipe[0] = 0;
1320                 swizzle_pipe[1] = 1;
1321                 break;
1322         case 4:
1323                 if (force_no_swizzle) {
1324                         swizzle_pipe[0] = 0;
1325                         swizzle_pipe[1] = 1;
1326                         swizzle_pipe[2] = 2;
1327                         swizzle_pipe[3] = 3;
1328                 } else {
1329                         swizzle_pipe[0] = 0;
1330                         swizzle_pipe[1] = 2;
1331                         swizzle_pipe[2] = 1;
1332                         swizzle_pipe[3] = 3;
1333                 }
1334                 break;
1335         case 6:
1336                 if (force_no_swizzle) {
1337                         swizzle_pipe[0] = 0;
1338                         swizzle_pipe[1] = 1;
1339                         swizzle_pipe[2] = 2;
1340                         swizzle_pipe[3] = 3;
1341                         swizzle_pipe[4] = 4;
1342                         swizzle_pipe[5] = 5;
1343                 } else {
1344                         swizzle_pipe[0] = 0;
1345                         swizzle_pipe[1] = 2;
1346                         swizzle_pipe[2] = 4;
1347                         swizzle_pipe[3] = 1;
1348                         swizzle_pipe[4] = 3;
1349                         swizzle_pipe[5] = 5;
1350                 }
1351                 break;
1352         case 8:
1353                 if (force_no_swizzle) {
1354                         swizzle_pipe[0] = 0;
1355                         swizzle_pipe[1] = 1;
1356                         swizzle_pipe[2] = 2;
1357                         swizzle_pipe[3] = 3;
1358                         swizzle_pipe[4] = 4;
1359                         swizzle_pipe[5] = 5;
1360                         swizzle_pipe[6] = 6;
1361                         swizzle_pipe[7] = 7;
1362                 } else {
1363                         swizzle_pipe[0] = 0;
1364                         swizzle_pipe[1] = 2;
1365                         swizzle_pipe[2] = 4;
1366                         swizzle_pipe[3] = 6;
1367                         swizzle_pipe[4] = 1;
1368                         swizzle_pipe[5] = 3;
1369                         swizzle_pipe[6] = 5;
1370                         swizzle_pipe[7] = 7;
1371                 }
1372                 break;
1373         }
1374
1375         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1376                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1377                         cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1378
1379                 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
1380
1381                 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1382         }
1383
1384         return backend_map;
1385 }
1386
1387 static void evergreen_gpu_init(struct radeon_device *rdev)
1388 {
1389         u32 cc_rb_backend_disable = 0;
1390         u32 cc_gc_shader_pipe_config;
1391         u32 gb_addr_config = 0;
1392         u32 mc_shared_chmap, mc_arb_ramcfg;
1393         u32 gb_backend_map;
1394         u32 grbm_gfx_index;
1395         u32 sx_debug_1;
1396         u32 smx_dc_ctl0;
1397         u32 sq_config;
1398         u32 sq_lds_resource_mgmt;
1399         u32 sq_gpr_resource_mgmt_1;
1400         u32 sq_gpr_resource_mgmt_2;
1401         u32 sq_gpr_resource_mgmt_3;
1402         u32 sq_thread_resource_mgmt;
1403         u32 sq_thread_resource_mgmt_2;
1404         u32 sq_stack_resource_mgmt_1;
1405         u32 sq_stack_resource_mgmt_2;
1406         u32 sq_stack_resource_mgmt_3;
1407         u32 vgt_cache_invalidation;
1408         u32 hdp_host_path_cntl;
1409         int i, j, num_shader_engines, ps_thread_count;
1410
1411         switch (rdev->family) {
1412         case CHIP_CYPRESS:
1413         case CHIP_HEMLOCK:
1414                 rdev->config.evergreen.num_ses = 2;
1415                 rdev->config.evergreen.max_pipes = 4;
1416                 rdev->config.evergreen.max_tile_pipes = 8;
1417                 rdev->config.evergreen.max_simds = 10;
1418                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1419                 rdev->config.evergreen.max_gprs = 256;
1420                 rdev->config.evergreen.max_threads = 248;
1421                 rdev->config.evergreen.max_gs_threads = 32;
1422                 rdev->config.evergreen.max_stack_entries = 512;
1423                 rdev->config.evergreen.sx_num_of_sets = 4;
1424                 rdev->config.evergreen.sx_max_export_size = 256;
1425                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1426                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1427                 rdev->config.evergreen.max_hw_contexts = 8;
1428                 rdev->config.evergreen.sq_num_cf_insts = 2;
1429
1430                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1431                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1432                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1433                 break;
1434         case CHIP_JUNIPER:
1435                 rdev->config.evergreen.num_ses = 1;
1436                 rdev->config.evergreen.max_pipes = 4;
1437                 rdev->config.evergreen.max_tile_pipes = 4;
1438                 rdev->config.evergreen.max_simds = 10;
1439                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1440                 rdev->config.evergreen.max_gprs = 256;
1441                 rdev->config.evergreen.max_threads = 248;
1442                 rdev->config.evergreen.max_gs_threads = 32;
1443                 rdev->config.evergreen.max_stack_entries = 512;
1444                 rdev->config.evergreen.sx_num_of_sets = 4;
1445                 rdev->config.evergreen.sx_max_export_size = 256;
1446                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1447                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1448                 rdev->config.evergreen.max_hw_contexts = 8;
1449                 rdev->config.evergreen.sq_num_cf_insts = 2;
1450
1451                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1452                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1453                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1454                 break;
1455         case CHIP_REDWOOD:
1456                 rdev->config.evergreen.num_ses = 1;
1457                 rdev->config.evergreen.max_pipes = 4;
1458                 rdev->config.evergreen.max_tile_pipes = 4;
1459                 rdev->config.evergreen.max_simds = 5;
1460                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1461                 rdev->config.evergreen.max_gprs = 256;
1462                 rdev->config.evergreen.max_threads = 248;
1463                 rdev->config.evergreen.max_gs_threads = 32;
1464                 rdev->config.evergreen.max_stack_entries = 256;
1465                 rdev->config.evergreen.sx_num_of_sets = 4;
1466                 rdev->config.evergreen.sx_max_export_size = 256;
1467                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1468                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1469                 rdev->config.evergreen.max_hw_contexts = 8;
1470                 rdev->config.evergreen.sq_num_cf_insts = 2;
1471
1472                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1473                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1474                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1475                 break;
1476         case CHIP_CEDAR:
1477         default:
1478                 rdev->config.evergreen.num_ses = 1;
1479                 rdev->config.evergreen.max_pipes = 2;
1480                 rdev->config.evergreen.max_tile_pipes = 2;
1481                 rdev->config.evergreen.max_simds = 2;
1482                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1483                 rdev->config.evergreen.max_gprs = 256;
1484                 rdev->config.evergreen.max_threads = 192;
1485                 rdev->config.evergreen.max_gs_threads = 16;
1486                 rdev->config.evergreen.max_stack_entries = 256;
1487                 rdev->config.evergreen.sx_num_of_sets = 4;
1488                 rdev->config.evergreen.sx_max_export_size = 128;
1489                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1490                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1491                 rdev->config.evergreen.max_hw_contexts = 4;
1492                 rdev->config.evergreen.sq_num_cf_insts = 1;
1493
1494                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1495                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1496                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1497                 break;
1498         }
1499
1500         /* Initialize HDP */
1501         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1502                 WREG32((0x2c14 + j), 0x00000000);
1503                 WREG32((0x2c18 + j), 0x00000000);
1504                 WREG32((0x2c1c + j), 0x00000000);
1505                 WREG32((0x2c20 + j), 0x00000000);
1506                 WREG32((0x2c24 + j), 0x00000000);
1507         }
1508
1509         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1510
1511         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
1512
1513         cc_gc_shader_pipe_config |=
1514                 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
1515                                   & EVERGREEN_MAX_PIPES_MASK);
1516         cc_gc_shader_pipe_config |=
1517                 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
1518                                & EVERGREEN_MAX_SIMDS_MASK);
1519
1520         cc_rb_backend_disable =
1521                 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
1522                                 & EVERGREEN_MAX_BACKENDS_MASK);
1523
1524
1525         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1526         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1527
1528         switch (rdev->config.evergreen.max_tile_pipes) {
1529         case 1:
1530         default:
1531                 gb_addr_config |= NUM_PIPES(0);
1532                 break;
1533         case 2:
1534                 gb_addr_config |= NUM_PIPES(1);
1535                 break;
1536         case 4:
1537                 gb_addr_config |= NUM_PIPES(2);
1538                 break;
1539         case 8:
1540                 gb_addr_config |= NUM_PIPES(3);
1541                 break;
1542         }
1543
1544         gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1545         gb_addr_config |= BANK_INTERLEAVE_SIZE(0);
1546         gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1);
1547         gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1);
1548         gb_addr_config |= NUM_GPUS(0); /* Hemlock? */
1549         gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
1550
1551         if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2)
1552                 gb_addr_config |= ROW_SIZE(2);
1553         else
1554                 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
1555
1556         if (rdev->ddev->pdev->device == 0x689e) {
1557                 u32 efuse_straps_4;
1558                 u32 efuse_straps_3;
1559                 u8 efuse_box_bit_131_124;
1560
1561                 WREG32(RCU_IND_INDEX, 0x204);
1562                 efuse_straps_4 = RREG32(RCU_IND_DATA);
1563                 WREG32(RCU_IND_INDEX, 0x203);
1564                 efuse_straps_3 = RREG32(RCU_IND_DATA);
1565                 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
1566
1567                 switch(efuse_box_bit_131_124) {
1568                 case 0x00:
1569                         gb_backend_map = 0x76543210;
1570                         break;
1571                 case 0x55:
1572                         gb_backend_map = 0x77553311;
1573                         break;
1574                 case 0x56:
1575                         gb_backend_map = 0x77553300;
1576                         break;
1577                 case 0x59:
1578                         gb_backend_map = 0x77552211;
1579                         break;
1580                 case 0x66:
1581                         gb_backend_map = 0x77443300;
1582                         break;
1583                 case 0x99:
1584                         gb_backend_map = 0x66552211;
1585                         break;
1586                 case 0x5a:
1587                         gb_backend_map = 0x77552200;
1588                         break;
1589                 case 0xaa:
1590                         gb_backend_map = 0x66442200;
1591                         break;
1592                 case 0x95:
1593                         gb_backend_map = 0x66553311;
1594                         break;
1595                 default:
1596                         DRM_ERROR("bad backend map, using default\n");
1597                         gb_backend_map =
1598                                 evergreen_get_tile_pipe_to_backend_map(rdev,
1599                                                                        rdev->config.evergreen.max_tile_pipes,
1600                                                                        rdev->config.evergreen.max_backends,
1601                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
1602                                                                    rdev->config.evergreen.max_backends) &
1603                                                                         EVERGREEN_MAX_BACKENDS_MASK));
1604                         break;
1605                 }
1606         } else if (rdev->ddev->pdev->device == 0x68b9) {
1607                 u32 efuse_straps_3;
1608                 u8 efuse_box_bit_127_124;
1609
1610                 WREG32(RCU_IND_INDEX, 0x203);
1611                 efuse_straps_3 = RREG32(RCU_IND_DATA);
1612                 efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28);
1613
1614                 switch(efuse_box_bit_127_124) {
1615                 case 0x0:
1616                         gb_backend_map = 0x00003210;
1617                         break;
1618                 case 0x5:
1619                 case 0x6:
1620                 case 0x9:
1621                 case 0xa:
1622                         gb_backend_map = 0x00003311;
1623                         break;
1624                 default:
1625                         DRM_ERROR("bad backend map, using default\n");
1626                         gb_backend_map =
1627                                 evergreen_get_tile_pipe_to_backend_map(rdev,
1628                                                                        rdev->config.evergreen.max_tile_pipes,
1629                                                                        rdev->config.evergreen.max_backends,
1630                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
1631                                                                    rdev->config.evergreen.max_backends) &
1632                                                                         EVERGREEN_MAX_BACKENDS_MASK));
1633                         break;
1634                 }
1635         } else {
1636                 switch (rdev->family) {
1637                 case CHIP_CYPRESS:
1638                 case CHIP_HEMLOCK:
1639                         gb_backend_map = 0x66442200;
1640                         break;
1641                 case CHIP_JUNIPER:
1642                         gb_backend_map = 0x00006420;
1643                         break;
1644                 default:
1645                         gb_backend_map =
1646                                 evergreen_get_tile_pipe_to_backend_map(rdev,
1647                                                                        rdev->config.evergreen.max_tile_pipes,
1648                                                                        rdev->config.evergreen.max_backends,
1649                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
1650                                                                          rdev->config.evergreen.max_backends) &
1651                                                                         EVERGREEN_MAX_BACKENDS_MASK));
1652                 }
1653         }
1654
1655         /* setup tiling info dword.  gb_addr_config is not adequate since it does
1656          * not have bank info, so create a custom tiling dword.
1657          * bits 3:0   num_pipes
1658          * bits 7:4   num_banks
1659          * bits 11:8  group_size
1660          * bits 15:12 row_size
1661          */
1662         rdev->config.evergreen.tile_config = 0;
1663         switch (rdev->config.evergreen.max_tile_pipes) {
1664         case 1:
1665         default:
1666                 rdev->config.evergreen.tile_config |= (0 << 0);
1667                 break;
1668         case 2:
1669                 rdev->config.evergreen.tile_config |= (1 << 0);
1670                 break;
1671         case 4:
1672                 rdev->config.evergreen.tile_config |= (2 << 0);
1673                 break;
1674         case 8:
1675                 rdev->config.evergreen.tile_config |= (3 << 0);
1676                 break;
1677         }
1678         rdev->config.evergreen.tile_config |=
1679                 ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
1680         rdev->config.evergreen.tile_config |=
1681                 ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
1682         rdev->config.evergreen.tile_config |=
1683                 ((gb_addr_config & 0x30000000) >> 28) << 12;
1684
1685         WREG32(GB_BACKEND_MAP, gb_backend_map);
1686         WREG32(GB_ADDR_CONFIG, gb_addr_config);
1687         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1688         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1689
1690         num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
1691         grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
1692
1693         for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
1694                 u32 rb = cc_rb_backend_disable | (0xf0 << 16);
1695                 u32 sp = cc_gc_shader_pipe_config;
1696                 u32 gfx = grbm_gfx_index | SE_INDEX(i);
1697
1698                 if (i == num_shader_engines) {
1699                         rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
1700                         sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
1701                 }
1702
1703                 WREG32(GRBM_GFX_INDEX, gfx);
1704                 WREG32(RLC_GFX_INDEX, gfx);
1705
1706                 WREG32(CC_RB_BACKEND_DISABLE, rb);
1707                 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
1708                 WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
1709                 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
1710         }
1711
1712         grbm_gfx_index |= SE_BROADCAST_WRITES;
1713         WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
1714         WREG32(RLC_GFX_INDEX, grbm_gfx_index);
1715
1716         WREG32(CGTS_SYS_TCC_DISABLE, 0);
1717         WREG32(CGTS_TCC_DISABLE, 0);
1718         WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
1719         WREG32(CGTS_USER_TCC_DISABLE, 0);
1720
1721         /* set HW defaults for 3D engine */
1722         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1723                                      ROQ_IB2_START(0x2b)));
1724
1725         WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
1726
1727         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
1728                              SYNC_GRADIENT |
1729                              SYNC_WALKER |
1730                              SYNC_ALIGNER));
1731
1732         sx_debug_1 = RREG32(SX_DEBUG_1);
1733         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
1734         WREG32(SX_DEBUG_1, sx_debug_1);
1735
1736
1737         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
1738         smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
1739         smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
1740         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1741
1742         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
1743                                         POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
1744                                         SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
1745
1746         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
1747                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
1748                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
1749
1750         WREG32(VGT_NUM_INSTANCES, 1);
1751         WREG32(SPI_CONFIG_CNTL, 0);
1752         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1753         WREG32(CP_PERFMON_CNTL, 0);
1754
1755         WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
1756                                   FETCH_FIFO_HIWATER(0x4) |
1757                                   DONE_FIFO_HIWATER(0xe0) |
1758                                   ALU_UPDATE_FIFO_HIWATER(0x8)));
1759
1760         sq_config = RREG32(SQ_CONFIG);
1761         sq_config &= ~(PS_PRIO(3) |
1762                        VS_PRIO(3) |
1763                        GS_PRIO(3) |
1764                        ES_PRIO(3));
1765         sq_config |= (VC_ENABLE |
1766                       EXPORT_SRC_C |
1767                       PS_PRIO(0) |
1768                       VS_PRIO(1) |
1769                       GS_PRIO(2) |
1770                       ES_PRIO(3));
1771
1772         if (rdev->family == CHIP_CEDAR)
1773                 /* no vertex cache */
1774                 sq_config &= ~VC_ENABLE;
1775
1776         sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
1777
1778         sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
1779         sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
1780         sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
1781         sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
1782         sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
1783         sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
1784         sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
1785
1786         if (rdev->family == CHIP_CEDAR)
1787                 ps_thread_count = 96;
1788         else
1789                 ps_thread_count = 128;
1790
1791         sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
1792         sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1793         sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1794         sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1795         sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1796         sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1797
1798         sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1799         sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1800         sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1801         sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1802         sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1803         sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1804
1805         WREG32(SQ_CONFIG, sq_config);
1806         WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1807         WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1808         WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
1809         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1810         WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
1811         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1812         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1813         WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
1814         WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
1815         WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
1816
1817         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1818                                           FORCE_EOV_MAX_REZ_CNT(255)));
1819
1820         if (rdev->family == CHIP_CEDAR)
1821                 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
1822         else
1823                 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
1824         vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
1825         WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
1826
1827         WREG32(VGT_GS_VERTEX_REUSE, 16);
1828         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1829
1830         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
1831         WREG32(VGT_OUT_DEALLOC_CNTL, 16);
1832
1833         WREG32(CB_PERF_CTR0_SEL_0, 0);
1834         WREG32(CB_PERF_CTR0_SEL_1, 0);
1835         WREG32(CB_PERF_CTR1_SEL_0, 0);
1836         WREG32(CB_PERF_CTR1_SEL_1, 0);
1837         WREG32(CB_PERF_CTR2_SEL_0, 0);
1838         WREG32(CB_PERF_CTR2_SEL_1, 0);
1839         WREG32(CB_PERF_CTR3_SEL_0, 0);
1840         WREG32(CB_PERF_CTR3_SEL_1, 0);
1841
1842         /* clear render buffer base addresses */
1843         WREG32(CB_COLOR0_BASE, 0);
1844         WREG32(CB_COLOR1_BASE, 0);
1845         WREG32(CB_COLOR2_BASE, 0);
1846         WREG32(CB_COLOR3_BASE, 0);
1847         WREG32(CB_COLOR4_BASE, 0);
1848         WREG32(CB_COLOR5_BASE, 0);
1849         WREG32(CB_COLOR6_BASE, 0);
1850         WREG32(CB_COLOR7_BASE, 0);
1851         WREG32(CB_COLOR8_BASE, 0);
1852         WREG32(CB_COLOR9_BASE, 0);
1853         WREG32(CB_COLOR10_BASE, 0);
1854         WREG32(CB_COLOR11_BASE, 0);
1855
1856         /* set the shader const cache sizes to 0 */
1857         for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
1858                 WREG32(i, 0);
1859         for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
1860                 WREG32(i, 0);
1861
1862         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1863         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1864
1865         WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1866
1867         udelay(50);
1868
1869 }
1870
1871 int evergreen_mc_init(struct radeon_device *rdev)
1872 {
1873         u32 tmp;
1874         int chansize, numchan;
1875
1876         /* Get VRAM informations */
1877         rdev->mc.vram_is_ddr = true;
1878         tmp = RREG32(MC_ARB_RAMCFG);
1879         if (tmp & CHANSIZE_OVERRIDE) {
1880                 chansize = 16;
1881         } else if (tmp & CHANSIZE_MASK) {
1882                 chansize = 64;
1883         } else {
1884                 chansize = 32;
1885         }
1886         tmp = RREG32(MC_SHARED_CHMAP);
1887         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1888         case 0:
1889         default:
1890                 numchan = 1;
1891                 break;
1892         case 1:
1893                 numchan = 2;
1894                 break;
1895         case 2:
1896                 numchan = 4;
1897                 break;
1898         case 3:
1899                 numchan = 8;
1900                 break;
1901         }
1902         rdev->mc.vram_width = numchan * chansize;
1903         /* Could aper size report 0 ? */
1904         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1905         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1906         /* Setup GPU memory space */
1907         /* size in MB on evergreen */
1908         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
1909         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
1910         rdev->mc.visible_vram_size = rdev->mc.aper_size;
1911         rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
1912         r600_vram_gtt_location(rdev, &rdev->mc);
1913         radeon_update_bandwidth_info(rdev);
1914
1915         return 0;
1916 }
1917
1918 bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
1919 {
1920         /* FIXME: implement for evergreen */
1921         return false;
1922 }
1923
1924 static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
1925 {
1926         struct evergreen_mc_save save;
1927         u32 grbm_reset = 0;
1928
1929         dev_info(rdev->dev, "GPU softreset \n");
1930         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
1931                 RREG32(GRBM_STATUS));
1932         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
1933                 RREG32(GRBM_STATUS_SE0));
1934         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
1935                 RREG32(GRBM_STATUS_SE1));
1936         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
1937                 RREG32(SRBM_STATUS));
1938         evergreen_mc_stop(rdev, &save);
1939         if (evergreen_mc_wait_for_idle(rdev)) {
1940                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1941         }
1942         /* Disable CP parsing/prefetching */
1943         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1944
1945         /* reset all the gfx blocks */
1946         grbm_reset = (SOFT_RESET_CP |
1947                       SOFT_RESET_CB |
1948                       SOFT_RESET_DB |
1949                       SOFT_RESET_PA |
1950                       SOFT_RESET_SC |
1951                       SOFT_RESET_SPI |
1952                       SOFT_RESET_SH |
1953                       SOFT_RESET_SX |
1954                       SOFT_RESET_TC |
1955                       SOFT_RESET_TA |
1956                       SOFT_RESET_VC |
1957                       SOFT_RESET_VGT);
1958
1959         dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
1960         WREG32(GRBM_SOFT_RESET, grbm_reset);
1961         (void)RREG32(GRBM_SOFT_RESET);
1962         udelay(50);
1963         WREG32(GRBM_SOFT_RESET, 0);
1964         (void)RREG32(GRBM_SOFT_RESET);
1965         /* Wait a little for things to settle down */
1966         udelay(50);
1967         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
1968                 RREG32(GRBM_STATUS));
1969         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
1970                 RREG32(GRBM_STATUS_SE0));
1971         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
1972                 RREG32(GRBM_STATUS_SE1));
1973         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
1974                 RREG32(SRBM_STATUS));
1975         evergreen_mc_resume(rdev, &save);
1976         return 0;
1977 }
1978
1979 int evergreen_asic_reset(struct radeon_device *rdev)
1980 {
1981         return evergreen_gpu_soft_reset(rdev);
1982 }
1983
1984 /* Interrupts */
1985
1986 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
1987 {
1988         switch (crtc) {
1989         case 0:
1990                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
1991         case 1:
1992                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
1993         case 2:
1994                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
1995         case 3:
1996                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
1997         case 4:
1998                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
1999         case 5:
2000                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
2001         default:
2002                 return 0;
2003         }
2004 }
2005
2006 void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2007 {
2008         u32 tmp;
2009
2010         WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2011         WREG32(GRBM_INT_CNTL, 0);
2012         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2013         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2014         WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2015         WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2016         WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2017         WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2018
2019         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2020         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2021         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2022         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2023         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2024         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2025
2026         WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2027         WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2028
2029         tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2030         WREG32(DC_HPD1_INT_CONTROL, tmp);
2031         tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2032         WREG32(DC_HPD2_INT_CONTROL, tmp);
2033         tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2034         WREG32(DC_HPD3_INT_CONTROL, tmp);
2035         tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2036         WREG32(DC_HPD4_INT_CONTROL, tmp);
2037         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2038         WREG32(DC_HPD5_INT_CONTROL, tmp);
2039         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2040         WREG32(DC_HPD6_INT_CONTROL, tmp);
2041
2042 }
2043
2044 int evergreen_irq_set(struct radeon_device *rdev)
2045 {
2046         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2047         u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2048         u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2049         u32 grbm_int_cntl = 0;
2050
2051         if (!rdev->irq.installed) {
2052                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
2053                 return -EINVAL;
2054         }
2055         /* don't enable anything if the ih is disabled */
2056         if (!rdev->ih.enabled) {
2057                 r600_disable_interrupts(rdev);
2058                 /* force the active interrupt state to all disabled */
2059                 evergreen_disable_interrupt_state(rdev);
2060                 return 0;
2061         }
2062
2063         hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2064         hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2065         hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2066         hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2067         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2068         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2069
2070         if (rdev->irq.sw_int) {
2071                 DRM_DEBUG("evergreen_irq_set: sw int\n");
2072                 cp_int_cntl |= RB_INT_ENABLE;
2073                 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2074         }
2075         if (rdev->irq.crtc_vblank_int[0]) {
2076                 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2077                 crtc1 |= VBLANK_INT_MASK;
2078         }
2079         if (rdev->irq.crtc_vblank_int[1]) {
2080                 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2081                 crtc2 |= VBLANK_INT_MASK;
2082         }
2083         if (rdev->irq.crtc_vblank_int[2]) {
2084                 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2085                 crtc3 |= VBLANK_INT_MASK;
2086         }
2087         if (rdev->irq.crtc_vblank_int[3]) {
2088                 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2089                 crtc4 |= VBLANK_INT_MASK;
2090         }
2091         if (rdev->irq.crtc_vblank_int[4]) {
2092                 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2093                 crtc5 |= VBLANK_INT_MASK;
2094         }
2095         if (rdev->irq.crtc_vblank_int[5]) {
2096                 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2097                 crtc6 |= VBLANK_INT_MASK;
2098         }
2099         if (rdev->irq.hpd[0]) {
2100                 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2101                 hpd1 |= DC_HPDx_INT_EN;
2102         }
2103         if (rdev->irq.hpd[1]) {
2104                 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2105                 hpd2 |= DC_HPDx_INT_EN;
2106         }
2107         if (rdev->irq.hpd[2]) {
2108                 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2109                 hpd3 |= DC_HPDx_INT_EN;
2110         }
2111         if (rdev->irq.hpd[3]) {
2112                 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2113                 hpd4 |= DC_HPDx_INT_EN;
2114         }
2115         if (rdev->irq.hpd[4]) {
2116                 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2117                 hpd5 |= DC_HPDx_INT_EN;
2118         }
2119         if (rdev->irq.hpd[5]) {
2120                 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2121                 hpd6 |= DC_HPDx_INT_EN;
2122         }
2123         if (rdev->irq.gui_idle) {
2124                 DRM_DEBUG("gui idle\n");
2125                 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2126         }
2127
2128         WREG32(CP_INT_CNTL, cp_int_cntl);
2129         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
2130
2131         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2132         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2133         WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2134         WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2135         WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2136         WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2137
2138         WREG32(DC_HPD1_INT_CONTROL, hpd1);
2139         WREG32(DC_HPD2_INT_CONTROL, hpd2);
2140         WREG32(DC_HPD3_INT_CONTROL, hpd3);
2141         WREG32(DC_HPD4_INT_CONTROL, hpd4);
2142         WREG32(DC_HPD5_INT_CONTROL, hpd5);
2143         WREG32(DC_HPD6_INT_CONTROL, hpd6);
2144
2145         return 0;
2146 }
2147
2148 static inline void evergreen_irq_ack(struct radeon_device *rdev,
2149                                      u32 *disp_int,
2150                                      u32 *disp_int_cont,
2151                                      u32 *disp_int_cont2,
2152                                      u32 *disp_int_cont3,
2153                                      u32 *disp_int_cont4,
2154                                      u32 *disp_int_cont5)
2155 {
2156         u32 tmp;
2157
2158         *disp_int = RREG32(DISP_INTERRUPT_STATUS);
2159         *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2160         *disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2161         *disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2162         *disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2163         *disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2164
2165         if (*disp_int & LB_D1_VBLANK_INTERRUPT)
2166                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
2167         if (*disp_int & LB_D1_VLINE_INTERRUPT)
2168                 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2169
2170         if (*disp_int_cont & LB_D2_VBLANK_INTERRUPT)
2171                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
2172         if (*disp_int_cont & LB_D2_VLINE_INTERRUPT)
2173                 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2174
2175         if (*disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2176                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2177         if (*disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2178                 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2179
2180         if (*disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2181                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2182         if (*disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2183                 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2184
2185         if (*disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2186                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2187         if (*disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2188                 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2189
2190         if (*disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2191                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2192         if (*disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2193                 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2194
2195         if (*disp_int & DC_HPD1_INTERRUPT) {
2196                 tmp = RREG32(DC_HPD1_INT_CONTROL);
2197                 tmp |= DC_HPDx_INT_ACK;
2198                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2199         }
2200         if (*disp_int_cont & DC_HPD2_INTERRUPT) {
2201                 tmp = RREG32(DC_HPD2_INT_CONTROL);
2202                 tmp |= DC_HPDx_INT_ACK;
2203                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2204         }
2205         if (*disp_int_cont2 & DC_HPD3_INTERRUPT) {
2206                 tmp = RREG32(DC_HPD3_INT_CONTROL);
2207                 tmp |= DC_HPDx_INT_ACK;
2208                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2209         }
2210         if (*disp_int_cont3 & DC_HPD4_INTERRUPT) {
2211                 tmp = RREG32(DC_HPD4_INT_CONTROL);
2212                 tmp |= DC_HPDx_INT_ACK;
2213                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2214         }
2215         if (*disp_int_cont4 & DC_HPD5_INTERRUPT) {
2216                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2217                 tmp |= DC_HPDx_INT_ACK;
2218                 WREG32(DC_HPD5_INT_CONTROL, tmp);
2219         }
2220         if (*disp_int_cont5 & DC_HPD6_INTERRUPT) {
2221                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2222                 tmp |= DC_HPDx_INT_ACK;
2223                 WREG32(DC_HPD6_INT_CONTROL, tmp);
2224         }
2225 }
2226
2227 void evergreen_irq_disable(struct radeon_device *rdev)
2228 {
2229         u32 disp_int, disp_int_cont, disp_int_cont2;
2230         u32 disp_int_cont3, disp_int_cont4, disp_int_cont5;
2231
2232         r600_disable_interrupts(rdev);
2233         /* Wait and acknowledge irq */
2234         mdelay(1);
2235         evergreen_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2,
2236                           &disp_int_cont3, &disp_int_cont4, &disp_int_cont5);
2237         evergreen_disable_interrupt_state(rdev);
2238 }
2239
2240 static void evergreen_irq_suspend(struct radeon_device *rdev)
2241 {
2242         evergreen_irq_disable(rdev);
2243         r600_rlc_stop(rdev);
2244 }
2245
2246 static inline u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2247 {
2248         u32 wptr, tmp;
2249
2250         if (rdev->wb.enabled)
2251                 wptr = rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4];
2252         else
2253                 wptr = RREG32(IH_RB_WPTR);
2254
2255         if (wptr & RB_OVERFLOW) {
2256                 /* When a ring buffer overflow happen start parsing interrupt
2257                  * from the last not overwritten vector (wptr + 16). Hopefully
2258                  * this should allow us to catchup.
2259                  */
2260                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2261                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2262                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2263                 tmp = RREG32(IH_RB_CNTL);
2264                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2265                 WREG32(IH_RB_CNTL, tmp);
2266         }
2267         return (wptr & rdev->ih.ptr_mask);
2268 }
2269
2270 int evergreen_irq_process(struct radeon_device *rdev)
2271 {
2272         u32 wptr = evergreen_get_ih_wptr(rdev);
2273         u32 rptr = rdev->ih.rptr;
2274         u32 src_id, src_data;
2275         u32 ring_index;
2276         u32 disp_int, disp_int_cont, disp_int_cont2;
2277         u32 disp_int_cont3, disp_int_cont4, disp_int_cont5;
2278         unsigned long flags;
2279         bool queue_hotplug = false;
2280
2281         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2282         if (!rdev->ih.enabled)
2283                 return IRQ_NONE;
2284
2285         spin_lock_irqsave(&rdev->ih.lock, flags);
2286
2287         if (rptr == wptr) {
2288                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2289                 return IRQ_NONE;
2290         }
2291         if (rdev->shutdown) {
2292                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2293                 return IRQ_NONE;
2294         }
2295
2296 restart_ih:
2297         /* display interrupts */
2298         evergreen_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2,
2299                           &disp_int_cont3, &disp_int_cont4, &disp_int_cont5);
2300
2301         rdev->ih.wptr = wptr;
2302         while (rptr != wptr) {
2303                 /* wptr/rptr are in bytes! */
2304                 ring_index = rptr / 4;
2305                 src_id =  rdev->ih.ring[ring_index] & 0xff;
2306                 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
2307
2308                 switch (src_id) {
2309                 case 1: /* D1 vblank/vline */
2310                         switch (src_data) {
2311                         case 0: /* D1 vblank */
2312                                 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
2313                                         drm_handle_vblank(rdev->ddev, 0);
2314                                         rdev->pm.vblank_sync = true;
2315                                         wake_up(&rdev->irq.vblank_queue);
2316                                         disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2317                                         DRM_DEBUG("IH: D1 vblank\n");
2318                                 }
2319                                 break;
2320                         case 1: /* D1 vline */
2321                                 if (disp_int & LB_D1_VLINE_INTERRUPT) {
2322                                         disp_int &= ~LB_D1_VLINE_INTERRUPT;
2323                                         DRM_DEBUG("IH: D1 vline\n");
2324                                 }
2325                                 break;
2326                         default:
2327                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2328                                 break;
2329                         }
2330                         break;
2331                 case 2: /* D2 vblank/vline */
2332                         switch (src_data) {
2333                         case 0: /* D2 vblank */
2334                                 if (disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
2335                                         drm_handle_vblank(rdev->ddev, 1);
2336                                         rdev->pm.vblank_sync = true;
2337                                         wake_up(&rdev->irq.vblank_queue);
2338                                         disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
2339                                         DRM_DEBUG("IH: D2 vblank\n");
2340                                 }
2341                                 break;
2342                         case 1: /* D2 vline */
2343                                 if (disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2344                                         disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
2345                                         DRM_DEBUG("IH: D2 vline\n");
2346                                 }
2347                                 break;
2348                         default:
2349                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2350                                 break;
2351                         }
2352                         break;
2353                 case 3: /* D3 vblank/vline */
2354                         switch (src_data) {
2355                         case 0: /* D3 vblank */
2356                                 if (disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2357                                         drm_handle_vblank(rdev->ddev, 2);
2358                                         rdev->pm.vblank_sync = true;
2359                                         wake_up(&rdev->irq.vblank_queue);
2360                                         disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
2361                                         DRM_DEBUG("IH: D3 vblank\n");
2362                                 }
2363                                 break;
2364                         case 1: /* D3 vline */
2365                                 if (disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
2366                                         disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
2367                                         DRM_DEBUG("IH: D3 vline\n");
2368                                 }
2369                                 break;
2370                         default:
2371                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2372                                 break;
2373                         }
2374                         break;
2375                 case 4: /* D4 vblank/vline */
2376                         switch (src_data) {
2377                         case 0: /* D4 vblank */
2378                                 if (disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
2379                                         drm_handle_vblank(rdev->ddev, 3);
2380                                         rdev->pm.vblank_sync = true;
2381                                         wake_up(&rdev->irq.vblank_queue);
2382                                         disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
2383                                         DRM_DEBUG("IH: D4 vblank\n");
2384                                 }
2385                                 break;
2386                         case 1: /* D4 vline */
2387                                 if (disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
2388                                         disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
2389                                         DRM_DEBUG("IH: D4 vline\n");
2390                                 }
2391                                 break;
2392                         default:
2393                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2394                                 break;
2395                         }
2396                         break;
2397                 case 5: /* D5 vblank/vline */
2398                         switch (src_data) {
2399                         case 0: /* D5 vblank */
2400                                 if (disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
2401                                         drm_handle_vblank(rdev->ddev, 4);
2402                                         rdev->pm.vblank_sync = true;
2403                                         wake_up(&rdev->irq.vblank_queue);
2404                                         disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
2405                                         DRM_DEBUG("IH: D5 vblank\n");
2406                                 }
2407                                 break;
2408                         case 1: /* D5 vline */
2409                                 if (disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
2410                                         disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
2411                                         DRM_DEBUG("IH: D5 vline\n");
2412                                 }
2413                                 break;
2414                         default:
2415                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2416                                 break;
2417                         }
2418                         break;
2419                 case 6: /* D6 vblank/vline */
2420                         switch (src_data) {
2421                         case 0: /* D6 vblank */
2422                                 if (disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
2423                                         drm_handle_vblank(rdev->ddev, 5);
2424                                         rdev->pm.vblank_sync = true;
2425                                         wake_up(&rdev->irq.vblank_queue);
2426                                         disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
2427                                         DRM_DEBUG("IH: D6 vblank\n");
2428                                 }
2429                                 break;
2430                         case 1: /* D6 vline */
2431                                 if (disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
2432                                         disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
2433                                         DRM_DEBUG("IH: D6 vline\n");
2434                                 }
2435                                 break;
2436                         default:
2437                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2438                                 break;
2439                         }
2440                         break;
2441                 case 42: /* HPD hotplug */
2442                         switch (src_data) {
2443                         case 0:
2444                                 if (disp_int & DC_HPD1_INTERRUPT) {
2445                                         disp_int &= ~DC_HPD1_INTERRUPT;
2446                                         queue_hotplug = true;
2447                                         DRM_DEBUG("IH: HPD1\n");
2448                                 }
2449                                 break;
2450                         case 1:
2451                                 if (disp_int_cont & DC_HPD2_INTERRUPT) {
2452                                         disp_int_cont &= ~DC_HPD2_INTERRUPT;
2453                                         queue_hotplug = true;
2454                                         DRM_DEBUG("IH: HPD2\n");
2455                                 }
2456                                 break;
2457                         case 2:
2458                                 if (disp_int_cont2 & DC_HPD3_INTERRUPT) {
2459                                         disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
2460                                         queue_hotplug = true;
2461                                         DRM_DEBUG("IH: HPD3\n");
2462                                 }
2463                                 break;
2464                         case 3:
2465                                 if (disp_int_cont3 & DC_HPD4_INTERRUPT) {
2466                                         disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
2467                                         queue_hotplug = true;
2468                                         DRM_DEBUG("IH: HPD4\n");
2469                                 }
2470                                 break;
2471                         case 4:
2472                                 if (disp_int_cont4 & DC_HPD5_INTERRUPT) {
2473                                         disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
2474                                         queue_hotplug = true;
2475                                         DRM_DEBUG("IH: HPD5\n");
2476                                 }
2477                                 break;
2478                         case 5:
2479                                 if (disp_int_cont5 & DC_HPD6_INTERRUPT) {
2480                                         disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
2481                                         queue_hotplug = true;
2482                                         DRM_DEBUG("IH: HPD6\n");
2483                                 }
2484                                 break;
2485                         default:
2486                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2487                                 break;
2488                         }
2489                         break;
2490                 case 176: /* CP_INT in ring buffer */
2491                 case 177: /* CP_INT in IB1 */
2492                 case 178: /* CP_INT in IB2 */
2493                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2494                         radeon_fence_process(rdev);
2495                         break;
2496                 case 181: /* CP EOP event */
2497                         DRM_DEBUG("IH: CP EOP\n");
2498                         radeon_fence_process(rdev);
2499                         break;
2500                 case 233: /* GUI IDLE */
2501                         DRM_DEBUG("IH: CP EOP\n");
2502                         rdev->pm.gui_idle = true;
2503                         wake_up(&rdev->irq.idle_queue);
2504                         break;
2505                 default:
2506                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2507                         break;
2508                 }
2509
2510                 /* wptr/rptr are in bytes! */
2511                 rptr += 16;
2512                 rptr &= rdev->ih.ptr_mask;
2513         }
2514         /* make sure wptr hasn't changed while processing */
2515         wptr = evergreen_get_ih_wptr(rdev);
2516         if (wptr != rdev->ih.wptr)
2517                 goto restart_ih;
2518         if (queue_hotplug)
2519                 queue_work(rdev->wq, &rdev->hotplug_work);
2520         rdev->ih.rptr = rptr;
2521         WREG32(IH_RB_RPTR, rdev->ih.rptr);
2522         spin_unlock_irqrestore(&rdev->ih.lock, flags);
2523         return IRQ_HANDLED;
2524 }
2525
2526 static int evergreen_startup(struct radeon_device *rdev)
2527 {
2528         int r;
2529
2530         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2531                 r = r600_init_microcode(rdev);
2532                 if (r) {
2533                         DRM_ERROR("Failed to load firmware!\n");
2534                         return r;
2535                 }
2536         }
2537
2538         evergreen_mc_program(rdev);
2539         if (rdev->flags & RADEON_IS_AGP) {
2540                 evergreen_agp_enable(rdev);
2541         } else {
2542                 r = evergreen_pcie_gart_enable(rdev);
2543                 if (r)
2544                         return r;
2545         }
2546         evergreen_gpu_init(rdev);
2547
2548         r = evergreen_blit_init(rdev);
2549         if (r) {
2550                 evergreen_blit_fini(rdev);
2551                 rdev->asic->copy = NULL;
2552                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2553         }
2554
2555         /* allocate wb buffer */
2556         r = radeon_wb_init(rdev);
2557         if (r)
2558                 return r;
2559
2560         /* Enable IRQ */
2561         r = r600_irq_init(rdev);
2562         if (r) {
2563                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2564                 radeon_irq_kms_fini(rdev);
2565                 return r;
2566         }
2567         evergreen_irq_set(rdev);
2568
2569         r = radeon_ring_init(rdev, rdev->cp.ring_size);
2570         if (r)
2571                 return r;
2572         r = evergreen_cp_load_microcode(rdev);
2573         if (r)
2574                 return r;
2575         r = evergreen_cp_resume(rdev);
2576         if (r)
2577                 return r;
2578
2579         return 0;
2580 }
2581
2582 int evergreen_resume(struct radeon_device *rdev)
2583 {
2584         int r;
2585
2586         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
2587          * posting will perform necessary task to bring back GPU into good
2588          * shape.
2589          */
2590         /* post card */
2591         atom_asic_init(rdev->mode_info.atom_context);
2592
2593         r = evergreen_startup(rdev);
2594         if (r) {
2595                 DRM_ERROR("r600 startup failed on resume\n");
2596                 return r;
2597         }
2598
2599         r = r600_ib_test(rdev);
2600         if (r) {
2601                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2602                 return r;
2603         }
2604
2605         return r;
2606
2607 }
2608
2609 int evergreen_suspend(struct radeon_device *rdev)
2610 {
2611         int r;
2612
2613         /* FIXME: we should wait for ring to be empty */
2614         r700_cp_stop(rdev);
2615         rdev->cp.ready = false;
2616         evergreen_irq_suspend(rdev);
2617         radeon_wb_disable(rdev);
2618         evergreen_pcie_gart_disable(rdev);
2619
2620         /* unpin shaders bo */
2621         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2622         if (likely(r == 0)) {
2623                 radeon_bo_unpin(rdev->r600_blit.shader_obj);
2624                 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2625         }
2626
2627         return 0;
2628 }
2629
2630 int evergreen_copy_blit(struct radeon_device *rdev,
2631                         uint64_t src_offset, uint64_t dst_offset,
2632                         unsigned num_pages, struct radeon_fence *fence)
2633 {
2634         int r;
2635
2636         mutex_lock(&rdev->r600_blit.mutex);
2637         rdev->r600_blit.vb_ib = NULL;
2638         r = evergreen_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
2639         if (r) {
2640                 if (rdev->r600_blit.vb_ib)
2641                         radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2642                 mutex_unlock(&rdev->r600_blit.mutex);
2643                 return r;
2644         }
2645         evergreen_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
2646         evergreen_blit_done_copy(rdev, fence);
2647         mutex_unlock(&rdev->r600_blit.mutex);
2648         return 0;
2649 }
2650
2651 static bool evergreen_card_posted(struct radeon_device *rdev)
2652 {
2653         u32 reg;
2654
2655         /* first check CRTCs */
2656         reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
2657                 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
2658                 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
2659                 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
2660                 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
2661                 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
2662         if (reg & EVERGREEN_CRTC_MASTER_EN)
2663                 return true;
2664
2665         /* then check MEM_SIZE, in case the crtcs are off */
2666         if (RREG32(CONFIG_MEMSIZE))
2667                 return true;
2668
2669         return false;
2670 }
2671
2672 /* Plan is to move initialization in that function and use
2673  * helper function so that radeon_device_init pretty much
2674  * do nothing more than calling asic specific function. This
2675  * should also allow to remove a bunch of callback function
2676  * like vram_info.
2677  */
2678 int evergreen_init(struct radeon_device *rdev)
2679 {
2680         int r;
2681
2682         r = radeon_dummy_page_init(rdev);
2683         if (r)
2684                 return r;
2685         /* This don't do much */
2686         r = radeon_gem_init(rdev);
2687         if (r)
2688                 return r;
2689         /* Read BIOS */
2690         if (!radeon_get_bios(rdev)) {
2691                 if (ASIC_IS_AVIVO(rdev))
2692                         return -EINVAL;
2693         }
2694         /* Must be an ATOMBIOS */
2695         if (!rdev->is_atom_bios) {
2696                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2697                 return -EINVAL;
2698         }
2699         r = radeon_atombios_init(rdev);
2700         if (r)
2701                 return r;
2702         /* Post card if necessary */
2703         if (!evergreen_card_posted(rdev)) {
2704                 if (!rdev->bios) {
2705                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2706                         return -EINVAL;
2707                 }
2708                 DRM_INFO("GPU not posted. posting now...\n");
2709                 atom_asic_init(rdev->mode_info.atom_context);
2710         }
2711         /* Initialize scratch registers */
2712         r600_scratch_init(rdev);
2713         /* Initialize surface registers */
2714         radeon_surface_init(rdev);
2715         /* Initialize clocks */
2716         radeon_get_clock_info(rdev->ddev);
2717         /* Fence driver */
2718         r = radeon_fence_driver_init(rdev);
2719         if (r)
2720                 return r;
2721         /* initialize AGP */
2722         if (rdev->flags & RADEON_IS_AGP) {
2723                 r = radeon_agp_init(rdev);
2724                 if (r)
2725                         radeon_agp_disable(rdev);
2726         }
2727         /* initialize memory controller */
2728         r = evergreen_mc_init(rdev);
2729         if (r)
2730                 return r;
2731         /* Memory manager */
2732         r = radeon_bo_init(rdev);
2733         if (r)
2734                 return r;
2735
2736         r = radeon_irq_kms_init(rdev);
2737         if (r)
2738                 return r;
2739
2740         rdev->cp.ring_obj = NULL;
2741         r600_ring_init(rdev, 1024 * 1024);
2742
2743         rdev->ih.ring_obj = NULL;
2744         r600_ih_ring_init(rdev, 64 * 1024);
2745
2746         r = r600_pcie_gart_init(rdev);
2747         if (r)
2748                 return r;
2749
2750         rdev->accel_working = true;
2751         r = evergreen_startup(rdev);
2752         if (r) {
2753                 dev_err(rdev->dev, "disabling GPU acceleration\n");
2754                 r700_cp_fini(rdev);
2755                 r600_irq_fini(rdev);
2756                 radeon_wb_fini(rdev);
2757                 radeon_irq_kms_fini(rdev);
2758                 evergreen_pcie_gart_fini(rdev);
2759                 rdev->accel_working = false;
2760         }
2761         if (rdev->accel_working) {
2762                 r = radeon_ib_pool_init(rdev);
2763                 if (r) {
2764                         DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
2765                         rdev->accel_working = false;
2766                 }
2767                 r = r600_ib_test(rdev);
2768                 if (r) {
2769                         DRM_ERROR("radeon: failed testing IB (%d).\n", r);
2770                         rdev->accel_working = false;
2771                 }
2772         }
2773         return 0;
2774 }
2775
2776 void evergreen_fini(struct radeon_device *rdev)
2777 {
2778         evergreen_blit_fini(rdev);
2779         r700_cp_fini(rdev);
2780         r600_irq_fini(rdev);
2781         radeon_wb_fini(rdev);
2782         radeon_irq_kms_fini(rdev);
2783         evergreen_pcie_gart_fini(rdev);
2784         radeon_gem_fini(rdev);
2785         radeon_fence_driver_fini(rdev);
2786         radeon_agp_fini(rdev);
2787         radeon_bo_fini(rdev);
2788         radeon_atombios_fini(rdev);
2789         kfree(rdev->bios);
2790         rdev->bios = NULL;
2791         radeon_dummy_page_fini(rdev);
2792 }