Merge branch 'drm-core-next' of git://people.freedesktop.org/~airlied/linux
[linux-2.6.git] / drivers / gpu / drm / radeon / evergreen.c
1 /*
2  * Copyright 2010 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Alex Deucher
23  */
24 #include <linux/firmware.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
27 #include "drmP.h"
28 #include "radeon.h"
29 #include "radeon_asic.h"
30 #include "radeon_drm.h"
31 #include "evergreend.h"
32 #include "atom.h"
33 #include "avivod.h"
34 #include "evergreen_reg.h"
35 #include "evergreen_blit_shaders.h"
36
37 #define EVERGREEN_PFP_UCODE_SIZE 1120
38 #define EVERGREEN_PM4_UCODE_SIZE 1376
39
40 static void evergreen_gpu_init(struct radeon_device *rdev);
41 void evergreen_fini(struct radeon_device *rdev);
42 void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
43 extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
44                                      int ring, u32 cp_int_cntl);
45
46 void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
47 {
48         u16 ctl, v;
49         int cap, err;
50
51         cap = pci_pcie_cap(rdev->pdev);
52         if (!cap)
53                 return;
54
55         err = pci_read_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, &ctl);
56         if (err)
57                 return;
58
59         v = (ctl & PCI_EXP_DEVCTL_READRQ) >> 12;
60
61         /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it
62          * to avoid hangs or perfomance issues
63          */
64         if ((v == 0) || (v == 6) || (v == 7)) {
65                 ctl &= ~PCI_EXP_DEVCTL_READRQ;
66                 ctl |= (2 << 12);
67                 pci_write_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, ctl);
68         }
69 }
70
71 void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
72 {
73         /* enable the pflip int */
74         radeon_irq_kms_pflip_irq_get(rdev, crtc);
75 }
76
77 void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
78 {
79         /* disable the pflip int */
80         radeon_irq_kms_pflip_irq_put(rdev, crtc);
81 }
82
83 u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
84 {
85         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
86         u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
87         int i;
88
89         /* Lock the graphics update lock */
90         tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
91         WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
92
93         /* update the scanout addresses */
94         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
95                upper_32_bits(crtc_base));
96         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
97                (u32)crtc_base);
98
99         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
100                upper_32_bits(crtc_base));
101         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
102                (u32)crtc_base);
103
104         /* Wait for update_pending to go high. */
105         for (i = 0; i < rdev->usec_timeout; i++) {
106                 if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING)
107                         break;
108                 udelay(1);
109         }
110         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
111
112         /* Unlock the lock, so double-buffering can take place inside vblank */
113         tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
114         WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
115
116         /* Return current update_pending status: */
117         return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
118 }
119
120 /* get temperature in millidegrees */
121 int evergreen_get_temp(struct radeon_device *rdev)
122 {
123         u32 temp, toffset;
124         int actual_temp = 0;
125
126         if (rdev->family == CHIP_JUNIPER) {
127                 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
128                         TOFFSET_SHIFT;
129                 temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >>
130                         TS0_ADC_DOUT_SHIFT;
131
132                 if (toffset & 0x100)
133                         actual_temp = temp / 2 - (0x200 - toffset);
134                 else
135                         actual_temp = temp / 2 + toffset;
136
137                 actual_temp = actual_temp * 1000;
138
139         } else {
140                 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
141                         ASIC_T_SHIFT;
142
143                 if (temp & 0x400)
144                         actual_temp = -256;
145                 else if (temp & 0x200)
146                         actual_temp = 255;
147                 else if (temp & 0x100) {
148                         actual_temp = temp & 0x1ff;
149                         actual_temp |= ~0x1ff;
150                 } else
151                         actual_temp = temp & 0xff;
152
153                 actual_temp = (actual_temp * 1000) / 2;
154         }
155
156         return actual_temp;
157 }
158
159 int sumo_get_temp(struct radeon_device *rdev)
160 {
161         u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
162         int actual_temp = temp - 49;
163
164         return actual_temp * 1000;
165 }
166
167 void sumo_pm_init_profile(struct radeon_device *rdev)
168 {
169         int idx;
170
171         /* default */
172         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
173         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
174         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
175         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
176
177         /* low,mid sh/mh */
178         if (rdev->flags & RADEON_IS_MOBILITY)
179                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
180         else
181                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
182
183         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
184         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
185         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
186         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
187
188         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
189         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
190         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
191         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
192
193         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
194         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
195         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
196         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
197
198         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
199         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
200         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
201         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
202
203         /* high sh/mh */
204         idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
205         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
206         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
207         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
208         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx =
209                 rdev->pm.power_state[idx].num_clock_modes - 1;
210
211         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
212         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
213         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
214         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx =
215                 rdev->pm.power_state[idx].num_clock_modes - 1;
216 }
217
218 void evergreen_pm_misc(struct radeon_device *rdev)
219 {
220         int req_ps_idx = rdev->pm.requested_power_state_index;
221         int req_cm_idx = rdev->pm.requested_clock_mode_index;
222         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
223         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
224
225         if (voltage->type == VOLTAGE_SW) {
226                 /* 0xff01 is a flag rather then an actual voltage */
227                 if (voltage->voltage == 0xff01)
228                         return;
229                 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
230                         radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
231                         rdev->pm.current_vddc = voltage->voltage;
232                         DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
233                 }
234                 /* 0xff01 is a flag rather then an actual voltage */
235                 if (voltage->vddci == 0xff01)
236                         return;
237                 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
238                         radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
239                         rdev->pm.current_vddci = voltage->vddci;
240                         DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);
241                 }
242         }
243 }
244
245 void evergreen_pm_prepare(struct radeon_device *rdev)
246 {
247         struct drm_device *ddev = rdev->ddev;
248         struct drm_crtc *crtc;
249         struct radeon_crtc *radeon_crtc;
250         u32 tmp;
251
252         /* disable any active CRTCs */
253         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
254                 radeon_crtc = to_radeon_crtc(crtc);
255                 if (radeon_crtc->enabled) {
256                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
257                         tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
258                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
259                 }
260         }
261 }
262
263 void evergreen_pm_finish(struct radeon_device *rdev)
264 {
265         struct drm_device *ddev = rdev->ddev;
266         struct drm_crtc *crtc;
267         struct radeon_crtc *radeon_crtc;
268         u32 tmp;
269
270         /* enable any active CRTCs */
271         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
272                 radeon_crtc = to_radeon_crtc(crtc);
273                 if (radeon_crtc->enabled) {
274                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
275                         tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
276                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
277                 }
278         }
279 }
280
281 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
282 {
283         bool connected = false;
284
285         switch (hpd) {
286         case RADEON_HPD_1:
287                 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
288                         connected = true;
289                 break;
290         case RADEON_HPD_2:
291                 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
292                         connected = true;
293                 break;
294         case RADEON_HPD_3:
295                 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
296                         connected = true;
297                 break;
298         case RADEON_HPD_4:
299                 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
300                         connected = true;
301                 break;
302         case RADEON_HPD_5:
303                 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
304                         connected = true;
305                 break;
306         case RADEON_HPD_6:
307                 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
308                         connected = true;
309                         break;
310         default:
311                 break;
312         }
313
314         return connected;
315 }
316
317 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
318                                 enum radeon_hpd_id hpd)
319 {
320         u32 tmp;
321         bool connected = evergreen_hpd_sense(rdev, hpd);
322
323         switch (hpd) {
324         case RADEON_HPD_1:
325                 tmp = RREG32(DC_HPD1_INT_CONTROL);
326                 if (connected)
327                         tmp &= ~DC_HPDx_INT_POLARITY;
328                 else
329                         tmp |= DC_HPDx_INT_POLARITY;
330                 WREG32(DC_HPD1_INT_CONTROL, tmp);
331                 break;
332         case RADEON_HPD_2:
333                 tmp = RREG32(DC_HPD2_INT_CONTROL);
334                 if (connected)
335                         tmp &= ~DC_HPDx_INT_POLARITY;
336                 else
337                         tmp |= DC_HPDx_INT_POLARITY;
338                 WREG32(DC_HPD2_INT_CONTROL, tmp);
339                 break;
340         case RADEON_HPD_3:
341                 tmp = RREG32(DC_HPD3_INT_CONTROL);
342                 if (connected)
343                         tmp &= ~DC_HPDx_INT_POLARITY;
344                 else
345                         tmp |= DC_HPDx_INT_POLARITY;
346                 WREG32(DC_HPD3_INT_CONTROL, tmp);
347                 break;
348         case RADEON_HPD_4:
349                 tmp = RREG32(DC_HPD4_INT_CONTROL);
350                 if (connected)
351                         tmp &= ~DC_HPDx_INT_POLARITY;
352                 else
353                         tmp |= DC_HPDx_INT_POLARITY;
354                 WREG32(DC_HPD4_INT_CONTROL, tmp);
355                 break;
356         case RADEON_HPD_5:
357                 tmp = RREG32(DC_HPD5_INT_CONTROL);
358                 if (connected)
359                         tmp &= ~DC_HPDx_INT_POLARITY;
360                 else
361                         tmp |= DC_HPDx_INT_POLARITY;
362                 WREG32(DC_HPD5_INT_CONTROL, tmp);
363                         break;
364         case RADEON_HPD_6:
365                 tmp = RREG32(DC_HPD6_INT_CONTROL);
366                 if (connected)
367                         tmp &= ~DC_HPDx_INT_POLARITY;
368                 else
369                         tmp |= DC_HPDx_INT_POLARITY;
370                 WREG32(DC_HPD6_INT_CONTROL, tmp);
371                 break;
372         default:
373                 break;
374         }
375 }
376
377 void evergreen_hpd_init(struct radeon_device *rdev)
378 {
379         struct drm_device *dev = rdev->ddev;
380         struct drm_connector *connector;
381         u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
382                 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
383
384         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
385                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
386                 switch (radeon_connector->hpd.hpd) {
387                 case RADEON_HPD_1:
388                         WREG32(DC_HPD1_CONTROL, tmp);
389                         rdev->irq.hpd[0] = true;
390                         break;
391                 case RADEON_HPD_2:
392                         WREG32(DC_HPD2_CONTROL, tmp);
393                         rdev->irq.hpd[1] = true;
394                         break;
395                 case RADEON_HPD_3:
396                         WREG32(DC_HPD3_CONTROL, tmp);
397                         rdev->irq.hpd[2] = true;
398                         break;
399                 case RADEON_HPD_4:
400                         WREG32(DC_HPD4_CONTROL, tmp);
401                         rdev->irq.hpd[3] = true;
402                         break;
403                 case RADEON_HPD_5:
404                         WREG32(DC_HPD5_CONTROL, tmp);
405                         rdev->irq.hpd[4] = true;
406                         break;
407                 case RADEON_HPD_6:
408                         WREG32(DC_HPD6_CONTROL, tmp);
409                         rdev->irq.hpd[5] = true;
410                         break;
411                 default:
412                         break;
413                 }
414                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
415         }
416         if (rdev->irq.installed)
417                 evergreen_irq_set(rdev);
418 }
419
420 void evergreen_hpd_fini(struct radeon_device *rdev)
421 {
422         struct drm_device *dev = rdev->ddev;
423         struct drm_connector *connector;
424
425         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
426                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
427                 switch (radeon_connector->hpd.hpd) {
428                 case RADEON_HPD_1:
429                         WREG32(DC_HPD1_CONTROL, 0);
430                         rdev->irq.hpd[0] = false;
431                         break;
432                 case RADEON_HPD_2:
433                         WREG32(DC_HPD2_CONTROL, 0);
434                         rdev->irq.hpd[1] = false;
435                         break;
436                 case RADEON_HPD_3:
437                         WREG32(DC_HPD3_CONTROL, 0);
438                         rdev->irq.hpd[2] = false;
439                         break;
440                 case RADEON_HPD_4:
441                         WREG32(DC_HPD4_CONTROL, 0);
442                         rdev->irq.hpd[3] = false;
443                         break;
444                 case RADEON_HPD_5:
445                         WREG32(DC_HPD5_CONTROL, 0);
446                         rdev->irq.hpd[4] = false;
447                         break;
448                 case RADEON_HPD_6:
449                         WREG32(DC_HPD6_CONTROL, 0);
450                         rdev->irq.hpd[5] = false;
451                         break;
452                 default:
453                         break;
454                 }
455         }
456 }
457
458 /* watermark setup */
459
460 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
461                                         struct radeon_crtc *radeon_crtc,
462                                         struct drm_display_mode *mode,
463                                         struct drm_display_mode *other_mode)
464 {
465         u32 tmp;
466         /*
467          * Line Buffer Setup
468          * There are 3 line buffers, each one shared by 2 display controllers.
469          * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
470          * the display controllers.  The paritioning is done via one of four
471          * preset allocations specified in bits 2:0:
472          * first display controller
473          *  0 - first half of lb (3840 * 2)
474          *  1 - first 3/4 of lb (5760 * 2)
475          *  2 - whole lb (7680 * 2), other crtc must be disabled
476          *  3 - first 1/4 of lb (1920 * 2)
477          * second display controller
478          *  4 - second half of lb (3840 * 2)
479          *  5 - second 3/4 of lb (5760 * 2)
480          *  6 - whole lb (7680 * 2), other crtc must be disabled
481          *  7 - last 1/4 of lb (1920 * 2)
482          */
483         /* this can get tricky if we have two large displays on a paired group
484          * of crtcs.  Ideally for multiple large displays we'd assign them to
485          * non-linked crtcs for maximum line buffer allocation.
486          */
487         if (radeon_crtc->base.enabled && mode) {
488                 if (other_mode)
489                         tmp = 0; /* 1/2 */
490                 else
491                         tmp = 2; /* whole */
492         } else
493                 tmp = 0;
494
495         /* second controller of the pair uses second half of the lb */
496         if (radeon_crtc->crtc_id % 2)
497                 tmp += 4;
498         WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
499
500         if (radeon_crtc->base.enabled && mode) {
501                 switch (tmp) {
502                 case 0:
503                 case 4:
504                 default:
505                         if (ASIC_IS_DCE5(rdev))
506                                 return 4096 * 2;
507                         else
508                                 return 3840 * 2;
509                 case 1:
510                 case 5:
511                         if (ASIC_IS_DCE5(rdev))
512                                 return 6144 * 2;
513                         else
514                                 return 5760 * 2;
515                 case 2:
516                 case 6:
517                         if (ASIC_IS_DCE5(rdev))
518                                 return 8192 * 2;
519                         else
520                                 return 7680 * 2;
521                 case 3:
522                 case 7:
523                         if (ASIC_IS_DCE5(rdev))
524                                 return 2048 * 2;
525                         else
526                                 return 1920 * 2;
527                 }
528         }
529
530         /* controller not enabled, so no lb used */
531         return 0;
532 }
533
534 static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
535 {
536         u32 tmp = RREG32(MC_SHARED_CHMAP);
537
538         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
539         case 0:
540         default:
541                 return 1;
542         case 1:
543                 return 2;
544         case 2:
545                 return 4;
546         case 3:
547                 return 8;
548         }
549 }
550
551 struct evergreen_wm_params {
552         u32 dram_channels; /* number of dram channels */
553         u32 yclk;          /* bandwidth per dram data pin in kHz */
554         u32 sclk;          /* engine clock in kHz */
555         u32 disp_clk;      /* display clock in kHz */
556         u32 src_width;     /* viewport width */
557         u32 active_time;   /* active display time in ns */
558         u32 blank_time;    /* blank time in ns */
559         bool interlaced;    /* mode is interlaced */
560         fixed20_12 vsc;    /* vertical scale ratio */
561         u32 num_heads;     /* number of active crtcs */
562         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
563         u32 lb_size;       /* line buffer allocated to pipe */
564         u32 vtaps;         /* vertical scaler taps */
565 };
566
567 static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
568 {
569         /* Calculate DRAM Bandwidth and the part allocated to display. */
570         fixed20_12 dram_efficiency; /* 0.7 */
571         fixed20_12 yclk, dram_channels, bandwidth;
572         fixed20_12 a;
573
574         a.full = dfixed_const(1000);
575         yclk.full = dfixed_const(wm->yclk);
576         yclk.full = dfixed_div(yclk, a);
577         dram_channels.full = dfixed_const(wm->dram_channels * 4);
578         a.full = dfixed_const(10);
579         dram_efficiency.full = dfixed_const(7);
580         dram_efficiency.full = dfixed_div(dram_efficiency, a);
581         bandwidth.full = dfixed_mul(dram_channels, yclk);
582         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
583
584         return dfixed_trunc(bandwidth);
585 }
586
587 static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
588 {
589         /* Calculate DRAM Bandwidth and the part allocated to display. */
590         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
591         fixed20_12 yclk, dram_channels, bandwidth;
592         fixed20_12 a;
593
594         a.full = dfixed_const(1000);
595         yclk.full = dfixed_const(wm->yclk);
596         yclk.full = dfixed_div(yclk, a);
597         dram_channels.full = dfixed_const(wm->dram_channels * 4);
598         a.full = dfixed_const(10);
599         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
600         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
601         bandwidth.full = dfixed_mul(dram_channels, yclk);
602         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
603
604         return dfixed_trunc(bandwidth);
605 }
606
607 static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
608 {
609         /* Calculate the display Data return Bandwidth */
610         fixed20_12 return_efficiency; /* 0.8 */
611         fixed20_12 sclk, bandwidth;
612         fixed20_12 a;
613
614         a.full = dfixed_const(1000);
615         sclk.full = dfixed_const(wm->sclk);
616         sclk.full = dfixed_div(sclk, a);
617         a.full = dfixed_const(10);
618         return_efficiency.full = dfixed_const(8);
619         return_efficiency.full = dfixed_div(return_efficiency, a);
620         a.full = dfixed_const(32);
621         bandwidth.full = dfixed_mul(a, sclk);
622         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
623
624         return dfixed_trunc(bandwidth);
625 }
626
627 static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
628 {
629         /* Calculate the DMIF Request Bandwidth */
630         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
631         fixed20_12 disp_clk, bandwidth;
632         fixed20_12 a;
633
634         a.full = dfixed_const(1000);
635         disp_clk.full = dfixed_const(wm->disp_clk);
636         disp_clk.full = dfixed_div(disp_clk, a);
637         a.full = dfixed_const(10);
638         disp_clk_request_efficiency.full = dfixed_const(8);
639         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
640         a.full = dfixed_const(32);
641         bandwidth.full = dfixed_mul(a, disp_clk);
642         bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
643
644         return dfixed_trunc(bandwidth);
645 }
646
647 static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
648 {
649         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
650         u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
651         u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
652         u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
653
654         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
655 }
656
657 static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
658 {
659         /* Calculate the display mode Average Bandwidth
660          * DisplayMode should contain the source and destination dimensions,
661          * timing, etc.
662          */
663         fixed20_12 bpp;
664         fixed20_12 line_time;
665         fixed20_12 src_width;
666         fixed20_12 bandwidth;
667         fixed20_12 a;
668
669         a.full = dfixed_const(1000);
670         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
671         line_time.full = dfixed_div(line_time, a);
672         bpp.full = dfixed_const(wm->bytes_per_pixel);
673         src_width.full = dfixed_const(wm->src_width);
674         bandwidth.full = dfixed_mul(src_width, bpp);
675         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
676         bandwidth.full = dfixed_div(bandwidth, line_time);
677
678         return dfixed_trunc(bandwidth);
679 }
680
681 static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
682 {
683         /* First calcualte the latency in ns */
684         u32 mc_latency = 2000; /* 2000 ns. */
685         u32 available_bandwidth = evergreen_available_bandwidth(wm);
686         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
687         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
688         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
689         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
690                 (wm->num_heads * cursor_line_pair_return_time);
691         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
692         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
693         fixed20_12 a, b, c;
694
695         if (wm->num_heads == 0)
696                 return 0;
697
698         a.full = dfixed_const(2);
699         b.full = dfixed_const(1);
700         if ((wm->vsc.full > a.full) ||
701             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
702             (wm->vtaps >= 5) ||
703             ((wm->vsc.full >= a.full) && wm->interlaced))
704                 max_src_lines_per_dst_line = 4;
705         else
706                 max_src_lines_per_dst_line = 2;
707
708         a.full = dfixed_const(available_bandwidth);
709         b.full = dfixed_const(wm->num_heads);
710         a.full = dfixed_div(a, b);
711
712         b.full = dfixed_const(1000);
713         c.full = dfixed_const(wm->disp_clk);
714         b.full = dfixed_div(c, b);
715         c.full = dfixed_const(wm->bytes_per_pixel);
716         b.full = dfixed_mul(b, c);
717
718         lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
719
720         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
721         b.full = dfixed_const(1000);
722         c.full = dfixed_const(lb_fill_bw);
723         b.full = dfixed_div(c, b);
724         a.full = dfixed_div(a, b);
725         line_fill_time = dfixed_trunc(a);
726
727         if (line_fill_time < wm->active_time)
728                 return latency;
729         else
730                 return latency + (line_fill_time - wm->active_time);
731
732 }
733
734 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
735 {
736         if (evergreen_average_bandwidth(wm) <=
737             (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
738                 return true;
739         else
740                 return false;
741 };
742
743 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
744 {
745         if (evergreen_average_bandwidth(wm) <=
746             (evergreen_available_bandwidth(wm) / wm->num_heads))
747                 return true;
748         else
749                 return false;
750 };
751
752 static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
753 {
754         u32 lb_partitions = wm->lb_size / wm->src_width;
755         u32 line_time = wm->active_time + wm->blank_time;
756         u32 latency_tolerant_lines;
757         u32 latency_hiding;
758         fixed20_12 a;
759
760         a.full = dfixed_const(1);
761         if (wm->vsc.full > a.full)
762                 latency_tolerant_lines = 1;
763         else {
764                 if (lb_partitions <= (wm->vtaps + 1))
765                         latency_tolerant_lines = 1;
766                 else
767                         latency_tolerant_lines = 2;
768         }
769
770         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
771
772         if (evergreen_latency_watermark(wm) <= latency_hiding)
773                 return true;
774         else
775                 return false;
776 }
777
778 static void evergreen_program_watermarks(struct radeon_device *rdev,
779                                          struct radeon_crtc *radeon_crtc,
780                                          u32 lb_size, u32 num_heads)
781 {
782         struct drm_display_mode *mode = &radeon_crtc->base.mode;
783         struct evergreen_wm_params wm;
784         u32 pixel_period;
785         u32 line_time = 0;
786         u32 latency_watermark_a = 0, latency_watermark_b = 0;
787         u32 priority_a_mark = 0, priority_b_mark = 0;
788         u32 priority_a_cnt = PRIORITY_OFF;
789         u32 priority_b_cnt = PRIORITY_OFF;
790         u32 pipe_offset = radeon_crtc->crtc_id * 16;
791         u32 tmp, arb_control3;
792         fixed20_12 a, b, c;
793
794         if (radeon_crtc->base.enabled && num_heads && mode) {
795                 pixel_period = 1000000 / (u32)mode->clock;
796                 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
797                 priority_a_cnt = 0;
798                 priority_b_cnt = 0;
799
800                 wm.yclk = rdev->pm.current_mclk * 10;
801                 wm.sclk = rdev->pm.current_sclk * 10;
802                 wm.disp_clk = mode->clock;
803                 wm.src_width = mode->crtc_hdisplay;
804                 wm.active_time = mode->crtc_hdisplay * pixel_period;
805                 wm.blank_time = line_time - wm.active_time;
806                 wm.interlaced = false;
807                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
808                         wm.interlaced = true;
809                 wm.vsc = radeon_crtc->vsc;
810                 wm.vtaps = 1;
811                 if (radeon_crtc->rmx_type != RMX_OFF)
812                         wm.vtaps = 2;
813                 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
814                 wm.lb_size = lb_size;
815                 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
816                 wm.num_heads = num_heads;
817
818                 /* set for high clocks */
819                 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
820                 /* set for low clocks */
821                 /* wm.yclk = low clk; wm.sclk = low clk */
822                 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
823
824                 /* possibly force display priority to high */
825                 /* should really do this at mode validation time... */
826                 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
827                     !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
828                     !evergreen_check_latency_hiding(&wm) ||
829                     (rdev->disp_priority == 2)) {
830                         DRM_DEBUG_KMS("force priority to high\n");
831                         priority_a_cnt |= PRIORITY_ALWAYS_ON;
832                         priority_b_cnt |= PRIORITY_ALWAYS_ON;
833                 }
834
835                 a.full = dfixed_const(1000);
836                 b.full = dfixed_const(mode->clock);
837                 b.full = dfixed_div(b, a);
838                 c.full = dfixed_const(latency_watermark_a);
839                 c.full = dfixed_mul(c, b);
840                 c.full = dfixed_mul(c, radeon_crtc->hsc);
841                 c.full = dfixed_div(c, a);
842                 a.full = dfixed_const(16);
843                 c.full = dfixed_div(c, a);
844                 priority_a_mark = dfixed_trunc(c);
845                 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
846
847                 a.full = dfixed_const(1000);
848                 b.full = dfixed_const(mode->clock);
849                 b.full = dfixed_div(b, a);
850                 c.full = dfixed_const(latency_watermark_b);
851                 c.full = dfixed_mul(c, b);
852                 c.full = dfixed_mul(c, radeon_crtc->hsc);
853                 c.full = dfixed_div(c, a);
854                 a.full = dfixed_const(16);
855                 c.full = dfixed_div(c, a);
856                 priority_b_mark = dfixed_trunc(c);
857                 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
858         }
859
860         /* select wm A */
861         arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
862         tmp = arb_control3;
863         tmp &= ~LATENCY_WATERMARK_MASK(3);
864         tmp |= LATENCY_WATERMARK_MASK(1);
865         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
866         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
867                (LATENCY_LOW_WATERMARK(latency_watermark_a) |
868                 LATENCY_HIGH_WATERMARK(line_time)));
869         /* select wm B */
870         tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
871         tmp &= ~LATENCY_WATERMARK_MASK(3);
872         tmp |= LATENCY_WATERMARK_MASK(2);
873         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
874         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
875                (LATENCY_LOW_WATERMARK(latency_watermark_b) |
876                 LATENCY_HIGH_WATERMARK(line_time)));
877         /* restore original selection */
878         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
879
880         /* write the priority marks */
881         WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
882         WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
883
884 }
885
886 void evergreen_bandwidth_update(struct radeon_device *rdev)
887 {
888         struct drm_display_mode *mode0 = NULL;
889         struct drm_display_mode *mode1 = NULL;
890         u32 num_heads = 0, lb_size;
891         int i;
892
893         radeon_update_display_priority(rdev);
894
895         for (i = 0; i < rdev->num_crtc; i++) {
896                 if (rdev->mode_info.crtcs[i]->base.enabled)
897                         num_heads++;
898         }
899         for (i = 0; i < rdev->num_crtc; i += 2) {
900                 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
901                 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
902                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
903                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
904                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
905                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
906         }
907 }
908
909 int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
910 {
911         unsigned i;
912         u32 tmp;
913
914         for (i = 0; i < rdev->usec_timeout; i++) {
915                 /* read MC_STATUS */
916                 tmp = RREG32(SRBM_STATUS) & 0x1F00;
917                 if (!tmp)
918                         return 0;
919                 udelay(1);
920         }
921         return -1;
922 }
923
924 /*
925  * GART
926  */
927 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
928 {
929         unsigned i;
930         u32 tmp;
931
932         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
933
934         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
935         for (i = 0; i < rdev->usec_timeout; i++) {
936                 /* read MC_STATUS */
937                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
938                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
939                 if (tmp == 2) {
940                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
941                         return;
942                 }
943                 if (tmp) {
944                         return;
945                 }
946                 udelay(1);
947         }
948 }
949
950 int evergreen_pcie_gart_enable(struct radeon_device *rdev)
951 {
952         u32 tmp;
953         int r;
954
955         if (rdev->gart.robj == NULL) {
956                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
957                 return -EINVAL;
958         }
959         r = radeon_gart_table_vram_pin(rdev);
960         if (r)
961                 return r;
962         radeon_gart_restore(rdev);
963         /* Setup L2 cache */
964         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
965                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
966                                 EFFECTIVE_L2_QUEUE_SIZE(7));
967         WREG32(VM_L2_CNTL2, 0);
968         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
969         /* Setup TLB control */
970         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
971                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
972                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
973                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
974         if (rdev->flags & RADEON_IS_IGP) {
975                 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
976                 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
977                 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
978         } else {
979                 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
980                 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
981                 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
982         }
983         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
984         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
985         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
986         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
987         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
988         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
989         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
990         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
991                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
992         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
993                         (u32)(rdev->dummy_page.addr >> 12));
994         WREG32(VM_CONTEXT1_CNTL, 0);
995
996         evergreen_pcie_gart_tlb_flush(rdev);
997         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
998                  (unsigned)(rdev->mc.gtt_size >> 20),
999                  (unsigned long long)rdev->gart.table_addr);
1000         rdev->gart.ready = true;
1001         return 0;
1002 }
1003
1004 void evergreen_pcie_gart_disable(struct radeon_device *rdev)
1005 {
1006         u32 tmp;
1007
1008         /* Disable all tables */
1009         WREG32(VM_CONTEXT0_CNTL, 0);
1010         WREG32(VM_CONTEXT1_CNTL, 0);
1011
1012         /* Setup L2 cache */
1013         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1014                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1015         WREG32(VM_L2_CNTL2, 0);
1016         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1017         /* Setup TLB control */
1018         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1019         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1020         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1021         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1022         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1023         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1024         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1025         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1026         radeon_gart_table_vram_unpin(rdev);
1027 }
1028
1029 void evergreen_pcie_gart_fini(struct radeon_device *rdev)
1030 {
1031         evergreen_pcie_gart_disable(rdev);
1032         radeon_gart_table_vram_free(rdev);
1033         radeon_gart_fini(rdev);
1034 }
1035
1036
1037 void evergreen_agp_enable(struct radeon_device *rdev)
1038 {
1039         u32 tmp;
1040
1041         /* Setup L2 cache */
1042         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1043                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1044                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1045         WREG32(VM_L2_CNTL2, 0);
1046         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1047         /* Setup TLB control */
1048         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1049                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1050                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1051                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1052         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1053         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1054         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1055         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1056         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1057         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1058         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1059         WREG32(VM_CONTEXT0_CNTL, 0);
1060         WREG32(VM_CONTEXT1_CNTL, 0);
1061 }
1062
1063 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
1064 {
1065         save->vga_control[0] = RREG32(D1VGA_CONTROL);
1066         save->vga_control[1] = RREG32(D2VGA_CONTROL);
1067         save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
1068         save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
1069         save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
1070         save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
1071         if (rdev->num_crtc >= 4) {
1072                 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
1073                 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
1074                 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
1075                 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
1076         }
1077         if (rdev->num_crtc >= 6) {
1078                 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
1079                 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
1080                 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
1081                 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
1082         }
1083
1084         /* Stop all video */
1085         WREG32(VGA_RENDER_CONTROL, 0);
1086         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1087         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1088         if (rdev->num_crtc >= 4) {
1089                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1090                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1091         }
1092         if (rdev->num_crtc >= 6) {
1093                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1094                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1095         }
1096         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1097         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1098         if (rdev->num_crtc >= 4) {
1099                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1100                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1101         }
1102         if (rdev->num_crtc >= 6) {
1103                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1104                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1105         }
1106         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1107         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1108         if (rdev->num_crtc >= 4) {
1109                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1110                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1111         }
1112         if (rdev->num_crtc >= 6) {
1113                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1114                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1115         }
1116
1117         WREG32(D1VGA_CONTROL, 0);
1118         WREG32(D2VGA_CONTROL, 0);
1119         if (rdev->num_crtc >= 4) {
1120                 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1121                 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1122         }
1123         if (rdev->num_crtc >= 6) {
1124                 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1125                 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1126         }
1127 }
1128
1129 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
1130 {
1131         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1132                upper_32_bits(rdev->mc.vram_start));
1133         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
1134                upper_32_bits(rdev->mc.vram_start));
1135         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1136                (u32)rdev->mc.vram_start);
1137         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
1138                (u32)rdev->mc.vram_start);
1139
1140         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1141                upper_32_bits(rdev->mc.vram_start));
1142         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
1143                upper_32_bits(rdev->mc.vram_start));
1144         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1145                (u32)rdev->mc.vram_start);
1146         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
1147                (u32)rdev->mc.vram_start);
1148
1149         if (rdev->num_crtc >= 4) {
1150                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1151                        upper_32_bits(rdev->mc.vram_start));
1152                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
1153                        upper_32_bits(rdev->mc.vram_start));
1154                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1155                        (u32)rdev->mc.vram_start);
1156                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
1157                        (u32)rdev->mc.vram_start);
1158
1159                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1160                        upper_32_bits(rdev->mc.vram_start));
1161                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
1162                        upper_32_bits(rdev->mc.vram_start));
1163                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1164                        (u32)rdev->mc.vram_start);
1165                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
1166                        (u32)rdev->mc.vram_start);
1167         }
1168         if (rdev->num_crtc >= 6) {
1169                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1170                        upper_32_bits(rdev->mc.vram_start));
1171                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
1172                        upper_32_bits(rdev->mc.vram_start));
1173                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1174                        (u32)rdev->mc.vram_start);
1175                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
1176                        (u32)rdev->mc.vram_start);
1177
1178                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1179                        upper_32_bits(rdev->mc.vram_start));
1180                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
1181                        upper_32_bits(rdev->mc.vram_start));
1182                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1183                        (u32)rdev->mc.vram_start);
1184                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1185                        (u32)rdev->mc.vram_start);
1186         }
1187
1188         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1189         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1190         /* Unlock host access */
1191         WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1192         mdelay(1);
1193         /* Restore video state */
1194         WREG32(D1VGA_CONTROL, save->vga_control[0]);
1195         WREG32(D2VGA_CONTROL, save->vga_control[1]);
1196         if (rdev->num_crtc >= 4) {
1197                 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
1198                 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
1199         }
1200         if (rdev->num_crtc >= 6) {
1201                 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
1202                 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
1203         }
1204         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1205         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1206         if (rdev->num_crtc >= 4) {
1207                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1208                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1209         }
1210         if (rdev->num_crtc >= 6) {
1211                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1212                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1213         }
1214         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1215         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
1216         if (rdev->num_crtc >= 4) {
1217                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1218                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
1219         }
1220         if (rdev->num_crtc >= 6) {
1221                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1222                 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1223         }
1224         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1225         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1226         if (rdev->num_crtc >= 4) {
1227                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1228                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1229         }
1230         if (rdev->num_crtc >= 6) {
1231                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1232                 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1233         }
1234         WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1235 }
1236
1237 void evergreen_mc_program(struct radeon_device *rdev)
1238 {
1239         struct evergreen_mc_save save;
1240         u32 tmp;
1241         int i, j;
1242
1243         /* Initialize HDP */
1244         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1245                 WREG32((0x2c14 + j), 0x00000000);
1246                 WREG32((0x2c18 + j), 0x00000000);
1247                 WREG32((0x2c1c + j), 0x00000000);
1248                 WREG32((0x2c20 + j), 0x00000000);
1249                 WREG32((0x2c24 + j), 0x00000000);
1250         }
1251         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1252
1253         evergreen_mc_stop(rdev, &save);
1254         if (evergreen_mc_wait_for_idle(rdev)) {
1255                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1256         }
1257         /* Lockout access through VGA aperture*/
1258         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1259         /* Update configuration */
1260         if (rdev->flags & RADEON_IS_AGP) {
1261                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1262                         /* VRAM before AGP */
1263                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1264                                 rdev->mc.vram_start >> 12);
1265                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1266                                 rdev->mc.gtt_end >> 12);
1267                 } else {
1268                         /* VRAM after AGP */
1269                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1270                                 rdev->mc.gtt_start >> 12);
1271                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1272                                 rdev->mc.vram_end >> 12);
1273                 }
1274         } else {
1275                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1276                         rdev->mc.vram_start >> 12);
1277                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1278                         rdev->mc.vram_end >> 12);
1279         }
1280         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1281         if (rdev->flags & RADEON_IS_IGP) {
1282                 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1283                 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1284                 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1285                 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1286         }
1287         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1288         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1289         WREG32(MC_VM_FB_LOCATION, tmp);
1290         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1291         WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
1292         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1293         if (rdev->flags & RADEON_IS_AGP) {
1294                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1295                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1296                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1297         } else {
1298                 WREG32(MC_VM_AGP_BASE, 0);
1299                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1300                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1301         }
1302         if (evergreen_mc_wait_for_idle(rdev)) {
1303                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1304         }
1305         evergreen_mc_resume(rdev, &save);
1306         /* we need to own VRAM, so turn off the VGA renderer here
1307          * to stop it overwriting our objects */
1308         rv515_vga_render_disable(rdev);
1309 }
1310
1311 /*
1312  * CP.
1313  */
1314 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1315 {
1316         struct radeon_ring *ring = &rdev->ring[ib->fence->ring];
1317
1318         /* set to DX10/11 mode */
1319         radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1320         radeon_ring_write(ring, 1);
1321         /* FIXME: implement */
1322         radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1323         radeon_ring_write(ring,
1324 #ifdef __BIG_ENDIAN
1325                           (2 << 0) |
1326 #endif
1327                           (ib->gpu_addr & 0xFFFFFFFC));
1328         radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
1329         radeon_ring_write(ring, ib->length_dw);
1330 }
1331
1332
1333 static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1334 {
1335         const __be32 *fw_data;
1336         int i;
1337
1338         if (!rdev->me_fw || !rdev->pfp_fw)
1339                 return -EINVAL;
1340
1341         r700_cp_stop(rdev);
1342         WREG32(CP_RB_CNTL,
1343 #ifdef __BIG_ENDIAN
1344                BUF_SWAP_32BIT |
1345 #endif
1346                RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1347
1348         fw_data = (const __be32 *)rdev->pfp_fw->data;
1349         WREG32(CP_PFP_UCODE_ADDR, 0);
1350         for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1351                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1352         WREG32(CP_PFP_UCODE_ADDR, 0);
1353
1354         fw_data = (const __be32 *)rdev->me_fw->data;
1355         WREG32(CP_ME_RAM_WADDR, 0);
1356         for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1357                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1358
1359         WREG32(CP_PFP_UCODE_ADDR, 0);
1360         WREG32(CP_ME_RAM_WADDR, 0);
1361         WREG32(CP_ME_RAM_RADDR, 0);
1362         return 0;
1363 }
1364
1365 static int evergreen_cp_start(struct radeon_device *rdev)
1366 {
1367         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1368         int r, i;
1369         uint32_t cp_me;
1370
1371         r = radeon_ring_lock(rdev, ring, 7);
1372         if (r) {
1373                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1374                 return r;
1375         }
1376         radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1377         radeon_ring_write(ring, 0x1);
1378         radeon_ring_write(ring, 0x0);
1379         radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1);
1380         radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1381         radeon_ring_write(ring, 0);
1382         radeon_ring_write(ring, 0);
1383         radeon_ring_unlock_commit(rdev, ring);
1384
1385         cp_me = 0xff;
1386         WREG32(CP_ME_CNTL, cp_me);
1387
1388         r = radeon_ring_lock(rdev, ring, evergreen_default_size + 19);
1389         if (r) {
1390                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1391                 return r;
1392         }
1393
1394         /* setup clear context state */
1395         radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1396         radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1397
1398         for (i = 0; i < evergreen_default_size; i++)
1399                 radeon_ring_write(ring, evergreen_default_state[i]);
1400
1401         radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1402         radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1403
1404         /* set clear context state */
1405         radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1406         radeon_ring_write(ring, 0);
1407
1408         /* SQ_VTX_BASE_VTX_LOC */
1409         radeon_ring_write(ring, 0xc0026f00);
1410         radeon_ring_write(ring, 0x00000000);
1411         radeon_ring_write(ring, 0x00000000);
1412         radeon_ring_write(ring, 0x00000000);
1413
1414         /* Clear consts */
1415         radeon_ring_write(ring, 0xc0036f00);
1416         radeon_ring_write(ring, 0x00000bc4);
1417         radeon_ring_write(ring, 0xffffffff);
1418         radeon_ring_write(ring, 0xffffffff);
1419         radeon_ring_write(ring, 0xffffffff);
1420
1421         radeon_ring_write(ring, 0xc0026900);
1422         radeon_ring_write(ring, 0x00000316);
1423         radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1424         radeon_ring_write(ring, 0x00000010); /*  */
1425
1426         radeon_ring_unlock_commit(rdev, ring);
1427
1428         return 0;
1429 }
1430
1431 int evergreen_cp_resume(struct radeon_device *rdev)
1432 {
1433         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1434         u32 tmp;
1435         u32 rb_bufsz;
1436         int r;
1437
1438         /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1439         WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1440                                  SOFT_RESET_PA |
1441                                  SOFT_RESET_SH |
1442                                  SOFT_RESET_VGT |
1443                                  SOFT_RESET_SPI |
1444                                  SOFT_RESET_SX));
1445         RREG32(GRBM_SOFT_RESET);
1446         mdelay(15);
1447         WREG32(GRBM_SOFT_RESET, 0);
1448         RREG32(GRBM_SOFT_RESET);
1449
1450         /* Set ring buffer size */
1451         rb_bufsz = drm_order(ring->ring_size / 8);
1452         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1453 #ifdef __BIG_ENDIAN
1454         tmp |= BUF_SWAP_32BIT;
1455 #endif
1456         WREG32(CP_RB_CNTL, tmp);
1457         WREG32(CP_SEM_WAIT_TIMER, 0x0);
1458
1459         /* Set the write pointer delay */
1460         WREG32(CP_RB_WPTR_DELAY, 0);
1461
1462         /* Initialize the ring buffer's read and write pointers */
1463         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1464         WREG32(CP_RB_RPTR_WR, 0);
1465         ring->wptr = 0;
1466         WREG32(CP_RB_WPTR, ring->wptr);
1467
1468         /* set the wb address wether it's enabled or not */
1469         WREG32(CP_RB_RPTR_ADDR,
1470                ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
1471         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1472         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1473
1474         if (rdev->wb.enabled)
1475                 WREG32(SCRATCH_UMSK, 0xff);
1476         else {
1477                 tmp |= RB_NO_UPDATE;
1478                 WREG32(SCRATCH_UMSK, 0);
1479         }
1480
1481         mdelay(1);
1482         WREG32(CP_RB_CNTL, tmp);
1483
1484         WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
1485         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1486
1487         ring->rptr = RREG32(CP_RB_RPTR);
1488
1489         evergreen_cp_start(rdev);
1490         ring->ready = true;
1491         r = radeon_ring_test(rdev, ring);
1492         if (r) {
1493                 ring->ready = false;
1494                 return r;
1495         }
1496         return 0;
1497 }
1498
1499 /*
1500  * Core functions
1501  */
1502 static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1503                                                   u32 num_tile_pipes,
1504                                                   u32 num_backends,
1505                                                   u32 backend_disable_mask)
1506 {
1507         u32 backend_map = 0;
1508         u32 enabled_backends_mask = 0;
1509         u32 enabled_backends_count = 0;
1510         u32 cur_pipe;
1511         u32 swizzle_pipe[EVERGREEN_MAX_PIPES];
1512         u32 cur_backend = 0;
1513         u32 i;
1514         bool force_no_swizzle;
1515
1516         if (num_tile_pipes > EVERGREEN_MAX_PIPES)
1517                 num_tile_pipes = EVERGREEN_MAX_PIPES;
1518         if (num_tile_pipes < 1)
1519                 num_tile_pipes = 1;
1520         if (num_backends > EVERGREEN_MAX_BACKENDS)
1521                 num_backends = EVERGREEN_MAX_BACKENDS;
1522         if (num_backends < 1)
1523                 num_backends = 1;
1524
1525         for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1526                 if (((backend_disable_mask >> i) & 1) == 0) {
1527                         enabled_backends_mask |= (1 << i);
1528                         ++enabled_backends_count;
1529                 }
1530                 if (enabled_backends_count == num_backends)
1531                         break;
1532         }
1533
1534         if (enabled_backends_count == 0) {
1535                 enabled_backends_mask = 1;
1536                 enabled_backends_count = 1;
1537         }
1538
1539         if (enabled_backends_count != num_backends)
1540                 num_backends = enabled_backends_count;
1541
1542         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES);
1543         switch (rdev->family) {
1544         case CHIP_CEDAR:
1545         case CHIP_REDWOOD:
1546         case CHIP_PALM:
1547         case CHIP_SUMO:
1548         case CHIP_SUMO2:
1549         case CHIP_TURKS:
1550         case CHIP_CAICOS:
1551                 force_no_swizzle = false;
1552                 break;
1553         case CHIP_CYPRESS:
1554         case CHIP_HEMLOCK:
1555         case CHIP_JUNIPER:
1556         case CHIP_BARTS:
1557         default:
1558                 force_no_swizzle = true;
1559                 break;
1560         }
1561         if (force_no_swizzle) {
1562                 bool last_backend_enabled = false;
1563
1564                 force_no_swizzle = false;
1565                 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1566                         if (((enabled_backends_mask >> i) & 1) == 1) {
1567                                 if (last_backend_enabled)
1568                                         force_no_swizzle = true;
1569                                 last_backend_enabled = true;
1570                         } else
1571                                 last_backend_enabled = false;
1572                 }
1573         }
1574
1575         switch (num_tile_pipes) {
1576         case 1:
1577         case 3:
1578         case 5:
1579         case 7:
1580                 DRM_ERROR("odd number of pipes!\n");
1581                 break;
1582         case 2:
1583                 swizzle_pipe[0] = 0;
1584                 swizzle_pipe[1] = 1;
1585                 break;
1586         case 4:
1587                 if (force_no_swizzle) {
1588                         swizzle_pipe[0] = 0;
1589                         swizzle_pipe[1] = 1;
1590                         swizzle_pipe[2] = 2;
1591                         swizzle_pipe[3] = 3;
1592                 } else {
1593                         swizzle_pipe[0] = 0;
1594                         swizzle_pipe[1] = 2;
1595                         swizzle_pipe[2] = 1;
1596                         swizzle_pipe[3] = 3;
1597                 }
1598                 break;
1599         case 6:
1600                 if (force_no_swizzle) {
1601                         swizzle_pipe[0] = 0;
1602                         swizzle_pipe[1] = 1;
1603                         swizzle_pipe[2] = 2;
1604                         swizzle_pipe[3] = 3;
1605                         swizzle_pipe[4] = 4;
1606                         swizzle_pipe[5] = 5;
1607                 } else {
1608                         swizzle_pipe[0] = 0;
1609                         swizzle_pipe[1] = 2;
1610                         swizzle_pipe[2] = 4;
1611                         swizzle_pipe[3] = 1;
1612                         swizzle_pipe[4] = 3;
1613                         swizzle_pipe[5] = 5;
1614                 }
1615                 break;
1616         case 8:
1617                 if (force_no_swizzle) {
1618                         swizzle_pipe[0] = 0;
1619                         swizzle_pipe[1] = 1;
1620                         swizzle_pipe[2] = 2;
1621                         swizzle_pipe[3] = 3;
1622                         swizzle_pipe[4] = 4;
1623                         swizzle_pipe[5] = 5;
1624                         swizzle_pipe[6] = 6;
1625                         swizzle_pipe[7] = 7;
1626                 } else {
1627                         swizzle_pipe[0] = 0;
1628                         swizzle_pipe[1] = 2;
1629                         swizzle_pipe[2] = 4;
1630                         swizzle_pipe[3] = 6;
1631                         swizzle_pipe[4] = 1;
1632                         swizzle_pipe[5] = 3;
1633                         swizzle_pipe[6] = 5;
1634                         swizzle_pipe[7] = 7;
1635                 }
1636                 break;
1637         }
1638
1639         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1640                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1641                         cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1642
1643                 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
1644
1645                 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1646         }
1647
1648         return backend_map;
1649 }
1650
1651 static void evergreen_gpu_init(struct radeon_device *rdev)
1652 {
1653         u32 cc_rb_backend_disable = 0;
1654         u32 cc_gc_shader_pipe_config;
1655         u32 gb_addr_config = 0;
1656         u32 mc_shared_chmap, mc_arb_ramcfg;
1657         u32 gb_backend_map;
1658         u32 grbm_gfx_index;
1659         u32 sx_debug_1;
1660         u32 smx_dc_ctl0;
1661         u32 sq_config;
1662         u32 sq_lds_resource_mgmt;
1663         u32 sq_gpr_resource_mgmt_1;
1664         u32 sq_gpr_resource_mgmt_2;
1665         u32 sq_gpr_resource_mgmt_3;
1666         u32 sq_thread_resource_mgmt;
1667         u32 sq_thread_resource_mgmt_2;
1668         u32 sq_stack_resource_mgmt_1;
1669         u32 sq_stack_resource_mgmt_2;
1670         u32 sq_stack_resource_mgmt_3;
1671         u32 vgt_cache_invalidation;
1672         u32 hdp_host_path_cntl, tmp;
1673         int i, j, num_shader_engines, ps_thread_count;
1674
1675         switch (rdev->family) {
1676         case CHIP_CYPRESS:
1677         case CHIP_HEMLOCK:
1678                 rdev->config.evergreen.num_ses = 2;
1679                 rdev->config.evergreen.max_pipes = 4;
1680                 rdev->config.evergreen.max_tile_pipes = 8;
1681                 rdev->config.evergreen.max_simds = 10;
1682                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1683                 rdev->config.evergreen.max_gprs = 256;
1684                 rdev->config.evergreen.max_threads = 248;
1685                 rdev->config.evergreen.max_gs_threads = 32;
1686                 rdev->config.evergreen.max_stack_entries = 512;
1687                 rdev->config.evergreen.sx_num_of_sets = 4;
1688                 rdev->config.evergreen.sx_max_export_size = 256;
1689                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1690                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1691                 rdev->config.evergreen.max_hw_contexts = 8;
1692                 rdev->config.evergreen.sq_num_cf_insts = 2;
1693
1694                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1695                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1696                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1697                 break;
1698         case CHIP_JUNIPER:
1699                 rdev->config.evergreen.num_ses = 1;
1700                 rdev->config.evergreen.max_pipes = 4;
1701                 rdev->config.evergreen.max_tile_pipes = 4;
1702                 rdev->config.evergreen.max_simds = 10;
1703                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1704                 rdev->config.evergreen.max_gprs = 256;
1705                 rdev->config.evergreen.max_threads = 248;
1706                 rdev->config.evergreen.max_gs_threads = 32;
1707                 rdev->config.evergreen.max_stack_entries = 512;
1708                 rdev->config.evergreen.sx_num_of_sets = 4;
1709                 rdev->config.evergreen.sx_max_export_size = 256;
1710                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1711                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1712                 rdev->config.evergreen.max_hw_contexts = 8;
1713                 rdev->config.evergreen.sq_num_cf_insts = 2;
1714
1715                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1716                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1717                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1718                 break;
1719         case CHIP_REDWOOD:
1720                 rdev->config.evergreen.num_ses = 1;
1721                 rdev->config.evergreen.max_pipes = 4;
1722                 rdev->config.evergreen.max_tile_pipes = 4;
1723                 rdev->config.evergreen.max_simds = 5;
1724                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1725                 rdev->config.evergreen.max_gprs = 256;
1726                 rdev->config.evergreen.max_threads = 248;
1727                 rdev->config.evergreen.max_gs_threads = 32;
1728                 rdev->config.evergreen.max_stack_entries = 256;
1729                 rdev->config.evergreen.sx_num_of_sets = 4;
1730                 rdev->config.evergreen.sx_max_export_size = 256;
1731                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1732                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1733                 rdev->config.evergreen.max_hw_contexts = 8;
1734                 rdev->config.evergreen.sq_num_cf_insts = 2;
1735
1736                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1737                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1738                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1739                 break;
1740         case CHIP_CEDAR:
1741         default:
1742                 rdev->config.evergreen.num_ses = 1;
1743                 rdev->config.evergreen.max_pipes = 2;
1744                 rdev->config.evergreen.max_tile_pipes = 2;
1745                 rdev->config.evergreen.max_simds = 2;
1746                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1747                 rdev->config.evergreen.max_gprs = 256;
1748                 rdev->config.evergreen.max_threads = 192;
1749                 rdev->config.evergreen.max_gs_threads = 16;
1750                 rdev->config.evergreen.max_stack_entries = 256;
1751                 rdev->config.evergreen.sx_num_of_sets = 4;
1752                 rdev->config.evergreen.sx_max_export_size = 128;
1753                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1754                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1755                 rdev->config.evergreen.max_hw_contexts = 4;
1756                 rdev->config.evergreen.sq_num_cf_insts = 1;
1757
1758                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1759                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1760                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1761                 break;
1762         case CHIP_PALM:
1763                 rdev->config.evergreen.num_ses = 1;
1764                 rdev->config.evergreen.max_pipes = 2;
1765                 rdev->config.evergreen.max_tile_pipes = 2;
1766                 rdev->config.evergreen.max_simds = 2;
1767                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1768                 rdev->config.evergreen.max_gprs = 256;
1769                 rdev->config.evergreen.max_threads = 192;
1770                 rdev->config.evergreen.max_gs_threads = 16;
1771                 rdev->config.evergreen.max_stack_entries = 256;
1772                 rdev->config.evergreen.sx_num_of_sets = 4;
1773                 rdev->config.evergreen.sx_max_export_size = 128;
1774                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1775                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1776                 rdev->config.evergreen.max_hw_contexts = 4;
1777                 rdev->config.evergreen.sq_num_cf_insts = 1;
1778
1779                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1780                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1781                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1782                 break;
1783         case CHIP_SUMO:
1784                 rdev->config.evergreen.num_ses = 1;
1785                 rdev->config.evergreen.max_pipes = 4;
1786                 rdev->config.evergreen.max_tile_pipes = 2;
1787                 if (rdev->pdev->device == 0x9648)
1788                         rdev->config.evergreen.max_simds = 3;
1789                 else if ((rdev->pdev->device == 0x9647) ||
1790                          (rdev->pdev->device == 0x964a))
1791                         rdev->config.evergreen.max_simds = 4;
1792                 else
1793                         rdev->config.evergreen.max_simds = 5;
1794                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1795                 rdev->config.evergreen.max_gprs = 256;
1796                 rdev->config.evergreen.max_threads = 248;
1797                 rdev->config.evergreen.max_gs_threads = 32;
1798                 rdev->config.evergreen.max_stack_entries = 256;
1799                 rdev->config.evergreen.sx_num_of_sets = 4;
1800                 rdev->config.evergreen.sx_max_export_size = 256;
1801                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1802                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1803                 rdev->config.evergreen.max_hw_contexts = 8;
1804                 rdev->config.evergreen.sq_num_cf_insts = 2;
1805
1806                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1807                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1808                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1809                 break;
1810         case CHIP_SUMO2:
1811                 rdev->config.evergreen.num_ses = 1;
1812                 rdev->config.evergreen.max_pipes = 4;
1813                 rdev->config.evergreen.max_tile_pipes = 4;
1814                 rdev->config.evergreen.max_simds = 2;
1815                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1816                 rdev->config.evergreen.max_gprs = 256;
1817                 rdev->config.evergreen.max_threads = 248;
1818                 rdev->config.evergreen.max_gs_threads = 32;
1819                 rdev->config.evergreen.max_stack_entries = 512;
1820                 rdev->config.evergreen.sx_num_of_sets = 4;
1821                 rdev->config.evergreen.sx_max_export_size = 256;
1822                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1823                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1824                 rdev->config.evergreen.max_hw_contexts = 8;
1825                 rdev->config.evergreen.sq_num_cf_insts = 2;
1826
1827                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1828                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1829                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1830                 break;
1831         case CHIP_BARTS:
1832                 rdev->config.evergreen.num_ses = 2;
1833                 rdev->config.evergreen.max_pipes = 4;
1834                 rdev->config.evergreen.max_tile_pipes = 8;
1835                 rdev->config.evergreen.max_simds = 7;
1836                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1837                 rdev->config.evergreen.max_gprs = 256;
1838                 rdev->config.evergreen.max_threads = 248;
1839                 rdev->config.evergreen.max_gs_threads = 32;
1840                 rdev->config.evergreen.max_stack_entries = 512;
1841                 rdev->config.evergreen.sx_num_of_sets = 4;
1842                 rdev->config.evergreen.sx_max_export_size = 256;
1843                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1844                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1845                 rdev->config.evergreen.max_hw_contexts = 8;
1846                 rdev->config.evergreen.sq_num_cf_insts = 2;
1847
1848                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1849                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1850                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1851                 break;
1852         case CHIP_TURKS:
1853                 rdev->config.evergreen.num_ses = 1;
1854                 rdev->config.evergreen.max_pipes = 4;
1855                 rdev->config.evergreen.max_tile_pipes = 4;
1856                 rdev->config.evergreen.max_simds = 6;
1857                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1858                 rdev->config.evergreen.max_gprs = 256;
1859                 rdev->config.evergreen.max_threads = 248;
1860                 rdev->config.evergreen.max_gs_threads = 32;
1861                 rdev->config.evergreen.max_stack_entries = 256;
1862                 rdev->config.evergreen.sx_num_of_sets = 4;
1863                 rdev->config.evergreen.sx_max_export_size = 256;
1864                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1865                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1866                 rdev->config.evergreen.max_hw_contexts = 8;
1867                 rdev->config.evergreen.sq_num_cf_insts = 2;
1868
1869                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1870                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1871                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1872                 break;
1873         case CHIP_CAICOS:
1874                 rdev->config.evergreen.num_ses = 1;
1875                 rdev->config.evergreen.max_pipes = 4;
1876                 rdev->config.evergreen.max_tile_pipes = 2;
1877                 rdev->config.evergreen.max_simds = 2;
1878                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1879                 rdev->config.evergreen.max_gprs = 256;
1880                 rdev->config.evergreen.max_threads = 192;
1881                 rdev->config.evergreen.max_gs_threads = 16;
1882                 rdev->config.evergreen.max_stack_entries = 256;
1883                 rdev->config.evergreen.sx_num_of_sets = 4;
1884                 rdev->config.evergreen.sx_max_export_size = 128;
1885                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1886                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1887                 rdev->config.evergreen.max_hw_contexts = 4;
1888                 rdev->config.evergreen.sq_num_cf_insts = 1;
1889
1890                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1891                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1892                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1893                 break;
1894         }
1895
1896         /* Initialize HDP */
1897         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1898                 WREG32((0x2c14 + j), 0x00000000);
1899                 WREG32((0x2c18 + j), 0x00000000);
1900                 WREG32((0x2c1c + j), 0x00000000);
1901                 WREG32((0x2c20 + j), 0x00000000);
1902                 WREG32((0x2c24 + j), 0x00000000);
1903         }
1904
1905         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1906
1907         evergreen_fix_pci_max_read_req_size(rdev);
1908
1909         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
1910
1911         cc_gc_shader_pipe_config |=
1912                 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
1913                                   & EVERGREEN_MAX_PIPES_MASK);
1914         cc_gc_shader_pipe_config |=
1915                 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
1916                                & EVERGREEN_MAX_SIMDS_MASK);
1917
1918         cc_rb_backend_disable =
1919                 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
1920                                 & EVERGREEN_MAX_BACKENDS_MASK);
1921
1922
1923         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1924         if (rdev->flags & RADEON_IS_IGP)
1925                 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
1926         else
1927                 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1928
1929         switch (rdev->config.evergreen.max_tile_pipes) {
1930         case 1:
1931         default:
1932                 gb_addr_config |= NUM_PIPES(0);
1933                 break;
1934         case 2:
1935                 gb_addr_config |= NUM_PIPES(1);
1936                 break;
1937         case 4:
1938                 gb_addr_config |= NUM_PIPES(2);
1939                 break;
1940         case 8:
1941                 gb_addr_config |= NUM_PIPES(3);
1942                 break;
1943         }
1944
1945         gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1946         gb_addr_config |= BANK_INTERLEAVE_SIZE(0);
1947         gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1);
1948         gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1);
1949         gb_addr_config |= NUM_GPUS(0); /* Hemlock? */
1950         gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
1951
1952         if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2)
1953                 gb_addr_config |= ROW_SIZE(2);
1954         else
1955                 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
1956
1957         if (rdev->ddev->pdev->device == 0x689e) {
1958                 u32 efuse_straps_4;
1959                 u32 efuse_straps_3;
1960                 u8 efuse_box_bit_131_124;
1961
1962                 WREG32(RCU_IND_INDEX, 0x204);
1963                 efuse_straps_4 = RREG32(RCU_IND_DATA);
1964                 WREG32(RCU_IND_INDEX, 0x203);
1965                 efuse_straps_3 = RREG32(RCU_IND_DATA);
1966                 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
1967
1968                 switch(efuse_box_bit_131_124) {
1969                 case 0x00:
1970                         gb_backend_map = 0x76543210;
1971                         break;
1972                 case 0x55:
1973                         gb_backend_map = 0x77553311;
1974                         break;
1975                 case 0x56:
1976                         gb_backend_map = 0x77553300;
1977                         break;
1978                 case 0x59:
1979                         gb_backend_map = 0x77552211;
1980                         break;
1981                 case 0x66:
1982                         gb_backend_map = 0x77443300;
1983                         break;
1984                 case 0x99:
1985                         gb_backend_map = 0x66552211;
1986                         break;
1987                 case 0x5a:
1988                         gb_backend_map = 0x77552200;
1989                         break;
1990                 case 0xaa:
1991                         gb_backend_map = 0x66442200;
1992                         break;
1993                 case 0x95:
1994                         gb_backend_map = 0x66553311;
1995                         break;
1996                 default:
1997                         DRM_ERROR("bad backend map, using default\n");
1998                         gb_backend_map =
1999                                 evergreen_get_tile_pipe_to_backend_map(rdev,
2000                                                                        rdev->config.evergreen.max_tile_pipes,
2001                                                                        rdev->config.evergreen.max_backends,
2002                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
2003                                                                    rdev->config.evergreen.max_backends) &
2004                                                                         EVERGREEN_MAX_BACKENDS_MASK));
2005                         break;
2006                 }
2007         } else if (rdev->ddev->pdev->device == 0x68b9) {
2008                 u32 efuse_straps_3;
2009                 u8 efuse_box_bit_127_124;
2010
2011                 WREG32(RCU_IND_INDEX, 0x203);
2012                 efuse_straps_3 = RREG32(RCU_IND_DATA);
2013                 efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28);
2014
2015                 switch(efuse_box_bit_127_124) {
2016                 case 0x0:
2017                         gb_backend_map = 0x00003210;
2018                         break;
2019                 case 0x5:
2020                 case 0x6:
2021                 case 0x9:
2022                 case 0xa:
2023                         gb_backend_map = 0x00003311;
2024                         break;
2025                 default:
2026                         DRM_ERROR("bad backend map, using default\n");
2027                         gb_backend_map =
2028                                 evergreen_get_tile_pipe_to_backend_map(rdev,
2029                                                                        rdev->config.evergreen.max_tile_pipes,
2030                                                                        rdev->config.evergreen.max_backends,
2031                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
2032                                                                    rdev->config.evergreen.max_backends) &
2033                                                                         EVERGREEN_MAX_BACKENDS_MASK));
2034                         break;
2035                 }
2036         } else {
2037                 switch (rdev->family) {
2038                 case CHIP_CYPRESS:
2039                 case CHIP_HEMLOCK:
2040                 case CHIP_BARTS:
2041                         gb_backend_map = 0x66442200;
2042                         break;
2043                 case CHIP_JUNIPER:
2044                         gb_backend_map = 0x00002200;
2045                         break;
2046                 default:
2047                         gb_backend_map =
2048                                 evergreen_get_tile_pipe_to_backend_map(rdev,
2049                                                                        rdev->config.evergreen.max_tile_pipes,
2050                                                                        rdev->config.evergreen.max_backends,
2051                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
2052                                                                          rdev->config.evergreen.max_backends) &
2053                                                                         EVERGREEN_MAX_BACKENDS_MASK));
2054                 }
2055         }
2056
2057         /* setup tiling info dword.  gb_addr_config is not adequate since it does
2058          * not have bank info, so create a custom tiling dword.
2059          * bits 3:0   num_pipes
2060          * bits 7:4   num_banks
2061          * bits 11:8  group_size
2062          * bits 15:12 row_size
2063          */
2064         rdev->config.evergreen.tile_config = 0;
2065         switch (rdev->config.evergreen.max_tile_pipes) {
2066         case 1:
2067         default:
2068                 rdev->config.evergreen.tile_config |= (0 << 0);
2069                 break;
2070         case 2:
2071                 rdev->config.evergreen.tile_config |= (1 << 0);
2072                 break;
2073         case 4:
2074                 rdev->config.evergreen.tile_config |= (2 << 0);
2075                 break;
2076         case 8:
2077                 rdev->config.evergreen.tile_config |= (3 << 0);
2078                 break;
2079         }
2080         /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
2081         if (rdev->flags & RADEON_IS_IGP)
2082                 rdev->config.evergreen.tile_config |= 1 << 4;
2083         else
2084                 rdev->config.evergreen.tile_config |=
2085                         ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) << 4;
2086         rdev->config.evergreen.tile_config |=
2087                 ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
2088         rdev->config.evergreen.tile_config |=
2089                 ((gb_addr_config & 0x30000000) >> 28) << 12;
2090
2091         rdev->config.evergreen.backend_map = gb_backend_map;
2092         WREG32(GB_BACKEND_MAP, gb_backend_map);
2093         WREG32(GB_ADDR_CONFIG, gb_addr_config);
2094         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
2095         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
2096
2097         num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
2098         grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
2099
2100         for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
2101                 u32 rb = cc_rb_backend_disable | (0xf0 << 16);
2102                 u32 sp = cc_gc_shader_pipe_config;
2103                 u32 gfx = grbm_gfx_index | SE_INDEX(i);
2104
2105                 if (i == num_shader_engines) {
2106                         rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
2107                         sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
2108                 }
2109
2110                 WREG32(GRBM_GFX_INDEX, gfx);
2111                 WREG32(RLC_GFX_INDEX, gfx);
2112
2113                 WREG32(CC_RB_BACKEND_DISABLE, rb);
2114                 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
2115                 WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
2116                 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
2117         }
2118
2119         grbm_gfx_index |= SE_BROADCAST_WRITES;
2120         WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
2121         WREG32(RLC_GFX_INDEX, grbm_gfx_index);
2122
2123         WREG32(CGTS_SYS_TCC_DISABLE, 0);
2124         WREG32(CGTS_TCC_DISABLE, 0);
2125         WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
2126         WREG32(CGTS_USER_TCC_DISABLE, 0);
2127
2128         /* set HW defaults for 3D engine */
2129         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
2130                                      ROQ_IB2_START(0x2b)));
2131
2132         WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
2133
2134         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
2135                              SYNC_GRADIENT |
2136                              SYNC_WALKER |
2137                              SYNC_ALIGNER));
2138
2139         sx_debug_1 = RREG32(SX_DEBUG_1);
2140         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
2141         WREG32(SX_DEBUG_1, sx_debug_1);
2142
2143
2144         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
2145         smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
2146         smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
2147         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
2148
2149         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
2150                                         POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
2151                                         SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
2152
2153         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
2154                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
2155                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
2156
2157         WREG32(VGT_NUM_INSTANCES, 1);
2158         WREG32(SPI_CONFIG_CNTL, 0);
2159         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
2160         WREG32(CP_PERFMON_CNTL, 0);
2161
2162         WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
2163                                   FETCH_FIFO_HIWATER(0x4) |
2164                                   DONE_FIFO_HIWATER(0xe0) |
2165                                   ALU_UPDATE_FIFO_HIWATER(0x8)));
2166
2167         sq_config = RREG32(SQ_CONFIG);
2168         sq_config &= ~(PS_PRIO(3) |
2169                        VS_PRIO(3) |
2170                        GS_PRIO(3) |
2171                        ES_PRIO(3));
2172         sq_config |= (VC_ENABLE |
2173                       EXPORT_SRC_C |
2174                       PS_PRIO(0) |
2175                       VS_PRIO(1) |
2176                       GS_PRIO(2) |
2177                       ES_PRIO(3));
2178
2179         switch (rdev->family) {
2180         case CHIP_CEDAR:
2181         case CHIP_PALM:
2182         case CHIP_SUMO:
2183         case CHIP_SUMO2:
2184         case CHIP_CAICOS:
2185                 /* no vertex cache */
2186                 sq_config &= ~VC_ENABLE;
2187                 break;
2188         default:
2189                 break;
2190         }
2191
2192         sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
2193
2194         sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
2195         sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
2196         sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
2197         sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2198         sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2199         sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2200         sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2201
2202         switch (rdev->family) {
2203         case CHIP_CEDAR:
2204         case CHIP_PALM:
2205         case CHIP_SUMO:
2206         case CHIP_SUMO2:
2207                 ps_thread_count = 96;
2208                 break;
2209         default:
2210                 ps_thread_count = 128;
2211                 break;
2212         }
2213
2214         sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
2215         sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2216         sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2217         sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2218         sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2219         sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2220
2221         sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2222         sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2223         sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2224         sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2225         sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2226         sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2227
2228         WREG32(SQ_CONFIG, sq_config);
2229         WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2230         WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2231         WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
2232         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2233         WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
2234         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2235         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2236         WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
2237         WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2238         WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
2239
2240         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
2241                                           FORCE_EOV_MAX_REZ_CNT(255)));
2242
2243         switch (rdev->family) {
2244         case CHIP_CEDAR:
2245         case CHIP_PALM:
2246         case CHIP_SUMO:
2247         case CHIP_SUMO2:
2248         case CHIP_CAICOS:
2249                 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
2250                 break;
2251         default:
2252                 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
2253                 break;
2254         }
2255         vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
2256         WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
2257
2258         WREG32(VGT_GS_VERTEX_REUSE, 16);
2259         WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
2260         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2261
2262         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
2263         WREG32(VGT_OUT_DEALLOC_CNTL, 16);
2264
2265         WREG32(CB_PERF_CTR0_SEL_0, 0);
2266         WREG32(CB_PERF_CTR0_SEL_1, 0);
2267         WREG32(CB_PERF_CTR1_SEL_0, 0);
2268         WREG32(CB_PERF_CTR1_SEL_1, 0);
2269         WREG32(CB_PERF_CTR2_SEL_0, 0);
2270         WREG32(CB_PERF_CTR2_SEL_1, 0);
2271         WREG32(CB_PERF_CTR3_SEL_0, 0);
2272         WREG32(CB_PERF_CTR3_SEL_1, 0);
2273
2274         /* clear render buffer base addresses */
2275         WREG32(CB_COLOR0_BASE, 0);
2276         WREG32(CB_COLOR1_BASE, 0);
2277         WREG32(CB_COLOR2_BASE, 0);
2278         WREG32(CB_COLOR3_BASE, 0);
2279         WREG32(CB_COLOR4_BASE, 0);
2280         WREG32(CB_COLOR5_BASE, 0);
2281         WREG32(CB_COLOR6_BASE, 0);
2282         WREG32(CB_COLOR7_BASE, 0);
2283         WREG32(CB_COLOR8_BASE, 0);
2284         WREG32(CB_COLOR9_BASE, 0);
2285         WREG32(CB_COLOR10_BASE, 0);
2286         WREG32(CB_COLOR11_BASE, 0);
2287
2288         /* set the shader const cache sizes to 0 */
2289         for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2290                 WREG32(i, 0);
2291         for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2292                 WREG32(i, 0);
2293
2294         tmp = RREG32(HDP_MISC_CNTL);
2295         tmp |= HDP_FLUSH_INVALIDATE_CACHE;
2296         WREG32(HDP_MISC_CNTL, tmp);
2297
2298         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2299         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2300
2301         WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2302
2303         udelay(50);
2304
2305 }
2306
2307 int evergreen_mc_init(struct radeon_device *rdev)
2308 {
2309         u32 tmp;
2310         int chansize, numchan;
2311
2312         /* Get VRAM informations */
2313         rdev->mc.vram_is_ddr = true;
2314         if (rdev->flags & RADEON_IS_IGP)
2315                 tmp = RREG32(FUS_MC_ARB_RAMCFG);
2316         else
2317                 tmp = RREG32(MC_ARB_RAMCFG);
2318         if (tmp & CHANSIZE_OVERRIDE) {
2319                 chansize = 16;
2320         } else if (tmp & CHANSIZE_MASK) {
2321                 chansize = 64;
2322         } else {
2323                 chansize = 32;
2324         }
2325         tmp = RREG32(MC_SHARED_CHMAP);
2326         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2327         case 0:
2328         default:
2329                 numchan = 1;
2330                 break;
2331         case 1:
2332                 numchan = 2;
2333                 break;
2334         case 2:
2335                 numchan = 4;
2336                 break;
2337         case 3:
2338                 numchan = 8;
2339                 break;
2340         }
2341         rdev->mc.vram_width = numchan * chansize;
2342         /* Could aper size report 0 ? */
2343         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2344         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2345         /* Setup GPU memory space */
2346         if (rdev->flags & RADEON_IS_IGP) {
2347                 /* size in bytes on fusion */
2348                 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2349                 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2350         } else {
2351                 /* size in MB on evergreen */
2352                 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2353                 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2354         }
2355         rdev->mc.visible_vram_size = rdev->mc.aper_size;
2356         r700_vram_gtt_location(rdev, &rdev->mc);
2357         radeon_update_bandwidth_info(rdev);
2358
2359         return 0;
2360 }
2361
2362 bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2363 {
2364         u32 srbm_status;
2365         u32 grbm_status;
2366         u32 grbm_status_se0, grbm_status_se1;
2367         struct r100_gpu_lockup *lockup = &rdev->config.evergreen.lockup;
2368         int r;
2369
2370         srbm_status = RREG32(SRBM_STATUS);
2371         grbm_status = RREG32(GRBM_STATUS);
2372         grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2373         grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2374         if (!(grbm_status & GUI_ACTIVE)) {
2375                 r100_gpu_lockup_update(lockup, ring);
2376                 return false;
2377         }
2378         /* force CP activities */
2379         r = radeon_ring_lock(rdev, ring, 2);
2380         if (!r) {
2381                 /* PACKET2 NOP */
2382                 radeon_ring_write(ring, 0x80000000);
2383                 radeon_ring_write(ring, 0x80000000);
2384                 radeon_ring_unlock_commit(rdev, ring);
2385         }
2386         ring->rptr = RREG32(CP_RB_RPTR);
2387         return r100_gpu_cp_is_lockup(rdev, lockup, ring);
2388 }
2389
2390 static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
2391 {
2392         struct evergreen_mc_save save;
2393         u32 grbm_reset = 0;
2394
2395         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2396                 return 0;
2397
2398         dev_info(rdev->dev, "GPU softreset \n");
2399         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
2400                 RREG32(GRBM_STATUS));
2401         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
2402                 RREG32(GRBM_STATUS_SE0));
2403         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
2404                 RREG32(GRBM_STATUS_SE1));
2405         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
2406                 RREG32(SRBM_STATUS));
2407         evergreen_mc_stop(rdev, &save);
2408         if (evergreen_mc_wait_for_idle(rdev)) {
2409                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2410         }
2411         /* Disable CP parsing/prefetching */
2412         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2413
2414         /* reset all the gfx blocks */
2415         grbm_reset = (SOFT_RESET_CP |
2416                       SOFT_RESET_CB |
2417                       SOFT_RESET_DB |
2418                       SOFT_RESET_PA |
2419                       SOFT_RESET_SC |
2420                       SOFT_RESET_SPI |
2421                       SOFT_RESET_SH |
2422                       SOFT_RESET_SX |
2423                       SOFT_RESET_TC |
2424                       SOFT_RESET_TA |
2425                       SOFT_RESET_VC |
2426                       SOFT_RESET_VGT);
2427
2428         dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2429         WREG32(GRBM_SOFT_RESET, grbm_reset);
2430         (void)RREG32(GRBM_SOFT_RESET);
2431         udelay(50);
2432         WREG32(GRBM_SOFT_RESET, 0);
2433         (void)RREG32(GRBM_SOFT_RESET);
2434         /* Wait a little for things to settle down */
2435         udelay(50);
2436         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
2437                 RREG32(GRBM_STATUS));
2438         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
2439                 RREG32(GRBM_STATUS_SE0));
2440         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
2441                 RREG32(GRBM_STATUS_SE1));
2442         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
2443                 RREG32(SRBM_STATUS));
2444         evergreen_mc_resume(rdev, &save);
2445         return 0;
2446 }
2447
2448 int evergreen_asic_reset(struct radeon_device *rdev)
2449 {
2450         return evergreen_gpu_soft_reset(rdev);
2451 }
2452
2453 /* Interrupts */
2454
2455 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2456 {
2457         switch (crtc) {
2458         case 0:
2459                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
2460         case 1:
2461                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
2462         case 2:
2463                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
2464         case 3:
2465                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
2466         case 4:
2467                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
2468         case 5:
2469                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
2470         default:
2471                 return 0;
2472         }
2473 }
2474
2475 void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2476 {
2477         u32 tmp;
2478
2479         if (rdev->family >= CHIP_CAYMAN) {
2480                 cayman_cp_int_cntl_setup(rdev, 0,
2481                                          CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2482                 cayman_cp_int_cntl_setup(rdev, 1, 0);
2483                 cayman_cp_int_cntl_setup(rdev, 2, 0);
2484         } else
2485                 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2486         WREG32(GRBM_INT_CNTL, 0);
2487         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2488         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2489         if (rdev->num_crtc >= 4) {
2490                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2491                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2492         }
2493         if (rdev->num_crtc >= 6) {
2494                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2495                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2496         }
2497
2498         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2499         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2500         if (rdev->num_crtc >= 4) {
2501                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2502                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2503         }
2504         if (rdev->num_crtc >= 6) {
2505                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2506                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2507         }
2508
2509         WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2510         WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2511
2512         tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2513         WREG32(DC_HPD1_INT_CONTROL, tmp);
2514         tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2515         WREG32(DC_HPD2_INT_CONTROL, tmp);
2516         tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2517         WREG32(DC_HPD3_INT_CONTROL, tmp);
2518         tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2519         WREG32(DC_HPD4_INT_CONTROL, tmp);
2520         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2521         WREG32(DC_HPD5_INT_CONTROL, tmp);
2522         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2523         WREG32(DC_HPD6_INT_CONTROL, tmp);
2524
2525 }
2526
2527 int evergreen_irq_set(struct radeon_device *rdev)
2528 {
2529         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2530         u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
2531         u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2532         u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2533         u32 grbm_int_cntl = 0;
2534         u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
2535
2536         if (!rdev->irq.installed) {
2537                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
2538                 return -EINVAL;
2539         }
2540         /* don't enable anything if the ih is disabled */
2541         if (!rdev->ih.enabled) {
2542                 r600_disable_interrupts(rdev);
2543                 /* force the active interrupt state to all disabled */
2544                 evergreen_disable_interrupt_state(rdev);
2545                 return 0;
2546         }
2547
2548         hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2549         hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2550         hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2551         hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2552         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2553         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2554
2555         if (rdev->family >= CHIP_CAYMAN) {
2556                 /* enable CP interrupts on all rings */
2557                 if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
2558                         DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2559                         cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2560                 }
2561                 if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP1_INDEX]) {
2562                         DRM_DEBUG("evergreen_irq_set: sw int cp1\n");
2563                         cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
2564                 }
2565                 if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP2_INDEX]) {
2566                         DRM_DEBUG("evergreen_irq_set: sw int cp2\n");
2567                         cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
2568                 }
2569         } else {
2570                 if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
2571                         DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2572                         cp_int_cntl |= RB_INT_ENABLE;
2573                         cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2574                 }
2575         }
2576
2577         if (rdev->irq.crtc_vblank_int[0] ||
2578             rdev->irq.pflip[0]) {
2579                 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2580                 crtc1 |= VBLANK_INT_MASK;
2581         }
2582         if (rdev->irq.crtc_vblank_int[1] ||
2583             rdev->irq.pflip[1]) {
2584                 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2585                 crtc2 |= VBLANK_INT_MASK;
2586         }
2587         if (rdev->irq.crtc_vblank_int[2] ||
2588             rdev->irq.pflip[2]) {
2589                 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2590                 crtc3 |= VBLANK_INT_MASK;
2591         }
2592         if (rdev->irq.crtc_vblank_int[3] ||
2593             rdev->irq.pflip[3]) {
2594                 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2595                 crtc4 |= VBLANK_INT_MASK;
2596         }
2597         if (rdev->irq.crtc_vblank_int[4] ||
2598             rdev->irq.pflip[4]) {
2599                 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2600                 crtc5 |= VBLANK_INT_MASK;
2601         }
2602         if (rdev->irq.crtc_vblank_int[5] ||
2603             rdev->irq.pflip[5]) {
2604                 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2605                 crtc6 |= VBLANK_INT_MASK;
2606         }
2607         if (rdev->irq.hpd[0]) {
2608                 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2609                 hpd1 |= DC_HPDx_INT_EN;
2610         }
2611         if (rdev->irq.hpd[1]) {
2612                 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2613                 hpd2 |= DC_HPDx_INT_EN;
2614         }
2615         if (rdev->irq.hpd[2]) {
2616                 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2617                 hpd3 |= DC_HPDx_INT_EN;
2618         }
2619         if (rdev->irq.hpd[3]) {
2620                 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2621                 hpd4 |= DC_HPDx_INT_EN;
2622         }
2623         if (rdev->irq.hpd[4]) {
2624                 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2625                 hpd5 |= DC_HPDx_INT_EN;
2626         }
2627         if (rdev->irq.hpd[5]) {
2628                 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2629                 hpd6 |= DC_HPDx_INT_EN;
2630         }
2631         if (rdev->irq.gui_idle) {
2632                 DRM_DEBUG("gui idle\n");
2633                 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2634         }
2635
2636         if (rdev->family >= CHIP_CAYMAN) {
2637                 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl);
2638                 cayman_cp_int_cntl_setup(rdev, 1, cp_int_cntl1);
2639                 cayman_cp_int_cntl_setup(rdev, 2, cp_int_cntl2);
2640         } else
2641                 WREG32(CP_INT_CNTL, cp_int_cntl);
2642         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
2643
2644         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2645         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2646         if (rdev->num_crtc >= 4) {
2647                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2648                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2649         }
2650         if (rdev->num_crtc >= 6) {
2651                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2652                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2653         }
2654
2655         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2656         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
2657         if (rdev->num_crtc >= 4) {
2658                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2659                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2660         }
2661         if (rdev->num_crtc >= 6) {
2662                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2663                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2664         }
2665
2666         WREG32(DC_HPD1_INT_CONTROL, hpd1);
2667         WREG32(DC_HPD2_INT_CONTROL, hpd2);
2668         WREG32(DC_HPD3_INT_CONTROL, hpd3);
2669         WREG32(DC_HPD4_INT_CONTROL, hpd4);
2670         WREG32(DC_HPD5_INT_CONTROL, hpd5);
2671         WREG32(DC_HPD6_INT_CONTROL, hpd6);
2672
2673         return 0;
2674 }
2675
2676 static void evergreen_irq_ack(struct radeon_device *rdev)
2677 {
2678         u32 tmp;
2679
2680         rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2681         rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2682         rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2683         rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2684         rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2685         rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2686         rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2687         rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2688         if (rdev->num_crtc >= 4) {
2689                 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2690                 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2691         }
2692         if (rdev->num_crtc >= 6) {
2693                 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2694                 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2695         }
2696
2697         if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2698                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2699         if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2700                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2701         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
2702                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
2703         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
2704                 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2705         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
2706                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
2707         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
2708                 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2709
2710         if (rdev->num_crtc >= 4) {
2711                 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2712                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2713                 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2714                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2715                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2716                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2717                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2718                         WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2719                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2720                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2721                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2722                         WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2723         }
2724
2725         if (rdev->num_crtc >= 6) {
2726                 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2727                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2728                 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2729                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2730                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2731                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2732                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2733                         WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2734                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2735                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2736                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2737                         WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2738         }
2739
2740         if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2741                 tmp = RREG32(DC_HPD1_INT_CONTROL);
2742                 tmp |= DC_HPDx_INT_ACK;
2743                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2744         }
2745         if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2746                 tmp = RREG32(DC_HPD2_INT_CONTROL);
2747                 tmp |= DC_HPDx_INT_ACK;
2748                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2749         }
2750         if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2751                 tmp = RREG32(DC_HPD3_INT_CONTROL);
2752                 tmp |= DC_HPDx_INT_ACK;
2753                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2754         }
2755         if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2756                 tmp = RREG32(DC_HPD4_INT_CONTROL);
2757                 tmp |= DC_HPDx_INT_ACK;
2758                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2759         }
2760         if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2761                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2762                 tmp |= DC_HPDx_INT_ACK;
2763                 WREG32(DC_HPD5_INT_CONTROL, tmp);
2764         }
2765         if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2766                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2767                 tmp |= DC_HPDx_INT_ACK;
2768                 WREG32(DC_HPD6_INT_CONTROL, tmp);
2769         }
2770 }
2771
2772 void evergreen_irq_disable(struct radeon_device *rdev)
2773 {
2774         r600_disable_interrupts(rdev);
2775         /* Wait and acknowledge irq */
2776         mdelay(1);
2777         evergreen_irq_ack(rdev);
2778         evergreen_disable_interrupt_state(rdev);
2779 }
2780
2781 void evergreen_irq_suspend(struct radeon_device *rdev)
2782 {
2783         evergreen_irq_disable(rdev);
2784         r600_rlc_stop(rdev);
2785 }
2786
2787 static u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2788 {
2789         u32 wptr, tmp;
2790
2791         if (rdev->wb.enabled)
2792                 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
2793         else
2794                 wptr = RREG32(IH_RB_WPTR);
2795
2796         if (wptr & RB_OVERFLOW) {
2797                 /* When a ring buffer overflow happen start parsing interrupt
2798                  * from the last not overwritten vector (wptr + 16). Hopefully
2799                  * this should allow us to catchup.
2800                  */
2801                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2802                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2803                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2804                 tmp = RREG32(IH_RB_CNTL);
2805                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2806                 WREG32(IH_RB_CNTL, tmp);
2807         }
2808         return (wptr & rdev->ih.ptr_mask);
2809 }
2810
2811 int evergreen_irq_process(struct radeon_device *rdev)
2812 {
2813         u32 wptr;
2814         u32 rptr;
2815         u32 src_id, src_data;
2816         u32 ring_index;
2817         unsigned long flags;
2818         bool queue_hotplug = false;
2819
2820         if (!rdev->ih.enabled || rdev->shutdown)
2821                 return IRQ_NONE;
2822
2823         wptr = evergreen_get_ih_wptr(rdev);
2824         rptr = rdev->ih.rptr;
2825         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2826
2827         spin_lock_irqsave(&rdev->ih.lock, flags);
2828         if (rptr == wptr) {
2829                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2830                 return IRQ_NONE;
2831         }
2832 restart_ih:
2833         /* Order reading of wptr vs. reading of IH ring data */
2834         rmb();
2835
2836         /* display interrupts */
2837         evergreen_irq_ack(rdev);
2838
2839         rdev->ih.wptr = wptr;
2840         while (rptr != wptr) {
2841                 /* wptr/rptr are in bytes! */
2842                 ring_index = rptr / 4;
2843                 src_id =  le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
2844                 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
2845
2846                 switch (src_id) {
2847                 case 1: /* D1 vblank/vline */
2848                         switch (src_data) {
2849                         case 0: /* D1 vblank */
2850                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
2851                                         if (rdev->irq.crtc_vblank_int[0]) {
2852                                                 drm_handle_vblank(rdev->ddev, 0);
2853                                                 rdev->pm.vblank_sync = true;
2854                                                 wake_up(&rdev->irq.vblank_queue);
2855                                         }
2856                                         if (rdev->irq.pflip[0])
2857                                                 radeon_crtc_handle_flip(rdev, 0);
2858                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2859                                         DRM_DEBUG("IH: D1 vblank\n");
2860                                 }
2861                                 break;
2862                         case 1: /* D1 vline */
2863                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
2864                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
2865                                         DRM_DEBUG("IH: D1 vline\n");
2866                                 }
2867                                 break;
2868                         default:
2869                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2870                                 break;
2871                         }
2872                         break;
2873                 case 2: /* D2 vblank/vline */
2874                         switch (src_data) {
2875                         case 0: /* D2 vblank */
2876                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
2877                                         if (rdev->irq.crtc_vblank_int[1]) {
2878                                                 drm_handle_vblank(rdev->ddev, 1);
2879                                                 rdev->pm.vblank_sync = true;
2880                                                 wake_up(&rdev->irq.vblank_queue);
2881                                         }
2882                                         if (rdev->irq.pflip[1])
2883                                                 radeon_crtc_handle_flip(rdev, 1);
2884                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
2885                                         DRM_DEBUG("IH: D2 vblank\n");
2886                                 }
2887                                 break;
2888                         case 1: /* D2 vline */
2889                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2890                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
2891                                         DRM_DEBUG("IH: D2 vline\n");
2892                                 }
2893                                 break;
2894                         default:
2895                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2896                                 break;
2897                         }
2898                         break;
2899                 case 3: /* D3 vblank/vline */
2900                         switch (src_data) {
2901                         case 0: /* D3 vblank */
2902                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2903                                         if (rdev->irq.crtc_vblank_int[2]) {
2904                                                 drm_handle_vblank(rdev->ddev, 2);
2905                                                 rdev->pm.vblank_sync = true;
2906                                                 wake_up(&rdev->irq.vblank_queue);
2907                                         }
2908                                         if (rdev->irq.pflip[2])
2909                                                 radeon_crtc_handle_flip(rdev, 2);
2910                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
2911                                         DRM_DEBUG("IH: D3 vblank\n");
2912                                 }
2913                                 break;
2914                         case 1: /* D3 vline */
2915                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
2916                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
2917                                         DRM_DEBUG("IH: D3 vline\n");
2918                                 }
2919                                 break;
2920                         default:
2921                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2922                                 break;
2923                         }
2924                         break;
2925                 case 4: /* D4 vblank/vline */
2926                         switch (src_data) {
2927                         case 0: /* D4 vblank */
2928                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
2929                                         if (rdev->irq.crtc_vblank_int[3]) {
2930                                                 drm_handle_vblank(rdev->ddev, 3);
2931                                                 rdev->pm.vblank_sync = true;
2932                                                 wake_up(&rdev->irq.vblank_queue);
2933                                         }
2934                                         if (rdev->irq.pflip[3])
2935                                                 radeon_crtc_handle_flip(rdev, 3);
2936                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
2937                                         DRM_DEBUG("IH: D4 vblank\n");
2938                                 }
2939                                 break;
2940                         case 1: /* D4 vline */
2941                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
2942                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
2943                                         DRM_DEBUG("IH: D4 vline\n");
2944                                 }
2945                                 break;
2946                         default:
2947                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2948                                 break;
2949                         }
2950                         break;
2951                 case 5: /* D5 vblank/vline */
2952                         switch (src_data) {
2953                         case 0: /* D5 vblank */
2954                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
2955                                         if (rdev->irq.crtc_vblank_int[4]) {
2956                                                 drm_handle_vblank(rdev->ddev, 4);
2957                                                 rdev->pm.vblank_sync = true;
2958                                                 wake_up(&rdev->irq.vblank_queue);
2959                                         }
2960                                         if (rdev->irq.pflip[4])
2961                                                 radeon_crtc_handle_flip(rdev, 4);
2962                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
2963                                         DRM_DEBUG("IH: D5 vblank\n");
2964                                 }
2965                                 break;
2966                         case 1: /* D5 vline */
2967                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
2968                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
2969                                         DRM_DEBUG("IH: D5 vline\n");
2970                                 }
2971                                 break;
2972                         default:
2973                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2974                                 break;
2975                         }
2976                         break;
2977                 case 6: /* D6 vblank/vline */
2978                         switch (src_data) {
2979                         case 0: /* D6 vblank */
2980                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
2981                                         if (rdev->irq.crtc_vblank_int[5]) {
2982                                                 drm_handle_vblank(rdev->ddev, 5);
2983                                                 rdev->pm.vblank_sync = true;
2984                                                 wake_up(&rdev->irq.vblank_queue);
2985                                         }
2986                                         if (rdev->irq.pflip[5])
2987                                                 radeon_crtc_handle_flip(rdev, 5);
2988                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
2989                                         DRM_DEBUG("IH: D6 vblank\n");
2990                                 }
2991                                 break;
2992                         case 1: /* D6 vline */
2993                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
2994                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
2995                                         DRM_DEBUG("IH: D6 vline\n");
2996                                 }
2997                                 break;
2998                         default:
2999                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3000                                 break;
3001                         }
3002                         break;
3003                 case 42: /* HPD hotplug */
3004                         switch (src_data) {
3005                         case 0:
3006                                 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
3007                                         rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
3008                                         queue_hotplug = true;
3009                                         DRM_DEBUG("IH: HPD1\n");
3010                                 }
3011                                 break;
3012                         case 1:
3013                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
3014                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
3015                                         queue_hotplug = true;
3016                                         DRM_DEBUG("IH: HPD2\n");
3017                                 }
3018                                 break;
3019                         case 2:
3020                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
3021                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
3022                                         queue_hotplug = true;
3023                                         DRM_DEBUG("IH: HPD3\n");
3024                                 }
3025                                 break;
3026                         case 3:
3027                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
3028                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
3029                                         queue_hotplug = true;
3030                                         DRM_DEBUG("IH: HPD4\n");
3031                                 }
3032                                 break;
3033                         case 4:
3034                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
3035                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
3036                                         queue_hotplug = true;
3037                                         DRM_DEBUG("IH: HPD5\n");
3038                                 }
3039                                 break;
3040                         case 5:
3041                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3042                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
3043                                         queue_hotplug = true;
3044                                         DRM_DEBUG("IH: HPD6\n");
3045                                 }
3046                                 break;
3047                         default:
3048                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3049                                 break;
3050                         }
3051                         break;
3052                 case 176: /* CP_INT in ring buffer */
3053                 case 177: /* CP_INT in IB1 */
3054                 case 178: /* CP_INT in IB2 */
3055                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3056                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3057                         break;
3058                 case 181: /* CP EOP event */
3059                         DRM_DEBUG("IH: CP EOP\n");
3060                         if (rdev->family >= CHIP_CAYMAN) {
3061                                 switch (src_data) {
3062                                 case 0:
3063                                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3064                                         break;
3065                                 case 1:
3066                                         radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
3067                                         break;
3068                                 case 2:
3069                                         radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
3070                                         break;
3071                                 }
3072                         } else
3073                                 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3074                         break;
3075                 case 233: /* GUI IDLE */
3076                         DRM_DEBUG("IH: GUI idle\n");
3077                         rdev->pm.gui_idle = true;
3078                         wake_up(&rdev->irq.idle_queue);
3079                         break;
3080                 default:
3081                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3082                         break;
3083                 }
3084
3085                 /* wptr/rptr are in bytes! */
3086                 rptr += 16;
3087                 rptr &= rdev->ih.ptr_mask;
3088         }
3089         /* make sure wptr hasn't changed while processing */
3090         wptr = evergreen_get_ih_wptr(rdev);
3091         if (wptr != rdev->ih.wptr)
3092                 goto restart_ih;
3093         if (queue_hotplug)
3094                 schedule_work(&rdev->hotplug_work);
3095         rdev->ih.rptr = rptr;
3096         WREG32(IH_RB_RPTR, rdev->ih.rptr);
3097         spin_unlock_irqrestore(&rdev->ih.lock, flags);
3098         return IRQ_HANDLED;
3099 }
3100
3101 static int evergreen_startup(struct radeon_device *rdev)
3102 {
3103         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3104         int r;
3105
3106         /* enable pcie gen2 link */
3107         evergreen_pcie_gen2_enable(rdev);
3108
3109         if (ASIC_IS_DCE5(rdev)) {
3110                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
3111                         r = ni_init_microcode(rdev);
3112                         if (r) {
3113                                 DRM_ERROR("Failed to load firmware!\n");
3114                                 return r;
3115                         }
3116                 }
3117                 r = ni_mc_load_microcode(rdev);
3118                 if (r) {
3119                         DRM_ERROR("Failed to load MC firmware!\n");
3120                         return r;
3121                 }
3122         } else {
3123                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3124                         r = r600_init_microcode(rdev);
3125                         if (r) {
3126                                 DRM_ERROR("Failed to load firmware!\n");
3127                                 return r;
3128                         }
3129                 }
3130         }
3131
3132         r = r600_vram_scratch_init(rdev);
3133         if (r)
3134                 return r;
3135
3136         evergreen_mc_program(rdev);
3137         if (rdev->flags & RADEON_IS_AGP) {
3138                 evergreen_agp_enable(rdev);
3139         } else {
3140                 r = evergreen_pcie_gart_enable(rdev);
3141                 if (r)
3142                         return r;
3143         }
3144         evergreen_gpu_init(rdev);
3145
3146         r = evergreen_blit_init(rdev);
3147         if (r) {
3148                 r600_blit_fini(rdev);
3149                 rdev->asic->copy = NULL;
3150                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
3151         }
3152
3153         /* allocate wb buffer */
3154         r = radeon_wb_init(rdev);
3155         if (r)
3156                 return r;
3157
3158         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3159         if (r) {
3160                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3161                 return r;
3162         }
3163
3164         /* Enable IRQ */
3165         r = r600_irq_init(rdev);
3166         if (r) {
3167                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3168                 radeon_irq_kms_fini(rdev);
3169                 return r;
3170         }
3171         evergreen_irq_set(rdev);
3172
3173         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
3174                              R600_CP_RB_RPTR, R600_CP_RB_WPTR,
3175                              0, 0xfffff, RADEON_CP_PACKET2);
3176         if (r)
3177                 return r;
3178         r = evergreen_cp_load_microcode(rdev);
3179         if (r)
3180                 return r;
3181         r = evergreen_cp_resume(rdev);
3182         if (r)
3183                 return r;
3184
3185         r = radeon_ib_pool_start(rdev);
3186         if (r)
3187                 return r;
3188
3189         r = r600_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX);
3190         if (r) {
3191                 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
3192                 rdev->accel_working = false;
3193         }
3194
3195         r = r600_audio_init(rdev);
3196         if (r) {
3197                 DRM_ERROR("radeon: audio init failed\n");
3198                 return r;
3199         }
3200
3201         return 0;
3202 }
3203
3204 int evergreen_resume(struct radeon_device *rdev)
3205 {
3206         int r;
3207
3208         /* reset the asic, the gfx blocks are often in a bad state
3209          * after the driver is unloaded or after a resume
3210          */
3211         if (radeon_asic_reset(rdev))
3212                 dev_warn(rdev->dev, "GPU reset failed !\n");
3213         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
3214          * posting will perform necessary task to bring back GPU into good
3215          * shape.
3216          */
3217         /* post card */
3218         atom_asic_init(rdev->mode_info.atom_context);
3219
3220         rdev->accel_working = true;
3221         r = evergreen_startup(rdev);
3222         if (r) {
3223                 DRM_ERROR("evergreen startup failed on resume\n");
3224                 return r;
3225         }
3226
3227         return r;
3228
3229 }
3230
3231 int evergreen_suspend(struct radeon_device *rdev)
3232 {
3233         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3234
3235         r600_audio_fini(rdev);
3236         /* FIXME: we should wait for ring to be empty */
3237         radeon_ib_pool_suspend(rdev);
3238         r600_blit_suspend(rdev);
3239         r700_cp_stop(rdev);
3240         ring->ready = false;
3241         evergreen_irq_suspend(rdev);
3242         radeon_wb_disable(rdev);
3243         evergreen_pcie_gart_disable(rdev);
3244
3245         return 0;
3246 }
3247
3248 /* Plan is to move initialization in that function and use
3249  * helper function so that radeon_device_init pretty much
3250  * do nothing more than calling asic specific function. This
3251  * should also allow to remove a bunch of callback function
3252  * like vram_info.
3253  */
3254 int evergreen_init(struct radeon_device *rdev)
3255 {
3256         int r;
3257
3258         /* This don't do much */
3259         r = radeon_gem_init(rdev);
3260         if (r)
3261                 return r;
3262         /* Read BIOS */
3263         if (!radeon_get_bios(rdev)) {
3264                 if (ASIC_IS_AVIVO(rdev))
3265                         return -EINVAL;
3266         }
3267         /* Must be an ATOMBIOS */
3268         if (!rdev->is_atom_bios) {
3269                 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");
3270                 return -EINVAL;
3271         }
3272         r = radeon_atombios_init(rdev);
3273         if (r)
3274                 return r;
3275         /* reset the asic, the gfx blocks are often in a bad state
3276          * after the driver is unloaded or after a resume
3277          */
3278         if (radeon_asic_reset(rdev))
3279                 dev_warn(rdev->dev, "GPU reset failed !\n");
3280         /* Post card if necessary */
3281         if (!radeon_card_posted(rdev)) {
3282                 if (!rdev->bios) {
3283                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3284                         return -EINVAL;
3285                 }
3286                 DRM_INFO("GPU not posted. posting now...\n");
3287                 atom_asic_init(rdev->mode_info.atom_context);
3288         }
3289         /* Initialize scratch registers */
3290         r600_scratch_init(rdev);
3291         /* Initialize surface registers */
3292         radeon_surface_init(rdev);
3293         /* Initialize clocks */
3294         radeon_get_clock_info(rdev->ddev);
3295         /* Fence driver */
3296         r = radeon_fence_driver_init(rdev);
3297         if (r)
3298                 return r;
3299         /* initialize AGP */
3300         if (rdev->flags & RADEON_IS_AGP) {
3301                 r = radeon_agp_init(rdev);
3302                 if (r)
3303                         radeon_agp_disable(rdev);
3304         }
3305         /* initialize memory controller */
3306         r = evergreen_mc_init(rdev);
3307         if (r)
3308                 return r;
3309         /* Memory manager */
3310         r = radeon_bo_init(rdev);
3311         if (r)
3312                 return r;
3313
3314         r = radeon_irq_kms_init(rdev);
3315         if (r)
3316                 return r;
3317
3318         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
3319         r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
3320
3321         rdev->ih.ring_obj = NULL;
3322         r600_ih_ring_init(rdev, 64 * 1024);
3323
3324         r = r600_pcie_gart_init(rdev);
3325         if (r)
3326                 return r;
3327
3328         r = radeon_ib_pool_init(rdev);
3329         rdev->accel_working = true;
3330         if (r) {
3331                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3332                 rdev->accel_working = false;
3333         }
3334
3335         r = evergreen_startup(rdev);
3336         if (r) {
3337                 dev_err(rdev->dev, "disabling GPU acceleration\n");
3338                 r700_cp_fini(rdev);
3339                 r600_irq_fini(rdev);
3340                 radeon_wb_fini(rdev);
3341                 r100_ib_fini(rdev);
3342                 radeon_irq_kms_fini(rdev);
3343                 evergreen_pcie_gart_fini(rdev);
3344                 rdev->accel_working = false;
3345         }
3346
3347         /* Don't start up if the MC ucode is missing on BTC parts.
3348          * The default clocks and voltages before the MC ucode
3349          * is loaded are not suffient for advanced operations.
3350          */
3351         if (ASIC_IS_DCE5(rdev)) {
3352                 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
3353                         DRM_ERROR("radeon: MC ucode required for NI+.\n");
3354                         return -EINVAL;
3355                 }
3356         }
3357
3358         return 0;
3359 }
3360
3361 void evergreen_fini(struct radeon_device *rdev)
3362 {
3363         r600_audio_fini(rdev);
3364         r600_blit_fini(rdev);
3365         r700_cp_fini(rdev);
3366         r600_irq_fini(rdev);
3367         radeon_wb_fini(rdev);
3368         r100_ib_fini(rdev);
3369         radeon_irq_kms_fini(rdev);
3370         evergreen_pcie_gart_fini(rdev);
3371         r600_vram_scratch_fini(rdev);
3372         radeon_gem_fini(rdev);
3373         radeon_semaphore_driver_fini(rdev);
3374         radeon_fence_driver_fini(rdev);
3375         radeon_agp_fini(rdev);
3376         radeon_bo_fini(rdev);
3377         radeon_atombios_fini(rdev);
3378         kfree(rdev->bios);
3379         rdev->bios = NULL;
3380 }
3381
3382 void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
3383 {
3384         u32 link_width_cntl, speed_cntl;
3385
3386         if (radeon_pcie_gen2 == 0)
3387                 return;
3388
3389         if (rdev->flags & RADEON_IS_IGP)
3390                 return;
3391
3392         if (!(rdev->flags & RADEON_IS_PCIE))
3393                 return;
3394
3395         /* x2 cards have a special sequence */
3396         if (ASIC_IS_X2(rdev))
3397                 return;
3398
3399         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3400         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3401             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3402
3403                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3404                 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3405                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3406
3407                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3408                 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3409                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3410
3411                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3412                 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3413                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3414
3415                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3416                 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3417                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3418
3419                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3420                 speed_cntl |= LC_GEN2_EN_STRAP;
3421                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3422
3423         } else {
3424                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3425                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3426                 if (1)
3427                         link_width_cntl |= LC_UPCONFIGURE_DIS;
3428                 else
3429                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3430                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3431         }
3432 }