drm/radeon: properly track the crtc not_enabled case evergreen_mc_stop()
[linux-2.6.git] / drivers / gpu / drm / radeon / evergreen.c
1 /*
2  * Copyright 2010 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Alex Deucher
23  */
24 #include <linux/firmware.h>
25 #include <linux/platform_device.h>
26 #include <linux/slab.h>
27 #include "drmP.h"
28 #include "radeon.h"
29 #include "radeon_asic.h"
30 #include "radeon_drm.h"
31 #include "evergreend.h"
32 #include "atom.h"
33 #include "avivod.h"
34 #include "evergreen_reg.h"
35 #include "evergreen_blit_shaders.h"
36
37 #define EVERGREEN_PFP_UCODE_SIZE 1120
38 #define EVERGREEN_PM4_UCODE_SIZE 1376
39
40 static const u32 crtc_offsets[6] =
41 {
42         EVERGREEN_CRTC0_REGISTER_OFFSET,
43         EVERGREEN_CRTC1_REGISTER_OFFSET,
44         EVERGREEN_CRTC2_REGISTER_OFFSET,
45         EVERGREEN_CRTC3_REGISTER_OFFSET,
46         EVERGREEN_CRTC4_REGISTER_OFFSET,
47         EVERGREEN_CRTC5_REGISTER_OFFSET
48 };
49
50 static void evergreen_gpu_init(struct radeon_device *rdev);
51 void evergreen_fini(struct radeon_device *rdev);
52 void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
53 extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
54                                      int ring, u32 cp_int_cntl);
55
56 void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
57                              unsigned *bankh, unsigned *mtaspect,
58                              unsigned *tile_split)
59 {
60         *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
61         *bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
62         *mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
63         *tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
64         switch (*bankw) {
65         default:
66         case 1: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_1; break;
67         case 2: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_2; break;
68         case 4: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_4; break;
69         case 8: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_8; break;
70         }
71         switch (*bankh) {
72         default:
73         case 1: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_1; break;
74         case 2: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_2; break;
75         case 4: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_4; break;
76         case 8: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_8; break;
77         }
78         switch (*mtaspect) {
79         default:
80         case 1: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1; break;
81         case 2: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2; break;
82         case 4: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4; break;
83         case 8: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8; break;
84         }
85 }
86
87 void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
88 {
89         u16 ctl, v;
90         int cap, err;
91
92         cap = pci_pcie_cap(rdev->pdev);
93         if (!cap)
94                 return;
95
96         err = pci_read_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, &ctl);
97         if (err)
98                 return;
99
100         v = (ctl & PCI_EXP_DEVCTL_READRQ) >> 12;
101
102         /* if bios or OS sets MAX_READ_REQUEST_SIZE to an invalid value, fix it
103          * to avoid hangs or perfomance issues
104          */
105         if ((v == 0) || (v == 6) || (v == 7)) {
106                 ctl &= ~PCI_EXP_DEVCTL_READRQ;
107                 ctl |= (2 << 12);
108                 pci_write_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, ctl);
109         }
110 }
111
112 void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc)
113 {
114         int i;
115
116         if (crtc >= rdev->num_crtc)
117                 return;
118
119         if (RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[crtc]) & EVERGREEN_CRTC_MASTER_EN) {
120                 for (i = 0; i < rdev->usec_timeout; i++) {
121                         if (!(RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK))
122                                 break;
123                         udelay(1);
124                 }
125                 for (i = 0; i < rdev->usec_timeout; i++) {
126                         if (RREG32(EVERGREEN_CRTC_STATUS + crtc_offsets[crtc]) & EVERGREEN_CRTC_V_BLANK)
127                                 break;
128                         udelay(1);
129                 }
130         }
131 }
132
133 void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
134 {
135         /* enable the pflip int */
136         radeon_irq_kms_pflip_irq_get(rdev, crtc);
137 }
138
139 void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
140 {
141         /* disable the pflip int */
142         radeon_irq_kms_pflip_irq_put(rdev, crtc);
143 }
144
145 u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
146 {
147         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
148         u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
149         int i;
150
151         /* Lock the graphics update lock */
152         tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
153         WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
154
155         /* update the scanout addresses */
156         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
157                upper_32_bits(crtc_base));
158         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
159                (u32)crtc_base);
160
161         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
162                upper_32_bits(crtc_base));
163         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
164                (u32)crtc_base);
165
166         /* Wait for update_pending to go high. */
167         for (i = 0; i < rdev->usec_timeout; i++) {
168                 if (RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING)
169                         break;
170                 udelay(1);
171         }
172         DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
173
174         /* Unlock the lock, so double-buffering can take place inside vblank */
175         tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
176         WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
177
178         /* Return current update_pending status: */
179         return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
180 }
181
182 /* get temperature in millidegrees */
183 int evergreen_get_temp(struct radeon_device *rdev)
184 {
185         u32 temp, toffset;
186         int actual_temp = 0;
187
188         if (rdev->family == CHIP_JUNIPER) {
189                 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
190                         TOFFSET_SHIFT;
191                 temp = (RREG32(CG_TS0_STATUS) & TS0_ADC_DOUT_MASK) >>
192                         TS0_ADC_DOUT_SHIFT;
193
194                 if (toffset & 0x100)
195                         actual_temp = temp / 2 - (0x200 - toffset);
196                 else
197                         actual_temp = temp / 2 + toffset;
198
199                 actual_temp = actual_temp * 1000;
200
201         } else {
202                 temp = (RREG32(CG_MULT_THERMAL_STATUS) & ASIC_T_MASK) >>
203                         ASIC_T_SHIFT;
204
205                 if (temp & 0x400)
206                         actual_temp = -256;
207                 else if (temp & 0x200)
208                         actual_temp = 255;
209                 else if (temp & 0x100) {
210                         actual_temp = temp & 0x1ff;
211                         actual_temp |= ~0x1ff;
212                 } else
213                         actual_temp = temp & 0xff;
214
215                 actual_temp = (actual_temp * 1000) / 2;
216         }
217
218         return actual_temp;
219 }
220
221 int sumo_get_temp(struct radeon_device *rdev)
222 {
223         u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
224         int actual_temp = temp - 49;
225
226         return actual_temp * 1000;
227 }
228
229 void sumo_pm_init_profile(struct radeon_device *rdev)
230 {
231         int idx;
232
233         /* default */
234         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
235         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
236         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
237         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
238
239         /* low,mid sh/mh */
240         if (rdev->flags & RADEON_IS_MOBILITY)
241                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
242         else
243                 idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
244
245         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = idx;
246         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = idx;
247         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
248         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
249
250         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = idx;
251         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = idx;
252         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
253         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
254
255         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = idx;
256         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = idx;
257         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
258         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
259
260         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = idx;
261         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = idx;
262         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
263         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
264
265         /* high sh/mh */
266         idx = radeon_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
267         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = idx;
268         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = idx;
269         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
270         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx =
271                 rdev->pm.power_state[idx].num_clock_modes - 1;
272
273         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = idx;
274         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = idx;
275         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
276         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx =
277                 rdev->pm.power_state[idx].num_clock_modes - 1;
278 }
279
280 void evergreen_pm_misc(struct radeon_device *rdev)
281 {
282         int req_ps_idx = rdev->pm.requested_power_state_index;
283         int req_cm_idx = rdev->pm.requested_clock_mode_index;
284         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
285         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
286
287         if (voltage->type == VOLTAGE_SW) {
288                 /* 0xff01 is a flag rather then an actual voltage */
289                 if (voltage->voltage == 0xff01)
290                         return;
291                 if (voltage->voltage && (voltage->voltage != rdev->pm.current_vddc)) {
292                         radeon_atom_set_voltage(rdev, voltage->voltage, SET_VOLTAGE_TYPE_ASIC_VDDC);
293                         rdev->pm.current_vddc = voltage->voltage;
294                         DRM_DEBUG("Setting: vddc: %d\n", voltage->voltage);
295                 }
296                 /* 0xff01 is a flag rather then an actual voltage */
297                 if (voltage->vddci == 0xff01)
298                         return;
299                 if (voltage->vddci && (voltage->vddci != rdev->pm.current_vddci)) {
300                         radeon_atom_set_voltage(rdev, voltage->vddci, SET_VOLTAGE_TYPE_ASIC_VDDCI);
301                         rdev->pm.current_vddci = voltage->vddci;
302                         DRM_DEBUG("Setting: vddci: %d\n", voltage->vddci);
303                 }
304         }
305 }
306
307 void evergreen_pm_prepare(struct radeon_device *rdev)
308 {
309         struct drm_device *ddev = rdev->ddev;
310         struct drm_crtc *crtc;
311         struct radeon_crtc *radeon_crtc;
312         u32 tmp;
313
314         /* disable any active CRTCs */
315         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
316                 radeon_crtc = to_radeon_crtc(crtc);
317                 if (radeon_crtc->enabled) {
318                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
319                         tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
320                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
321                 }
322         }
323 }
324
325 void evergreen_pm_finish(struct radeon_device *rdev)
326 {
327         struct drm_device *ddev = rdev->ddev;
328         struct drm_crtc *crtc;
329         struct radeon_crtc *radeon_crtc;
330         u32 tmp;
331
332         /* enable any active CRTCs */
333         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
334                 radeon_crtc = to_radeon_crtc(crtc);
335                 if (radeon_crtc->enabled) {
336                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
337                         tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
338                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
339                 }
340         }
341 }
342
343 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
344 {
345         bool connected = false;
346
347         switch (hpd) {
348         case RADEON_HPD_1:
349                 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
350                         connected = true;
351                 break;
352         case RADEON_HPD_2:
353                 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
354                         connected = true;
355                 break;
356         case RADEON_HPD_3:
357                 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
358                         connected = true;
359                 break;
360         case RADEON_HPD_4:
361                 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
362                         connected = true;
363                 break;
364         case RADEON_HPD_5:
365                 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
366                         connected = true;
367                 break;
368         case RADEON_HPD_6:
369                 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
370                         connected = true;
371                         break;
372         default:
373                 break;
374         }
375
376         return connected;
377 }
378
379 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
380                                 enum radeon_hpd_id hpd)
381 {
382         u32 tmp;
383         bool connected = evergreen_hpd_sense(rdev, hpd);
384
385         switch (hpd) {
386         case RADEON_HPD_1:
387                 tmp = RREG32(DC_HPD1_INT_CONTROL);
388                 if (connected)
389                         tmp &= ~DC_HPDx_INT_POLARITY;
390                 else
391                         tmp |= DC_HPDx_INT_POLARITY;
392                 WREG32(DC_HPD1_INT_CONTROL, tmp);
393                 break;
394         case RADEON_HPD_2:
395                 tmp = RREG32(DC_HPD2_INT_CONTROL);
396                 if (connected)
397                         tmp &= ~DC_HPDx_INT_POLARITY;
398                 else
399                         tmp |= DC_HPDx_INT_POLARITY;
400                 WREG32(DC_HPD2_INT_CONTROL, tmp);
401                 break;
402         case RADEON_HPD_3:
403                 tmp = RREG32(DC_HPD3_INT_CONTROL);
404                 if (connected)
405                         tmp &= ~DC_HPDx_INT_POLARITY;
406                 else
407                         tmp |= DC_HPDx_INT_POLARITY;
408                 WREG32(DC_HPD3_INT_CONTROL, tmp);
409                 break;
410         case RADEON_HPD_4:
411                 tmp = RREG32(DC_HPD4_INT_CONTROL);
412                 if (connected)
413                         tmp &= ~DC_HPDx_INT_POLARITY;
414                 else
415                         tmp |= DC_HPDx_INT_POLARITY;
416                 WREG32(DC_HPD4_INT_CONTROL, tmp);
417                 break;
418         case RADEON_HPD_5:
419                 tmp = RREG32(DC_HPD5_INT_CONTROL);
420                 if (connected)
421                         tmp &= ~DC_HPDx_INT_POLARITY;
422                 else
423                         tmp |= DC_HPDx_INT_POLARITY;
424                 WREG32(DC_HPD5_INT_CONTROL, tmp);
425                         break;
426         case RADEON_HPD_6:
427                 tmp = RREG32(DC_HPD6_INT_CONTROL);
428                 if (connected)
429                         tmp &= ~DC_HPDx_INT_POLARITY;
430                 else
431                         tmp |= DC_HPDx_INT_POLARITY;
432                 WREG32(DC_HPD6_INT_CONTROL, tmp);
433                 break;
434         default:
435                 break;
436         }
437 }
438
439 void evergreen_hpd_init(struct radeon_device *rdev)
440 {
441         struct drm_device *dev = rdev->ddev;
442         struct drm_connector *connector;
443         u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
444                 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
445
446         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
447                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
448                 switch (radeon_connector->hpd.hpd) {
449                 case RADEON_HPD_1:
450                         WREG32(DC_HPD1_CONTROL, tmp);
451                         rdev->irq.hpd[0] = true;
452                         break;
453                 case RADEON_HPD_2:
454                         WREG32(DC_HPD2_CONTROL, tmp);
455                         rdev->irq.hpd[1] = true;
456                         break;
457                 case RADEON_HPD_3:
458                         WREG32(DC_HPD3_CONTROL, tmp);
459                         rdev->irq.hpd[2] = true;
460                         break;
461                 case RADEON_HPD_4:
462                         WREG32(DC_HPD4_CONTROL, tmp);
463                         rdev->irq.hpd[3] = true;
464                         break;
465                 case RADEON_HPD_5:
466                         WREG32(DC_HPD5_CONTROL, tmp);
467                         rdev->irq.hpd[4] = true;
468                         break;
469                 case RADEON_HPD_6:
470                         WREG32(DC_HPD6_CONTROL, tmp);
471                         rdev->irq.hpd[5] = true;
472                         break;
473                 default:
474                         break;
475                 }
476                 radeon_hpd_set_polarity(rdev, radeon_connector->hpd.hpd);
477         }
478         if (rdev->irq.installed)
479                 evergreen_irq_set(rdev);
480 }
481
482 void evergreen_hpd_fini(struct radeon_device *rdev)
483 {
484         struct drm_device *dev = rdev->ddev;
485         struct drm_connector *connector;
486
487         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
488                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
489                 switch (radeon_connector->hpd.hpd) {
490                 case RADEON_HPD_1:
491                         WREG32(DC_HPD1_CONTROL, 0);
492                         rdev->irq.hpd[0] = false;
493                         break;
494                 case RADEON_HPD_2:
495                         WREG32(DC_HPD2_CONTROL, 0);
496                         rdev->irq.hpd[1] = false;
497                         break;
498                 case RADEON_HPD_3:
499                         WREG32(DC_HPD3_CONTROL, 0);
500                         rdev->irq.hpd[2] = false;
501                         break;
502                 case RADEON_HPD_4:
503                         WREG32(DC_HPD4_CONTROL, 0);
504                         rdev->irq.hpd[3] = false;
505                         break;
506                 case RADEON_HPD_5:
507                         WREG32(DC_HPD5_CONTROL, 0);
508                         rdev->irq.hpd[4] = false;
509                         break;
510                 case RADEON_HPD_6:
511                         WREG32(DC_HPD6_CONTROL, 0);
512                         rdev->irq.hpd[5] = false;
513                         break;
514                 default:
515                         break;
516                 }
517         }
518 }
519
520 /* watermark setup */
521
522 static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
523                                         struct radeon_crtc *radeon_crtc,
524                                         struct drm_display_mode *mode,
525                                         struct drm_display_mode *other_mode)
526 {
527         u32 tmp;
528         /*
529          * Line Buffer Setup
530          * There are 3 line buffers, each one shared by 2 display controllers.
531          * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between
532          * the display controllers.  The paritioning is done via one of four
533          * preset allocations specified in bits 2:0:
534          * first display controller
535          *  0 - first half of lb (3840 * 2)
536          *  1 - first 3/4 of lb (5760 * 2)
537          *  2 - whole lb (7680 * 2), other crtc must be disabled
538          *  3 - first 1/4 of lb (1920 * 2)
539          * second display controller
540          *  4 - second half of lb (3840 * 2)
541          *  5 - second 3/4 of lb (5760 * 2)
542          *  6 - whole lb (7680 * 2), other crtc must be disabled
543          *  7 - last 1/4 of lb (1920 * 2)
544          */
545         /* this can get tricky if we have two large displays on a paired group
546          * of crtcs.  Ideally for multiple large displays we'd assign them to
547          * non-linked crtcs for maximum line buffer allocation.
548          */
549         if (radeon_crtc->base.enabled && mode) {
550                 if (other_mode)
551                         tmp = 0; /* 1/2 */
552                 else
553                         tmp = 2; /* whole */
554         } else
555                 tmp = 0;
556
557         /* second controller of the pair uses second half of the lb */
558         if (radeon_crtc->crtc_id % 2)
559                 tmp += 4;
560         WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
561
562         if (radeon_crtc->base.enabled && mode) {
563                 switch (tmp) {
564                 case 0:
565                 case 4:
566                 default:
567                         if (ASIC_IS_DCE5(rdev))
568                                 return 4096 * 2;
569                         else
570                                 return 3840 * 2;
571                 case 1:
572                 case 5:
573                         if (ASIC_IS_DCE5(rdev))
574                                 return 6144 * 2;
575                         else
576                                 return 5760 * 2;
577                 case 2:
578                 case 6:
579                         if (ASIC_IS_DCE5(rdev))
580                                 return 8192 * 2;
581                         else
582                                 return 7680 * 2;
583                 case 3:
584                 case 7:
585                         if (ASIC_IS_DCE5(rdev))
586                                 return 2048 * 2;
587                         else
588                                 return 1920 * 2;
589                 }
590         }
591
592         /* controller not enabled, so no lb used */
593         return 0;
594 }
595
596 u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
597 {
598         u32 tmp = RREG32(MC_SHARED_CHMAP);
599
600         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
601         case 0:
602         default:
603                 return 1;
604         case 1:
605                 return 2;
606         case 2:
607                 return 4;
608         case 3:
609                 return 8;
610         }
611 }
612
613 struct evergreen_wm_params {
614         u32 dram_channels; /* number of dram channels */
615         u32 yclk;          /* bandwidth per dram data pin in kHz */
616         u32 sclk;          /* engine clock in kHz */
617         u32 disp_clk;      /* display clock in kHz */
618         u32 src_width;     /* viewport width */
619         u32 active_time;   /* active display time in ns */
620         u32 blank_time;    /* blank time in ns */
621         bool interlaced;    /* mode is interlaced */
622         fixed20_12 vsc;    /* vertical scale ratio */
623         u32 num_heads;     /* number of active crtcs */
624         u32 bytes_per_pixel; /* bytes per pixel display + overlay */
625         u32 lb_size;       /* line buffer allocated to pipe */
626         u32 vtaps;         /* vertical scaler taps */
627 };
628
629 static u32 evergreen_dram_bandwidth(struct evergreen_wm_params *wm)
630 {
631         /* Calculate DRAM Bandwidth and the part allocated to display. */
632         fixed20_12 dram_efficiency; /* 0.7 */
633         fixed20_12 yclk, dram_channels, bandwidth;
634         fixed20_12 a;
635
636         a.full = dfixed_const(1000);
637         yclk.full = dfixed_const(wm->yclk);
638         yclk.full = dfixed_div(yclk, a);
639         dram_channels.full = dfixed_const(wm->dram_channels * 4);
640         a.full = dfixed_const(10);
641         dram_efficiency.full = dfixed_const(7);
642         dram_efficiency.full = dfixed_div(dram_efficiency, a);
643         bandwidth.full = dfixed_mul(dram_channels, yclk);
644         bandwidth.full = dfixed_mul(bandwidth, dram_efficiency);
645
646         return dfixed_trunc(bandwidth);
647 }
648
649 static u32 evergreen_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
650 {
651         /* Calculate DRAM Bandwidth and the part allocated to display. */
652         fixed20_12 disp_dram_allocation; /* 0.3 to 0.7 */
653         fixed20_12 yclk, dram_channels, bandwidth;
654         fixed20_12 a;
655
656         a.full = dfixed_const(1000);
657         yclk.full = dfixed_const(wm->yclk);
658         yclk.full = dfixed_div(yclk, a);
659         dram_channels.full = dfixed_const(wm->dram_channels * 4);
660         a.full = dfixed_const(10);
661         disp_dram_allocation.full = dfixed_const(3); /* XXX worse case value 0.3 */
662         disp_dram_allocation.full = dfixed_div(disp_dram_allocation, a);
663         bandwidth.full = dfixed_mul(dram_channels, yclk);
664         bandwidth.full = dfixed_mul(bandwidth, disp_dram_allocation);
665
666         return dfixed_trunc(bandwidth);
667 }
668
669 static u32 evergreen_data_return_bandwidth(struct evergreen_wm_params *wm)
670 {
671         /* Calculate the display Data return Bandwidth */
672         fixed20_12 return_efficiency; /* 0.8 */
673         fixed20_12 sclk, bandwidth;
674         fixed20_12 a;
675
676         a.full = dfixed_const(1000);
677         sclk.full = dfixed_const(wm->sclk);
678         sclk.full = dfixed_div(sclk, a);
679         a.full = dfixed_const(10);
680         return_efficiency.full = dfixed_const(8);
681         return_efficiency.full = dfixed_div(return_efficiency, a);
682         a.full = dfixed_const(32);
683         bandwidth.full = dfixed_mul(a, sclk);
684         bandwidth.full = dfixed_mul(bandwidth, return_efficiency);
685
686         return dfixed_trunc(bandwidth);
687 }
688
689 static u32 evergreen_dmif_request_bandwidth(struct evergreen_wm_params *wm)
690 {
691         /* Calculate the DMIF Request Bandwidth */
692         fixed20_12 disp_clk_request_efficiency; /* 0.8 */
693         fixed20_12 disp_clk, bandwidth;
694         fixed20_12 a;
695
696         a.full = dfixed_const(1000);
697         disp_clk.full = dfixed_const(wm->disp_clk);
698         disp_clk.full = dfixed_div(disp_clk, a);
699         a.full = dfixed_const(10);
700         disp_clk_request_efficiency.full = dfixed_const(8);
701         disp_clk_request_efficiency.full = dfixed_div(disp_clk_request_efficiency, a);
702         a.full = dfixed_const(32);
703         bandwidth.full = dfixed_mul(a, disp_clk);
704         bandwidth.full = dfixed_mul(bandwidth, disp_clk_request_efficiency);
705
706         return dfixed_trunc(bandwidth);
707 }
708
709 static u32 evergreen_available_bandwidth(struct evergreen_wm_params *wm)
710 {
711         /* Calculate the Available bandwidth. Display can use this temporarily but not in average. */
712         u32 dram_bandwidth = evergreen_dram_bandwidth(wm);
713         u32 data_return_bandwidth = evergreen_data_return_bandwidth(wm);
714         u32 dmif_req_bandwidth = evergreen_dmif_request_bandwidth(wm);
715
716         return min(dram_bandwidth, min(data_return_bandwidth, dmif_req_bandwidth));
717 }
718
719 static u32 evergreen_average_bandwidth(struct evergreen_wm_params *wm)
720 {
721         /* Calculate the display mode Average Bandwidth
722          * DisplayMode should contain the source and destination dimensions,
723          * timing, etc.
724          */
725         fixed20_12 bpp;
726         fixed20_12 line_time;
727         fixed20_12 src_width;
728         fixed20_12 bandwidth;
729         fixed20_12 a;
730
731         a.full = dfixed_const(1000);
732         line_time.full = dfixed_const(wm->active_time + wm->blank_time);
733         line_time.full = dfixed_div(line_time, a);
734         bpp.full = dfixed_const(wm->bytes_per_pixel);
735         src_width.full = dfixed_const(wm->src_width);
736         bandwidth.full = dfixed_mul(src_width, bpp);
737         bandwidth.full = dfixed_mul(bandwidth, wm->vsc);
738         bandwidth.full = dfixed_div(bandwidth, line_time);
739
740         return dfixed_trunc(bandwidth);
741 }
742
743 static u32 evergreen_latency_watermark(struct evergreen_wm_params *wm)
744 {
745         /* First calcualte the latency in ns */
746         u32 mc_latency = 2000; /* 2000 ns. */
747         u32 available_bandwidth = evergreen_available_bandwidth(wm);
748         u32 worst_chunk_return_time = (512 * 8 * 1000) / available_bandwidth;
749         u32 cursor_line_pair_return_time = (128 * 4 * 1000) / available_bandwidth;
750         u32 dc_latency = 40000000 / wm->disp_clk; /* dc pipe latency */
751         u32 other_heads_data_return_time = ((wm->num_heads + 1) * worst_chunk_return_time) +
752                 (wm->num_heads * cursor_line_pair_return_time);
753         u32 latency = mc_latency + other_heads_data_return_time + dc_latency;
754         u32 max_src_lines_per_dst_line, lb_fill_bw, line_fill_time;
755         fixed20_12 a, b, c;
756
757         if (wm->num_heads == 0)
758                 return 0;
759
760         a.full = dfixed_const(2);
761         b.full = dfixed_const(1);
762         if ((wm->vsc.full > a.full) ||
763             ((wm->vsc.full > b.full) && (wm->vtaps >= 3)) ||
764             (wm->vtaps >= 5) ||
765             ((wm->vsc.full >= a.full) && wm->interlaced))
766                 max_src_lines_per_dst_line = 4;
767         else
768                 max_src_lines_per_dst_line = 2;
769
770         a.full = dfixed_const(available_bandwidth);
771         b.full = dfixed_const(wm->num_heads);
772         a.full = dfixed_div(a, b);
773
774         b.full = dfixed_const(1000);
775         c.full = dfixed_const(wm->disp_clk);
776         b.full = dfixed_div(c, b);
777         c.full = dfixed_const(wm->bytes_per_pixel);
778         b.full = dfixed_mul(b, c);
779
780         lb_fill_bw = min(dfixed_trunc(a), dfixed_trunc(b));
781
782         a.full = dfixed_const(max_src_lines_per_dst_line * wm->src_width * wm->bytes_per_pixel);
783         b.full = dfixed_const(1000);
784         c.full = dfixed_const(lb_fill_bw);
785         b.full = dfixed_div(c, b);
786         a.full = dfixed_div(a, b);
787         line_fill_time = dfixed_trunc(a);
788
789         if (line_fill_time < wm->active_time)
790                 return latency;
791         else
792                 return latency + (line_fill_time - wm->active_time);
793
794 }
795
796 static bool evergreen_average_bandwidth_vs_dram_bandwidth_for_display(struct evergreen_wm_params *wm)
797 {
798         if (evergreen_average_bandwidth(wm) <=
799             (evergreen_dram_bandwidth_for_display(wm) / wm->num_heads))
800                 return true;
801         else
802                 return false;
803 };
804
805 static bool evergreen_average_bandwidth_vs_available_bandwidth(struct evergreen_wm_params *wm)
806 {
807         if (evergreen_average_bandwidth(wm) <=
808             (evergreen_available_bandwidth(wm) / wm->num_heads))
809                 return true;
810         else
811                 return false;
812 };
813
814 static bool evergreen_check_latency_hiding(struct evergreen_wm_params *wm)
815 {
816         u32 lb_partitions = wm->lb_size / wm->src_width;
817         u32 line_time = wm->active_time + wm->blank_time;
818         u32 latency_tolerant_lines;
819         u32 latency_hiding;
820         fixed20_12 a;
821
822         a.full = dfixed_const(1);
823         if (wm->vsc.full > a.full)
824                 latency_tolerant_lines = 1;
825         else {
826                 if (lb_partitions <= (wm->vtaps + 1))
827                         latency_tolerant_lines = 1;
828                 else
829                         latency_tolerant_lines = 2;
830         }
831
832         latency_hiding = (latency_tolerant_lines * line_time + wm->blank_time);
833
834         if (evergreen_latency_watermark(wm) <= latency_hiding)
835                 return true;
836         else
837                 return false;
838 }
839
840 static void evergreen_program_watermarks(struct radeon_device *rdev,
841                                          struct radeon_crtc *radeon_crtc,
842                                          u32 lb_size, u32 num_heads)
843 {
844         struct drm_display_mode *mode = &radeon_crtc->base.mode;
845         struct evergreen_wm_params wm;
846         u32 pixel_period;
847         u32 line_time = 0;
848         u32 latency_watermark_a = 0, latency_watermark_b = 0;
849         u32 priority_a_mark = 0, priority_b_mark = 0;
850         u32 priority_a_cnt = PRIORITY_OFF;
851         u32 priority_b_cnt = PRIORITY_OFF;
852         u32 pipe_offset = radeon_crtc->crtc_id * 16;
853         u32 tmp, arb_control3;
854         fixed20_12 a, b, c;
855
856         if (radeon_crtc->base.enabled && num_heads && mode) {
857                 pixel_period = 1000000 / (u32)mode->clock;
858                 line_time = min((u32)mode->crtc_htotal * pixel_period, (u32)65535);
859                 priority_a_cnt = 0;
860                 priority_b_cnt = 0;
861
862                 wm.yclk = rdev->pm.current_mclk * 10;
863                 wm.sclk = rdev->pm.current_sclk * 10;
864                 wm.disp_clk = mode->clock;
865                 wm.src_width = mode->crtc_hdisplay;
866                 wm.active_time = mode->crtc_hdisplay * pixel_period;
867                 wm.blank_time = line_time - wm.active_time;
868                 wm.interlaced = false;
869                 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
870                         wm.interlaced = true;
871                 wm.vsc = radeon_crtc->vsc;
872                 wm.vtaps = 1;
873                 if (radeon_crtc->rmx_type != RMX_OFF)
874                         wm.vtaps = 2;
875                 wm.bytes_per_pixel = 4; /* XXX: get this from fb config */
876                 wm.lb_size = lb_size;
877                 wm.dram_channels = evergreen_get_number_of_dram_channels(rdev);
878                 wm.num_heads = num_heads;
879
880                 /* set for high clocks */
881                 latency_watermark_a = min(evergreen_latency_watermark(&wm), (u32)65535);
882                 /* set for low clocks */
883                 /* wm.yclk = low clk; wm.sclk = low clk */
884                 latency_watermark_b = min(evergreen_latency_watermark(&wm), (u32)65535);
885
886                 /* possibly force display priority to high */
887                 /* should really do this at mode validation time... */
888                 if (!evergreen_average_bandwidth_vs_dram_bandwidth_for_display(&wm) ||
889                     !evergreen_average_bandwidth_vs_available_bandwidth(&wm) ||
890                     !evergreen_check_latency_hiding(&wm) ||
891                     (rdev->disp_priority == 2)) {
892                         DRM_DEBUG_KMS("force priority to high\n");
893                         priority_a_cnt |= PRIORITY_ALWAYS_ON;
894                         priority_b_cnt |= PRIORITY_ALWAYS_ON;
895                 }
896
897                 a.full = dfixed_const(1000);
898                 b.full = dfixed_const(mode->clock);
899                 b.full = dfixed_div(b, a);
900                 c.full = dfixed_const(latency_watermark_a);
901                 c.full = dfixed_mul(c, b);
902                 c.full = dfixed_mul(c, radeon_crtc->hsc);
903                 c.full = dfixed_div(c, a);
904                 a.full = dfixed_const(16);
905                 c.full = dfixed_div(c, a);
906                 priority_a_mark = dfixed_trunc(c);
907                 priority_a_cnt |= priority_a_mark & PRIORITY_MARK_MASK;
908
909                 a.full = dfixed_const(1000);
910                 b.full = dfixed_const(mode->clock);
911                 b.full = dfixed_div(b, a);
912                 c.full = dfixed_const(latency_watermark_b);
913                 c.full = dfixed_mul(c, b);
914                 c.full = dfixed_mul(c, radeon_crtc->hsc);
915                 c.full = dfixed_div(c, a);
916                 a.full = dfixed_const(16);
917                 c.full = dfixed_div(c, a);
918                 priority_b_mark = dfixed_trunc(c);
919                 priority_b_cnt |= priority_b_mark & PRIORITY_MARK_MASK;
920         }
921
922         /* select wm A */
923         arb_control3 = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
924         tmp = arb_control3;
925         tmp &= ~LATENCY_WATERMARK_MASK(3);
926         tmp |= LATENCY_WATERMARK_MASK(1);
927         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
928         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
929                (LATENCY_LOW_WATERMARK(latency_watermark_a) |
930                 LATENCY_HIGH_WATERMARK(line_time)));
931         /* select wm B */
932         tmp = RREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset);
933         tmp &= ~LATENCY_WATERMARK_MASK(3);
934         tmp |= LATENCY_WATERMARK_MASK(2);
935         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, tmp);
936         WREG32(PIPE0_LATENCY_CONTROL + pipe_offset,
937                (LATENCY_LOW_WATERMARK(latency_watermark_b) |
938                 LATENCY_HIGH_WATERMARK(line_time)));
939         /* restore original selection */
940         WREG32(PIPE0_ARBITRATION_CONTROL3 + pipe_offset, arb_control3);
941
942         /* write the priority marks */
943         WREG32(PRIORITY_A_CNT + radeon_crtc->crtc_offset, priority_a_cnt);
944         WREG32(PRIORITY_B_CNT + radeon_crtc->crtc_offset, priority_b_cnt);
945
946 }
947
948 void evergreen_bandwidth_update(struct radeon_device *rdev)
949 {
950         struct drm_display_mode *mode0 = NULL;
951         struct drm_display_mode *mode1 = NULL;
952         u32 num_heads = 0, lb_size;
953         int i;
954
955         radeon_update_display_priority(rdev);
956
957         for (i = 0; i < rdev->num_crtc; i++) {
958                 if (rdev->mode_info.crtcs[i]->base.enabled)
959                         num_heads++;
960         }
961         for (i = 0; i < rdev->num_crtc; i += 2) {
962                 mode0 = &rdev->mode_info.crtcs[i]->base.mode;
963                 mode1 = &rdev->mode_info.crtcs[i+1]->base.mode;
964                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i], mode0, mode1);
965                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i], lb_size, num_heads);
966                 lb_size = evergreen_line_buffer_adjust(rdev, rdev->mode_info.crtcs[i+1], mode1, mode0);
967                 evergreen_program_watermarks(rdev, rdev->mode_info.crtcs[i+1], lb_size, num_heads);
968         }
969 }
970
971 int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
972 {
973         unsigned i;
974         u32 tmp;
975
976         for (i = 0; i < rdev->usec_timeout; i++) {
977                 /* read MC_STATUS */
978                 tmp = RREG32(SRBM_STATUS) & 0x1F00;
979                 if (!tmp)
980                         return 0;
981                 udelay(1);
982         }
983         return -1;
984 }
985
986 /*
987  * GART
988  */
989 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
990 {
991         unsigned i;
992         u32 tmp;
993
994         WREG32(HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
995
996         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
997         for (i = 0; i < rdev->usec_timeout; i++) {
998                 /* read MC_STATUS */
999                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
1000                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
1001                 if (tmp == 2) {
1002                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
1003                         return;
1004                 }
1005                 if (tmp) {
1006                         return;
1007                 }
1008                 udelay(1);
1009         }
1010 }
1011
1012 int evergreen_pcie_gart_enable(struct radeon_device *rdev)
1013 {
1014         u32 tmp;
1015         int r;
1016
1017         if (rdev->gart.robj == NULL) {
1018                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
1019                 return -EINVAL;
1020         }
1021         r = radeon_gart_table_vram_pin(rdev);
1022         if (r)
1023                 return r;
1024         radeon_gart_restore(rdev);
1025         /* Setup L2 cache */
1026         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1027                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1028                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1029         WREG32(VM_L2_CNTL2, 0);
1030         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1031         /* Setup TLB control */
1032         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1033                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1034                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1035                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1036         if (rdev->flags & RADEON_IS_IGP) {
1037                 WREG32(FUS_MC_VM_MD_L1_TLB0_CNTL, tmp);
1038                 WREG32(FUS_MC_VM_MD_L1_TLB1_CNTL, tmp);
1039                 WREG32(FUS_MC_VM_MD_L1_TLB2_CNTL, tmp);
1040         } else {
1041                 WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1042                 WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1043                 WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1044                 if ((rdev->family == CHIP_JUNIPER) ||
1045                     (rdev->family == CHIP_CYPRESS) ||
1046                     (rdev->family == CHIP_HEMLOCK) ||
1047                     (rdev->family == CHIP_BARTS))
1048                         WREG32(MC_VM_MD_L1_TLB3_CNTL, tmp);
1049         }
1050         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1051         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1052         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1053         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1054         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
1055         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
1056         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
1057         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
1058                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
1059         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
1060                         (u32)(rdev->dummy_page.addr >> 12));
1061         WREG32(VM_CONTEXT1_CNTL, 0);
1062
1063         evergreen_pcie_gart_tlb_flush(rdev);
1064         DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
1065                  (unsigned)(rdev->mc.gtt_size >> 20),
1066                  (unsigned long long)rdev->gart.table_addr);
1067         rdev->gart.ready = true;
1068         return 0;
1069 }
1070
1071 void evergreen_pcie_gart_disable(struct radeon_device *rdev)
1072 {
1073         u32 tmp;
1074
1075         /* Disable all tables */
1076         WREG32(VM_CONTEXT0_CNTL, 0);
1077         WREG32(VM_CONTEXT1_CNTL, 0);
1078
1079         /* Setup L2 cache */
1080         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
1081                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1082         WREG32(VM_L2_CNTL2, 0);
1083         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1084         /* Setup TLB control */
1085         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1086         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1087         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1088         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1089         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1090         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1091         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1092         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1093         radeon_gart_table_vram_unpin(rdev);
1094 }
1095
1096 void evergreen_pcie_gart_fini(struct radeon_device *rdev)
1097 {
1098         evergreen_pcie_gart_disable(rdev);
1099         radeon_gart_table_vram_free(rdev);
1100         radeon_gart_fini(rdev);
1101 }
1102
1103
1104 void evergreen_agp_enable(struct radeon_device *rdev)
1105 {
1106         u32 tmp;
1107
1108         /* Setup L2 cache */
1109         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1110                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1111                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1112         WREG32(VM_L2_CNTL2, 0);
1113         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
1114         /* Setup TLB control */
1115         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1116                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1117                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
1118                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
1119         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
1120         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
1121         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
1122         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
1123         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
1124         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
1125         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
1126         WREG32(VM_CONTEXT0_CNTL, 0);
1127         WREG32(VM_CONTEXT1_CNTL, 0);
1128 }
1129
1130 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
1131 {
1132         u32 crtc_enabled, tmp, frame_count, blackout;
1133         int i, j;
1134
1135         save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
1136         save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
1137
1138         /* disable VGA render */
1139         WREG32(VGA_RENDER_CONTROL, 0);
1140         /* blank the display controllers */
1141         for (i = 0; i < rdev->num_crtc; i++) {
1142                 crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN;
1143                 if (crtc_enabled) {
1144                         save->crtc_enabled[i] = true;
1145                         if (ASIC_IS_DCE6(rdev)) {
1146                                 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
1147                                 if (!(tmp & EVERGREEN_CRTC_BLANK_DATA_EN)) {
1148                                         radeon_wait_for_vblank(rdev, i);
1149                                         tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
1150                                         WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
1151                                 }
1152                         } else {
1153                                 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
1154                                 if (!(tmp & EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE)) {
1155                                         radeon_wait_for_vblank(rdev, i);
1156                                         tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
1157                                         WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
1158                                 }
1159                         }
1160                         /* wait for the next frame */
1161                         frame_count = radeon_get_vblank_counter(rdev, i);
1162                         for (j = 0; j < rdev->usec_timeout; j++) {
1163                                 if (radeon_get_vblank_counter(rdev, i) != frame_count)
1164                                         break;
1165                                 udelay(1);
1166                         }
1167                 } else {
1168                         save->crtc_enabled[i] = false;
1169                 }
1170         }
1171
1172         radeon_mc_wait_for_idle(rdev);
1173
1174         blackout = RREG32(MC_SHARED_BLACKOUT_CNTL);
1175         if ((blackout & BLACKOUT_MODE_MASK) != 1) {
1176                 /* Block CPU access */
1177                 WREG32(BIF_FB_EN, 0);
1178                 /* blackout the MC */
1179                 blackout &= ~BLACKOUT_MODE_MASK;
1180                 WREG32(MC_SHARED_BLACKOUT_CNTL, blackout | 1);
1181         }
1182 }
1183
1184 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
1185 {
1186         u32 tmp, frame_count;
1187         int i, j;
1188
1189         /* update crtc base addresses */
1190         for (i = 0; i < rdev->num_crtc; i++) {
1191                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
1192                        upper_32_bits(rdev->mc.vram_start));
1193                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + crtc_offsets[i],
1194                        upper_32_bits(rdev->mc.vram_start));
1195                 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
1196                        (u32)rdev->mc.vram_start);
1197                 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
1198                        (u32)rdev->mc.vram_start);
1199         }
1200         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
1201         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
1202
1203         /* unblackout the MC */
1204         tmp = RREG32(MC_SHARED_BLACKOUT_CNTL);
1205         tmp &= ~BLACKOUT_MODE_MASK;
1206         WREG32(MC_SHARED_BLACKOUT_CNTL, tmp);
1207         /* allow CPU access */
1208         WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
1209
1210         for (i = 0; i < rdev->num_crtc; i++) {
1211                 if (save->crtc_enabled) {
1212                         if (ASIC_IS_DCE6(rdev)) {
1213                                 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
1214                                 tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
1215                                 WREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i], tmp);
1216                         } else {
1217                                 tmp = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]);
1218                                 tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
1219                                 WREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i], tmp);
1220                         }
1221                         /* wait for the next frame */
1222                         frame_count = radeon_get_vblank_counter(rdev, i);
1223                         for (j = 0; j < rdev->usec_timeout; j++) {
1224                                 if (radeon_get_vblank_counter(rdev, i) != frame_count)
1225                                         break;
1226                                 udelay(1);
1227                         }
1228                 }
1229         }
1230         /* Unlock vga access */
1231         WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1232         mdelay(1);
1233         WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1234 }
1235
1236 void evergreen_mc_program(struct radeon_device *rdev)
1237 {
1238         struct evergreen_mc_save save;
1239         u32 tmp;
1240         int i, j;
1241
1242         /* Initialize HDP */
1243         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1244                 WREG32((0x2c14 + j), 0x00000000);
1245                 WREG32((0x2c18 + j), 0x00000000);
1246                 WREG32((0x2c1c + j), 0x00000000);
1247                 WREG32((0x2c20 + j), 0x00000000);
1248                 WREG32((0x2c24 + j), 0x00000000);
1249         }
1250         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1251
1252         evergreen_mc_stop(rdev, &save);
1253         if (evergreen_mc_wait_for_idle(rdev)) {
1254                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1255         }
1256         /* Lockout access through VGA aperture*/
1257         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1258         /* Update configuration */
1259         if (rdev->flags & RADEON_IS_AGP) {
1260                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1261                         /* VRAM before AGP */
1262                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1263                                 rdev->mc.vram_start >> 12);
1264                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1265                                 rdev->mc.gtt_end >> 12);
1266                 } else {
1267                         /* VRAM after AGP */
1268                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1269                                 rdev->mc.gtt_start >> 12);
1270                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1271                                 rdev->mc.vram_end >> 12);
1272                 }
1273         } else {
1274                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1275                         rdev->mc.vram_start >> 12);
1276                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1277                         rdev->mc.vram_end >> 12);
1278         }
1279         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
1280         /* llano/ontario only */
1281         if ((rdev->family == CHIP_PALM) ||
1282             (rdev->family == CHIP_SUMO) ||
1283             (rdev->family == CHIP_SUMO2)) {
1284                 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1285                 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1286                 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1287                 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1288         }
1289         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1290         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1291         WREG32(MC_VM_FB_LOCATION, tmp);
1292         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1293         WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
1294         WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1295         if (rdev->flags & RADEON_IS_AGP) {
1296                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
1297                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
1298                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1299         } else {
1300                 WREG32(MC_VM_AGP_BASE, 0);
1301                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1302                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1303         }
1304         if (evergreen_mc_wait_for_idle(rdev)) {
1305                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1306         }
1307         evergreen_mc_resume(rdev, &save);
1308         /* we need to own VRAM, so turn off the VGA renderer here
1309          * to stop it overwriting our objects */
1310         rv515_vga_render_disable(rdev);
1311 }
1312
1313 /*
1314  * CP.
1315  */
1316 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1317 {
1318         struct radeon_ring *ring = &rdev->ring[ib->fence->ring];
1319
1320         /* set to DX10/11 mode */
1321         radeon_ring_write(ring, PACKET3(PACKET3_MODE_CONTROL, 0));
1322         radeon_ring_write(ring, 1);
1323         /* FIXME: implement */
1324         radeon_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1325         radeon_ring_write(ring,
1326 #ifdef __BIG_ENDIAN
1327                           (2 << 0) |
1328 #endif
1329                           (ib->gpu_addr & 0xFFFFFFFC));
1330         radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xFF);
1331         radeon_ring_write(ring, ib->length_dw);
1332 }
1333
1334
1335 static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1336 {
1337         const __be32 *fw_data;
1338         int i;
1339
1340         if (!rdev->me_fw || !rdev->pfp_fw)
1341                 return -EINVAL;
1342
1343         r700_cp_stop(rdev);
1344         WREG32(CP_RB_CNTL,
1345 #ifdef __BIG_ENDIAN
1346                BUF_SWAP_32BIT |
1347 #endif
1348                RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1349
1350         fw_data = (const __be32 *)rdev->pfp_fw->data;
1351         WREG32(CP_PFP_UCODE_ADDR, 0);
1352         for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
1353                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
1354         WREG32(CP_PFP_UCODE_ADDR, 0);
1355
1356         fw_data = (const __be32 *)rdev->me_fw->data;
1357         WREG32(CP_ME_RAM_WADDR, 0);
1358         for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
1359                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
1360
1361         WREG32(CP_PFP_UCODE_ADDR, 0);
1362         WREG32(CP_ME_RAM_WADDR, 0);
1363         WREG32(CP_ME_RAM_RADDR, 0);
1364         return 0;
1365 }
1366
1367 static int evergreen_cp_start(struct radeon_device *rdev)
1368 {
1369         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1370         int r, i;
1371         uint32_t cp_me;
1372
1373         r = radeon_ring_lock(rdev, ring, 7);
1374         if (r) {
1375                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1376                 return r;
1377         }
1378         radeon_ring_write(ring, PACKET3(PACKET3_ME_INITIALIZE, 5));
1379         radeon_ring_write(ring, 0x1);
1380         radeon_ring_write(ring, 0x0);
1381         radeon_ring_write(ring, rdev->config.evergreen.max_hw_contexts - 1);
1382         radeon_ring_write(ring, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1383         radeon_ring_write(ring, 0);
1384         radeon_ring_write(ring, 0);
1385         radeon_ring_unlock_commit(rdev, ring);
1386
1387         cp_me = 0xff;
1388         WREG32(CP_ME_CNTL, cp_me);
1389
1390         r = radeon_ring_lock(rdev, ring, evergreen_default_size + 19);
1391         if (r) {
1392                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1393                 return r;
1394         }
1395
1396         /* setup clear context state */
1397         radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1398         radeon_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
1399
1400         for (i = 0; i < evergreen_default_size; i++)
1401                 radeon_ring_write(ring, evergreen_default_state[i]);
1402
1403         radeon_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
1404         radeon_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
1405
1406         /* set clear context state */
1407         radeon_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
1408         radeon_ring_write(ring, 0);
1409
1410         /* SQ_VTX_BASE_VTX_LOC */
1411         radeon_ring_write(ring, 0xc0026f00);
1412         radeon_ring_write(ring, 0x00000000);
1413         radeon_ring_write(ring, 0x00000000);
1414         radeon_ring_write(ring, 0x00000000);
1415
1416         /* Clear consts */
1417         radeon_ring_write(ring, 0xc0036f00);
1418         radeon_ring_write(ring, 0x00000bc4);
1419         radeon_ring_write(ring, 0xffffffff);
1420         radeon_ring_write(ring, 0xffffffff);
1421         radeon_ring_write(ring, 0xffffffff);
1422
1423         radeon_ring_write(ring, 0xc0026900);
1424         radeon_ring_write(ring, 0x00000316);
1425         radeon_ring_write(ring, 0x0000000e); /* VGT_VERTEX_REUSE_BLOCK_CNTL */
1426         radeon_ring_write(ring, 0x00000010); /*  */
1427
1428         radeon_ring_unlock_commit(rdev, ring);
1429
1430         return 0;
1431 }
1432
1433 int evergreen_cp_resume(struct radeon_device *rdev)
1434 {
1435         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
1436         u32 tmp;
1437         u32 rb_bufsz;
1438         int r;
1439
1440         /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
1441         WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
1442                                  SOFT_RESET_PA |
1443                                  SOFT_RESET_SH |
1444                                  SOFT_RESET_VGT |
1445                                  SOFT_RESET_SPI |
1446                                  SOFT_RESET_SX));
1447         RREG32(GRBM_SOFT_RESET);
1448         mdelay(15);
1449         WREG32(GRBM_SOFT_RESET, 0);
1450         RREG32(GRBM_SOFT_RESET);
1451
1452         /* Set ring buffer size */
1453         rb_bufsz = drm_order(ring->ring_size / 8);
1454         tmp = (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1455 #ifdef __BIG_ENDIAN
1456         tmp |= BUF_SWAP_32BIT;
1457 #endif
1458         WREG32(CP_RB_CNTL, tmp);
1459         WREG32(CP_SEM_WAIT_TIMER, 0x0);
1460         WREG32(CP_SEM_INCOMPLETE_TIMER_CNTL, 0x0);
1461
1462         /* Set the write pointer delay */
1463         WREG32(CP_RB_WPTR_DELAY, 0);
1464
1465         /* Initialize the ring buffer's read and write pointers */
1466         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1467         WREG32(CP_RB_RPTR_WR, 0);
1468         ring->wptr = 0;
1469         WREG32(CP_RB_WPTR, ring->wptr);
1470
1471         /* set the wb address wether it's enabled or not */
1472         WREG32(CP_RB_RPTR_ADDR,
1473                ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
1474         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1475         WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1476
1477         if (rdev->wb.enabled)
1478                 WREG32(SCRATCH_UMSK, 0xff);
1479         else {
1480                 tmp |= RB_NO_UPDATE;
1481                 WREG32(SCRATCH_UMSK, 0);
1482         }
1483
1484         mdelay(1);
1485         WREG32(CP_RB_CNTL, tmp);
1486
1487         WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
1488         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1489
1490         ring->rptr = RREG32(CP_RB_RPTR);
1491
1492         evergreen_cp_start(rdev);
1493         ring->ready = true;
1494         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
1495         if (r) {
1496                 ring->ready = false;
1497                 return r;
1498         }
1499         return 0;
1500 }
1501
1502 /*
1503  * Core functions
1504  */
1505 static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1506                                                   u32 num_tile_pipes,
1507                                                   u32 num_backends,
1508                                                   u32 backend_disable_mask)
1509 {
1510         u32 backend_map = 0;
1511         u32 enabled_backends_mask = 0;
1512         u32 enabled_backends_count = 0;
1513         u32 cur_pipe;
1514         u32 swizzle_pipe[EVERGREEN_MAX_PIPES];
1515         u32 cur_backend = 0;
1516         u32 i;
1517         bool force_no_swizzle;
1518
1519         if (num_tile_pipes > EVERGREEN_MAX_PIPES)
1520                 num_tile_pipes = EVERGREEN_MAX_PIPES;
1521         if (num_tile_pipes < 1)
1522                 num_tile_pipes = 1;
1523         if (num_backends > EVERGREEN_MAX_BACKENDS)
1524                 num_backends = EVERGREEN_MAX_BACKENDS;
1525         if (num_backends < 1)
1526                 num_backends = 1;
1527
1528         for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1529                 if (((backend_disable_mask >> i) & 1) == 0) {
1530                         enabled_backends_mask |= (1 << i);
1531                         ++enabled_backends_count;
1532                 }
1533                 if (enabled_backends_count == num_backends)
1534                         break;
1535         }
1536
1537         if (enabled_backends_count == 0) {
1538                 enabled_backends_mask = 1;
1539                 enabled_backends_count = 1;
1540         }
1541
1542         if (enabled_backends_count != num_backends)
1543                 num_backends = enabled_backends_count;
1544
1545         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES);
1546         switch (rdev->family) {
1547         case CHIP_CEDAR:
1548         case CHIP_REDWOOD:
1549         case CHIP_PALM:
1550         case CHIP_SUMO:
1551         case CHIP_SUMO2:
1552         case CHIP_TURKS:
1553         case CHIP_CAICOS:
1554                 force_no_swizzle = false;
1555                 break;
1556         case CHIP_CYPRESS:
1557         case CHIP_HEMLOCK:
1558         case CHIP_JUNIPER:
1559         case CHIP_BARTS:
1560         default:
1561                 force_no_swizzle = true;
1562                 break;
1563         }
1564         if (force_no_swizzle) {
1565                 bool last_backend_enabled = false;
1566
1567                 force_no_swizzle = false;
1568                 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
1569                         if (((enabled_backends_mask >> i) & 1) == 1) {
1570                                 if (last_backend_enabled)
1571                                         force_no_swizzle = true;
1572                                 last_backend_enabled = true;
1573                         } else
1574                                 last_backend_enabled = false;
1575                 }
1576         }
1577
1578         switch (num_tile_pipes) {
1579         case 1:
1580         case 3:
1581         case 5:
1582         case 7:
1583                 DRM_ERROR("odd number of pipes!\n");
1584                 break;
1585         case 2:
1586                 swizzle_pipe[0] = 0;
1587                 swizzle_pipe[1] = 1;
1588                 break;
1589         case 4:
1590                 if (force_no_swizzle) {
1591                         swizzle_pipe[0] = 0;
1592                         swizzle_pipe[1] = 1;
1593                         swizzle_pipe[2] = 2;
1594                         swizzle_pipe[3] = 3;
1595                 } else {
1596                         swizzle_pipe[0] = 0;
1597                         swizzle_pipe[1] = 2;
1598                         swizzle_pipe[2] = 1;
1599                         swizzle_pipe[3] = 3;
1600                 }
1601                 break;
1602         case 6:
1603                 if (force_no_swizzle) {
1604                         swizzle_pipe[0] = 0;
1605                         swizzle_pipe[1] = 1;
1606                         swizzle_pipe[2] = 2;
1607                         swizzle_pipe[3] = 3;
1608                         swizzle_pipe[4] = 4;
1609                         swizzle_pipe[5] = 5;
1610                 } else {
1611                         swizzle_pipe[0] = 0;
1612                         swizzle_pipe[1] = 2;
1613                         swizzle_pipe[2] = 4;
1614                         swizzle_pipe[3] = 1;
1615                         swizzle_pipe[4] = 3;
1616                         swizzle_pipe[5] = 5;
1617                 }
1618                 break;
1619         case 8:
1620                 if (force_no_swizzle) {
1621                         swizzle_pipe[0] = 0;
1622                         swizzle_pipe[1] = 1;
1623                         swizzle_pipe[2] = 2;
1624                         swizzle_pipe[3] = 3;
1625                         swizzle_pipe[4] = 4;
1626                         swizzle_pipe[5] = 5;
1627                         swizzle_pipe[6] = 6;
1628                         swizzle_pipe[7] = 7;
1629                 } else {
1630                         swizzle_pipe[0] = 0;
1631                         swizzle_pipe[1] = 2;
1632                         swizzle_pipe[2] = 4;
1633                         swizzle_pipe[3] = 6;
1634                         swizzle_pipe[4] = 1;
1635                         swizzle_pipe[5] = 3;
1636                         swizzle_pipe[6] = 5;
1637                         swizzle_pipe[7] = 7;
1638                 }
1639                 break;
1640         }
1641
1642         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1643                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1644                         cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1645
1646                 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
1647
1648                 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
1649         }
1650
1651         return backend_map;
1652 }
1653
1654 static void evergreen_gpu_init(struct radeon_device *rdev)
1655 {
1656         u32 cc_rb_backend_disable = 0;
1657         u32 cc_gc_shader_pipe_config;
1658         u32 gb_addr_config = 0;
1659         u32 mc_shared_chmap, mc_arb_ramcfg;
1660         u32 gb_backend_map;
1661         u32 grbm_gfx_index;
1662         u32 sx_debug_1;
1663         u32 smx_dc_ctl0;
1664         u32 sq_config;
1665         u32 sq_lds_resource_mgmt;
1666         u32 sq_gpr_resource_mgmt_1;
1667         u32 sq_gpr_resource_mgmt_2;
1668         u32 sq_gpr_resource_mgmt_3;
1669         u32 sq_thread_resource_mgmt;
1670         u32 sq_thread_resource_mgmt_2;
1671         u32 sq_stack_resource_mgmt_1;
1672         u32 sq_stack_resource_mgmt_2;
1673         u32 sq_stack_resource_mgmt_3;
1674         u32 vgt_cache_invalidation;
1675         u32 hdp_host_path_cntl, tmp;
1676         int i, j, num_shader_engines, ps_thread_count;
1677
1678         switch (rdev->family) {
1679         case CHIP_CYPRESS:
1680         case CHIP_HEMLOCK:
1681                 rdev->config.evergreen.num_ses = 2;
1682                 rdev->config.evergreen.max_pipes = 4;
1683                 rdev->config.evergreen.max_tile_pipes = 8;
1684                 rdev->config.evergreen.max_simds = 10;
1685                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1686                 rdev->config.evergreen.max_gprs = 256;
1687                 rdev->config.evergreen.max_threads = 248;
1688                 rdev->config.evergreen.max_gs_threads = 32;
1689                 rdev->config.evergreen.max_stack_entries = 512;
1690                 rdev->config.evergreen.sx_num_of_sets = 4;
1691                 rdev->config.evergreen.sx_max_export_size = 256;
1692                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1693                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1694                 rdev->config.evergreen.max_hw_contexts = 8;
1695                 rdev->config.evergreen.sq_num_cf_insts = 2;
1696
1697                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1698                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1699                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1700                 break;
1701         case CHIP_JUNIPER:
1702                 rdev->config.evergreen.num_ses = 1;
1703                 rdev->config.evergreen.max_pipes = 4;
1704                 rdev->config.evergreen.max_tile_pipes = 4;
1705                 rdev->config.evergreen.max_simds = 10;
1706                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1707                 rdev->config.evergreen.max_gprs = 256;
1708                 rdev->config.evergreen.max_threads = 248;
1709                 rdev->config.evergreen.max_gs_threads = 32;
1710                 rdev->config.evergreen.max_stack_entries = 512;
1711                 rdev->config.evergreen.sx_num_of_sets = 4;
1712                 rdev->config.evergreen.sx_max_export_size = 256;
1713                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1714                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1715                 rdev->config.evergreen.max_hw_contexts = 8;
1716                 rdev->config.evergreen.sq_num_cf_insts = 2;
1717
1718                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1719                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1720                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1721                 break;
1722         case CHIP_REDWOOD:
1723                 rdev->config.evergreen.num_ses = 1;
1724                 rdev->config.evergreen.max_pipes = 4;
1725                 rdev->config.evergreen.max_tile_pipes = 4;
1726                 rdev->config.evergreen.max_simds = 5;
1727                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1728                 rdev->config.evergreen.max_gprs = 256;
1729                 rdev->config.evergreen.max_threads = 248;
1730                 rdev->config.evergreen.max_gs_threads = 32;
1731                 rdev->config.evergreen.max_stack_entries = 256;
1732                 rdev->config.evergreen.sx_num_of_sets = 4;
1733                 rdev->config.evergreen.sx_max_export_size = 256;
1734                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1735                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1736                 rdev->config.evergreen.max_hw_contexts = 8;
1737                 rdev->config.evergreen.sq_num_cf_insts = 2;
1738
1739                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1740                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1741                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1742                 break;
1743         case CHIP_CEDAR:
1744         default:
1745                 rdev->config.evergreen.num_ses = 1;
1746                 rdev->config.evergreen.max_pipes = 2;
1747                 rdev->config.evergreen.max_tile_pipes = 2;
1748                 rdev->config.evergreen.max_simds = 2;
1749                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1750                 rdev->config.evergreen.max_gprs = 256;
1751                 rdev->config.evergreen.max_threads = 192;
1752                 rdev->config.evergreen.max_gs_threads = 16;
1753                 rdev->config.evergreen.max_stack_entries = 256;
1754                 rdev->config.evergreen.sx_num_of_sets = 4;
1755                 rdev->config.evergreen.sx_max_export_size = 128;
1756                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1757                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1758                 rdev->config.evergreen.max_hw_contexts = 4;
1759                 rdev->config.evergreen.sq_num_cf_insts = 1;
1760
1761                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1762                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1763                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1764                 break;
1765         case CHIP_PALM:
1766                 rdev->config.evergreen.num_ses = 1;
1767                 rdev->config.evergreen.max_pipes = 2;
1768                 rdev->config.evergreen.max_tile_pipes = 2;
1769                 rdev->config.evergreen.max_simds = 2;
1770                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1771                 rdev->config.evergreen.max_gprs = 256;
1772                 rdev->config.evergreen.max_threads = 192;
1773                 rdev->config.evergreen.max_gs_threads = 16;
1774                 rdev->config.evergreen.max_stack_entries = 256;
1775                 rdev->config.evergreen.sx_num_of_sets = 4;
1776                 rdev->config.evergreen.sx_max_export_size = 128;
1777                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1778                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1779                 rdev->config.evergreen.max_hw_contexts = 4;
1780                 rdev->config.evergreen.sq_num_cf_insts = 1;
1781
1782                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1783                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1784                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1785                 break;
1786         case CHIP_SUMO:
1787                 rdev->config.evergreen.num_ses = 1;
1788                 rdev->config.evergreen.max_pipes = 4;
1789                 rdev->config.evergreen.max_tile_pipes = 2;
1790                 if (rdev->pdev->device == 0x9648)
1791                         rdev->config.evergreen.max_simds = 3;
1792                 else if ((rdev->pdev->device == 0x9647) ||
1793                          (rdev->pdev->device == 0x964a))
1794                         rdev->config.evergreen.max_simds = 4;
1795                 else
1796                         rdev->config.evergreen.max_simds = 5;
1797                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1798                 rdev->config.evergreen.max_gprs = 256;
1799                 rdev->config.evergreen.max_threads = 248;
1800                 rdev->config.evergreen.max_gs_threads = 32;
1801                 rdev->config.evergreen.max_stack_entries = 256;
1802                 rdev->config.evergreen.sx_num_of_sets = 4;
1803                 rdev->config.evergreen.sx_max_export_size = 256;
1804                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1805                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1806                 rdev->config.evergreen.max_hw_contexts = 8;
1807                 rdev->config.evergreen.sq_num_cf_insts = 2;
1808
1809                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1810                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1811                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1812                 break;
1813         case CHIP_SUMO2:
1814                 rdev->config.evergreen.num_ses = 1;
1815                 rdev->config.evergreen.max_pipes = 4;
1816                 rdev->config.evergreen.max_tile_pipes = 4;
1817                 rdev->config.evergreen.max_simds = 2;
1818                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1819                 rdev->config.evergreen.max_gprs = 256;
1820                 rdev->config.evergreen.max_threads = 248;
1821                 rdev->config.evergreen.max_gs_threads = 32;
1822                 rdev->config.evergreen.max_stack_entries = 512;
1823                 rdev->config.evergreen.sx_num_of_sets = 4;
1824                 rdev->config.evergreen.sx_max_export_size = 256;
1825                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1826                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1827                 rdev->config.evergreen.max_hw_contexts = 8;
1828                 rdev->config.evergreen.sq_num_cf_insts = 2;
1829
1830                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1831                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1832                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1833                 break;
1834         case CHIP_BARTS:
1835                 rdev->config.evergreen.num_ses = 2;
1836                 rdev->config.evergreen.max_pipes = 4;
1837                 rdev->config.evergreen.max_tile_pipes = 8;
1838                 rdev->config.evergreen.max_simds = 7;
1839                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1840                 rdev->config.evergreen.max_gprs = 256;
1841                 rdev->config.evergreen.max_threads = 248;
1842                 rdev->config.evergreen.max_gs_threads = 32;
1843                 rdev->config.evergreen.max_stack_entries = 512;
1844                 rdev->config.evergreen.sx_num_of_sets = 4;
1845                 rdev->config.evergreen.sx_max_export_size = 256;
1846                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1847                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1848                 rdev->config.evergreen.max_hw_contexts = 8;
1849                 rdev->config.evergreen.sq_num_cf_insts = 2;
1850
1851                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1852                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1853                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1854                 break;
1855         case CHIP_TURKS:
1856                 rdev->config.evergreen.num_ses = 1;
1857                 rdev->config.evergreen.max_pipes = 4;
1858                 rdev->config.evergreen.max_tile_pipes = 4;
1859                 rdev->config.evergreen.max_simds = 6;
1860                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1861                 rdev->config.evergreen.max_gprs = 256;
1862                 rdev->config.evergreen.max_threads = 248;
1863                 rdev->config.evergreen.max_gs_threads = 32;
1864                 rdev->config.evergreen.max_stack_entries = 256;
1865                 rdev->config.evergreen.sx_num_of_sets = 4;
1866                 rdev->config.evergreen.sx_max_export_size = 256;
1867                 rdev->config.evergreen.sx_max_export_pos_size = 64;
1868                 rdev->config.evergreen.sx_max_export_smx_size = 192;
1869                 rdev->config.evergreen.max_hw_contexts = 8;
1870                 rdev->config.evergreen.sq_num_cf_insts = 2;
1871
1872                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1873                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1874                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1875                 break;
1876         case CHIP_CAICOS:
1877                 rdev->config.evergreen.num_ses = 1;
1878                 rdev->config.evergreen.max_pipes = 4;
1879                 rdev->config.evergreen.max_tile_pipes = 2;
1880                 rdev->config.evergreen.max_simds = 2;
1881                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1882                 rdev->config.evergreen.max_gprs = 256;
1883                 rdev->config.evergreen.max_threads = 192;
1884                 rdev->config.evergreen.max_gs_threads = 16;
1885                 rdev->config.evergreen.max_stack_entries = 256;
1886                 rdev->config.evergreen.sx_num_of_sets = 4;
1887                 rdev->config.evergreen.sx_max_export_size = 128;
1888                 rdev->config.evergreen.sx_max_export_pos_size = 32;
1889                 rdev->config.evergreen.sx_max_export_smx_size = 96;
1890                 rdev->config.evergreen.max_hw_contexts = 4;
1891                 rdev->config.evergreen.sq_num_cf_insts = 1;
1892
1893                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1894                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1895                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1896                 break;
1897         }
1898
1899         /* Initialize HDP */
1900         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1901                 WREG32((0x2c14 + j), 0x00000000);
1902                 WREG32((0x2c18 + j), 0x00000000);
1903                 WREG32((0x2c1c + j), 0x00000000);
1904                 WREG32((0x2c20 + j), 0x00000000);
1905                 WREG32((0x2c24 + j), 0x00000000);
1906         }
1907
1908         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1909
1910         evergreen_fix_pci_max_read_req_size(rdev);
1911
1912         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
1913
1914         cc_gc_shader_pipe_config |=
1915                 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
1916                                   & EVERGREEN_MAX_PIPES_MASK);
1917         cc_gc_shader_pipe_config |=
1918                 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
1919                                & EVERGREEN_MAX_SIMDS_MASK);
1920
1921         cc_rb_backend_disable =
1922                 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
1923                                 & EVERGREEN_MAX_BACKENDS_MASK);
1924
1925
1926         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
1927         if ((rdev->family == CHIP_PALM) ||
1928             (rdev->family == CHIP_SUMO) ||
1929             (rdev->family == CHIP_SUMO2))
1930                 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
1931         else
1932                 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1933
1934         switch (rdev->config.evergreen.max_tile_pipes) {
1935         case 1:
1936         default:
1937                 gb_addr_config |= NUM_PIPES(0);
1938                 break;
1939         case 2:
1940                 gb_addr_config |= NUM_PIPES(1);
1941                 break;
1942         case 4:
1943                 gb_addr_config |= NUM_PIPES(2);
1944                 break;
1945         case 8:
1946                 gb_addr_config |= NUM_PIPES(3);
1947                 break;
1948         }
1949
1950         gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1951         gb_addr_config |= BANK_INTERLEAVE_SIZE(0);
1952         gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1);
1953         gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1);
1954         gb_addr_config |= NUM_GPUS(0); /* Hemlock? */
1955         gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
1956
1957         if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2)
1958                 gb_addr_config |= ROW_SIZE(2);
1959         else
1960                 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
1961
1962         if (rdev->ddev->pdev->device == 0x689e) {
1963                 u32 efuse_straps_4;
1964                 u32 efuse_straps_3;
1965                 u8 efuse_box_bit_131_124;
1966
1967                 WREG32(RCU_IND_INDEX, 0x204);
1968                 efuse_straps_4 = RREG32(RCU_IND_DATA);
1969                 WREG32(RCU_IND_INDEX, 0x203);
1970                 efuse_straps_3 = RREG32(RCU_IND_DATA);
1971                 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
1972
1973                 switch(efuse_box_bit_131_124) {
1974                 case 0x00:
1975                         gb_backend_map = 0x76543210;
1976                         break;
1977                 case 0x55:
1978                         gb_backend_map = 0x77553311;
1979                         break;
1980                 case 0x56:
1981                         gb_backend_map = 0x77553300;
1982                         break;
1983                 case 0x59:
1984                         gb_backend_map = 0x77552211;
1985                         break;
1986                 case 0x66:
1987                         gb_backend_map = 0x77443300;
1988                         break;
1989                 case 0x99:
1990                         gb_backend_map = 0x66552211;
1991                         break;
1992                 case 0x5a:
1993                         gb_backend_map = 0x77552200;
1994                         break;
1995                 case 0xaa:
1996                         gb_backend_map = 0x66442200;
1997                         break;
1998                 case 0x95:
1999                         gb_backend_map = 0x66553311;
2000                         break;
2001                 default:
2002                         DRM_ERROR("bad backend map, using default\n");
2003                         gb_backend_map =
2004                                 evergreen_get_tile_pipe_to_backend_map(rdev,
2005                                                                        rdev->config.evergreen.max_tile_pipes,
2006                                                                        rdev->config.evergreen.max_backends,
2007                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
2008                                                                    rdev->config.evergreen.max_backends) &
2009                                                                         EVERGREEN_MAX_BACKENDS_MASK));
2010                         break;
2011                 }
2012         } else if (rdev->ddev->pdev->device == 0x68b9) {
2013                 u32 efuse_straps_3;
2014                 u8 efuse_box_bit_127_124;
2015
2016                 WREG32(RCU_IND_INDEX, 0x203);
2017                 efuse_straps_3 = RREG32(RCU_IND_DATA);
2018                 efuse_box_bit_127_124 = (u8)((efuse_straps_3 & 0xF0000000) >> 28);
2019
2020                 switch(efuse_box_bit_127_124) {
2021                 case 0x0:
2022                         gb_backend_map = 0x00003210;
2023                         break;
2024                 case 0x5:
2025                 case 0x6:
2026                 case 0x9:
2027                 case 0xa:
2028                         gb_backend_map = 0x00003311;
2029                         break;
2030                 default:
2031                         DRM_ERROR("bad backend map, using default\n");
2032                         gb_backend_map =
2033                                 evergreen_get_tile_pipe_to_backend_map(rdev,
2034                                                                        rdev->config.evergreen.max_tile_pipes,
2035                                                                        rdev->config.evergreen.max_backends,
2036                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
2037                                                                    rdev->config.evergreen.max_backends) &
2038                                                                         EVERGREEN_MAX_BACKENDS_MASK));
2039                         break;
2040                 }
2041         } else {
2042                 switch (rdev->family) {
2043                 case CHIP_CYPRESS:
2044                 case CHIP_HEMLOCK:
2045                 case CHIP_BARTS:
2046                         gb_backend_map = 0x66442200;
2047                         break;
2048                 case CHIP_JUNIPER:
2049                         gb_backend_map = 0x00002200;
2050                         break;
2051                 default:
2052                         gb_backend_map =
2053                                 evergreen_get_tile_pipe_to_backend_map(rdev,
2054                                                                        rdev->config.evergreen.max_tile_pipes,
2055                                                                        rdev->config.evergreen.max_backends,
2056                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
2057                                                                          rdev->config.evergreen.max_backends) &
2058                                                                         EVERGREEN_MAX_BACKENDS_MASK));
2059                 }
2060         }
2061
2062         /* setup tiling info dword.  gb_addr_config is not adequate since it does
2063          * not have bank info, so create a custom tiling dword.
2064          * bits 3:0   num_pipes
2065          * bits 7:4   num_banks
2066          * bits 11:8  group_size
2067          * bits 15:12 row_size
2068          */
2069         rdev->config.evergreen.tile_config = 0;
2070         switch (rdev->config.evergreen.max_tile_pipes) {
2071         case 1:
2072         default:
2073                 rdev->config.evergreen.tile_config |= (0 << 0);
2074                 break;
2075         case 2:
2076                 rdev->config.evergreen.tile_config |= (1 << 0);
2077                 break;
2078         case 4:
2079                 rdev->config.evergreen.tile_config |= (2 << 0);
2080                 break;
2081         case 8:
2082                 rdev->config.evergreen.tile_config |= (3 << 0);
2083                 break;
2084         }
2085         /* num banks is 8 on all fusion asics. 0 = 4, 1 = 8, 2 = 16 */
2086         if (rdev->flags & RADEON_IS_IGP)
2087                 rdev->config.evergreen.tile_config |= 1 << 4;
2088         else {
2089                 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
2090                 case 0: /* four banks */
2091                         rdev->config.evergreen.tile_config |= 0 << 4;
2092                         break;
2093                 case 1: /* eight banks */
2094                         rdev->config.evergreen.tile_config |= 1 << 4;
2095                         break;
2096                 case 2: /* sixteen banks */
2097                 default:
2098                         rdev->config.evergreen.tile_config |= 2 << 4;
2099                         break;
2100                 }
2101         }
2102         rdev->config.evergreen.tile_config |=
2103                 ((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT) << 8;
2104         rdev->config.evergreen.tile_config |=
2105                 ((gb_addr_config & 0x30000000) >> 28) << 12;
2106
2107         rdev->config.evergreen.backend_map = gb_backend_map;
2108         WREG32(GB_BACKEND_MAP, gb_backend_map);
2109         WREG32(GB_ADDR_CONFIG, gb_addr_config);
2110         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
2111         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
2112
2113         num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
2114         grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
2115
2116         for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
2117                 u32 rb = cc_rb_backend_disable | (0xf0 << 16);
2118                 u32 sp = cc_gc_shader_pipe_config;
2119                 u32 gfx = grbm_gfx_index | SE_INDEX(i);
2120
2121                 if (i == num_shader_engines) {
2122                         rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
2123                         sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
2124                 }
2125
2126                 WREG32(GRBM_GFX_INDEX, gfx);
2127                 WREG32(RLC_GFX_INDEX, gfx);
2128
2129                 WREG32(CC_RB_BACKEND_DISABLE, rb);
2130                 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
2131                 WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
2132                 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
2133         }
2134
2135         grbm_gfx_index = INSTANCE_BROADCAST_WRITES | SE_BROADCAST_WRITES;
2136         WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
2137         WREG32(RLC_GFX_INDEX, grbm_gfx_index);
2138
2139         WREG32(CGTS_SYS_TCC_DISABLE, 0);
2140         WREG32(CGTS_TCC_DISABLE, 0);
2141         WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
2142         WREG32(CGTS_USER_TCC_DISABLE, 0);
2143
2144         /* set HW defaults for 3D engine */
2145         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
2146                                      ROQ_IB2_START(0x2b)));
2147
2148         WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
2149
2150         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
2151                              SYNC_GRADIENT |
2152                              SYNC_WALKER |
2153                              SYNC_ALIGNER));
2154
2155         sx_debug_1 = RREG32(SX_DEBUG_1);
2156         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
2157         WREG32(SX_DEBUG_1, sx_debug_1);
2158
2159
2160         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
2161         smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
2162         smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
2163         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
2164
2165         if (rdev->family <= CHIP_SUMO2)
2166                 WREG32(SMX_SAR_CTL0, 0x00010000);
2167
2168         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
2169                                         POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
2170                                         SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
2171
2172         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
2173                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
2174                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
2175
2176         WREG32(VGT_NUM_INSTANCES, 1);
2177         WREG32(SPI_CONFIG_CNTL, 0);
2178         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
2179         WREG32(CP_PERFMON_CNTL, 0);
2180
2181         WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
2182                                   FETCH_FIFO_HIWATER(0x4) |
2183                                   DONE_FIFO_HIWATER(0xe0) |
2184                                   ALU_UPDATE_FIFO_HIWATER(0x8)));
2185
2186         sq_config = RREG32(SQ_CONFIG);
2187         sq_config &= ~(PS_PRIO(3) |
2188                        VS_PRIO(3) |
2189                        GS_PRIO(3) |
2190                        ES_PRIO(3));
2191         sq_config |= (VC_ENABLE |
2192                       EXPORT_SRC_C |
2193                       PS_PRIO(0) |
2194                       VS_PRIO(1) |
2195                       GS_PRIO(2) |
2196                       ES_PRIO(3));
2197
2198         switch (rdev->family) {
2199         case CHIP_CEDAR:
2200         case CHIP_PALM:
2201         case CHIP_SUMO:
2202         case CHIP_SUMO2:
2203         case CHIP_CAICOS:
2204                 /* no vertex cache */
2205                 sq_config &= ~VC_ENABLE;
2206                 break;
2207         default:
2208                 break;
2209         }
2210
2211         sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
2212
2213         sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
2214         sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
2215         sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
2216         sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2217         sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
2218         sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2219         sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
2220
2221         switch (rdev->family) {
2222         case CHIP_CEDAR:
2223         case CHIP_PALM:
2224         case CHIP_SUMO:
2225         case CHIP_SUMO2:
2226                 ps_thread_count = 96;
2227                 break;
2228         default:
2229                 ps_thread_count = 128;
2230                 break;
2231         }
2232
2233         sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
2234         sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2235         sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2236         sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2237         sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2238         sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
2239
2240         sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2241         sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2242         sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2243         sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2244         sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2245         sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
2246
2247         WREG32(SQ_CONFIG, sq_config);
2248         WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
2249         WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
2250         WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
2251         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
2252         WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
2253         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
2254         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
2255         WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
2256         WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
2257         WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
2258
2259         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
2260                                           FORCE_EOV_MAX_REZ_CNT(255)));
2261
2262         switch (rdev->family) {
2263         case CHIP_CEDAR:
2264         case CHIP_PALM:
2265         case CHIP_SUMO:
2266         case CHIP_SUMO2:
2267         case CHIP_CAICOS:
2268                 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
2269                 break;
2270         default:
2271                 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
2272                 break;
2273         }
2274         vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
2275         WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
2276
2277         WREG32(VGT_GS_VERTEX_REUSE, 16);
2278         WREG32(PA_SU_LINE_STIPPLE_VALUE, 0);
2279         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
2280
2281         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
2282         WREG32(VGT_OUT_DEALLOC_CNTL, 16);
2283
2284         WREG32(CB_PERF_CTR0_SEL_0, 0);
2285         WREG32(CB_PERF_CTR0_SEL_1, 0);
2286         WREG32(CB_PERF_CTR1_SEL_0, 0);
2287         WREG32(CB_PERF_CTR1_SEL_1, 0);
2288         WREG32(CB_PERF_CTR2_SEL_0, 0);
2289         WREG32(CB_PERF_CTR2_SEL_1, 0);
2290         WREG32(CB_PERF_CTR3_SEL_0, 0);
2291         WREG32(CB_PERF_CTR3_SEL_1, 0);
2292
2293         /* clear render buffer base addresses */
2294         WREG32(CB_COLOR0_BASE, 0);
2295         WREG32(CB_COLOR1_BASE, 0);
2296         WREG32(CB_COLOR2_BASE, 0);
2297         WREG32(CB_COLOR3_BASE, 0);
2298         WREG32(CB_COLOR4_BASE, 0);
2299         WREG32(CB_COLOR5_BASE, 0);
2300         WREG32(CB_COLOR6_BASE, 0);
2301         WREG32(CB_COLOR7_BASE, 0);
2302         WREG32(CB_COLOR8_BASE, 0);
2303         WREG32(CB_COLOR9_BASE, 0);
2304         WREG32(CB_COLOR10_BASE, 0);
2305         WREG32(CB_COLOR11_BASE, 0);
2306
2307         /* set the shader const cache sizes to 0 */
2308         for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
2309                 WREG32(i, 0);
2310         for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
2311                 WREG32(i, 0);
2312
2313         tmp = RREG32(HDP_MISC_CNTL);
2314         tmp |= HDP_FLUSH_INVALIDATE_CACHE;
2315         WREG32(HDP_MISC_CNTL, tmp);
2316
2317         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
2318         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
2319
2320         WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
2321
2322         udelay(50);
2323
2324 }
2325
2326 int evergreen_mc_init(struct radeon_device *rdev)
2327 {
2328         u32 tmp;
2329         int chansize, numchan;
2330
2331         /* Get VRAM informations */
2332         rdev->mc.vram_is_ddr = true;
2333         if ((rdev->family == CHIP_PALM) ||
2334             (rdev->family == CHIP_SUMO) ||
2335             (rdev->family == CHIP_SUMO2))
2336                 tmp = RREG32(FUS_MC_ARB_RAMCFG);
2337         else
2338                 tmp = RREG32(MC_ARB_RAMCFG);
2339         if (tmp & CHANSIZE_OVERRIDE) {
2340                 chansize = 16;
2341         } else if (tmp & CHANSIZE_MASK) {
2342                 chansize = 64;
2343         } else {
2344                 chansize = 32;
2345         }
2346         tmp = RREG32(MC_SHARED_CHMAP);
2347         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
2348         case 0:
2349         default:
2350                 numchan = 1;
2351                 break;
2352         case 1:
2353                 numchan = 2;
2354                 break;
2355         case 2:
2356                 numchan = 4;
2357                 break;
2358         case 3:
2359                 numchan = 8;
2360                 break;
2361         }
2362         rdev->mc.vram_width = numchan * chansize;
2363         /* Could aper size report 0 ? */
2364         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
2365         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
2366         /* Setup GPU memory space */
2367         if ((rdev->family == CHIP_PALM) ||
2368             (rdev->family == CHIP_SUMO) ||
2369             (rdev->family == CHIP_SUMO2)) {
2370                 /* size in bytes on fusion */
2371                 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2372                 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2373         } else {
2374                 /* size in MB on evergreen/cayman/tn */
2375                 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2376                 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2377         }
2378         rdev->mc.visible_vram_size = rdev->mc.aper_size;
2379         r700_vram_gtt_location(rdev, &rdev->mc);
2380         radeon_update_bandwidth_info(rdev);
2381
2382         return 0;
2383 }
2384
2385 bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
2386 {
2387         u32 srbm_status;
2388         u32 grbm_status;
2389         u32 grbm_status_se0, grbm_status_se1;
2390         struct r100_gpu_lockup *lockup = &rdev->config.evergreen.lockup;
2391         int r;
2392
2393         srbm_status = RREG32(SRBM_STATUS);
2394         grbm_status = RREG32(GRBM_STATUS);
2395         grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2396         grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2397         if (!(grbm_status & GUI_ACTIVE)) {
2398                 r100_gpu_lockup_update(lockup, ring);
2399                 return false;
2400         }
2401         /* force CP activities */
2402         r = radeon_ring_lock(rdev, ring, 2);
2403         if (!r) {
2404                 /* PACKET2 NOP */
2405                 radeon_ring_write(ring, 0x80000000);
2406                 radeon_ring_write(ring, 0x80000000);
2407                 radeon_ring_unlock_commit(rdev, ring);
2408         }
2409         ring->rptr = RREG32(CP_RB_RPTR);
2410         return r100_gpu_cp_is_lockup(rdev, lockup, ring);
2411 }
2412
2413 static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
2414 {
2415         struct evergreen_mc_save save;
2416         u32 grbm_reset = 0;
2417
2418         if (!(RREG32(GRBM_STATUS) & GUI_ACTIVE))
2419                 return 0;
2420
2421         dev_info(rdev->dev, "GPU softreset \n");
2422         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
2423                 RREG32(GRBM_STATUS));
2424         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
2425                 RREG32(GRBM_STATUS_SE0));
2426         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
2427                 RREG32(GRBM_STATUS_SE1));
2428         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
2429                 RREG32(SRBM_STATUS));
2430         evergreen_mc_stop(rdev, &save);
2431         if (evergreen_mc_wait_for_idle(rdev)) {
2432                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
2433         }
2434         /* Disable CP parsing/prefetching */
2435         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
2436
2437         /* reset all the gfx blocks */
2438         grbm_reset = (SOFT_RESET_CP |
2439                       SOFT_RESET_CB |
2440                       SOFT_RESET_DB |
2441                       SOFT_RESET_PA |
2442                       SOFT_RESET_SC |
2443                       SOFT_RESET_SPI |
2444                       SOFT_RESET_SH |
2445                       SOFT_RESET_SX |
2446                       SOFT_RESET_TC |
2447                       SOFT_RESET_TA |
2448                       SOFT_RESET_VC |
2449                       SOFT_RESET_VGT);
2450
2451         dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
2452         WREG32(GRBM_SOFT_RESET, grbm_reset);
2453         (void)RREG32(GRBM_SOFT_RESET);
2454         udelay(50);
2455         WREG32(GRBM_SOFT_RESET, 0);
2456         (void)RREG32(GRBM_SOFT_RESET);
2457         /* Wait a little for things to settle down */
2458         udelay(50);
2459         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
2460                 RREG32(GRBM_STATUS));
2461         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
2462                 RREG32(GRBM_STATUS_SE0));
2463         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
2464                 RREG32(GRBM_STATUS_SE1));
2465         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
2466                 RREG32(SRBM_STATUS));
2467         evergreen_mc_resume(rdev, &save);
2468         return 0;
2469 }
2470
2471 int evergreen_asic_reset(struct radeon_device *rdev)
2472 {
2473         return evergreen_gpu_soft_reset(rdev);
2474 }
2475
2476 /* Interrupts */
2477
2478 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
2479 {
2480         switch (crtc) {
2481         case 0:
2482                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
2483         case 1:
2484                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
2485         case 2:
2486                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
2487         case 3:
2488                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
2489         case 4:
2490                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
2491         case 5:
2492                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
2493         default:
2494                 return 0;
2495         }
2496 }
2497
2498 void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2499 {
2500         u32 tmp;
2501
2502         if (rdev->family >= CHIP_CAYMAN) {
2503                 cayman_cp_int_cntl_setup(rdev, 0,
2504                                          CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2505                 cayman_cp_int_cntl_setup(rdev, 1, 0);
2506                 cayman_cp_int_cntl_setup(rdev, 2, 0);
2507         } else
2508                 WREG32(CP_INT_CNTL, CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE);
2509         WREG32(GRBM_INT_CNTL, 0);
2510         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2511         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2512         if (rdev->num_crtc >= 4) {
2513                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2514                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2515         }
2516         if (rdev->num_crtc >= 6) {
2517                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2518                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2519         }
2520
2521         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2522         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2523         if (rdev->num_crtc >= 4) {
2524                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2525                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2526         }
2527         if (rdev->num_crtc >= 6) {
2528                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2529                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2530         }
2531
2532         /* only one DAC on DCE6 */
2533         if (!ASIC_IS_DCE6(rdev))
2534                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2535         WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2536
2537         tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2538         WREG32(DC_HPD1_INT_CONTROL, tmp);
2539         tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2540         WREG32(DC_HPD2_INT_CONTROL, tmp);
2541         tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2542         WREG32(DC_HPD3_INT_CONTROL, tmp);
2543         tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2544         WREG32(DC_HPD4_INT_CONTROL, tmp);
2545         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2546         WREG32(DC_HPD5_INT_CONTROL, tmp);
2547         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2548         WREG32(DC_HPD6_INT_CONTROL, tmp);
2549
2550 }
2551
2552 int evergreen_irq_set(struct radeon_device *rdev)
2553 {
2554         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2555         u32 cp_int_cntl1 = 0, cp_int_cntl2 = 0;
2556         u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2557         u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2558         u32 grbm_int_cntl = 0;
2559         u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
2560
2561         if (!rdev->irq.installed) {
2562                 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
2563                 return -EINVAL;
2564         }
2565         /* don't enable anything if the ih is disabled */
2566         if (!rdev->ih.enabled) {
2567                 r600_disable_interrupts(rdev);
2568                 /* force the active interrupt state to all disabled */
2569                 evergreen_disable_interrupt_state(rdev);
2570                 return 0;
2571         }
2572
2573         hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2574         hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2575         hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2576         hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2577         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2578         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2579
2580         if (rdev->family >= CHIP_CAYMAN) {
2581                 /* enable CP interrupts on all rings */
2582                 if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
2583                         DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2584                         cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2585                 }
2586                 if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP1_INDEX]) {
2587                         DRM_DEBUG("evergreen_irq_set: sw int cp1\n");
2588                         cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
2589                 }
2590                 if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP2_INDEX]) {
2591                         DRM_DEBUG("evergreen_irq_set: sw int cp2\n");
2592                         cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
2593                 }
2594         } else {
2595                 if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
2596                         DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
2597                         cp_int_cntl |= RB_INT_ENABLE;
2598                         cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2599                 }
2600         }
2601
2602         if (rdev->irq.crtc_vblank_int[0] ||
2603             rdev->irq.pflip[0]) {
2604                 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2605                 crtc1 |= VBLANK_INT_MASK;
2606         }
2607         if (rdev->irq.crtc_vblank_int[1] ||
2608             rdev->irq.pflip[1]) {
2609                 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2610                 crtc2 |= VBLANK_INT_MASK;
2611         }
2612         if (rdev->irq.crtc_vblank_int[2] ||
2613             rdev->irq.pflip[2]) {
2614                 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2615                 crtc3 |= VBLANK_INT_MASK;
2616         }
2617         if (rdev->irq.crtc_vblank_int[3] ||
2618             rdev->irq.pflip[3]) {
2619                 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2620                 crtc4 |= VBLANK_INT_MASK;
2621         }
2622         if (rdev->irq.crtc_vblank_int[4] ||
2623             rdev->irq.pflip[4]) {
2624                 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2625                 crtc5 |= VBLANK_INT_MASK;
2626         }
2627         if (rdev->irq.crtc_vblank_int[5] ||
2628             rdev->irq.pflip[5]) {
2629                 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2630                 crtc6 |= VBLANK_INT_MASK;
2631         }
2632         if (rdev->irq.hpd[0]) {
2633                 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
2634                 hpd1 |= DC_HPDx_INT_EN;
2635         }
2636         if (rdev->irq.hpd[1]) {
2637                 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
2638                 hpd2 |= DC_HPDx_INT_EN;
2639         }
2640         if (rdev->irq.hpd[2]) {
2641                 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
2642                 hpd3 |= DC_HPDx_INT_EN;
2643         }
2644         if (rdev->irq.hpd[3]) {
2645                 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
2646                 hpd4 |= DC_HPDx_INT_EN;
2647         }
2648         if (rdev->irq.hpd[4]) {
2649                 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
2650                 hpd5 |= DC_HPDx_INT_EN;
2651         }
2652         if (rdev->irq.hpd[5]) {
2653                 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
2654                 hpd6 |= DC_HPDx_INT_EN;
2655         }
2656         if (rdev->irq.gui_idle) {
2657                 DRM_DEBUG("gui idle\n");
2658                 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
2659         }
2660
2661         if (rdev->family >= CHIP_CAYMAN) {
2662                 cayman_cp_int_cntl_setup(rdev, 0, cp_int_cntl);
2663                 cayman_cp_int_cntl_setup(rdev, 1, cp_int_cntl1);
2664                 cayman_cp_int_cntl_setup(rdev, 2, cp_int_cntl2);
2665         } else
2666                 WREG32(CP_INT_CNTL, cp_int_cntl);
2667         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
2668
2669         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2670         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2671         if (rdev->num_crtc >= 4) {
2672                 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2673                 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2674         }
2675         if (rdev->num_crtc >= 6) {
2676                 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2677                 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2678         }
2679
2680         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2681         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
2682         if (rdev->num_crtc >= 4) {
2683                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2684                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2685         }
2686         if (rdev->num_crtc >= 6) {
2687                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2688                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2689         }
2690
2691         WREG32(DC_HPD1_INT_CONTROL, hpd1);
2692         WREG32(DC_HPD2_INT_CONTROL, hpd2);
2693         WREG32(DC_HPD3_INT_CONTROL, hpd3);
2694         WREG32(DC_HPD4_INT_CONTROL, hpd4);
2695         WREG32(DC_HPD5_INT_CONTROL, hpd5);
2696         WREG32(DC_HPD6_INT_CONTROL, hpd6);
2697
2698         return 0;
2699 }
2700
2701 static void evergreen_irq_ack(struct radeon_device *rdev)
2702 {
2703         u32 tmp;
2704
2705         rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2706         rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2707         rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2708         rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2709         rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2710         rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2711         rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2712         rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2713         if (rdev->num_crtc >= 4) {
2714                 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2715                 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2716         }
2717         if (rdev->num_crtc >= 6) {
2718                 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2719                 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2720         }
2721
2722         if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2723                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2724         if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2725                 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2726         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
2727                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
2728         if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
2729                 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2730         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
2731                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
2732         if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
2733                 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2734
2735         if (rdev->num_crtc >= 4) {
2736                 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2737                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2738                 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2739                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2740                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2741                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2742                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2743                         WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2744                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2745                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2746                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2747                         WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2748         }
2749
2750         if (rdev->num_crtc >= 6) {
2751                 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2752                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2753                 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2754                         WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2755                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2756                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2757                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2758                         WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2759                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2760                         WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2761                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2762                         WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2763         }
2764
2765         if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2766                 tmp = RREG32(DC_HPD1_INT_CONTROL);
2767                 tmp |= DC_HPDx_INT_ACK;
2768                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2769         }
2770         if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2771                 tmp = RREG32(DC_HPD2_INT_CONTROL);
2772                 tmp |= DC_HPDx_INT_ACK;
2773                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2774         }
2775         if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2776                 tmp = RREG32(DC_HPD3_INT_CONTROL);
2777                 tmp |= DC_HPDx_INT_ACK;
2778                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2779         }
2780         if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2781                 tmp = RREG32(DC_HPD4_INT_CONTROL);
2782                 tmp |= DC_HPDx_INT_ACK;
2783                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2784         }
2785         if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2786                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2787                 tmp |= DC_HPDx_INT_ACK;
2788                 WREG32(DC_HPD5_INT_CONTROL, tmp);
2789         }
2790         if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2791                 tmp = RREG32(DC_HPD5_INT_CONTROL);
2792                 tmp |= DC_HPDx_INT_ACK;
2793                 WREG32(DC_HPD6_INT_CONTROL, tmp);
2794         }
2795 }
2796
2797 void evergreen_irq_disable(struct radeon_device *rdev)
2798 {
2799         r600_disable_interrupts(rdev);
2800         /* Wait and acknowledge irq */
2801         mdelay(1);
2802         evergreen_irq_ack(rdev);
2803         evergreen_disable_interrupt_state(rdev);
2804 }
2805
2806 void evergreen_irq_suspend(struct radeon_device *rdev)
2807 {
2808         evergreen_irq_disable(rdev);
2809         r600_rlc_stop(rdev);
2810 }
2811
2812 static u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2813 {
2814         u32 wptr, tmp;
2815
2816         if (rdev->wb.enabled)
2817                 wptr = le32_to_cpu(rdev->wb.wb[R600_WB_IH_WPTR_OFFSET/4]);
2818         else
2819                 wptr = RREG32(IH_RB_WPTR);
2820
2821         if (wptr & RB_OVERFLOW) {
2822                 /* When a ring buffer overflow happen start parsing interrupt
2823                  * from the last not overwritten vector (wptr + 16). Hopefully
2824                  * this should allow us to catchup.
2825                  */
2826                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2827                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2828                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2829                 tmp = RREG32(IH_RB_CNTL);
2830                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2831                 WREG32(IH_RB_CNTL, tmp);
2832         }
2833         return (wptr & rdev->ih.ptr_mask);
2834 }
2835
2836 int evergreen_irq_process(struct radeon_device *rdev)
2837 {
2838         u32 wptr;
2839         u32 rptr;
2840         u32 src_id, src_data;
2841         u32 ring_index;
2842         unsigned long flags;
2843         bool queue_hotplug = false;
2844
2845         if (!rdev->ih.enabled || rdev->shutdown)
2846                 return IRQ_NONE;
2847
2848         wptr = evergreen_get_ih_wptr(rdev);
2849         rptr = rdev->ih.rptr;
2850         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2851
2852         spin_lock_irqsave(&rdev->ih.lock, flags);
2853         if (rptr == wptr) {
2854                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2855                 return IRQ_NONE;
2856         }
2857 restart_ih:
2858         /* Order reading of wptr vs. reading of IH ring data */
2859         rmb();
2860
2861         /* display interrupts */
2862         evergreen_irq_ack(rdev);
2863
2864         rdev->ih.wptr = wptr;
2865         while (rptr != wptr) {
2866                 /* wptr/rptr are in bytes! */
2867                 ring_index = rptr / 4;
2868                 src_id =  le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
2869                 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
2870
2871                 switch (src_id) {
2872                 case 1: /* D1 vblank/vline */
2873                         switch (src_data) {
2874                         case 0: /* D1 vblank */
2875                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
2876                                         if (rdev->irq.crtc_vblank_int[0]) {
2877                                                 drm_handle_vblank(rdev->ddev, 0);
2878                                                 rdev->pm.vblank_sync = true;
2879                                                 wake_up(&rdev->irq.vblank_queue);
2880                                         }
2881                                         if (rdev->irq.pflip[0])
2882                                                 radeon_crtc_handle_flip(rdev, 0);
2883                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2884                                         DRM_DEBUG("IH: D1 vblank\n");
2885                                 }
2886                                 break;
2887                         case 1: /* D1 vline */
2888                                 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
2889                                         rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
2890                                         DRM_DEBUG("IH: D1 vline\n");
2891                                 }
2892                                 break;
2893                         default:
2894                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2895                                 break;
2896                         }
2897                         break;
2898                 case 2: /* D2 vblank/vline */
2899                         switch (src_data) {
2900                         case 0: /* D2 vblank */
2901                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
2902                                         if (rdev->irq.crtc_vblank_int[1]) {
2903                                                 drm_handle_vblank(rdev->ddev, 1);
2904                                                 rdev->pm.vblank_sync = true;
2905                                                 wake_up(&rdev->irq.vblank_queue);
2906                                         }
2907                                         if (rdev->irq.pflip[1])
2908                                                 radeon_crtc_handle_flip(rdev, 1);
2909                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
2910                                         DRM_DEBUG("IH: D2 vblank\n");
2911                                 }
2912                                 break;
2913                         case 1: /* D2 vline */
2914                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2915                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
2916                                         DRM_DEBUG("IH: D2 vline\n");
2917                                 }
2918                                 break;
2919                         default:
2920                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2921                                 break;
2922                         }
2923                         break;
2924                 case 3: /* D3 vblank/vline */
2925                         switch (src_data) {
2926                         case 0: /* D3 vblank */
2927                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2928                                         if (rdev->irq.crtc_vblank_int[2]) {
2929                                                 drm_handle_vblank(rdev->ddev, 2);
2930                                                 rdev->pm.vblank_sync = true;
2931                                                 wake_up(&rdev->irq.vblank_queue);
2932                                         }
2933                                         if (rdev->irq.pflip[2])
2934                                                 radeon_crtc_handle_flip(rdev, 2);
2935                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
2936                                         DRM_DEBUG("IH: D3 vblank\n");
2937                                 }
2938                                 break;
2939                         case 1: /* D3 vline */
2940                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
2941                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
2942                                         DRM_DEBUG("IH: D3 vline\n");
2943                                 }
2944                                 break;
2945                         default:
2946                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2947                                 break;
2948                         }
2949                         break;
2950                 case 4: /* D4 vblank/vline */
2951                         switch (src_data) {
2952                         case 0: /* D4 vblank */
2953                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
2954                                         if (rdev->irq.crtc_vblank_int[3]) {
2955                                                 drm_handle_vblank(rdev->ddev, 3);
2956                                                 rdev->pm.vblank_sync = true;
2957                                                 wake_up(&rdev->irq.vblank_queue);
2958                                         }
2959                                         if (rdev->irq.pflip[3])
2960                                                 radeon_crtc_handle_flip(rdev, 3);
2961                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
2962                                         DRM_DEBUG("IH: D4 vblank\n");
2963                                 }
2964                                 break;
2965                         case 1: /* D4 vline */
2966                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
2967                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
2968                                         DRM_DEBUG("IH: D4 vline\n");
2969                                 }
2970                                 break;
2971                         default:
2972                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2973                                 break;
2974                         }
2975                         break;
2976                 case 5: /* D5 vblank/vline */
2977                         switch (src_data) {
2978                         case 0: /* D5 vblank */
2979                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
2980                                         if (rdev->irq.crtc_vblank_int[4]) {
2981                                                 drm_handle_vblank(rdev->ddev, 4);
2982                                                 rdev->pm.vblank_sync = true;
2983                                                 wake_up(&rdev->irq.vblank_queue);
2984                                         }
2985                                         if (rdev->irq.pflip[4])
2986                                                 radeon_crtc_handle_flip(rdev, 4);
2987                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
2988                                         DRM_DEBUG("IH: D5 vblank\n");
2989                                 }
2990                                 break;
2991                         case 1: /* D5 vline */
2992                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
2993                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
2994                                         DRM_DEBUG("IH: D5 vline\n");
2995                                 }
2996                                 break;
2997                         default:
2998                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2999                                 break;
3000                         }
3001                         break;
3002                 case 6: /* D6 vblank/vline */
3003                         switch (src_data) {
3004                         case 0: /* D6 vblank */
3005                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
3006                                         if (rdev->irq.crtc_vblank_int[5]) {
3007                                                 drm_handle_vblank(rdev->ddev, 5);
3008                                                 rdev->pm.vblank_sync = true;
3009                                                 wake_up(&rdev->irq.vblank_queue);
3010                                         }
3011                                         if (rdev->irq.pflip[5])
3012                                                 radeon_crtc_handle_flip(rdev, 5);
3013                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
3014                                         DRM_DEBUG("IH: D6 vblank\n");
3015                                 }
3016                                 break;
3017                         case 1: /* D6 vline */
3018                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
3019                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
3020                                         DRM_DEBUG("IH: D6 vline\n");
3021                                 }
3022                                 break;
3023                         default:
3024                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3025                                 break;
3026                         }
3027                         break;
3028                 case 42: /* HPD hotplug */
3029                         switch (src_data) {
3030                         case 0:
3031                                 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
3032                                         rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
3033                                         queue_hotplug = true;
3034                                         DRM_DEBUG("IH: HPD1\n");
3035                                 }
3036                                 break;
3037                         case 1:
3038                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
3039                                         rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
3040                                         queue_hotplug = true;
3041                                         DRM_DEBUG("IH: HPD2\n");
3042                                 }
3043                                 break;
3044                         case 2:
3045                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
3046                                         rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
3047                                         queue_hotplug = true;
3048                                         DRM_DEBUG("IH: HPD3\n");
3049                                 }
3050                                 break;
3051                         case 3:
3052                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
3053                                         rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
3054                                         queue_hotplug = true;
3055                                         DRM_DEBUG("IH: HPD4\n");
3056                                 }
3057                                 break;
3058                         case 4:
3059                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
3060                                         rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
3061                                         queue_hotplug = true;
3062                                         DRM_DEBUG("IH: HPD5\n");
3063                                 }
3064                                 break;
3065                         case 5:
3066                                 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
3067                                         rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
3068                                         queue_hotplug = true;
3069                                         DRM_DEBUG("IH: HPD6\n");
3070                                 }
3071                                 break;
3072                         default:
3073                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3074                                 break;
3075                         }
3076                         break;
3077                 case 176: /* CP_INT in ring buffer */
3078                 case 177: /* CP_INT in IB1 */
3079                 case 178: /* CP_INT in IB2 */
3080                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3081                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3082                         break;
3083                 case 181: /* CP EOP event */
3084                         DRM_DEBUG("IH: CP EOP\n");
3085                         if (rdev->family >= CHIP_CAYMAN) {
3086                                 switch (src_data) {
3087                                 case 0:
3088                                         radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3089                                         break;
3090                                 case 1:
3091                                         radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP1_INDEX);
3092                                         break;
3093                                 case 2:
3094                                         radeon_fence_process(rdev, CAYMAN_RING_TYPE_CP2_INDEX);
3095                                         break;
3096                                 }
3097                         } else
3098                                 radeon_fence_process(rdev, RADEON_RING_TYPE_GFX_INDEX);
3099                         break;
3100                 case 233: /* GUI IDLE */
3101                         DRM_DEBUG("IH: GUI idle\n");
3102                         rdev->pm.gui_idle = true;
3103                         wake_up(&rdev->irq.idle_queue);
3104                         break;
3105                 default:
3106                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3107                         break;
3108                 }
3109
3110                 /* wptr/rptr are in bytes! */
3111                 rptr += 16;
3112                 rptr &= rdev->ih.ptr_mask;
3113         }
3114         /* make sure wptr hasn't changed while processing */
3115         wptr = evergreen_get_ih_wptr(rdev);
3116         if (wptr != rdev->ih.wptr)
3117                 goto restart_ih;
3118         if (queue_hotplug)
3119                 schedule_work(&rdev->hotplug_work);
3120         rdev->ih.rptr = rptr;
3121         WREG32(IH_RB_RPTR, rdev->ih.rptr);
3122         spin_unlock_irqrestore(&rdev->ih.lock, flags);
3123         return IRQ_HANDLED;
3124 }
3125
3126 static int evergreen_startup(struct radeon_device *rdev)
3127 {
3128         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3129         int r;
3130
3131         /* enable pcie gen2 link */
3132         evergreen_pcie_gen2_enable(rdev);
3133
3134         if (ASIC_IS_DCE5(rdev)) {
3135                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
3136                         r = ni_init_microcode(rdev);
3137                         if (r) {
3138                                 DRM_ERROR("Failed to load firmware!\n");
3139                                 return r;
3140                         }
3141                 }
3142                 r = ni_mc_load_microcode(rdev);
3143                 if (r) {
3144                         DRM_ERROR("Failed to load MC firmware!\n");
3145                         return r;
3146                 }
3147         } else {
3148                 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
3149                         r = r600_init_microcode(rdev);
3150                         if (r) {
3151                                 DRM_ERROR("Failed to load firmware!\n");
3152                                 return r;
3153                         }
3154                 }
3155         }
3156
3157         r = r600_vram_scratch_init(rdev);
3158         if (r)
3159                 return r;
3160
3161         evergreen_mc_program(rdev);
3162         if (rdev->flags & RADEON_IS_AGP) {
3163                 evergreen_agp_enable(rdev);
3164         } else {
3165                 r = evergreen_pcie_gart_enable(rdev);
3166                 if (r)
3167                         return r;
3168         }
3169         evergreen_gpu_init(rdev);
3170
3171         r = evergreen_blit_init(rdev);
3172         if (r) {
3173                 r600_blit_fini(rdev);
3174                 rdev->asic->copy.copy = NULL;
3175                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
3176         }
3177
3178         /* allocate wb buffer */
3179         r = radeon_wb_init(rdev);
3180         if (r)
3181                 return r;
3182
3183         r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
3184         if (r) {
3185                 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
3186                 return r;
3187         }
3188
3189         /* Enable IRQ */
3190         r = r600_irq_init(rdev);
3191         if (r) {
3192                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
3193                 radeon_irq_kms_fini(rdev);
3194                 return r;
3195         }
3196         evergreen_irq_set(rdev);
3197
3198         r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
3199                              R600_CP_RB_RPTR, R600_CP_RB_WPTR,
3200                              0, 0xfffff, RADEON_CP_PACKET2);
3201         if (r)
3202                 return r;
3203         r = evergreen_cp_load_microcode(rdev);
3204         if (r)
3205                 return r;
3206         r = evergreen_cp_resume(rdev);
3207         if (r)
3208                 return r;
3209
3210         r = radeon_ib_pool_start(rdev);
3211         if (r)
3212                 return r;
3213
3214         r = radeon_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
3215         if (r) {
3216                 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
3217                 rdev->accel_working = false;
3218                 return r;
3219         }
3220
3221         r = r600_audio_init(rdev);
3222         if (r) {
3223                 DRM_ERROR("radeon: audio init failed\n");
3224                 return r;
3225         }
3226
3227         return 0;
3228 }
3229
3230 int evergreen_resume(struct radeon_device *rdev)
3231 {
3232         int r;
3233
3234         /* reset the asic, the gfx blocks are often in a bad state
3235          * after the driver is unloaded or after a resume
3236          */
3237         if (radeon_asic_reset(rdev))
3238                 dev_warn(rdev->dev, "GPU reset failed !\n");
3239         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
3240          * posting will perform necessary task to bring back GPU into good
3241          * shape.
3242          */
3243         /* post card */
3244         atom_asic_init(rdev->mode_info.atom_context);
3245
3246         rdev->accel_working = true;
3247         r = evergreen_startup(rdev);
3248         if (r) {
3249                 DRM_ERROR("evergreen startup failed on resume\n");
3250                 rdev->accel_working = false;
3251                 return r;
3252         }
3253
3254         return r;
3255
3256 }
3257
3258 int evergreen_suspend(struct radeon_device *rdev)
3259 {
3260         struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3261
3262         r600_audio_fini(rdev);
3263         /* FIXME: we should wait for ring to be empty */
3264         radeon_ib_pool_suspend(rdev);
3265         r600_blit_suspend(rdev);
3266         r700_cp_stop(rdev);
3267         ring->ready = false;
3268         evergreen_irq_suspend(rdev);
3269         radeon_wb_disable(rdev);
3270         evergreen_pcie_gart_disable(rdev);
3271
3272         return 0;
3273 }
3274
3275 /* Plan is to move initialization in that function and use
3276  * helper function so that radeon_device_init pretty much
3277  * do nothing more than calling asic specific function. This
3278  * should also allow to remove a bunch of callback function
3279  * like vram_info.
3280  */
3281 int evergreen_init(struct radeon_device *rdev)
3282 {
3283         int r;
3284
3285         /* This don't do much */
3286         r = radeon_gem_init(rdev);
3287         if (r)
3288                 return r;
3289         /* Read BIOS */
3290         if (!radeon_get_bios(rdev)) {
3291                 if (ASIC_IS_AVIVO(rdev))
3292                         return -EINVAL;
3293         }
3294         /* Must be an ATOMBIOS */
3295         if (!rdev->is_atom_bios) {
3296                 dev_err(rdev->dev, "Expecting atombios for evergreen GPU\n");
3297                 return -EINVAL;
3298         }
3299         r = radeon_atombios_init(rdev);
3300         if (r)
3301                 return r;
3302         /* reset the asic, the gfx blocks are often in a bad state
3303          * after the driver is unloaded or after a resume
3304          */
3305         if (radeon_asic_reset(rdev))
3306                 dev_warn(rdev->dev, "GPU reset failed !\n");
3307         /* Post card if necessary */
3308         if (!radeon_card_posted(rdev)) {
3309                 if (!rdev->bios) {
3310                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
3311                         return -EINVAL;
3312                 }
3313                 DRM_INFO("GPU not posted. posting now...\n");
3314                 atom_asic_init(rdev->mode_info.atom_context);
3315         }
3316         /* Initialize scratch registers */
3317         r600_scratch_init(rdev);
3318         /* Initialize surface registers */
3319         radeon_surface_init(rdev);
3320         /* Initialize clocks */
3321         radeon_get_clock_info(rdev->ddev);
3322         /* Fence driver */
3323         r = radeon_fence_driver_init(rdev);
3324         if (r)
3325                 return r;
3326         /* initialize AGP */
3327         if (rdev->flags & RADEON_IS_AGP) {
3328                 r = radeon_agp_init(rdev);
3329                 if (r)
3330                         radeon_agp_disable(rdev);
3331         }
3332         /* initialize memory controller */
3333         r = evergreen_mc_init(rdev);
3334         if (r)
3335                 return r;
3336         /* Memory manager */
3337         r = radeon_bo_init(rdev);
3338         if (r)
3339                 return r;
3340
3341         r = radeon_irq_kms_init(rdev);
3342         if (r)
3343                 return r;
3344
3345         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
3346         r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
3347
3348         rdev->ih.ring_obj = NULL;
3349         r600_ih_ring_init(rdev, 64 * 1024);
3350
3351         r = r600_pcie_gart_init(rdev);
3352         if (r)
3353                 return r;
3354
3355         r = radeon_ib_pool_init(rdev);
3356         rdev->accel_working = true;
3357         if (r) {
3358                 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
3359                 rdev->accel_working = false;
3360         }
3361
3362         r = evergreen_startup(rdev);
3363         if (r) {
3364                 dev_err(rdev->dev, "disabling GPU acceleration\n");
3365                 r700_cp_fini(rdev);
3366                 r600_irq_fini(rdev);
3367                 radeon_wb_fini(rdev);
3368                 r100_ib_fini(rdev);
3369                 radeon_irq_kms_fini(rdev);
3370                 evergreen_pcie_gart_fini(rdev);
3371                 rdev->accel_working = false;
3372         }
3373
3374         /* Don't start up if the MC ucode is missing on BTC parts.
3375          * The default clocks and voltages before the MC ucode
3376          * is loaded are not suffient for advanced operations.
3377          */
3378         if (ASIC_IS_DCE5(rdev)) {
3379                 if (!rdev->mc_fw && !(rdev->flags & RADEON_IS_IGP)) {
3380                         DRM_ERROR("radeon: MC ucode required for NI+.\n");
3381                         return -EINVAL;
3382                 }
3383         }
3384
3385         return 0;
3386 }
3387
3388 void evergreen_fini(struct radeon_device *rdev)
3389 {
3390         r600_audio_fini(rdev);
3391         r600_blit_fini(rdev);
3392         r700_cp_fini(rdev);
3393         r600_irq_fini(rdev);
3394         radeon_wb_fini(rdev);
3395         r100_ib_fini(rdev);
3396         radeon_irq_kms_fini(rdev);
3397         evergreen_pcie_gart_fini(rdev);
3398         r600_vram_scratch_fini(rdev);
3399         radeon_gem_fini(rdev);
3400         radeon_semaphore_driver_fini(rdev);
3401         radeon_fence_driver_fini(rdev);
3402         radeon_agp_fini(rdev);
3403         radeon_bo_fini(rdev);
3404         radeon_atombios_fini(rdev);
3405         kfree(rdev->bios);
3406         rdev->bios = NULL;
3407 }
3408
3409 void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
3410 {
3411         u32 link_width_cntl, speed_cntl;
3412
3413         if (radeon_pcie_gen2 == 0)
3414                 return;
3415
3416         if (rdev->flags & RADEON_IS_IGP)
3417                 return;
3418
3419         if (!(rdev->flags & RADEON_IS_PCIE))
3420                 return;
3421
3422         /* x2 cards have a special sequence */
3423         if (ASIC_IS_X2(rdev))
3424                 return;
3425
3426         speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3427         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3428             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3429
3430                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3431                 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3432                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3433
3434                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3435                 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3436                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3437
3438                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3439                 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3440                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3441
3442                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3443                 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3444                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3445
3446                 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3447                 speed_cntl |= LC_GEN2_EN_STRAP;
3448                 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3449
3450         } else {
3451                 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3452                 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3453                 if (1)
3454                         link_width_cntl |= LC_UPCONFIGURE_DIS;
3455                 else
3456                         link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3457                 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3458         }
3459 }