drm/radeon: fix dpms on/off on trinity/aruba v2
[linux-2.6.git] / drivers / gpu / drm / radeon / atombios_encoders.c
1 /*
2  * Copyright 2007-11 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: Dave Airlie
24  *          Alex Deucher
25  */
26 #include "drmP.h"
27 #include "drm_crtc_helper.h"
28 #include "radeon_drm.h"
29 #include "radeon.h"
30 #include "atom.h"
31
32 extern int atom_debug;
33
34 /* evil but including atombios.h is much worse */
35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36                                 struct drm_display_mode *mode);
37
38
39 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
40 {
41         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
42         switch (radeon_encoder->encoder_id) {
43         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
44         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
45         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
46         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
47         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
48         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
49         case ENCODER_OBJECT_ID_INTERNAL_DDI:
50         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
51         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
52         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
53         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
54                 return true;
55         default:
56                 return false;
57         }
58 }
59
60 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
61                                    struct drm_display_mode *mode,
62                                    struct drm_display_mode *adjusted_mode)
63 {
64         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
65         struct drm_device *dev = encoder->dev;
66         struct radeon_device *rdev = dev->dev_private;
67
68         /* set the active encoder to connector routing */
69         radeon_encoder_set_active_device(encoder);
70         drm_mode_set_crtcinfo(adjusted_mode, 0);
71
72         /* hw bug */
73         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
74             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
75                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
76
77         /* get the native mode for LVDS */
78         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
79                 radeon_panel_mode_fixup(encoder, adjusted_mode);
80
81         /* get the native mode for TV */
82         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
83                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
84                 if (tv_dac) {
85                         if (tv_dac->tv_std == TV_STD_NTSC ||
86                             tv_dac->tv_std == TV_STD_NTSC_J ||
87                             tv_dac->tv_std == TV_STD_PAL_M)
88                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
89                         else
90                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
91                 }
92         }
93
94         if (ASIC_IS_DCE3(rdev) &&
95             ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
96              (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
97                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
98                 radeon_dp_set_link_config(connector, mode);
99         }
100
101         return true;
102 }
103
104 static void
105 atombios_dac_setup(struct drm_encoder *encoder, int action)
106 {
107         struct drm_device *dev = encoder->dev;
108         struct radeon_device *rdev = dev->dev_private;
109         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
110         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
111         int index = 0;
112         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
113
114         memset(&args, 0, sizeof(args));
115
116         switch (radeon_encoder->encoder_id) {
117         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
118         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
119                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
120                 break;
121         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
122         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
123                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
124                 break;
125         }
126
127         args.ucAction = action;
128
129         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
130                 args.ucDacStandard = ATOM_DAC1_PS2;
131         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
132                 args.ucDacStandard = ATOM_DAC1_CV;
133         else {
134                 switch (dac_info->tv_std) {
135                 case TV_STD_PAL:
136                 case TV_STD_PAL_M:
137                 case TV_STD_SCART_PAL:
138                 case TV_STD_SECAM:
139                 case TV_STD_PAL_CN:
140                         args.ucDacStandard = ATOM_DAC1_PAL;
141                         break;
142                 case TV_STD_NTSC:
143                 case TV_STD_NTSC_J:
144                 case TV_STD_PAL_60:
145                 default:
146                         args.ucDacStandard = ATOM_DAC1_NTSC;
147                         break;
148                 }
149         }
150         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
151
152         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
153
154 }
155
156 static void
157 atombios_tv_setup(struct drm_encoder *encoder, int action)
158 {
159         struct drm_device *dev = encoder->dev;
160         struct radeon_device *rdev = dev->dev_private;
161         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
162         TV_ENCODER_CONTROL_PS_ALLOCATION args;
163         int index = 0;
164         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
165
166         memset(&args, 0, sizeof(args));
167
168         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
169
170         args.sTVEncoder.ucAction = action;
171
172         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
173                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
174         else {
175                 switch (dac_info->tv_std) {
176                 case TV_STD_NTSC:
177                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
178                         break;
179                 case TV_STD_PAL:
180                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
181                         break;
182                 case TV_STD_PAL_M:
183                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
184                         break;
185                 case TV_STD_PAL_60:
186                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
187                         break;
188                 case TV_STD_NTSC_J:
189                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
190                         break;
191                 case TV_STD_SCART_PAL:
192                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
193                         break;
194                 case TV_STD_SECAM:
195                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
196                         break;
197                 case TV_STD_PAL_CN:
198                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
199                         break;
200                 default:
201                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
202                         break;
203                 }
204         }
205
206         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
207
208         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
209
210 }
211
212 union dvo_encoder_control {
213         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
214         DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
215         DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
216 };
217
218 void
219 atombios_dvo_setup(struct drm_encoder *encoder, int action)
220 {
221         struct drm_device *dev = encoder->dev;
222         struct radeon_device *rdev = dev->dev_private;
223         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
224         union dvo_encoder_control args;
225         int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
226         uint8_t frev, crev;
227
228         memset(&args, 0, sizeof(args));
229
230         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
231                 return;
232
233         /* some R4xx chips have the wrong frev */
234         if (rdev->family <= CHIP_RV410)
235                 frev = 1;
236
237         switch (frev) {
238         case 1:
239                 switch (crev) {
240                 case 1:
241                         /* R4xx, R5xx */
242                         args.ext_tmds.sXTmdsEncoder.ucEnable = action;
243
244                         if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
245                                 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
246
247                         args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
248                         break;
249                 case 2:
250                         /* RS600/690/740 */
251                         args.dvo.sDVOEncoder.ucAction = action;
252                         args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
253                         /* DFP1, CRT1, TV1 depending on the type of port */
254                         args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
255
256                         if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
257                                 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
258                         break;
259                 case 3:
260                         /* R6xx */
261                         args.dvo_v3.ucAction = action;
262                         args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
263                         args.dvo_v3.ucDVOConfig = 0; /* XXX */
264                         break;
265                 default:
266                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
267                         break;
268                 }
269                 break;
270         default:
271                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
272                 break;
273         }
274
275         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
276 }
277
278 union lvds_encoder_control {
279         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
280         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
281 };
282
283 void
284 atombios_digital_setup(struct drm_encoder *encoder, int action)
285 {
286         struct drm_device *dev = encoder->dev;
287         struct radeon_device *rdev = dev->dev_private;
288         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
289         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
290         union lvds_encoder_control args;
291         int index = 0;
292         int hdmi_detected = 0;
293         uint8_t frev, crev;
294
295         if (!dig)
296                 return;
297
298         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
299                 hdmi_detected = 1;
300
301         memset(&args, 0, sizeof(args));
302
303         switch (radeon_encoder->encoder_id) {
304         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
305                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
306                 break;
307         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
308         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
309                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
310                 break;
311         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
312                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
313                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
314                 else
315                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
316                 break;
317         }
318
319         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
320                 return;
321
322         switch (frev) {
323         case 1:
324         case 2:
325                 switch (crev) {
326                 case 1:
327                         args.v1.ucMisc = 0;
328                         args.v1.ucAction = action;
329                         if (hdmi_detected)
330                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
331                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
332                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
333                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
334                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
335                                 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
336                                         args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
337                         } else {
338                                 if (dig->linkb)
339                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
340                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
341                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
342                                 /*if (pScrn->rgbBits == 8) */
343                                 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
344                         }
345                         break;
346                 case 2:
347                 case 3:
348                         args.v2.ucMisc = 0;
349                         args.v2.ucAction = action;
350                         if (crev == 3) {
351                                 if (dig->coherent_mode)
352                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
353                         }
354                         if (hdmi_detected)
355                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
356                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
357                         args.v2.ucTruncate = 0;
358                         args.v2.ucSpatial = 0;
359                         args.v2.ucTemporal = 0;
360                         args.v2.ucFRC = 0;
361                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
362                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
363                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
364                                 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
365                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
366                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
367                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
368                                 }
369                                 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
370                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
371                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
372                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
373                                         if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
374                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
375                                 }
376                         } else {
377                                 if (dig->linkb)
378                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
379                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
380                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
381                         }
382                         break;
383                 default:
384                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
385                         break;
386                 }
387                 break;
388         default:
389                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
390                 break;
391         }
392
393         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
394 }
395
396 int
397 atombios_get_encoder_mode(struct drm_encoder *encoder)
398 {
399         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
400         struct drm_connector *connector;
401         struct radeon_connector *radeon_connector;
402         struct radeon_connector_atom_dig *dig_connector;
403
404         /* dp bridges are always DP */
405         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
406                 return ATOM_ENCODER_MODE_DP;
407
408         /* DVO is always DVO */
409         if (radeon_encoder->encoder_id == ATOM_ENCODER_MODE_DVO)
410                 return ATOM_ENCODER_MODE_DVO;
411
412         connector = radeon_get_connector_for_encoder(encoder);
413         /* if we don't have an active device yet, just use one of
414          * the connectors tied to the encoder.
415          */
416         if (!connector)
417                 connector = radeon_get_connector_for_encoder_init(encoder);
418         radeon_connector = to_radeon_connector(connector);
419
420         switch (connector->connector_type) {
421         case DRM_MODE_CONNECTOR_DVII:
422         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
423                 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
424                     radeon_audio)
425                         return ATOM_ENCODER_MODE_HDMI;
426                 else if (radeon_connector->use_digital)
427                         return ATOM_ENCODER_MODE_DVI;
428                 else
429                         return ATOM_ENCODER_MODE_CRT;
430                 break;
431         case DRM_MODE_CONNECTOR_DVID:
432         case DRM_MODE_CONNECTOR_HDMIA:
433         default:
434                 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
435                     radeon_audio)
436                         return ATOM_ENCODER_MODE_HDMI;
437                 else
438                         return ATOM_ENCODER_MODE_DVI;
439                 break;
440         case DRM_MODE_CONNECTOR_LVDS:
441                 return ATOM_ENCODER_MODE_LVDS;
442                 break;
443         case DRM_MODE_CONNECTOR_DisplayPort:
444                 dig_connector = radeon_connector->con_priv;
445                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
446                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
447                         return ATOM_ENCODER_MODE_DP;
448                 else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
449                          radeon_audio)
450                         return ATOM_ENCODER_MODE_HDMI;
451                 else
452                         return ATOM_ENCODER_MODE_DVI;
453                 break;
454         case DRM_MODE_CONNECTOR_eDP:
455                 return ATOM_ENCODER_MODE_DP;
456         case DRM_MODE_CONNECTOR_DVIA:
457         case DRM_MODE_CONNECTOR_VGA:
458                 return ATOM_ENCODER_MODE_CRT;
459                 break;
460         case DRM_MODE_CONNECTOR_Composite:
461         case DRM_MODE_CONNECTOR_SVIDEO:
462         case DRM_MODE_CONNECTOR_9PinDIN:
463                 /* fix me */
464                 return ATOM_ENCODER_MODE_TV;
465                 /*return ATOM_ENCODER_MODE_CV;*/
466                 break;
467         }
468 }
469
470 /*
471  * DIG Encoder/Transmitter Setup
472  *
473  * DCE 3.0/3.1
474  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
475  * Supports up to 3 digital outputs
476  * - 2 DIG encoder blocks.
477  * DIG1 can drive UNIPHY link A or link B
478  * DIG2 can drive UNIPHY link B or LVTMA
479  *
480  * DCE 3.2
481  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
482  * Supports up to 5 digital outputs
483  * - 2 DIG encoder blocks.
484  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
485  *
486  * DCE 4.0/5.0/6.0
487  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
488  * Supports up to 6 digital outputs
489  * - 6 DIG encoder blocks.
490  * - DIG to PHY mapping is hardcoded
491  * DIG1 drives UNIPHY0 link A, A+B
492  * DIG2 drives UNIPHY0 link B
493  * DIG3 drives UNIPHY1 link A, A+B
494  * DIG4 drives UNIPHY1 link B
495  * DIG5 drives UNIPHY2 link A, A+B
496  * DIG6 drives UNIPHY2 link B
497  *
498  * DCE 4.1
499  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
500  * Supports up to 6 digital outputs
501  * - 2 DIG encoder blocks.
502  * llano
503  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
504  * ontario
505  * DIG1 drives UNIPHY0/1/2 link A
506  * DIG2 drives UNIPHY0/1/2 link B
507  *
508  * Routing
509  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
510  * Examples:
511  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
512  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
513  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
514  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
515  */
516
517 union dig_encoder_control {
518         DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
519         DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
520         DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
521         DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
522 };
523
524 void
525 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
526 {
527         struct drm_device *dev = encoder->dev;
528         struct radeon_device *rdev = dev->dev_private;
529         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
530         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
531         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
532         union dig_encoder_control args;
533         int index = 0;
534         uint8_t frev, crev;
535         int dp_clock = 0;
536         int dp_lane_count = 0;
537         int hpd_id = RADEON_HPD_NONE;
538         int bpc = 8;
539
540         if (connector) {
541                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
542                 struct radeon_connector_atom_dig *dig_connector =
543                         radeon_connector->con_priv;
544
545                 dp_clock = dig_connector->dp_clock;
546                 dp_lane_count = dig_connector->dp_lane_count;
547                 hpd_id = radeon_connector->hpd.hpd;
548                 /* bpc = connector->display_info.bpc; */
549         }
550
551         /* no dig encoder assigned */
552         if (dig->dig_encoder == -1)
553                 return;
554
555         memset(&args, 0, sizeof(args));
556
557         if (ASIC_IS_DCE4(rdev))
558                 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
559         else {
560                 if (dig->dig_encoder)
561                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
562                 else
563                         index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
564         }
565
566         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
567                 return;
568
569         switch (frev) {
570         case 1:
571                 switch (crev) {
572                 case 1:
573                         args.v1.ucAction = action;
574                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
575                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
576                                 args.v3.ucPanelMode = panel_mode;
577                         else
578                                 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
579
580                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
581                                 args.v1.ucLaneNum = dp_lane_count;
582                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
583                                 args.v1.ucLaneNum = 8;
584                         else
585                                 args.v1.ucLaneNum = 4;
586
587                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
588                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
589                         switch (radeon_encoder->encoder_id) {
590                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
591                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
592                                 break;
593                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
594                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
595                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
596                                 break;
597                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
598                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
599                                 break;
600                         }
601                         if (dig->linkb)
602                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
603                         else
604                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
605                         break;
606                 case 2:
607                 case 3:
608                         args.v3.ucAction = action;
609                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
610                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
611                                 args.v3.ucPanelMode = panel_mode;
612                         else
613                                 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
614
615                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
616                                 args.v3.ucLaneNum = dp_lane_count;
617                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
618                                 args.v3.ucLaneNum = 8;
619                         else
620                                 args.v3.ucLaneNum = 4;
621
622                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
623                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
624                         args.v3.acConfig.ucDigSel = dig->dig_encoder;
625                         switch (bpc) {
626                         case 0:
627                                 args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE;
628                                 break;
629                         case 6:
630                                 args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR;
631                                 break;
632                         case 8:
633                         default:
634                                 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
635                                 break;
636                         case 10:
637                                 args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR;
638                                 break;
639                         case 12:
640                                 args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR;
641                                 break;
642                         case 16:
643                                 args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR;
644                                 break;
645                         }
646                         break;
647                 case 4:
648                         args.v4.ucAction = action;
649                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
650                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
651                                 args.v4.ucPanelMode = panel_mode;
652                         else
653                                 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
654
655                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
656                                 args.v4.ucLaneNum = dp_lane_count;
657                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
658                                 args.v4.ucLaneNum = 8;
659                         else
660                                 args.v4.ucLaneNum = 4;
661
662                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) {
663                                 if (dp_clock == 270000)
664                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
665                                 else if (dp_clock == 540000)
666                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
667                         }
668                         args.v4.acConfig.ucDigSel = dig->dig_encoder;
669                         switch (bpc) {
670                         case 0:
671                                 args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE;
672                                 break;
673                         case 6:
674                                 args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR;
675                                 break;
676                         case 8:
677                         default:
678                                 args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR;
679                                 break;
680                         case 10:
681                                 args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR;
682                                 break;
683                         case 12:
684                                 args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR;
685                                 break;
686                         case 16:
687                                 args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR;
688                                 break;
689                         }
690                         if (hpd_id == RADEON_HPD_NONE)
691                                 args.v4.ucHPD_ID = 0;
692                         else
693                                 args.v4.ucHPD_ID = hpd_id + 1;
694                         break;
695                 default:
696                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
697                         break;
698                 }
699                 break;
700         default:
701                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
702                 break;
703         }
704
705         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
706
707 }
708
709 union dig_transmitter_control {
710         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
711         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
712         DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
713         DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
714         DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
715 };
716
717 void
718 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
719 {
720         struct drm_device *dev = encoder->dev;
721         struct radeon_device *rdev = dev->dev_private;
722         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
723         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
724         struct drm_connector *connector;
725         union dig_transmitter_control args;
726         int index = 0;
727         uint8_t frev, crev;
728         bool is_dp = false;
729         int pll_id = 0;
730         int dp_clock = 0;
731         int dp_lane_count = 0;
732         int connector_object_id = 0;
733         int igp_lane_info = 0;
734         int dig_encoder = dig->dig_encoder;
735         int hpd_id = RADEON_HPD_NONE;
736
737         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
738                 connector = radeon_get_connector_for_encoder_init(encoder);
739                 /* just needed to avoid bailing in the encoder check.  the encoder
740                  * isn't used for init
741                  */
742                 dig_encoder = 0;
743         } else
744                 connector = radeon_get_connector_for_encoder(encoder);
745
746         if (connector) {
747                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
748                 struct radeon_connector_atom_dig *dig_connector =
749                         radeon_connector->con_priv;
750
751                 hpd_id = radeon_connector->hpd.hpd;
752                 dp_clock = dig_connector->dp_clock;
753                 dp_lane_count = dig_connector->dp_lane_count;
754                 connector_object_id =
755                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
756                 igp_lane_info = dig_connector->igp_lane_info;
757         }
758
759         if (encoder->crtc) {
760                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
761                 pll_id = radeon_crtc->pll_id;
762         }
763
764         /* no dig encoder assigned */
765         if (dig_encoder == -1)
766                 return;
767
768         if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
769                 is_dp = true;
770
771         memset(&args, 0, sizeof(args));
772
773         switch (radeon_encoder->encoder_id) {
774         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
775                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
776                 break;
777         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
778         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
779         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
780                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
781                 break;
782         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
783                 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
784                 break;
785         }
786
787         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
788                 return;
789
790         switch (frev) {
791         case 1:
792                 switch (crev) {
793                 case 1:
794                         args.v1.ucAction = action;
795                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
796                                 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
797                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
798                                 args.v1.asMode.ucLaneSel = lane_num;
799                                 args.v1.asMode.ucLaneSet = lane_set;
800                         } else {
801                                 if (is_dp)
802                                         args.v1.usPixelClock =
803                                                 cpu_to_le16(dp_clock / 10);
804                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
805                                         args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
806                                 else
807                                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
808                         }
809
810                         args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
811
812                         if (dig_encoder)
813                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
814                         else
815                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
816
817                         if ((rdev->flags & RADEON_IS_IGP) &&
818                             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
819                                 if (is_dp ||
820                                     !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
821                                         if (igp_lane_info & 0x1)
822                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
823                                         else if (igp_lane_info & 0x2)
824                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
825                                         else if (igp_lane_info & 0x4)
826                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
827                                         else if (igp_lane_info & 0x8)
828                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
829                                 } else {
830                                         if (igp_lane_info & 0x3)
831                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
832                                         else if (igp_lane_info & 0xc)
833                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
834                                 }
835                         }
836
837                         if (dig->linkb)
838                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
839                         else
840                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
841
842                         if (is_dp)
843                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
844                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
845                                 if (dig->coherent_mode)
846                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
847                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
848                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
849                         }
850                         break;
851                 case 2:
852                         args.v2.ucAction = action;
853                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
854                                 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
855                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
856                                 args.v2.asMode.ucLaneSel = lane_num;
857                                 args.v2.asMode.ucLaneSet = lane_set;
858                         } else {
859                                 if (is_dp)
860                                         args.v2.usPixelClock =
861                                                 cpu_to_le16(dp_clock / 10);
862                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
863                                         args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
864                                 else
865                                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
866                         }
867
868                         args.v2.acConfig.ucEncoderSel = dig_encoder;
869                         if (dig->linkb)
870                                 args.v2.acConfig.ucLinkSel = 1;
871
872                         switch (radeon_encoder->encoder_id) {
873                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
874                                 args.v2.acConfig.ucTransmitterSel = 0;
875                                 break;
876                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
877                                 args.v2.acConfig.ucTransmitterSel = 1;
878                                 break;
879                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
880                                 args.v2.acConfig.ucTransmitterSel = 2;
881                                 break;
882                         }
883
884                         if (is_dp) {
885                                 args.v2.acConfig.fCoherentMode = 1;
886                                 args.v2.acConfig.fDPConnector = 1;
887                         } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
888                                 if (dig->coherent_mode)
889                                         args.v2.acConfig.fCoherentMode = 1;
890                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
891                                         args.v2.acConfig.fDualLinkConnector = 1;
892                         }
893                         break;
894                 case 3:
895                         args.v3.ucAction = action;
896                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
897                                 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
898                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
899                                 args.v3.asMode.ucLaneSel = lane_num;
900                                 args.v3.asMode.ucLaneSet = lane_set;
901                         } else {
902                                 if (is_dp)
903                                         args.v3.usPixelClock =
904                                                 cpu_to_le16(dp_clock / 10);
905                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
906                                         args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
907                                 else
908                                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
909                         }
910
911                         if (is_dp)
912                                 args.v3.ucLaneNum = dp_lane_count;
913                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
914                                 args.v3.ucLaneNum = 8;
915                         else
916                                 args.v3.ucLaneNum = 4;
917
918                         if (dig->linkb)
919                                 args.v3.acConfig.ucLinkSel = 1;
920                         if (dig_encoder & 1)
921                                 args.v3.acConfig.ucEncoderSel = 1;
922
923                         /* Select the PLL for the PHY
924                          * DP PHY should be clocked from external src if there is
925                          * one.
926                          */
927                         /* On DCE4, if there is an external clock, it generates the DP ref clock */
928                         if (is_dp && rdev->clock.dp_extclk)
929                                 args.v3.acConfig.ucRefClkSource = 2; /* external src */
930                         else
931                                 args.v3.acConfig.ucRefClkSource = pll_id;
932
933                         switch (radeon_encoder->encoder_id) {
934                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
935                                 args.v3.acConfig.ucTransmitterSel = 0;
936                                 break;
937                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
938                                 args.v3.acConfig.ucTransmitterSel = 1;
939                                 break;
940                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
941                                 args.v3.acConfig.ucTransmitterSel = 2;
942                                 break;
943                         }
944
945                         if (is_dp)
946                                 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
947                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
948                                 if (dig->coherent_mode)
949                                         args.v3.acConfig.fCoherentMode = 1;
950                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
951                                         args.v3.acConfig.fDualLinkConnector = 1;
952                         }
953                         break;
954                 case 4:
955                         args.v4.ucAction = action;
956                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
957                                 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
958                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
959                                 args.v4.asMode.ucLaneSel = lane_num;
960                                 args.v4.asMode.ucLaneSet = lane_set;
961                         } else {
962                                 if (is_dp)
963                                         args.v4.usPixelClock =
964                                                 cpu_to_le16(dp_clock / 10);
965                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
966                                         args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
967                                 else
968                                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
969                         }
970
971                         if (is_dp)
972                                 args.v4.ucLaneNum = dp_lane_count;
973                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
974                                 args.v4.ucLaneNum = 8;
975                         else
976                                 args.v4.ucLaneNum = 4;
977
978                         if (dig->linkb)
979                                 args.v4.acConfig.ucLinkSel = 1;
980                         if (dig_encoder & 1)
981                                 args.v4.acConfig.ucEncoderSel = 1;
982
983                         /* Select the PLL for the PHY
984                          * DP PHY should be clocked from external src if there is
985                          * one.
986                          */
987                         /* On DCE5 DCPLL usually generates the DP ref clock */
988                         if (is_dp) {
989                                 if (rdev->clock.dp_extclk)
990                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
991                                 else
992                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
993                         } else
994                                 args.v4.acConfig.ucRefClkSource = pll_id;
995
996                         switch (radeon_encoder->encoder_id) {
997                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
998                                 args.v4.acConfig.ucTransmitterSel = 0;
999                                 break;
1000                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1001                                 args.v4.acConfig.ucTransmitterSel = 1;
1002                                 break;
1003                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1004                                 args.v4.acConfig.ucTransmitterSel = 2;
1005                                 break;
1006                         }
1007
1008                         if (is_dp)
1009                                 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1010                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1011                                 if (dig->coherent_mode)
1012                                         args.v4.acConfig.fCoherentMode = 1;
1013                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1014                                         args.v4.acConfig.fDualLinkConnector = 1;
1015                         }
1016                         break;
1017                 case 5:
1018                         args.v5.ucAction = action;
1019                         if (is_dp)
1020                                 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1021                         else
1022                                 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1023
1024                         switch (radeon_encoder->encoder_id) {
1025                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1026                                 if (dig->linkb)
1027                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1028                                 else
1029                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1030                                 break;
1031                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1032                                 if (dig->linkb)
1033                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1034                                 else
1035                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1036                                 break;
1037                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1038                                 if (dig->linkb)
1039                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1040                                 else
1041                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1042                                 break;
1043                         }
1044                         if (is_dp)
1045                                 args.v5.ucLaneNum = dp_lane_count;
1046                         else if (radeon_encoder->pixel_clock > 165000)
1047                                 args.v5.ucLaneNum = 8;
1048                         else
1049                                 args.v5.ucLaneNum = 4;
1050                         args.v5.ucConnObjId = connector_object_id;
1051                         args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1052
1053                         if (is_dp && rdev->clock.dp_extclk)
1054                                 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1055                         else
1056                                 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1057
1058                         if (is_dp)
1059                                 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1060                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1061                                 if (dig->coherent_mode)
1062                                         args.v5.asConfig.ucCoherentMode = 1;
1063                         }
1064                         if (hpd_id == RADEON_HPD_NONE)
1065                                 args.v5.asConfig.ucHPDSel = 0;
1066                         else
1067                                 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1068                         args.v5.ucDigEncoderSel = 1 << dig_encoder;
1069                         args.v5.ucDPLaneSet = lane_set;
1070                         break;
1071                 default:
1072                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1073                         break;
1074                 }
1075                 break;
1076         default:
1077                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1078                 break;
1079         }
1080
1081         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1082 }
1083
1084 bool
1085 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1086 {
1087         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1088         struct drm_device *dev = radeon_connector->base.dev;
1089         struct radeon_device *rdev = dev->dev_private;
1090         union dig_transmitter_control args;
1091         int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1092         uint8_t frev, crev;
1093
1094         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1095                 goto done;
1096
1097         if (!ASIC_IS_DCE4(rdev))
1098                 goto done;
1099
1100         if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1101             (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1102                 goto done;
1103
1104         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1105                 goto done;
1106
1107         memset(&args, 0, sizeof(args));
1108
1109         args.v1.ucAction = action;
1110
1111         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1112
1113         /* wait for the panel to power up */
1114         if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1115                 int i;
1116
1117                 for (i = 0; i < 300; i++) {
1118                         if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1119                                 return true;
1120                         mdelay(1);
1121                 }
1122                 return false;
1123         }
1124 done:
1125         return true;
1126 }
1127
1128 union external_encoder_control {
1129         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1130         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1131 };
1132
1133 static void
1134 atombios_external_encoder_setup(struct drm_encoder *encoder,
1135                                 struct drm_encoder *ext_encoder,
1136                                 int action)
1137 {
1138         struct drm_device *dev = encoder->dev;
1139         struct radeon_device *rdev = dev->dev_private;
1140         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1141         struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1142         union external_encoder_control args;
1143         struct drm_connector *connector;
1144         int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1145         u8 frev, crev;
1146         int dp_clock = 0;
1147         int dp_lane_count = 0;
1148         int connector_object_id = 0;
1149         u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1150         int bpc = 8;
1151
1152         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1153                 connector = radeon_get_connector_for_encoder_init(encoder);
1154         else
1155                 connector = radeon_get_connector_for_encoder(encoder);
1156
1157         if (connector) {
1158                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1159                 struct radeon_connector_atom_dig *dig_connector =
1160                         radeon_connector->con_priv;
1161
1162                 dp_clock = dig_connector->dp_clock;
1163                 dp_lane_count = dig_connector->dp_lane_count;
1164                 connector_object_id =
1165                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1166                 /* bpc = connector->display_info.bpc; */
1167         }
1168
1169         memset(&args, 0, sizeof(args));
1170
1171         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1172                 return;
1173
1174         switch (frev) {
1175         case 1:
1176                 /* no params on frev 1 */
1177                 break;
1178         case 2:
1179                 switch (crev) {
1180                 case 1:
1181                 case 2:
1182                         args.v1.sDigEncoder.ucAction = action;
1183                         args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1184                         args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1185
1186                         if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1187                                 if (dp_clock == 270000)
1188                                         args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1189                                 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1190                         } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1191                                 args.v1.sDigEncoder.ucLaneNum = 8;
1192                         else
1193                                 args.v1.sDigEncoder.ucLaneNum = 4;
1194                         break;
1195                 case 3:
1196                         args.v3.sExtEncoder.ucAction = action;
1197                         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1198                                 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1199                         else
1200                                 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1201                         args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1202
1203                         if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1204                                 if (dp_clock == 270000)
1205                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1206                                 else if (dp_clock == 540000)
1207                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1208                                 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1209                         } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1210                                 args.v3.sExtEncoder.ucLaneNum = 8;
1211                         else
1212                                 args.v3.sExtEncoder.ucLaneNum = 4;
1213                         switch (ext_enum) {
1214                         case GRAPH_OBJECT_ENUM_ID1:
1215                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1216                                 break;
1217                         case GRAPH_OBJECT_ENUM_ID2:
1218                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1219                                 break;
1220                         case GRAPH_OBJECT_ENUM_ID3:
1221                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1222                                 break;
1223                         }
1224                         switch (bpc) {
1225                         case 0:
1226                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE;
1227                                 break;
1228                         case 6:
1229                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR;
1230                                 break;
1231                         case 8:
1232                         default:
1233                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR;
1234                                 break;
1235                         case 10:
1236                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR;
1237                                 break;
1238                         case 12:
1239                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR;
1240                                 break;
1241                         case 16:
1242                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR;
1243                                 break;
1244                         }
1245                         break;
1246                 default:
1247                         DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1248                         return;
1249                 }
1250                 break;
1251         default:
1252                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1253                 return;
1254         }
1255         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1256 }
1257
1258 static void
1259 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1260 {
1261         struct drm_device *dev = encoder->dev;
1262         struct radeon_device *rdev = dev->dev_private;
1263         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1264         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1265         ENABLE_YUV_PS_ALLOCATION args;
1266         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1267         uint32_t temp, reg;
1268
1269         memset(&args, 0, sizeof(args));
1270
1271         if (rdev->family >= CHIP_R600)
1272                 reg = R600_BIOS_3_SCRATCH;
1273         else
1274                 reg = RADEON_BIOS_3_SCRATCH;
1275
1276         /* XXX: fix up scratch reg handling */
1277         temp = RREG32(reg);
1278         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1279                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1280                              (radeon_crtc->crtc_id << 18)));
1281         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1282                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1283         else
1284                 WREG32(reg, 0);
1285
1286         if (enable)
1287                 args.ucEnable = ATOM_ENABLE;
1288         args.ucCRTC = radeon_crtc->crtc_id;
1289
1290         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1291
1292         WREG32(reg, temp);
1293 }
1294
1295 static void
1296 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1297 {
1298         struct drm_device *dev = encoder->dev;
1299         struct radeon_device *rdev = dev->dev_private;
1300         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1301         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1302         int index = 0;
1303
1304         memset(&args, 0, sizeof(args));
1305
1306         switch (radeon_encoder->encoder_id) {
1307         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1308         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1309                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1310                 break;
1311         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1312         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1313         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1314                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1315                 break;
1316         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1317                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1318                 break;
1319         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1320                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1321                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1322                 else
1323                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1324                 break;
1325         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1326         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1327                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1328                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1329                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1330                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1331                 else
1332                         index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1333                 break;
1334         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1335         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1336                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1337                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1338                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1339                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1340                 else
1341                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1342                 break;
1343         default:
1344                 return;
1345         }
1346
1347         switch (mode) {
1348         case DRM_MODE_DPMS_ON:
1349                 args.ucAction = ATOM_ENABLE;
1350                 /* workaround for DVOOutputControl on some RS690 systems */
1351                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1352                         u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1353                         WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1354                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1355                         WREG32(RADEON_BIOS_3_SCRATCH, reg);
1356                 } else
1357                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1358                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1359                         args.ucAction = ATOM_LCD_BLON;
1360                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1361                 }
1362                 break;
1363         case DRM_MODE_DPMS_STANDBY:
1364         case DRM_MODE_DPMS_SUSPEND:
1365         case DRM_MODE_DPMS_OFF:
1366                 args.ucAction = ATOM_DISABLE;
1367                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1368                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1369                         args.ucAction = ATOM_LCD_BLOFF;
1370                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1371                 }
1372                 break;
1373         }
1374 }
1375
1376 static void
1377 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1378 {
1379         struct drm_device *dev = encoder->dev;
1380         struct radeon_device *rdev = dev->dev_private;
1381         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1382         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1383         struct radeon_connector *radeon_connector = NULL;
1384         struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1385
1386         if (connector) {
1387                 radeon_connector = to_radeon_connector(connector);
1388                 radeon_dig_connector = radeon_connector->con_priv;
1389         }
1390
1391         switch (mode) {
1392         case DRM_MODE_DPMS_ON:
1393                 /* some early dce3.2 boards have a bug in their transmitter control table */
1394                 if ((rdev->family == CHIP_RV710) || (rdev->family == CHIP_RV730) ||
1395                     ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1396                         if (ASIC_IS_DCE6(rdev)) {
1397                                 /* It seems we need to call ATOM_ENCODER_CMD_SETUP again
1398                                  * before reenabling encoder on DPMS ON, otherwise we never
1399                                  * get picture
1400                                  */
1401                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1402                         }
1403                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1404                 } else {
1405                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1406                 }
1407                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1408                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1409                                 atombios_set_edp_panel_power(connector,
1410                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
1411                                 radeon_dig_connector->edp_on = true;
1412                         }
1413                         radeon_dp_link_train(encoder, connector);
1414                         if (ASIC_IS_DCE4(rdev))
1415                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1416                 }
1417                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1418                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1419                 break;
1420         case DRM_MODE_DPMS_STANDBY:
1421         case DRM_MODE_DPMS_SUSPEND:
1422         case DRM_MODE_DPMS_OFF:
1423                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev))
1424                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1425                 else
1426                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1427                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1428                         if (ASIC_IS_DCE4(rdev))
1429                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1430                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1431                                 atombios_set_edp_panel_power(connector,
1432                                                              ATOM_TRANSMITTER_ACTION_POWER_OFF);
1433                                 radeon_dig_connector->edp_on = false;
1434                         }
1435                 }
1436                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1437                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1438                 break;
1439         }
1440 }
1441
1442 static void
1443 radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
1444                              struct drm_encoder *ext_encoder,
1445                              int mode)
1446 {
1447         struct drm_device *dev = encoder->dev;
1448         struct radeon_device *rdev = dev->dev_private;
1449
1450         switch (mode) {
1451         case DRM_MODE_DPMS_ON:
1452         default:
1453                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
1454                         atombios_external_encoder_setup(encoder, ext_encoder,
1455                                                         EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1456                         atombios_external_encoder_setup(encoder, ext_encoder,
1457                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1458                 } else
1459                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1460                 break;
1461         case DRM_MODE_DPMS_STANDBY:
1462         case DRM_MODE_DPMS_SUSPEND:
1463         case DRM_MODE_DPMS_OFF:
1464                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
1465                         atombios_external_encoder_setup(encoder, ext_encoder,
1466                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1467                         atombios_external_encoder_setup(encoder, ext_encoder,
1468                                                         EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1469                 } else
1470                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1471                 break;
1472         }
1473 }
1474
1475 static void
1476 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1477 {
1478         struct drm_device *dev = encoder->dev;
1479         struct radeon_device *rdev = dev->dev_private;
1480         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1481         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1482
1483         DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1484                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1485                   radeon_encoder->active_device);
1486         switch (radeon_encoder->encoder_id) {
1487         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1488         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1489         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1490         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1491         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1492         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1493         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1494         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1495                 radeon_atom_encoder_dpms_avivo(encoder, mode);
1496                 break;
1497         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1498         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1499         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1500         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1501                 radeon_atom_encoder_dpms_dig(encoder, mode);
1502                 break;
1503         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1504                 if (ASIC_IS_DCE5(rdev)) {
1505                         switch (mode) {
1506                         case DRM_MODE_DPMS_ON:
1507                                 atombios_dvo_setup(encoder, ATOM_ENABLE);
1508                                 break;
1509                         case DRM_MODE_DPMS_STANDBY:
1510                         case DRM_MODE_DPMS_SUSPEND:
1511                         case DRM_MODE_DPMS_OFF:
1512                                 atombios_dvo_setup(encoder, ATOM_DISABLE);
1513                                 break;
1514                         }
1515                 } else if (ASIC_IS_DCE3(rdev))
1516                         radeon_atom_encoder_dpms_dig(encoder, mode);
1517                 else
1518                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1519                 break;
1520         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1521         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1522                 if (ASIC_IS_DCE5(rdev)) {
1523                         switch (mode) {
1524                         case DRM_MODE_DPMS_ON:
1525                                 atombios_dac_setup(encoder, ATOM_ENABLE);
1526                                 break;
1527                         case DRM_MODE_DPMS_STANDBY:
1528                         case DRM_MODE_DPMS_SUSPEND:
1529                         case DRM_MODE_DPMS_OFF:
1530                                 atombios_dac_setup(encoder, ATOM_DISABLE);
1531                                 break;
1532                         }
1533                 } else
1534                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1535                 break;
1536         default:
1537                 return;
1538         }
1539
1540         if (ext_encoder)
1541                 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
1542
1543         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1544
1545 }
1546
1547 union crtc_source_param {
1548         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1549         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1550 };
1551
1552 static void
1553 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1554 {
1555         struct drm_device *dev = encoder->dev;
1556         struct radeon_device *rdev = dev->dev_private;
1557         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1558         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1559         union crtc_source_param args;
1560         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1561         uint8_t frev, crev;
1562         struct radeon_encoder_atom_dig *dig;
1563
1564         memset(&args, 0, sizeof(args));
1565
1566         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1567                 return;
1568
1569         switch (frev) {
1570         case 1:
1571                 switch (crev) {
1572                 case 1:
1573                 default:
1574                         if (ASIC_IS_AVIVO(rdev))
1575                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
1576                         else {
1577                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1578                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
1579                                 } else {
1580                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1581                                 }
1582                         }
1583                         switch (radeon_encoder->encoder_id) {
1584                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1585                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1586                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1587                                 break;
1588                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1589                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1590                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1591                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1592                                 else
1593                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1594                                 break;
1595                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1596                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1597                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1598                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1599                                 break;
1600                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1601                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1602                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1603                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1604                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1605                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1606                                 else
1607                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1608                                 break;
1609                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1610                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1611                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1612                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1613                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1614                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1615                                 else
1616                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1617                                 break;
1618                         }
1619                         break;
1620                 case 2:
1621                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1622                         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1623                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1624
1625                                 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1626                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1627                                 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1628                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1629                                 else
1630                                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1631                         } else
1632                                 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1633                         switch (radeon_encoder->encoder_id) {
1634                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1635                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1636                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1637                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1638                                 dig = radeon_encoder->enc_priv;
1639                                 switch (dig->dig_encoder) {
1640                                 case 0:
1641                                         args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1642                                         break;
1643                                 case 1:
1644                                         args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1645                                         break;
1646                                 case 2:
1647                                         args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1648                                         break;
1649                                 case 3:
1650                                         args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1651                                         break;
1652                                 case 4:
1653                                         args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1654                                         break;
1655                                 case 5:
1656                                         args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1657                                         break;
1658                                 }
1659                                 break;
1660                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1661                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1662                                 break;
1663                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1664                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1665                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1666                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1667                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1668                                 else
1669                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1670                                 break;
1671                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1672                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1673                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1674                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1675                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1676                                 else
1677                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1678                                 break;
1679                         }
1680                         break;
1681                 }
1682                 break;
1683         default:
1684                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1685                 return;
1686         }
1687
1688         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1689
1690         /* update scratch regs with new routing */
1691         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1692 }
1693
1694 static void
1695 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1696                               struct drm_display_mode *mode)
1697 {
1698         struct drm_device *dev = encoder->dev;
1699         struct radeon_device *rdev = dev->dev_private;
1700         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1701         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1702
1703         /* Funky macbooks */
1704         if ((dev->pdev->device == 0x71C5) &&
1705             (dev->pdev->subsystem_vendor == 0x106b) &&
1706             (dev->pdev->subsystem_device == 0x0080)) {
1707                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1708                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1709
1710                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1711                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1712
1713                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1714                 }
1715         }
1716
1717         /* set scaler clears this on some chips */
1718         if (ASIC_IS_AVIVO(rdev) &&
1719             (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1720                 if (ASIC_IS_DCE4(rdev)) {
1721                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1722                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1723                                        EVERGREEN_INTERLEAVE_EN);
1724                         else
1725                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1726                 } else {
1727                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1728                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1729                                        AVIVO_D1MODE_INTERLEAVE_EN);
1730                         else
1731                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1732                 }
1733         }
1734 }
1735
1736 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1737 {
1738         struct drm_device *dev = encoder->dev;
1739         struct radeon_device *rdev = dev->dev_private;
1740         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1741         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1742         struct drm_encoder *test_encoder;
1743         struct radeon_encoder_atom_dig *dig;
1744         uint32_t dig_enc_in_use = 0;
1745
1746         /* DCE4/5 */
1747         if (ASIC_IS_DCE4(rdev)) {
1748                 dig = radeon_encoder->enc_priv;
1749                 if (ASIC_IS_DCE41(rdev)) {
1750                         /* ontario follows DCE4 */
1751                         if (rdev->family == CHIP_PALM) {
1752                                 if (dig->linkb)
1753                                         return 1;
1754                                 else
1755                                         return 0;
1756                         } else
1757                                 /* llano follows DCE3.2 */
1758                                 return radeon_crtc->crtc_id;
1759                 } else {
1760                         switch (radeon_encoder->encoder_id) {
1761                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1762                                 if (dig->linkb)
1763                                         return 1;
1764                                 else
1765                                         return 0;
1766                                 break;
1767                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1768                                 if (dig->linkb)
1769                                         return 3;
1770                                 else
1771                                         return 2;
1772                                 break;
1773                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1774                                 if (dig->linkb)
1775                                         return 5;
1776                                 else
1777                                         return 4;
1778                                 break;
1779                         }
1780                 }
1781         }
1782
1783         /* on DCE32 and encoder can driver any block so just crtc id */
1784         if (ASIC_IS_DCE32(rdev)) {
1785                 return radeon_crtc->crtc_id;
1786         }
1787
1788         /* on DCE3 - LVTMA can only be driven by DIGB */
1789         list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1790                 struct radeon_encoder *radeon_test_encoder;
1791
1792                 if (encoder == test_encoder)
1793                         continue;
1794
1795                 if (!radeon_encoder_is_digital(test_encoder))
1796                         continue;
1797
1798                 radeon_test_encoder = to_radeon_encoder(test_encoder);
1799                 dig = radeon_test_encoder->enc_priv;
1800
1801                 if (dig->dig_encoder >= 0)
1802                         dig_enc_in_use |= (1 << dig->dig_encoder);
1803         }
1804
1805         if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1806                 if (dig_enc_in_use & 0x2)
1807                         DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1808                 return 1;
1809         }
1810         if (!(dig_enc_in_use & 1))
1811                 return 0;
1812         return 1;
1813 }
1814
1815 /* This only needs to be called once at startup */
1816 void
1817 radeon_atom_encoder_init(struct radeon_device *rdev)
1818 {
1819         struct drm_device *dev = rdev->ddev;
1820         struct drm_encoder *encoder;
1821
1822         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1823                 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1824                 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1825
1826                 switch (radeon_encoder->encoder_id) {
1827                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1828                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1829                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1830                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1831                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1832                         break;
1833                 default:
1834                         break;
1835                 }
1836
1837                 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
1838                         atombios_external_encoder_setup(encoder, ext_encoder,
1839                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
1840         }
1841 }
1842
1843 static void
1844 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1845                              struct drm_display_mode *mode,
1846                              struct drm_display_mode *adjusted_mode)
1847 {
1848         struct drm_device *dev = encoder->dev;
1849         struct radeon_device *rdev = dev->dev_private;
1850         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1851         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1852
1853         radeon_encoder->pixel_clock = adjusted_mode->clock;
1854
1855         if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1856                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1857                         atombios_yuv_setup(encoder, true);
1858                 else
1859                         atombios_yuv_setup(encoder, false);
1860         }
1861
1862         switch (radeon_encoder->encoder_id) {
1863         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1864         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1865         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1866         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1867                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1868                 break;
1869         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1870         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1871         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1872         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1873                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1874                         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1875                         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1876
1877                         if (!connector)
1878                                 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1879                         else
1880                                 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1881
1882                         /* setup and enable the encoder */
1883                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1884                         atombios_dig_encoder_setup(encoder,
1885                                                    ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1886                                                    dig->panel_mode);
1887                 } else if (ASIC_IS_DCE4(rdev)) {
1888                         /* disable the transmitter */
1889                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1890                         /* setup and enable the encoder */
1891                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1892
1893                         /* enable the transmitter */
1894                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1895                 } else {
1896                         /* disable the encoder and transmitter */
1897                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1898                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1899
1900                         /* setup and enable the encoder and transmitter */
1901                         atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1902                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1903                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1904                 }
1905                 break;
1906         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1907         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1908         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1909                 atombios_dvo_setup(encoder, ATOM_ENABLE);
1910                 break;
1911         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1912         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1913         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1914         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1915                 atombios_dac_setup(encoder, ATOM_ENABLE);
1916                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1917                         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1918                                 atombios_tv_setup(encoder, ATOM_ENABLE);
1919                         else
1920                                 atombios_tv_setup(encoder, ATOM_DISABLE);
1921                 }
1922                 break;
1923         }
1924
1925         if (ext_encoder) {
1926                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1927                         atombios_external_encoder_setup(encoder, ext_encoder,
1928                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1929                 else
1930                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1931         }
1932
1933         atombios_apply_encoder_quirks(encoder, adjusted_mode);
1934
1935         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1936                 r600_hdmi_enable(encoder);
1937                 r600_hdmi_setmode(encoder, adjusted_mode);
1938         }
1939 }
1940
1941 static bool
1942 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1943 {
1944         struct drm_device *dev = encoder->dev;
1945         struct radeon_device *rdev = dev->dev_private;
1946         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1947         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1948
1949         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1950                                        ATOM_DEVICE_CV_SUPPORT |
1951                                        ATOM_DEVICE_CRT_SUPPORT)) {
1952                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1953                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1954                 uint8_t frev, crev;
1955
1956                 memset(&args, 0, sizeof(args));
1957
1958                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1959                         return false;
1960
1961                 args.sDacload.ucMisc = 0;
1962
1963                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1964                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1965                         args.sDacload.ucDacType = ATOM_DAC_A;
1966                 else
1967                         args.sDacload.ucDacType = ATOM_DAC_B;
1968
1969                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1970                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1971                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1972                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1973                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1974                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1975                         if (crev >= 3)
1976                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1977                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1978                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1979                         if (crev >= 3)
1980                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1981                 }
1982
1983                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1984
1985                 return true;
1986         } else
1987                 return false;
1988 }
1989
1990 static enum drm_connector_status
1991 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1992 {
1993         struct drm_device *dev = encoder->dev;
1994         struct radeon_device *rdev = dev->dev_private;
1995         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1996         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1997         uint32_t bios_0_scratch;
1998
1999         if (!atombios_dac_load_detect(encoder, connector)) {
2000                 DRM_DEBUG_KMS("detect returned false \n");
2001                 return connector_status_unknown;
2002         }
2003
2004         if (rdev->family >= CHIP_R600)
2005                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2006         else
2007                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2008
2009         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2010         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2011                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2012                         return connector_status_connected;
2013         }
2014         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2015                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2016                         return connector_status_connected;
2017         }
2018         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2019                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2020                         return connector_status_connected;
2021         }
2022         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2023                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2024                         return connector_status_connected; /* CTV */
2025                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2026                         return connector_status_connected; /* STV */
2027         }
2028         return connector_status_disconnected;
2029 }
2030
2031 static enum drm_connector_status
2032 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2033 {
2034         struct drm_device *dev = encoder->dev;
2035         struct radeon_device *rdev = dev->dev_private;
2036         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2037         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2038         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2039         u32 bios_0_scratch;
2040
2041         if (!ASIC_IS_DCE4(rdev))
2042                 return connector_status_unknown;
2043
2044         if (!ext_encoder)
2045                 return connector_status_unknown;
2046
2047         if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2048                 return connector_status_unknown;
2049
2050         /* load detect on the dp bridge */
2051         atombios_external_encoder_setup(encoder, ext_encoder,
2052                                         EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2053
2054         bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2055
2056         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2057         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2058                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2059                         return connector_status_connected;
2060         }
2061         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2062                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2063                         return connector_status_connected;
2064         }
2065         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2066                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2067                         return connector_status_connected;
2068         }
2069         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2070                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2071                         return connector_status_connected; /* CTV */
2072                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2073                         return connector_status_connected; /* STV */
2074         }
2075         return connector_status_disconnected;
2076 }
2077
2078 void
2079 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2080 {
2081         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2082
2083         if (ext_encoder)
2084                 /* ddc_setup on the dp bridge */
2085                 atombios_external_encoder_setup(encoder, ext_encoder,
2086                                                 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2087
2088 }
2089
2090 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2091 {
2092         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2093         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2094
2095         if ((radeon_encoder->active_device &
2096              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2097             (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2098              ENCODER_OBJECT_ID_NONE)) {
2099                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2100                 if (dig)
2101                         dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
2102         }
2103
2104         radeon_atom_output_lock(encoder, true);
2105         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2106
2107         if (connector) {
2108                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2109
2110                 /* select the clock/data port if it uses a router */
2111                 if (radeon_connector->router.cd_valid)
2112                         radeon_router_select_cd_port(radeon_connector);
2113
2114                 /* turn eDP panel on for mode set */
2115                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2116                         atombios_set_edp_panel_power(connector,
2117                                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
2118         }
2119
2120         /* this is needed for the pll/ss setup to work correctly in some cases */
2121         atombios_set_encoder_crtc_source(encoder);
2122 }
2123
2124 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2125 {
2126         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2127         radeon_atom_output_lock(encoder, false);
2128 }
2129
2130 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2131 {
2132         struct drm_device *dev = encoder->dev;
2133         struct radeon_device *rdev = dev->dev_private;
2134         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2135         struct radeon_encoder_atom_dig *dig;
2136
2137         /* check for pre-DCE3 cards with shared encoders;
2138          * can't really use the links individually, so don't disable
2139          * the encoder if it's in use by another connector
2140          */
2141         if (!ASIC_IS_DCE3(rdev)) {
2142                 struct drm_encoder *other_encoder;
2143                 struct radeon_encoder *other_radeon_encoder;
2144
2145                 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2146                         other_radeon_encoder = to_radeon_encoder(other_encoder);
2147                         if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2148                             drm_helper_encoder_in_use(other_encoder))
2149                                 goto disable_done;
2150                 }
2151         }
2152
2153         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2154
2155         switch (radeon_encoder->encoder_id) {
2156         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2157         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2158         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2159         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2160                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2161                 break;
2162         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2163         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2164         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2165         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2166                 if (ASIC_IS_DCE4(rdev))
2167                         /* disable the transmitter */
2168                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2169                 else {
2170                         /* disable the encoder and transmitter */
2171                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
2172                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
2173                 }
2174                 break;
2175         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2176         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2177         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2178                 atombios_dvo_setup(encoder, ATOM_DISABLE);
2179                 break;
2180         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2181         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2182         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2183         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2184                 atombios_dac_setup(encoder, ATOM_DISABLE);
2185                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2186                         atombios_tv_setup(encoder, ATOM_DISABLE);
2187                 break;
2188         }
2189
2190 disable_done:
2191         if (radeon_encoder_is_digital(encoder)) {
2192                 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
2193                         r600_hdmi_disable(encoder);
2194                 dig = radeon_encoder->enc_priv;
2195                 dig->dig_encoder = -1;
2196         }
2197         radeon_encoder->active_device = 0;
2198 }
2199
2200 /* these are handled by the primary encoders */
2201 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2202 {
2203
2204 }
2205
2206 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2207 {
2208
2209 }
2210
2211 static void
2212 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2213                          struct drm_display_mode *mode,
2214                          struct drm_display_mode *adjusted_mode)
2215 {
2216
2217 }
2218
2219 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2220 {
2221
2222 }
2223
2224 static void
2225 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2226 {
2227
2228 }
2229
2230 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2231                                        struct drm_display_mode *mode,
2232                                        struct drm_display_mode *adjusted_mode)
2233 {
2234         return true;
2235 }
2236
2237 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2238         .dpms = radeon_atom_ext_dpms,
2239         .mode_fixup = radeon_atom_ext_mode_fixup,
2240         .prepare = radeon_atom_ext_prepare,
2241         .mode_set = radeon_atom_ext_mode_set,
2242         .commit = radeon_atom_ext_commit,
2243         .disable = radeon_atom_ext_disable,
2244         /* no detect for TMDS/LVDS yet */
2245 };
2246
2247 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2248         .dpms = radeon_atom_encoder_dpms,
2249         .mode_fixup = radeon_atom_mode_fixup,
2250         .prepare = radeon_atom_encoder_prepare,
2251         .mode_set = radeon_atom_encoder_mode_set,
2252         .commit = radeon_atom_encoder_commit,
2253         .disable = radeon_atom_encoder_disable,
2254         .detect = radeon_atom_dig_detect,
2255 };
2256
2257 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2258         .dpms = radeon_atom_encoder_dpms,
2259         .mode_fixup = radeon_atom_mode_fixup,
2260         .prepare = radeon_atom_encoder_prepare,
2261         .mode_set = radeon_atom_encoder_mode_set,
2262         .commit = radeon_atom_encoder_commit,
2263         .detect = radeon_atom_dac_detect,
2264 };
2265
2266 void radeon_enc_destroy(struct drm_encoder *encoder)
2267 {
2268         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2269         kfree(radeon_encoder->enc_priv);
2270         drm_encoder_cleanup(encoder);
2271         kfree(radeon_encoder);
2272 }
2273
2274 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2275         .destroy = radeon_enc_destroy,
2276 };
2277
2278 struct radeon_encoder_atom_dac *
2279 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2280 {
2281         struct drm_device *dev = radeon_encoder->base.dev;
2282         struct radeon_device *rdev = dev->dev_private;
2283         struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2284
2285         if (!dac)
2286                 return NULL;
2287
2288         dac->tv_std = radeon_atombios_get_tv_info(rdev);
2289         return dac;
2290 }
2291
2292 struct radeon_encoder_atom_dig *
2293 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2294 {
2295         int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2296         struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2297
2298         if (!dig)
2299                 return NULL;
2300
2301         /* coherent mode by default */
2302         dig->coherent_mode = true;
2303         dig->dig_encoder = -1;
2304
2305         if (encoder_enum == 2)
2306                 dig->linkb = true;
2307         else
2308                 dig->linkb = false;
2309
2310         return dig;
2311 }
2312
2313 void
2314 radeon_add_atom_encoder(struct drm_device *dev,
2315                         uint32_t encoder_enum,
2316                         uint32_t supported_device,
2317                         u16 caps)
2318 {
2319         struct radeon_device *rdev = dev->dev_private;
2320         struct drm_encoder *encoder;
2321         struct radeon_encoder *radeon_encoder;
2322
2323         /* see if we already added it */
2324         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2325                 radeon_encoder = to_radeon_encoder(encoder);
2326                 if (radeon_encoder->encoder_enum == encoder_enum) {
2327                         radeon_encoder->devices |= supported_device;
2328                         return;
2329                 }
2330
2331         }
2332
2333         /* add a new one */
2334         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2335         if (!radeon_encoder)
2336                 return;
2337
2338         encoder = &radeon_encoder->base;
2339         switch (rdev->num_crtc) {
2340         case 1:
2341                 encoder->possible_crtcs = 0x1;
2342                 break;
2343         case 2:
2344         default:
2345                 encoder->possible_crtcs = 0x3;
2346                 break;
2347         case 4:
2348                 encoder->possible_crtcs = 0xf;
2349                 break;
2350         case 6:
2351                 encoder->possible_crtcs = 0x3f;
2352                 break;
2353         }
2354
2355         radeon_encoder->enc_priv = NULL;
2356
2357         radeon_encoder->encoder_enum = encoder_enum;
2358         radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2359         radeon_encoder->devices = supported_device;
2360         radeon_encoder->rmx_type = RMX_OFF;
2361         radeon_encoder->underscan_type = UNDERSCAN_OFF;
2362         radeon_encoder->is_ext_encoder = false;
2363         radeon_encoder->caps = caps;
2364
2365         switch (radeon_encoder->encoder_id) {
2366         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2367         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2368         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2369         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2370                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2371                         radeon_encoder->rmx_type = RMX_FULL;
2372                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2373                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2374                 } else {
2375                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2376                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2377                 }
2378                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2379                 break;
2380         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2381                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2382                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2383                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2384                 break;
2385         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2386         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2387         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2388                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2389                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2390                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2391                 break;
2392         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2393         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2394         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2395         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2396         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2397         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2398         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2399                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2400                         radeon_encoder->rmx_type = RMX_FULL;
2401                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2402                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2403                 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2404                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2405                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2406                 } else {
2407                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2408                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2409                 }
2410                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2411                 break;
2412         case ENCODER_OBJECT_ID_SI170B:
2413         case ENCODER_OBJECT_ID_CH7303:
2414         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2415         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2416         case ENCODER_OBJECT_ID_TITFP513:
2417         case ENCODER_OBJECT_ID_VT1623:
2418         case ENCODER_OBJECT_ID_HDMI_SI1930:
2419         case ENCODER_OBJECT_ID_TRAVIS:
2420         case ENCODER_OBJECT_ID_NUTMEG:
2421                 /* these are handled by the primary encoders */
2422                 radeon_encoder->is_ext_encoder = true;
2423                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2424                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2425                 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2426                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2427                 else
2428                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2429                 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2430                 break;
2431         }
2432 }