drm/radeon: don't allow audio on DCE6
[linux-2.6.git] / drivers / gpu / drm / radeon / atombios_encoders.c
1 /*
2  * Copyright 2007-11 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: Dave Airlie
24  *          Alex Deucher
25  */
26 #include "drmP.h"
27 #include "drm_crtc_helper.h"
28 #include "radeon_drm.h"
29 #include "radeon.h"
30 #include "atom.h"
31
32 extern int atom_debug;
33
34 /* evil but including atombios.h is much worse */
35 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
36                                 struct drm_display_mode *mode);
37
38
39 static inline bool radeon_encoder_is_digital(struct drm_encoder *encoder)
40 {
41         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
42         switch (radeon_encoder->encoder_id) {
43         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
44         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
45         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
46         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
47         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
48         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
49         case ENCODER_OBJECT_ID_INTERNAL_DDI:
50         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
51         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
52         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
53         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
54                 return true;
55         default:
56                 return false;
57         }
58 }
59
60 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
61                                    struct drm_display_mode *mode,
62                                    struct drm_display_mode *adjusted_mode)
63 {
64         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
65         struct drm_device *dev = encoder->dev;
66         struct radeon_device *rdev = dev->dev_private;
67
68         /* set the active encoder to connector routing */
69         radeon_encoder_set_active_device(encoder);
70         drm_mode_set_crtcinfo(adjusted_mode, 0);
71
72         /* hw bug */
73         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
74             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
75                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
76
77         /* get the native mode for LVDS */
78         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT))
79                 radeon_panel_mode_fixup(encoder, adjusted_mode);
80
81         /* get the native mode for TV */
82         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
83                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
84                 if (tv_dac) {
85                         if (tv_dac->tv_std == TV_STD_NTSC ||
86                             tv_dac->tv_std == TV_STD_NTSC_J ||
87                             tv_dac->tv_std == TV_STD_PAL_M)
88                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
89                         else
90                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
91                 }
92         }
93
94         if (ASIC_IS_DCE3(rdev) &&
95             ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
96              (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
97                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
98                 radeon_dp_set_link_config(connector, adjusted_mode);
99         }
100
101         return true;
102 }
103
104 static void
105 atombios_dac_setup(struct drm_encoder *encoder, int action)
106 {
107         struct drm_device *dev = encoder->dev;
108         struct radeon_device *rdev = dev->dev_private;
109         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
110         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
111         int index = 0;
112         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
113
114         memset(&args, 0, sizeof(args));
115
116         switch (radeon_encoder->encoder_id) {
117         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
118         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
119                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
120                 break;
121         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
122         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
123                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
124                 break;
125         }
126
127         args.ucAction = action;
128
129         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
130                 args.ucDacStandard = ATOM_DAC1_PS2;
131         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
132                 args.ucDacStandard = ATOM_DAC1_CV;
133         else {
134                 switch (dac_info->tv_std) {
135                 case TV_STD_PAL:
136                 case TV_STD_PAL_M:
137                 case TV_STD_SCART_PAL:
138                 case TV_STD_SECAM:
139                 case TV_STD_PAL_CN:
140                         args.ucDacStandard = ATOM_DAC1_PAL;
141                         break;
142                 case TV_STD_NTSC:
143                 case TV_STD_NTSC_J:
144                 case TV_STD_PAL_60:
145                 default:
146                         args.ucDacStandard = ATOM_DAC1_NTSC;
147                         break;
148                 }
149         }
150         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
151
152         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
153
154 }
155
156 static void
157 atombios_tv_setup(struct drm_encoder *encoder, int action)
158 {
159         struct drm_device *dev = encoder->dev;
160         struct radeon_device *rdev = dev->dev_private;
161         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
162         TV_ENCODER_CONTROL_PS_ALLOCATION args;
163         int index = 0;
164         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
165
166         memset(&args, 0, sizeof(args));
167
168         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
169
170         args.sTVEncoder.ucAction = action;
171
172         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
173                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
174         else {
175                 switch (dac_info->tv_std) {
176                 case TV_STD_NTSC:
177                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
178                         break;
179                 case TV_STD_PAL:
180                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
181                         break;
182                 case TV_STD_PAL_M:
183                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
184                         break;
185                 case TV_STD_PAL_60:
186                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
187                         break;
188                 case TV_STD_NTSC_J:
189                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
190                         break;
191                 case TV_STD_SCART_PAL:
192                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
193                         break;
194                 case TV_STD_SECAM:
195                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
196                         break;
197                 case TV_STD_PAL_CN:
198                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
199                         break;
200                 default:
201                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
202                         break;
203                 }
204         }
205
206         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
207
208         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
209
210 }
211
212 union dvo_encoder_control {
213         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
214         DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
215         DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
216 };
217
218 void
219 atombios_dvo_setup(struct drm_encoder *encoder, int action)
220 {
221         struct drm_device *dev = encoder->dev;
222         struct radeon_device *rdev = dev->dev_private;
223         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
224         union dvo_encoder_control args;
225         int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
226         uint8_t frev, crev;
227
228         memset(&args, 0, sizeof(args));
229
230         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
231                 return;
232
233         /* some R4xx chips have the wrong frev */
234         if (rdev->family <= CHIP_RV410)
235                 frev = 1;
236
237         switch (frev) {
238         case 1:
239                 switch (crev) {
240                 case 1:
241                         /* R4xx, R5xx */
242                         args.ext_tmds.sXTmdsEncoder.ucEnable = action;
243
244                         if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
245                                 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
246
247                         args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
248                         break;
249                 case 2:
250                         /* RS600/690/740 */
251                         args.dvo.sDVOEncoder.ucAction = action;
252                         args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
253                         /* DFP1, CRT1, TV1 depending on the type of port */
254                         args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
255
256                         if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
257                                 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
258                         break;
259                 case 3:
260                         /* R6xx */
261                         args.dvo_v3.ucAction = action;
262                         args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
263                         args.dvo_v3.ucDVOConfig = 0; /* XXX */
264                         break;
265                 default:
266                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
267                         break;
268                 }
269                 break;
270         default:
271                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
272                 break;
273         }
274
275         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
276 }
277
278 union lvds_encoder_control {
279         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
280         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
281 };
282
283 void
284 atombios_digital_setup(struct drm_encoder *encoder, int action)
285 {
286         struct drm_device *dev = encoder->dev;
287         struct radeon_device *rdev = dev->dev_private;
288         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
289         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
290         union lvds_encoder_control args;
291         int index = 0;
292         int hdmi_detected = 0;
293         uint8_t frev, crev;
294
295         if (!dig)
296                 return;
297
298         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
299                 hdmi_detected = 1;
300
301         memset(&args, 0, sizeof(args));
302
303         switch (radeon_encoder->encoder_id) {
304         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
305                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
306                 break;
307         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
308         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
309                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
310                 break;
311         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
312                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
313                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
314                 else
315                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
316                 break;
317         }
318
319         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
320                 return;
321
322         switch (frev) {
323         case 1:
324         case 2:
325                 switch (crev) {
326                 case 1:
327                         args.v1.ucMisc = 0;
328                         args.v1.ucAction = action;
329                         if (hdmi_detected)
330                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
331                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
332                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
333                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
334                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
335                                 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
336                                         args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
337                         } else {
338                                 if (dig->linkb)
339                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
340                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
341                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
342                                 /*if (pScrn->rgbBits == 8) */
343                                 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
344                         }
345                         break;
346                 case 2:
347                 case 3:
348                         args.v2.ucMisc = 0;
349                         args.v2.ucAction = action;
350                         if (crev == 3) {
351                                 if (dig->coherent_mode)
352                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
353                         }
354                         if (hdmi_detected)
355                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
356                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
357                         args.v2.ucTruncate = 0;
358                         args.v2.ucSpatial = 0;
359                         args.v2.ucTemporal = 0;
360                         args.v2.ucFRC = 0;
361                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
362                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
363                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
364                                 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
365                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
366                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
367                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
368                                 }
369                                 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
370                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
371                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
372                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
373                                         if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
374                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
375                                 }
376                         } else {
377                                 if (dig->linkb)
378                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
379                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
380                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
381                         }
382                         break;
383                 default:
384                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
385                         break;
386                 }
387                 break;
388         default:
389                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
390                 break;
391         }
392
393         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
394 }
395
396 int
397 atombios_get_encoder_mode(struct drm_encoder *encoder)
398 {
399         struct drm_device *dev = encoder->dev;
400         struct radeon_device *rdev = dev->dev_private;
401         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
402         struct drm_connector *connector;
403         struct radeon_connector *radeon_connector;
404         struct radeon_connector_atom_dig *dig_connector;
405
406         /* dp bridges are always DP */
407         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
408                 return ATOM_ENCODER_MODE_DP;
409
410         /* DVO is always DVO */
411         if (radeon_encoder->encoder_id == ATOM_ENCODER_MODE_DVO)
412                 return ATOM_ENCODER_MODE_DVO;
413
414         connector = radeon_get_connector_for_encoder(encoder);
415         /* if we don't have an active device yet, just use one of
416          * the connectors tied to the encoder.
417          */
418         if (!connector)
419                 connector = radeon_get_connector_for_encoder_init(encoder);
420         radeon_connector = to_radeon_connector(connector);
421
422         switch (connector->connector_type) {
423         case DRM_MODE_CONNECTOR_DVII:
424         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
425                 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
426                     radeon_audio &&
427                     !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
428                         return ATOM_ENCODER_MODE_HDMI;
429                 else if (radeon_connector->use_digital)
430                         return ATOM_ENCODER_MODE_DVI;
431                 else
432                         return ATOM_ENCODER_MODE_CRT;
433                 break;
434         case DRM_MODE_CONNECTOR_DVID:
435         case DRM_MODE_CONNECTOR_HDMIA:
436         default:
437                 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
438                     radeon_audio &&
439                     !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
440                         return ATOM_ENCODER_MODE_HDMI;
441                 else
442                         return ATOM_ENCODER_MODE_DVI;
443                 break;
444         case DRM_MODE_CONNECTOR_LVDS:
445                 return ATOM_ENCODER_MODE_LVDS;
446                 break;
447         case DRM_MODE_CONNECTOR_DisplayPort:
448                 dig_connector = radeon_connector->con_priv;
449                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
450                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
451                         return ATOM_ENCODER_MODE_DP;
452                 else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
453                          radeon_audio &&
454                          !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
455                         return ATOM_ENCODER_MODE_HDMI;
456                 else
457                         return ATOM_ENCODER_MODE_DVI;
458                 break;
459         case DRM_MODE_CONNECTOR_eDP:
460                 return ATOM_ENCODER_MODE_DP;
461         case DRM_MODE_CONNECTOR_DVIA:
462         case DRM_MODE_CONNECTOR_VGA:
463                 return ATOM_ENCODER_MODE_CRT;
464                 break;
465         case DRM_MODE_CONNECTOR_Composite:
466         case DRM_MODE_CONNECTOR_SVIDEO:
467         case DRM_MODE_CONNECTOR_9PinDIN:
468                 /* fix me */
469                 return ATOM_ENCODER_MODE_TV;
470                 /*return ATOM_ENCODER_MODE_CV;*/
471                 break;
472         }
473 }
474
475 /*
476  * DIG Encoder/Transmitter Setup
477  *
478  * DCE 3.0/3.1
479  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
480  * Supports up to 3 digital outputs
481  * - 2 DIG encoder blocks.
482  * DIG1 can drive UNIPHY link A or link B
483  * DIG2 can drive UNIPHY link B or LVTMA
484  *
485  * DCE 3.2
486  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
487  * Supports up to 5 digital outputs
488  * - 2 DIG encoder blocks.
489  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
490  *
491  * DCE 4.0/5.0/6.0
492  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
493  * Supports up to 6 digital outputs
494  * - 6 DIG encoder blocks.
495  * - DIG to PHY mapping is hardcoded
496  * DIG1 drives UNIPHY0 link A, A+B
497  * DIG2 drives UNIPHY0 link B
498  * DIG3 drives UNIPHY1 link A, A+B
499  * DIG4 drives UNIPHY1 link B
500  * DIG5 drives UNIPHY2 link A, A+B
501  * DIG6 drives UNIPHY2 link B
502  *
503  * DCE 4.1
504  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
505  * Supports up to 6 digital outputs
506  * - 2 DIG encoder blocks.
507  * llano
508  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
509  * ontario
510  * DIG1 drives UNIPHY0/1/2 link A
511  * DIG2 drives UNIPHY0/1/2 link B
512  *
513  * Routing
514  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
515  * Examples:
516  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
517  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
518  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
519  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
520  */
521
522 union dig_encoder_control {
523         DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
524         DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
525         DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
526         DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
527 };
528
529 void
530 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
531 {
532         struct drm_device *dev = encoder->dev;
533         struct radeon_device *rdev = dev->dev_private;
534         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
535         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
536         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
537         union dig_encoder_control args;
538         int index = 0;
539         uint8_t frev, crev;
540         int dp_clock = 0;
541         int dp_lane_count = 0;
542         int hpd_id = RADEON_HPD_NONE;
543         int bpc = 8;
544
545         if (connector) {
546                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
547                 struct radeon_connector_atom_dig *dig_connector =
548                         radeon_connector->con_priv;
549
550                 dp_clock = dig_connector->dp_clock;
551                 dp_lane_count = dig_connector->dp_lane_count;
552                 hpd_id = radeon_connector->hpd.hpd;
553                 /* bpc = connector->display_info.bpc; */
554         }
555
556         /* no dig encoder assigned */
557         if (dig->dig_encoder == -1)
558                 return;
559
560         memset(&args, 0, sizeof(args));
561
562         if (ASIC_IS_DCE4(rdev))
563                 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
564         else {
565                 if (dig->dig_encoder)
566                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
567                 else
568                         index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
569         }
570
571         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
572                 return;
573
574         switch (frev) {
575         case 1:
576                 switch (crev) {
577                 case 1:
578                         args.v1.ucAction = action;
579                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
580                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
581                                 args.v3.ucPanelMode = panel_mode;
582                         else
583                                 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
584
585                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
586                                 args.v1.ucLaneNum = dp_lane_count;
587                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
588                                 args.v1.ucLaneNum = 8;
589                         else
590                                 args.v1.ucLaneNum = 4;
591
592                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
593                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
594                         switch (radeon_encoder->encoder_id) {
595                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
596                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
597                                 break;
598                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
599                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
600                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
601                                 break;
602                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
603                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
604                                 break;
605                         }
606                         if (dig->linkb)
607                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
608                         else
609                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
610                         break;
611                 case 2:
612                 case 3:
613                         args.v3.ucAction = action;
614                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
615                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
616                                 args.v3.ucPanelMode = panel_mode;
617                         else
618                                 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
619
620                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
621                                 args.v3.ucLaneNum = dp_lane_count;
622                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
623                                 args.v3.ucLaneNum = 8;
624                         else
625                                 args.v3.ucLaneNum = 4;
626
627                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
628                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
629                         args.v3.acConfig.ucDigSel = dig->dig_encoder;
630                         switch (bpc) {
631                         case 0:
632                                 args.v3.ucBitPerColor = PANEL_BPC_UNDEFINE;
633                                 break;
634                         case 6:
635                                 args.v3.ucBitPerColor = PANEL_6BIT_PER_COLOR;
636                                 break;
637                         case 8:
638                         default:
639                                 args.v3.ucBitPerColor = PANEL_8BIT_PER_COLOR;
640                                 break;
641                         case 10:
642                                 args.v3.ucBitPerColor = PANEL_10BIT_PER_COLOR;
643                                 break;
644                         case 12:
645                                 args.v3.ucBitPerColor = PANEL_12BIT_PER_COLOR;
646                                 break;
647                         case 16:
648                                 args.v3.ucBitPerColor = PANEL_16BIT_PER_COLOR;
649                                 break;
650                         }
651                         break;
652                 case 4:
653                         args.v4.ucAction = action;
654                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
655                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
656                                 args.v4.ucPanelMode = panel_mode;
657                         else
658                                 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
659
660                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
661                                 args.v4.ucLaneNum = dp_lane_count;
662                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
663                                 args.v4.ucLaneNum = 8;
664                         else
665                                 args.v4.ucLaneNum = 4;
666
667                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode)) {
668                                 if (dp_clock == 270000)
669                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
670                                 else if (dp_clock == 540000)
671                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
672                         }
673                         args.v4.acConfig.ucDigSel = dig->dig_encoder;
674                         switch (bpc) {
675                         case 0:
676                                 args.v4.ucBitPerColor = PANEL_BPC_UNDEFINE;
677                                 break;
678                         case 6:
679                                 args.v4.ucBitPerColor = PANEL_6BIT_PER_COLOR;
680                                 break;
681                         case 8:
682                         default:
683                                 args.v4.ucBitPerColor = PANEL_8BIT_PER_COLOR;
684                                 break;
685                         case 10:
686                                 args.v4.ucBitPerColor = PANEL_10BIT_PER_COLOR;
687                                 break;
688                         case 12:
689                                 args.v4.ucBitPerColor = PANEL_12BIT_PER_COLOR;
690                                 break;
691                         case 16:
692                                 args.v4.ucBitPerColor = PANEL_16BIT_PER_COLOR;
693                                 break;
694                         }
695                         if (hpd_id == RADEON_HPD_NONE)
696                                 args.v4.ucHPD_ID = 0;
697                         else
698                                 args.v4.ucHPD_ID = hpd_id + 1;
699                         break;
700                 default:
701                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
702                         break;
703                 }
704                 break;
705         default:
706                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
707                 break;
708         }
709
710         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
711
712 }
713
714 union dig_transmitter_control {
715         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
716         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
717         DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
718         DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
719         DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
720 };
721
722 void
723 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
724 {
725         struct drm_device *dev = encoder->dev;
726         struct radeon_device *rdev = dev->dev_private;
727         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
728         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
729         struct drm_connector *connector;
730         union dig_transmitter_control args;
731         int index = 0;
732         uint8_t frev, crev;
733         bool is_dp = false;
734         int pll_id = 0;
735         int dp_clock = 0;
736         int dp_lane_count = 0;
737         int connector_object_id = 0;
738         int igp_lane_info = 0;
739         int dig_encoder = dig->dig_encoder;
740         int hpd_id = RADEON_HPD_NONE;
741
742         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
743                 connector = radeon_get_connector_for_encoder_init(encoder);
744                 /* just needed to avoid bailing in the encoder check.  the encoder
745                  * isn't used for init
746                  */
747                 dig_encoder = 0;
748         } else
749                 connector = radeon_get_connector_for_encoder(encoder);
750
751         if (connector) {
752                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
753                 struct radeon_connector_atom_dig *dig_connector =
754                         radeon_connector->con_priv;
755
756                 hpd_id = radeon_connector->hpd.hpd;
757                 dp_clock = dig_connector->dp_clock;
758                 dp_lane_count = dig_connector->dp_lane_count;
759                 connector_object_id =
760                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
761                 igp_lane_info = dig_connector->igp_lane_info;
762         }
763
764         if (encoder->crtc) {
765                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
766                 pll_id = radeon_crtc->pll_id;
767         }
768
769         /* no dig encoder assigned */
770         if (dig_encoder == -1)
771                 return;
772
773         if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
774                 is_dp = true;
775
776         memset(&args, 0, sizeof(args));
777
778         switch (radeon_encoder->encoder_id) {
779         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
780                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
781                 break;
782         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
783         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
784         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
785                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
786                 break;
787         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
788                 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
789                 break;
790         }
791
792         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
793                 return;
794
795         switch (frev) {
796         case 1:
797                 switch (crev) {
798                 case 1:
799                         args.v1.ucAction = action;
800                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
801                                 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
802                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
803                                 args.v1.asMode.ucLaneSel = lane_num;
804                                 args.v1.asMode.ucLaneSet = lane_set;
805                         } else {
806                                 if (is_dp)
807                                         args.v1.usPixelClock =
808                                                 cpu_to_le16(dp_clock / 10);
809                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
810                                         args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
811                                 else
812                                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
813                         }
814
815                         args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
816
817                         if (dig_encoder)
818                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
819                         else
820                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
821
822                         if ((rdev->flags & RADEON_IS_IGP) &&
823                             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
824                                 if (is_dp ||
825                                     !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
826                                         if (igp_lane_info & 0x1)
827                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
828                                         else if (igp_lane_info & 0x2)
829                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
830                                         else if (igp_lane_info & 0x4)
831                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
832                                         else if (igp_lane_info & 0x8)
833                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
834                                 } else {
835                                         if (igp_lane_info & 0x3)
836                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
837                                         else if (igp_lane_info & 0xc)
838                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
839                                 }
840                         }
841
842                         if (dig->linkb)
843                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
844                         else
845                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
846
847                         if (is_dp)
848                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
849                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
850                                 if (dig->coherent_mode)
851                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
852                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
853                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
854                         }
855                         break;
856                 case 2:
857                         args.v2.ucAction = action;
858                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
859                                 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
860                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
861                                 args.v2.asMode.ucLaneSel = lane_num;
862                                 args.v2.asMode.ucLaneSet = lane_set;
863                         } else {
864                                 if (is_dp)
865                                         args.v2.usPixelClock =
866                                                 cpu_to_le16(dp_clock / 10);
867                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
868                                         args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
869                                 else
870                                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
871                         }
872
873                         args.v2.acConfig.ucEncoderSel = dig_encoder;
874                         if (dig->linkb)
875                                 args.v2.acConfig.ucLinkSel = 1;
876
877                         switch (radeon_encoder->encoder_id) {
878                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
879                                 args.v2.acConfig.ucTransmitterSel = 0;
880                                 break;
881                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
882                                 args.v2.acConfig.ucTransmitterSel = 1;
883                                 break;
884                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
885                                 args.v2.acConfig.ucTransmitterSel = 2;
886                                 break;
887                         }
888
889                         if (is_dp) {
890                                 args.v2.acConfig.fCoherentMode = 1;
891                                 args.v2.acConfig.fDPConnector = 1;
892                         } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
893                                 if (dig->coherent_mode)
894                                         args.v2.acConfig.fCoherentMode = 1;
895                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
896                                         args.v2.acConfig.fDualLinkConnector = 1;
897                         }
898                         break;
899                 case 3:
900                         args.v3.ucAction = action;
901                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
902                                 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
903                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
904                                 args.v3.asMode.ucLaneSel = lane_num;
905                                 args.v3.asMode.ucLaneSet = lane_set;
906                         } else {
907                                 if (is_dp)
908                                         args.v3.usPixelClock =
909                                                 cpu_to_le16(dp_clock / 10);
910                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
911                                         args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
912                                 else
913                                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
914                         }
915
916                         if (is_dp)
917                                 args.v3.ucLaneNum = dp_lane_count;
918                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
919                                 args.v3.ucLaneNum = 8;
920                         else
921                                 args.v3.ucLaneNum = 4;
922
923                         if (dig->linkb)
924                                 args.v3.acConfig.ucLinkSel = 1;
925                         if (dig_encoder & 1)
926                                 args.v3.acConfig.ucEncoderSel = 1;
927
928                         /* Select the PLL for the PHY
929                          * DP PHY should be clocked from external src if there is
930                          * one.
931                          */
932                         /* On DCE4, if there is an external clock, it generates the DP ref clock */
933                         if (is_dp && rdev->clock.dp_extclk)
934                                 args.v3.acConfig.ucRefClkSource = 2; /* external src */
935                         else
936                                 args.v3.acConfig.ucRefClkSource = pll_id;
937
938                         switch (radeon_encoder->encoder_id) {
939                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
940                                 args.v3.acConfig.ucTransmitterSel = 0;
941                                 break;
942                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
943                                 args.v3.acConfig.ucTransmitterSel = 1;
944                                 break;
945                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
946                                 args.v3.acConfig.ucTransmitterSel = 2;
947                                 break;
948                         }
949
950                         if (is_dp)
951                                 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
952                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
953                                 if (dig->coherent_mode)
954                                         args.v3.acConfig.fCoherentMode = 1;
955                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
956                                         args.v3.acConfig.fDualLinkConnector = 1;
957                         }
958                         break;
959                 case 4:
960                         args.v4.ucAction = action;
961                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
962                                 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
963                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
964                                 args.v4.asMode.ucLaneSel = lane_num;
965                                 args.v4.asMode.ucLaneSet = lane_set;
966                         } else {
967                                 if (is_dp)
968                                         args.v4.usPixelClock =
969                                                 cpu_to_le16(dp_clock / 10);
970                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
971                                         args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
972                                 else
973                                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
974                         }
975
976                         if (is_dp)
977                                 args.v4.ucLaneNum = dp_lane_count;
978                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
979                                 args.v4.ucLaneNum = 8;
980                         else
981                                 args.v4.ucLaneNum = 4;
982
983                         if (dig->linkb)
984                                 args.v4.acConfig.ucLinkSel = 1;
985                         if (dig_encoder & 1)
986                                 args.v4.acConfig.ucEncoderSel = 1;
987
988                         /* Select the PLL for the PHY
989                          * DP PHY should be clocked from external src if there is
990                          * one.
991                          */
992                         /* On DCE5 DCPLL usually generates the DP ref clock */
993                         if (is_dp) {
994                                 if (rdev->clock.dp_extclk)
995                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
996                                 else
997                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
998                         } else
999                                 args.v4.acConfig.ucRefClkSource = pll_id;
1000
1001                         switch (radeon_encoder->encoder_id) {
1002                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1003                                 args.v4.acConfig.ucTransmitterSel = 0;
1004                                 break;
1005                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1006                                 args.v4.acConfig.ucTransmitterSel = 1;
1007                                 break;
1008                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1009                                 args.v4.acConfig.ucTransmitterSel = 2;
1010                                 break;
1011                         }
1012
1013                         if (is_dp)
1014                                 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1015                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1016                                 if (dig->coherent_mode)
1017                                         args.v4.acConfig.fCoherentMode = 1;
1018                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1019                                         args.v4.acConfig.fDualLinkConnector = 1;
1020                         }
1021                         break;
1022                 case 5:
1023                         args.v5.ucAction = action;
1024                         if (is_dp)
1025                                 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1026                         else
1027                                 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1028
1029                         switch (radeon_encoder->encoder_id) {
1030                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1031                                 if (dig->linkb)
1032                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1033                                 else
1034                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1035                                 break;
1036                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1037                                 if (dig->linkb)
1038                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1039                                 else
1040                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1041                                 break;
1042                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1043                                 if (dig->linkb)
1044                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1045                                 else
1046                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1047                                 break;
1048                         }
1049                         if (is_dp)
1050                                 args.v5.ucLaneNum = dp_lane_count;
1051                         else if (radeon_encoder->pixel_clock > 165000)
1052                                 args.v5.ucLaneNum = 8;
1053                         else
1054                                 args.v5.ucLaneNum = 4;
1055                         args.v5.ucConnObjId = connector_object_id;
1056                         args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1057
1058                         if (is_dp && rdev->clock.dp_extclk)
1059                                 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1060                         else
1061                                 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1062
1063                         if (is_dp)
1064                                 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1065                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1066                                 if (dig->coherent_mode)
1067                                         args.v5.asConfig.ucCoherentMode = 1;
1068                         }
1069                         if (hpd_id == RADEON_HPD_NONE)
1070                                 args.v5.asConfig.ucHPDSel = 0;
1071                         else
1072                                 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1073                         args.v5.ucDigEncoderSel = 1 << dig_encoder;
1074                         args.v5.ucDPLaneSet = lane_set;
1075                         break;
1076                 default:
1077                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1078                         break;
1079                 }
1080                 break;
1081         default:
1082                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1083                 break;
1084         }
1085
1086         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1087 }
1088
1089 bool
1090 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1091 {
1092         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1093         struct drm_device *dev = radeon_connector->base.dev;
1094         struct radeon_device *rdev = dev->dev_private;
1095         union dig_transmitter_control args;
1096         int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1097         uint8_t frev, crev;
1098
1099         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1100                 goto done;
1101
1102         if (!ASIC_IS_DCE4(rdev))
1103                 goto done;
1104
1105         if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1106             (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1107                 goto done;
1108
1109         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1110                 goto done;
1111
1112         memset(&args, 0, sizeof(args));
1113
1114         args.v1.ucAction = action;
1115
1116         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1117
1118         /* wait for the panel to power up */
1119         if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1120                 int i;
1121
1122                 for (i = 0; i < 300; i++) {
1123                         if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1124                                 return true;
1125                         mdelay(1);
1126                 }
1127                 return false;
1128         }
1129 done:
1130         return true;
1131 }
1132
1133 union external_encoder_control {
1134         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1135         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1136 };
1137
1138 static void
1139 atombios_external_encoder_setup(struct drm_encoder *encoder,
1140                                 struct drm_encoder *ext_encoder,
1141                                 int action)
1142 {
1143         struct drm_device *dev = encoder->dev;
1144         struct radeon_device *rdev = dev->dev_private;
1145         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1146         struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1147         union external_encoder_control args;
1148         struct drm_connector *connector;
1149         int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1150         u8 frev, crev;
1151         int dp_clock = 0;
1152         int dp_lane_count = 0;
1153         int connector_object_id = 0;
1154         u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1155         int bpc = 8;
1156
1157         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1158                 connector = radeon_get_connector_for_encoder_init(encoder);
1159         else
1160                 connector = radeon_get_connector_for_encoder(encoder);
1161
1162         if (connector) {
1163                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1164                 struct radeon_connector_atom_dig *dig_connector =
1165                         radeon_connector->con_priv;
1166
1167                 dp_clock = dig_connector->dp_clock;
1168                 dp_lane_count = dig_connector->dp_lane_count;
1169                 connector_object_id =
1170                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1171                 /* bpc = connector->display_info.bpc; */
1172         }
1173
1174         memset(&args, 0, sizeof(args));
1175
1176         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1177                 return;
1178
1179         switch (frev) {
1180         case 1:
1181                 /* no params on frev 1 */
1182                 break;
1183         case 2:
1184                 switch (crev) {
1185                 case 1:
1186                 case 2:
1187                         args.v1.sDigEncoder.ucAction = action;
1188                         args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1189                         args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1190
1191                         if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1192                                 if (dp_clock == 270000)
1193                                         args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1194                                 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1195                         } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1196                                 args.v1.sDigEncoder.ucLaneNum = 8;
1197                         else
1198                                 args.v1.sDigEncoder.ucLaneNum = 4;
1199                         break;
1200                 case 3:
1201                         args.v3.sExtEncoder.ucAction = action;
1202                         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1203                                 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1204                         else
1205                                 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1206                         args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1207
1208                         if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1209                                 if (dp_clock == 270000)
1210                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1211                                 else if (dp_clock == 540000)
1212                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1213                                 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1214                         } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1215                                 args.v3.sExtEncoder.ucLaneNum = 8;
1216                         else
1217                                 args.v3.sExtEncoder.ucLaneNum = 4;
1218                         switch (ext_enum) {
1219                         case GRAPH_OBJECT_ENUM_ID1:
1220                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1221                                 break;
1222                         case GRAPH_OBJECT_ENUM_ID2:
1223                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1224                                 break;
1225                         case GRAPH_OBJECT_ENUM_ID3:
1226                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1227                                 break;
1228                         }
1229                         switch (bpc) {
1230                         case 0:
1231                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_BPC_UNDEFINE;
1232                                 break;
1233                         case 6:
1234                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_6BIT_PER_COLOR;
1235                                 break;
1236                         case 8:
1237                         default:
1238                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_8BIT_PER_COLOR;
1239                                 break;
1240                         case 10:
1241                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_10BIT_PER_COLOR;
1242                                 break;
1243                         case 12:
1244                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_12BIT_PER_COLOR;
1245                                 break;
1246                         case 16:
1247                                 args.v3.sExtEncoder.ucBitPerColor = PANEL_16BIT_PER_COLOR;
1248                                 break;
1249                         }
1250                         break;
1251                 default:
1252                         DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1253                         return;
1254                 }
1255                 break;
1256         default:
1257                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1258                 return;
1259         }
1260         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1261 }
1262
1263 static void
1264 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1265 {
1266         struct drm_device *dev = encoder->dev;
1267         struct radeon_device *rdev = dev->dev_private;
1268         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1269         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1270         ENABLE_YUV_PS_ALLOCATION args;
1271         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1272         uint32_t temp, reg;
1273
1274         memset(&args, 0, sizeof(args));
1275
1276         if (rdev->family >= CHIP_R600)
1277                 reg = R600_BIOS_3_SCRATCH;
1278         else
1279                 reg = RADEON_BIOS_3_SCRATCH;
1280
1281         /* XXX: fix up scratch reg handling */
1282         temp = RREG32(reg);
1283         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1284                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1285                              (radeon_crtc->crtc_id << 18)));
1286         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1287                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1288         else
1289                 WREG32(reg, 0);
1290
1291         if (enable)
1292                 args.ucEnable = ATOM_ENABLE;
1293         args.ucCRTC = radeon_crtc->crtc_id;
1294
1295         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1296
1297         WREG32(reg, temp);
1298 }
1299
1300 static void
1301 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1302 {
1303         struct drm_device *dev = encoder->dev;
1304         struct radeon_device *rdev = dev->dev_private;
1305         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1306         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1307         int index = 0;
1308
1309         memset(&args, 0, sizeof(args));
1310
1311         switch (radeon_encoder->encoder_id) {
1312         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1313         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1314                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1315                 break;
1316         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1317         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1318         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1319                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1320                 break;
1321         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1322                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1323                 break;
1324         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1325                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1326                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1327                 else
1328                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1329                 break;
1330         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1331         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1332                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1333                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1334                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1335                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1336                 else
1337                         index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1338                 break;
1339         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1340         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1341                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1342                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1343                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1344                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1345                 else
1346                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1347                 break;
1348         default:
1349                 return;
1350         }
1351
1352         switch (mode) {
1353         case DRM_MODE_DPMS_ON:
1354                 args.ucAction = ATOM_ENABLE;
1355                 /* workaround for DVOOutputControl on some RS690 systems */
1356                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1357                         u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1358                         WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1359                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1360                         WREG32(RADEON_BIOS_3_SCRATCH, reg);
1361                 } else
1362                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1363                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1364                         args.ucAction = ATOM_LCD_BLON;
1365                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1366                 }
1367                 break;
1368         case DRM_MODE_DPMS_STANDBY:
1369         case DRM_MODE_DPMS_SUSPEND:
1370         case DRM_MODE_DPMS_OFF:
1371                 args.ucAction = ATOM_DISABLE;
1372                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1373                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1374                         args.ucAction = ATOM_LCD_BLOFF;
1375                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1376                 }
1377                 break;
1378         }
1379 }
1380
1381 static void
1382 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1383 {
1384         struct drm_device *dev = encoder->dev;
1385         struct radeon_device *rdev = dev->dev_private;
1386         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1387         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1388         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1389         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1390         struct radeon_connector *radeon_connector = NULL;
1391         struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1392
1393         if (connector) {
1394                 radeon_connector = to_radeon_connector(connector);
1395                 radeon_dig_connector = radeon_connector->con_priv;
1396         }
1397
1398         switch (mode) {
1399         case DRM_MODE_DPMS_ON:
1400                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1401                         if (!connector)
1402                                 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1403                         else
1404                                 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1405
1406                         /* setup and enable the encoder */
1407                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1408                         atombios_dig_encoder_setup(encoder,
1409                                                    ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1410                                                    dig->panel_mode);
1411                         if (ext_encoder) {
1412                                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1413                                         atombios_external_encoder_setup(encoder, ext_encoder,
1414                                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1415                         }
1416                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1417                 } else if (ASIC_IS_DCE4(rdev)) {
1418                         /* setup and enable the encoder */
1419                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1420                         /* enable the transmitter */
1421                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1422                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1423                 } else {
1424                         /* setup and enable the encoder and transmitter */
1425                         atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1426                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1427                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1428                         /* some early dce3.2 boards have a bug in their transmitter control table */
1429                         if ((rdev->family != CHIP_RV710) && (rdev->family != CHIP_RV730))
1430                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE_OUTPUT, 0, 0);
1431                 }
1432                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1433                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1434                                 atombios_set_edp_panel_power(connector,
1435                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
1436                                 radeon_dig_connector->edp_on = true;
1437                         }
1438                         radeon_dp_link_train(encoder, connector);
1439                         if (ASIC_IS_DCE4(rdev))
1440                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1441                 }
1442                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1443                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1444                 break;
1445         case DRM_MODE_DPMS_STANDBY:
1446         case DRM_MODE_DPMS_SUSPEND:
1447         case DRM_MODE_DPMS_OFF:
1448                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1449                         /* disable the transmitter */
1450                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1451                 } else if (ASIC_IS_DCE4(rdev)) {
1452                         /* disable the transmitter */
1453                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1454                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1455                 } else {
1456                         /* disable the encoder and transmitter */
1457                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE_OUTPUT, 0, 0);
1458                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1459                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1460                 }
1461                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1462                         if (ASIC_IS_DCE4(rdev))
1463                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1464                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1465                                 atombios_set_edp_panel_power(connector,
1466                                                              ATOM_TRANSMITTER_ACTION_POWER_OFF);
1467                                 radeon_dig_connector->edp_on = false;
1468                         }
1469                 }
1470                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1471                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1472                 break;
1473         }
1474 }
1475
1476 static void
1477 radeon_atom_encoder_dpms_ext(struct drm_encoder *encoder,
1478                              struct drm_encoder *ext_encoder,
1479                              int mode)
1480 {
1481         struct drm_device *dev = encoder->dev;
1482         struct radeon_device *rdev = dev->dev_private;
1483
1484         switch (mode) {
1485         case DRM_MODE_DPMS_ON:
1486         default:
1487                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
1488                         atombios_external_encoder_setup(encoder, ext_encoder,
1489                                                         EXTERNAL_ENCODER_ACTION_V3_ENABLE_OUTPUT);
1490                         atombios_external_encoder_setup(encoder, ext_encoder,
1491                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING_OFF);
1492                 } else
1493                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1494                 break;
1495         case DRM_MODE_DPMS_STANDBY:
1496         case DRM_MODE_DPMS_SUSPEND:
1497         case DRM_MODE_DPMS_OFF:
1498                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)) {
1499                         atombios_external_encoder_setup(encoder, ext_encoder,
1500                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_BLANKING);
1501                         atombios_external_encoder_setup(encoder, ext_encoder,
1502                                                         EXTERNAL_ENCODER_ACTION_V3_DISABLE_OUTPUT);
1503                 } else
1504                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1505                 break;
1506         }
1507 }
1508
1509 static void
1510 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1511 {
1512         struct drm_device *dev = encoder->dev;
1513         struct radeon_device *rdev = dev->dev_private;
1514         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1515         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1516
1517         DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1518                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1519                   radeon_encoder->active_device);
1520         switch (radeon_encoder->encoder_id) {
1521         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1522         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1523         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1524         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1525         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1526         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1527         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1528         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1529                 radeon_atom_encoder_dpms_avivo(encoder, mode);
1530                 break;
1531         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1532         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1533         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1534         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1535                 radeon_atom_encoder_dpms_dig(encoder, mode);
1536                 break;
1537         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1538                 if (ASIC_IS_DCE5(rdev)) {
1539                         switch (mode) {
1540                         case DRM_MODE_DPMS_ON:
1541                                 atombios_dvo_setup(encoder, ATOM_ENABLE);
1542                                 break;
1543                         case DRM_MODE_DPMS_STANDBY:
1544                         case DRM_MODE_DPMS_SUSPEND:
1545                         case DRM_MODE_DPMS_OFF:
1546                                 atombios_dvo_setup(encoder, ATOM_DISABLE);
1547                                 break;
1548                         }
1549                 } else if (ASIC_IS_DCE3(rdev))
1550                         radeon_atom_encoder_dpms_dig(encoder, mode);
1551                 else
1552                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1553                 break;
1554         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1555         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1556                 if (ASIC_IS_DCE5(rdev)) {
1557                         switch (mode) {
1558                         case DRM_MODE_DPMS_ON:
1559                                 atombios_dac_setup(encoder, ATOM_ENABLE);
1560                                 break;
1561                         case DRM_MODE_DPMS_STANDBY:
1562                         case DRM_MODE_DPMS_SUSPEND:
1563                         case DRM_MODE_DPMS_OFF:
1564                                 atombios_dac_setup(encoder, ATOM_DISABLE);
1565                                 break;
1566                         }
1567                 } else
1568                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1569                 break;
1570         default:
1571                 return;
1572         }
1573
1574         if (ext_encoder)
1575                 radeon_atom_encoder_dpms_ext(encoder, ext_encoder, mode);
1576
1577         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1578
1579 }
1580
1581 union crtc_source_param {
1582         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1583         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1584 };
1585
1586 static void
1587 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1588 {
1589         struct drm_device *dev = encoder->dev;
1590         struct radeon_device *rdev = dev->dev_private;
1591         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1592         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1593         union crtc_source_param args;
1594         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1595         uint8_t frev, crev;
1596         struct radeon_encoder_atom_dig *dig;
1597
1598         memset(&args, 0, sizeof(args));
1599
1600         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1601                 return;
1602
1603         switch (frev) {
1604         case 1:
1605                 switch (crev) {
1606                 case 1:
1607                 default:
1608                         if (ASIC_IS_AVIVO(rdev))
1609                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
1610                         else {
1611                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) {
1612                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
1613                                 } else {
1614                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1615                                 }
1616                         }
1617                         switch (radeon_encoder->encoder_id) {
1618                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1619                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1620                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1621                                 break;
1622                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1623                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1624                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1625                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1626                                 else
1627                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1628                                 break;
1629                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1630                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1631                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1632                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1633                                 break;
1634                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1635                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1636                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1637                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1638                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1639                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1640                                 else
1641                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1642                                 break;
1643                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1644                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1645                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1646                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1647                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1648                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1649                                 else
1650                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1651                                 break;
1652                         }
1653                         break;
1654                 case 2:
1655                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1656                         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1657                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1658
1659                                 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1660                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1661                                 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1662                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1663                                 else
1664                                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1665                         } else
1666                                 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1667                         switch (radeon_encoder->encoder_id) {
1668                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1669                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1670                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1671                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1672                                 dig = radeon_encoder->enc_priv;
1673                                 switch (dig->dig_encoder) {
1674                                 case 0:
1675                                         args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1676                                         break;
1677                                 case 1:
1678                                         args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1679                                         break;
1680                                 case 2:
1681                                         args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1682                                         break;
1683                                 case 3:
1684                                         args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1685                                         break;
1686                                 case 4:
1687                                         args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1688                                         break;
1689                                 case 5:
1690                                         args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1691                                         break;
1692                                 }
1693                                 break;
1694                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1695                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1696                                 break;
1697                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1698                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1699                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1700                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1701                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1702                                 else
1703                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1704                                 break;
1705                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1706                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1707                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1708                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1709                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1710                                 else
1711                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1712                                 break;
1713                         }
1714                         break;
1715                 }
1716                 break;
1717         default:
1718                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1719                 return;
1720         }
1721
1722         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1723
1724         /* update scratch regs with new routing */
1725         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1726 }
1727
1728 static void
1729 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
1730                               struct drm_display_mode *mode)
1731 {
1732         struct drm_device *dev = encoder->dev;
1733         struct radeon_device *rdev = dev->dev_private;
1734         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1735         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1736
1737         /* Funky macbooks */
1738         if ((dev->pdev->device == 0x71C5) &&
1739             (dev->pdev->subsystem_vendor == 0x106b) &&
1740             (dev->pdev->subsystem_device == 0x0080)) {
1741                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
1742                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
1743
1744                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
1745                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
1746
1747                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
1748                 }
1749         }
1750
1751         /* set scaler clears this on some chips */
1752         if (ASIC_IS_AVIVO(rdev) &&
1753             (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
1754                 if (ASIC_IS_DCE4(rdev)) {
1755                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1756                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
1757                                        EVERGREEN_INTERLEAVE_EN);
1758                         else
1759                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1760                 } else {
1761                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
1762                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
1763                                        AVIVO_D1MODE_INTERLEAVE_EN);
1764                         else
1765                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
1766                 }
1767         }
1768 }
1769
1770 static int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder)
1771 {
1772         struct drm_device *dev = encoder->dev;
1773         struct radeon_device *rdev = dev->dev_private;
1774         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1775         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1776         struct drm_encoder *test_encoder;
1777         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1778         uint32_t dig_enc_in_use = 0;
1779
1780         if (ASIC_IS_DCE6(rdev)) {
1781                 /* DCE6 */
1782                 switch (radeon_encoder->encoder_id) {
1783                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1784                         if (dig->linkb)
1785                                 return 1;
1786                         else
1787                                 return 0;
1788                         break;
1789                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1790                         if (dig->linkb)
1791                                 return 3;
1792                         else
1793                                 return 2;
1794                         break;
1795                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1796                         if (dig->linkb)
1797                                 return 5;
1798                         else
1799                                 return 4;
1800                         break;
1801                 }
1802         } else if (ASIC_IS_DCE4(rdev)) {
1803                 /* DCE4/5 */
1804                 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
1805                         /* ontario follows DCE4 */
1806                         if (rdev->family == CHIP_PALM) {
1807                                 if (dig->linkb)
1808                                         return 1;
1809                                 else
1810                                         return 0;
1811                         } else
1812                                 /* llano follows DCE3.2 */
1813                                 return radeon_crtc->crtc_id;
1814                 } else {
1815                         switch (radeon_encoder->encoder_id) {
1816                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1817                                 if (dig->linkb)
1818                                         return 1;
1819                                 else
1820                                         return 0;
1821                                 break;
1822                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1823                                 if (dig->linkb)
1824                                         return 3;
1825                                 else
1826                                         return 2;
1827                                 break;
1828                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1829                                 if (dig->linkb)
1830                                         return 5;
1831                                 else
1832                                         return 4;
1833                                 break;
1834                         }
1835                 }
1836         }
1837
1838         /* on DCE32 and encoder can driver any block so just crtc id */
1839         if (ASIC_IS_DCE32(rdev)) {
1840                 return radeon_crtc->crtc_id;
1841         }
1842
1843         /* on DCE3 - LVTMA can only be driven by DIGB */
1844         list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1845                 struct radeon_encoder *radeon_test_encoder;
1846
1847                 if (encoder == test_encoder)
1848                         continue;
1849
1850                 if (!radeon_encoder_is_digital(test_encoder))
1851                         continue;
1852
1853                 radeon_test_encoder = to_radeon_encoder(test_encoder);
1854                 dig = radeon_test_encoder->enc_priv;
1855
1856                 if (dig->dig_encoder >= 0)
1857                         dig_enc_in_use |= (1 << dig->dig_encoder);
1858         }
1859
1860         if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
1861                 if (dig_enc_in_use & 0x2)
1862                         DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
1863                 return 1;
1864         }
1865         if (!(dig_enc_in_use & 1))
1866                 return 0;
1867         return 1;
1868 }
1869
1870 /* This only needs to be called once at startup */
1871 void
1872 radeon_atom_encoder_init(struct radeon_device *rdev)
1873 {
1874         struct drm_device *dev = rdev->ddev;
1875         struct drm_encoder *encoder;
1876
1877         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1878                 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1879                 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1880
1881                 switch (radeon_encoder->encoder_id) {
1882                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1883                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1884                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1885                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1886                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
1887                         break;
1888                 default:
1889                         break;
1890                 }
1891
1892                 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
1893                         atombios_external_encoder_setup(encoder, ext_encoder,
1894                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
1895         }
1896 }
1897
1898 static void
1899 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
1900                              struct drm_display_mode *mode,
1901                              struct drm_display_mode *adjusted_mode)
1902 {
1903         struct drm_device *dev = encoder->dev;
1904         struct radeon_device *rdev = dev->dev_private;
1905         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1906
1907         radeon_encoder->pixel_clock = adjusted_mode->clock;
1908
1909         /* need to call this here rather than in prepare() since we need some crtc info */
1910         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
1911
1912         if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
1913                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
1914                         atombios_yuv_setup(encoder, true);
1915                 else
1916                         atombios_yuv_setup(encoder, false);
1917         }
1918
1919         switch (radeon_encoder->encoder_id) {
1920         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1921         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1922         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1923         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1924                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
1925                 break;
1926         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1927         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1928         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1929         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1930                 /* handled in dpms */
1931                 break;
1932         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1933         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1934         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1935                 atombios_dvo_setup(encoder, ATOM_ENABLE);
1936                 break;
1937         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1938         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1939         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1940         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1941                 atombios_dac_setup(encoder, ATOM_ENABLE);
1942                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
1943                         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1944                                 atombios_tv_setup(encoder, ATOM_ENABLE);
1945                         else
1946                                 atombios_tv_setup(encoder, ATOM_DISABLE);
1947                 }
1948                 break;
1949         }
1950
1951         atombios_apply_encoder_quirks(encoder, adjusted_mode);
1952
1953         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
1954                 r600_hdmi_enable(encoder);
1955                 r600_hdmi_setmode(encoder, adjusted_mode);
1956         }
1957 }
1958
1959 static bool
1960 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
1961 {
1962         struct drm_device *dev = encoder->dev;
1963         struct radeon_device *rdev = dev->dev_private;
1964         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1965         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1966
1967         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
1968                                        ATOM_DEVICE_CV_SUPPORT |
1969                                        ATOM_DEVICE_CRT_SUPPORT)) {
1970                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
1971                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
1972                 uint8_t frev, crev;
1973
1974                 memset(&args, 0, sizeof(args));
1975
1976                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1977                         return false;
1978
1979                 args.sDacload.ucMisc = 0;
1980
1981                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
1982                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
1983                         args.sDacload.ucDacType = ATOM_DAC_A;
1984                 else
1985                         args.sDacload.ucDacType = ATOM_DAC_B;
1986
1987                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
1988                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
1989                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
1990                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
1991                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
1992                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
1993                         if (crev >= 3)
1994                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1995                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
1996                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
1997                         if (crev >= 3)
1998                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
1999                 }
2000
2001                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2002
2003                 return true;
2004         } else
2005                 return false;
2006 }
2007
2008 static enum drm_connector_status
2009 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2010 {
2011         struct drm_device *dev = encoder->dev;
2012         struct radeon_device *rdev = dev->dev_private;
2013         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2014         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2015         uint32_t bios_0_scratch;
2016
2017         if (!atombios_dac_load_detect(encoder, connector)) {
2018                 DRM_DEBUG_KMS("detect returned false \n");
2019                 return connector_status_unknown;
2020         }
2021
2022         if (rdev->family >= CHIP_R600)
2023                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2024         else
2025                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2026
2027         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2028         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2029                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2030                         return connector_status_connected;
2031         }
2032         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2033                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2034                         return connector_status_connected;
2035         }
2036         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2037                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2038                         return connector_status_connected;
2039         }
2040         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2041                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2042                         return connector_status_connected; /* CTV */
2043                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2044                         return connector_status_connected; /* STV */
2045         }
2046         return connector_status_disconnected;
2047 }
2048
2049 static enum drm_connector_status
2050 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2051 {
2052         struct drm_device *dev = encoder->dev;
2053         struct radeon_device *rdev = dev->dev_private;
2054         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2055         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2056         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2057         u32 bios_0_scratch;
2058
2059         if (!ASIC_IS_DCE4(rdev))
2060                 return connector_status_unknown;
2061
2062         if (!ext_encoder)
2063                 return connector_status_unknown;
2064
2065         if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2066                 return connector_status_unknown;
2067
2068         /* load detect on the dp bridge */
2069         atombios_external_encoder_setup(encoder, ext_encoder,
2070                                         EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2071
2072         bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2073
2074         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2075         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2076                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2077                         return connector_status_connected;
2078         }
2079         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2080                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2081                         return connector_status_connected;
2082         }
2083         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2084                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2085                         return connector_status_connected;
2086         }
2087         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2088                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2089                         return connector_status_connected; /* CTV */
2090                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2091                         return connector_status_connected; /* STV */
2092         }
2093         return connector_status_disconnected;
2094 }
2095
2096 void
2097 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2098 {
2099         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2100
2101         if (ext_encoder)
2102                 /* ddc_setup on the dp bridge */
2103                 atombios_external_encoder_setup(encoder, ext_encoder,
2104                                                 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2105
2106 }
2107
2108 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2109 {
2110         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2111         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2112
2113         if ((radeon_encoder->active_device &
2114              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2115             (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2116              ENCODER_OBJECT_ID_NONE)) {
2117                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2118                 if (dig)
2119                         dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder);
2120         }
2121
2122         radeon_atom_output_lock(encoder, true);
2123
2124         if (connector) {
2125                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2126
2127                 /* select the clock/data port if it uses a router */
2128                 if (radeon_connector->router.cd_valid)
2129                         radeon_router_select_cd_port(radeon_connector);
2130
2131                 /* turn eDP panel on for mode set */
2132                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2133                         atombios_set_edp_panel_power(connector,
2134                                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
2135         }
2136
2137         /* this is needed for the pll/ss setup to work correctly in some cases */
2138         atombios_set_encoder_crtc_source(encoder);
2139 }
2140
2141 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2142 {
2143         /* need to call this here as we need the crtc set up */
2144         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2145         radeon_atom_output_lock(encoder, false);
2146 }
2147
2148 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2149 {
2150         struct drm_device *dev = encoder->dev;
2151         struct radeon_device *rdev = dev->dev_private;
2152         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2153         struct radeon_encoder_atom_dig *dig;
2154
2155         /* check for pre-DCE3 cards with shared encoders;
2156          * can't really use the links individually, so don't disable
2157          * the encoder if it's in use by another connector
2158          */
2159         if (!ASIC_IS_DCE3(rdev)) {
2160                 struct drm_encoder *other_encoder;
2161                 struct radeon_encoder *other_radeon_encoder;
2162
2163                 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2164                         other_radeon_encoder = to_radeon_encoder(other_encoder);
2165                         if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2166                             drm_helper_encoder_in_use(other_encoder))
2167                                 goto disable_done;
2168                 }
2169         }
2170
2171         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2172
2173         switch (radeon_encoder->encoder_id) {
2174         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2175         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2176         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2177         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2178                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2179                 break;
2180         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2181         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2182         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2183         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2184                 /* handled in dpms */
2185                 break;
2186         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2187         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2188         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2189                 atombios_dvo_setup(encoder, ATOM_DISABLE);
2190                 break;
2191         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2192         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2193         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2194         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2195                 atombios_dac_setup(encoder, ATOM_DISABLE);
2196                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2197                         atombios_tv_setup(encoder, ATOM_DISABLE);
2198                 break;
2199         }
2200
2201 disable_done:
2202         if (radeon_encoder_is_digital(encoder)) {
2203                 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
2204                         r600_hdmi_disable(encoder);
2205                 dig = radeon_encoder->enc_priv;
2206                 dig->dig_encoder = -1;
2207         }
2208         radeon_encoder->active_device = 0;
2209 }
2210
2211 /* these are handled by the primary encoders */
2212 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2213 {
2214
2215 }
2216
2217 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2218 {
2219
2220 }
2221
2222 static void
2223 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2224                          struct drm_display_mode *mode,
2225                          struct drm_display_mode *adjusted_mode)
2226 {
2227
2228 }
2229
2230 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2231 {
2232
2233 }
2234
2235 static void
2236 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2237 {
2238
2239 }
2240
2241 static bool radeon_atom_ext_mode_fixup(struct drm_encoder *encoder,
2242                                        struct drm_display_mode *mode,
2243                                        struct drm_display_mode *adjusted_mode)
2244 {
2245         return true;
2246 }
2247
2248 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2249         .dpms = radeon_atom_ext_dpms,
2250         .mode_fixup = radeon_atom_ext_mode_fixup,
2251         .prepare = radeon_atom_ext_prepare,
2252         .mode_set = radeon_atom_ext_mode_set,
2253         .commit = radeon_atom_ext_commit,
2254         .disable = radeon_atom_ext_disable,
2255         /* no detect for TMDS/LVDS yet */
2256 };
2257
2258 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2259         .dpms = radeon_atom_encoder_dpms,
2260         .mode_fixup = radeon_atom_mode_fixup,
2261         .prepare = radeon_atom_encoder_prepare,
2262         .mode_set = radeon_atom_encoder_mode_set,
2263         .commit = radeon_atom_encoder_commit,
2264         .disable = radeon_atom_encoder_disable,
2265         .detect = radeon_atom_dig_detect,
2266 };
2267
2268 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2269         .dpms = radeon_atom_encoder_dpms,
2270         .mode_fixup = radeon_atom_mode_fixup,
2271         .prepare = radeon_atom_encoder_prepare,
2272         .mode_set = radeon_atom_encoder_mode_set,
2273         .commit = radeon_atom_encoder_commit,
2274         .detect = radeon_atom_dac_detect,
2275 };
2276
2277 void radeon_enc_destroy(struct drm_encoder *encoder)
2278 {
2279         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2280         kfree(radeon_encoder->enc_priv);
2281         drm_encoder_cleanup(encoder);
2282         kfree(radeon_encoder);
2283 }
2284
2285 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2286         .destroy = radeon_enc_destroy,
2287 };
2288
2289 struct radeon_encoder_atom_dac *
2290 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2291 {
2292         struct drm_device *dev = radeon_encoder->base.dev;
2293         struct radeon_device *rdev = dev->dev_private;
2294         struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2295
2296         if (!dac)
2297                 return NULL;
2298
2299         dac->tv_std = radeon_atombios_get_tv_info(rdev);
2300         return dac;
2301 }
2302
2303 struct radeon_encoder_atom_dig *
2304 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2305 {
2306         int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2307         struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2308
2309         if (!dig)
2310                 return NULL;
2311
2312         /* coherent mode by default */
2313         dig->coherent_mode = true;
2314         dig->dig_encoder = -1;
2315
2316         if (encoder_enum == 2)
2317                 dig->linkb = true;
2318         else
2319                 dig->linkb = false;
2320
2321         return dig;
2322 }
2323
2324 void
2325 radeon_add_atom_encoder(struct drm_device *dev,
2326                         uint32_t encoder_enum,
2327                         uint32_t supported_device,
2328                         u16 caps)
2329 {
2330         struct radeon_device *rdev = dev->dev_private;
2331         struct drm_encoder *encoder;
2332         struct radeon_encoder *radeon_encoder;
2333
2334         /* see if we already added it */
2335         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2336                 radeon_encoder = to_radeon_encoder(encoder);
2337                 if (radeon_encoder->encoder_enum == encoder_enum) {
2338                         radeon_encoder->devices |= supported_device;
2339                         return;
2340                 }
2341
2342         }
2343
2344         /* add a new one */
2345         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2346         if (!radeon_encoder)
2347                 return;
2348
2349         encoder = &radeon_encoder->base;
2350         switch (rdev->num_crtc) {
2351         case 1:
2352                 encoder->possible_crtcs = 0x1;
2353                 break;
2354         case 2:
2355         default:
2356                 encoder->possible_crtcs = 0x3;
2357                 break;
2358         case 4:
2359                 encoder->possible_crtcs = 0xf;
2360                 break;
2361         case 6:
2362                 encoder->possible_crtcs = 0x3f;
2363                 break;
2364         }
2365
2366         radeon_encoder->enc_priv = NULL;
2367
2368         radeon_encoder->encoder_enum = encoder_enum;
2369         radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2370         radeon_encoder->devices = supported_device;
2371         radeon_encoder->rmx_type = RMX_OFF;
2372         radeon_encoder->underscan_type = UNDERSCAN_OFF;
2373         radeon_encoder->is_ext_encoder = false;
2374         radeon_encoder->caps = caps;
2375
2376         switch (radeon_encoder->encoder_id) {
2377         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2378         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2379         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2380         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2381                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2382                         radeon_encoder->rmx_type = RMX_FULL;
2383                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2384                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2385                 } else {
2386                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2387                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2388                 }
2389                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2390                 break;
2391         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2392                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2393                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2394                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2395                 break;
2396         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2397         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2398         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2399                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TVDAC);
2400                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2401                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2402                 break;
2403         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2404         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2405         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2406         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2407         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2408         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2409         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2410                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2411                         radeon_encoder->rmx_type = RMX_FULL;
2412                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2413                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2414                 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2415                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2416                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2417                 } else {
2418                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2419                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2420                 }
2421                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2422                 break;
2423         case ENCODER_OBJECT_ID_SI170B:
2424         case ENCODER_OBJECT_ID_CH7303:
2425         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2426         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2427         case ENCODER_OBJECT_ID_TITFP513:
2428         case ENCODER_OBJECT_ID_VT1623:
2429         case ENCODER_OBJECT_ID_HDMI_SI1930:
2430         case ENCODER_OBJECT_ID_TRAVIS:
2431         case ENCODER_OBJECT_ID_NUTMEG:
2432                 /* these are handled by the primary encoders */
2433                 radeon_encoder->is_ext_encoder = true;
2434                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2435                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_LVDS);
2436                 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2437                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_DAC);
2438                 else
2439                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs, DRM_MODE_ENCODER_TMDS);
2440                 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2441                 break;
2442         }
2443 }