drm/radeon/kms: add initial colortiling support.
[linux-2.6.git] / drivers / gpu / drm / radeon / atombios_crtc.c
1 /*
2  * Copyright 2007-8 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: Dave Airlie
24  *          Alex Deucher
25  */
26 #include <drm/drmP.h>
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
29 #include "radeon_fixed.h"
30 #include "radeon.h"
31 #include "atom.h"
32 #include "atom-bits.h"
33
34 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
35 {
36         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
37         struct drm_device *dev = crtc->dev;
38         struct radeon_device *rdev = dev->dev_private;
39         int index =
40             GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
41         ENABLE_CRTC_PS_ALLOCATION args;
42
43         memset(&args, 0, sizeof(args));
44
45         args.ucCRTC = radeon_crtc->crtc_id;
46         args.ucEnable = lock;
47
48         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
49 }
50
51 static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
52 {
53         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
54         struct drm_device *dev = crtc->dev;
55         struct radeon_device *rdev = dev->dev_private;
56         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
57         ENABLE_CRTC_PS_ALLOCATION args;
58
59         memset(&args, 0, sizeof(args));
60
61         args.ucCRTC = radeon_crtc->crtc_id;
62         args.ucEnable = state;
63
64         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
65 }
66
67 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
68 {
69         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
70         struct drm_device *dev = crtc->dev;
71         struct radeon_device *rdev = dev->dev_private;
72         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
73         ENABLE_CRTC_PS_ALLOCATION args;
74
75         memset(&args, 0, sizeof(args));
76
77         args.ucCRTC = radeon_crtc->crtc_id;
78         args.ucEnable = state;
79
80         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
81 }
82
83 static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
84 {
85         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
86         struct drm_device *dev = crtc->dev;
87         struct radeon_device *rdev = dev->dev_private;
88         int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
89         BLANK_CRTC_PS_ALLOCATION args;
90
91         memset(&args, 0, sizeof(args));
92
93         args.ucCRTC = radeon_crtc->crtc_id;
94         args.ucBlanking = state;
95
96         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
97 }
98
99 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
100 {
101         struct drm_device *dev = crtc->dev;
102         struct radeon_device *rdev = dev->dev_private;
103
104         switch (mode) {
105         case DRM_MODE_DPMS_ON:
106                 if (ASIC_IS_DCE3(rdev))
107                         atombios_enable_crtc_memreq(crtc, 1);
108                 atombios_enable_crtc(crtc, 1);
109                 atombios_blank_crtc(crtc, 0);
110                 break;
111         case DRM_MODE_DPMS_STANDBY:
112         case DRM_MODE_DPMS_SUSPEND:
113         case DRM_MODE_DPMS_OFF:
114                 atombios_blank_crtc(crtc, 1);
115                 atombios_enable_crtc(crtc, 0);
116                 if (ASIC_IS_DCE3(rdev))
117                         atombios_enable_crtc_memreq(crtc, 0);
118                 break;
119         }
120
121         if (mode != DRM_MODE_DPMS_OFF) {
122                 radeon_crtc_load_lut(crtc);
123         }
124 }
125
126 static void
127 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
128                              SET_CRTC_USING_DTD_TIMING_PARAMETERS * crtc_param)
129 {
130         struct drm_device *dev = crtc->dev;
131         struct radeon_device *rdev = dev->dev_private;
132         SET_CRTC_USING_DTD_TIMING_PARAMETERS conv_param;
133         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
134
135         conv_param.usH_Size = cpu_to_le16(crtc_param->usH_Size);
136         conv_param.usH_Blanking_Time =
137             cpu_to_le16(crtc_param->usH_Blanking_Time);
138         conv_param.usV_Size = cpu_to_le16(crtc_param->usV_Size);
139         conv_param.usV_Blanking_Time =
140             cpu_to_le16(crtc_param->usV_Blanking_Time);
141         conv_param.usH_SyncOffset = cpu_to_le16(crtc_param->usH_SyncOffset);
142         conv_param.usH_SyncWidth = cpu_to_le16(crtc_param->usH_SyncWidth);
143         conv_param.usV_SyncOffset = cpu_to_le16(crtc_param->usV_SyncOffset);
144         conv_param.usV_SyncWidth = cpu_to_le16(crtc_param->usV_SyncWidth);
145         conv_param.susModeMiscInfo.usAccess =
146             cpu_to_le16(crtc_param->susModeMiscInfo.usAccess);
147         conv_param.ucCRTC = crtc_param->ucCRTC;
148
149         printk("executing set crtc dtd timing\n");
150         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&conv_param);
151 }
152
153 void atombios_crtc_set_timing(struct drm_crtc *crtc,
154                               SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *
155                               crtc_param)
156 {
157         struct drm_device *dev = crtc->dev;
158         struct radeon_device *rdev = dev->dev_private;
159         SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION conv_param;
160         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
161
162         conv_param.usH_Total = cpu_to_le16(crtc_param->usH_Total);
163         conv_param.usH_Disp = cpu_to_le16(crtc_param->usH_Disp);
164         conv_param.usH_SyncStart = cpu_to_le16(crtc_param->usH_SyncStart);
165         conv_param.usH_SyncWidth = cpu_to_le16(crtc_param->usH_SyncWidth);
166         conv_param.usV_Total = cpu_to_le16(crtc_param->usV_Total);
167         conv_param.usV_Disp = cpu_to_le16(crtc_param->usV_Disp);
168         conv_param.usV_SyncStart = cpu_to_le16(crtc_param->usV_SyncStart);
169         conv_param.usV_SyncWidth = cpu_to_le16(crtc_param->usV_SyncWidth);
170         conv_param.susModeMiscInfo.usAccess =
171             cpu_to_le16(crtc_param->susModeMiscInfo.usAccess);
172         conv_param.ucCRTC = crtc_param->ucCRTC;
173         conv_param.ucOverscanRight = crtc_param->ucOverscanRight;
174         conv_param.ucOverscanLeft = crtc_param->ucOverscanLeft;
175         conv_param.ucOverscanBottom = crtc_param->ucOverscanBottom;
176         conv_param.ucOverscanTop = crtc_param->ucOverscanTop;
177         conv_param.ucReserved = crtc_param->ucReserved;
178
179         printk("executing set crtc timing\n");
180         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&conv_param);
181 }
182
183 void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
184 {
185         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
186         struct drm_device *dev = crtc->dev;
187         struct radeon_device *rdev = dev->dev_private;
188         struct drm_encoder *encoder = NULL;
189         struct radeon_encoder *radeon_encoder = NULL;
190         uint8_t frev, crev;
191         int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
192         SET_PIXEL_CLOCK_PS_ALLOCATION args;
193         PIXEL_CLOCK_PARAMETERS *spc1_ptr;
194         PIXEL_CLOCK_PARAMETERS_V2 *spc2_ptr;
195         PIXEL_CLOCK_PARAMETERS_V3 *spc3_ptr;
196         uint32_t sclock = mode->clock;
197         uint32_t ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
198         struct radeon_pll *pll;
199         int pll_flags = 0;
200
201         memset(&args, 0, sizeof(args));
202
203         if (ASIC_IS_AVIVO(rdev)) {
204                 uint32_t ss_cntl;
205
206                 if ((rdev->family == CHIP_RS600) ||
207                     (rdev->family == CHIP_RS690) ||
208                     (rdev->family == CHIP_RS740))
209                         pll_flags |= (RADEON_PLL_USE_FRAC_FB_DIV |
210                                       RADEON_PLL_PREFER_CLOSEST_LOWER);
211
212                 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000)        /* range limits??? */
213                         pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
214                 else
215                         pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
216
217                 /* disable spread spectrum clocking for now -- thanks Hedy Lamarr */
218                 if (radeon_crtc->crtc_id == 0) {
219                         ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
220                         WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl & ~1);
221                 } else {
222                         ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
223                         WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl & ~1);
224                 }
225         } else {
226                 pll_flags |= RADEON_PLL_LEGACY;
227
228                 if (mode->clock > 200000)       /* range limits??? */
229                         pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
230                 else
231                         pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
232
233         }
234
235         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
236                 if (encoder->crtc == crtc) {
237                         if (!ASIC_IS_AVIVO(rdev)) {
238                                 if (encoder->encoder_type !=
239                                     DRM_MODE_ENCODER_DAC)
240                                         pll_flags |= RADEON_PLL_NO_ODD_POST_DIV;
241                                 if (!ASIC_IS_AVIVO(rdev)
242                                     && (encoder->encoder_type ==
243                                         DRM_MODE_ENCODER_LVDS))
244                                         pll_flags |= RADEON_PLL_USE_REF_DIV;
245                         }
246                         radeon_encoder = to_radeon_encoder(encoder);
247                 }
248         }
249
250         if (radeon_crtc->crtc_id == 0)
251                 pll = &rdev->clock.p1pll;
252         else
253                 pll = &rdev->clock.p2pll;
254
255         radeon_compute_pll(pll, mode->clock, &sclock, &fb_div, &frac_fb_div,
256                            &ref_div, &post_div, pll_flags);
257
258         atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
259                               &crev);
260
261         switch (frev) {
262         case 1:
263                 switch (crev) {
264                 case 1:
265                         spc1_ptr = (PIXEL_CLOCK_PARAMETERS *) & args.sPCLKInput;
266                         spc1_ptr->usPixelClock = cpu_to_le16(sclock);
267                         spc1_ptr->usRefDiv = cpu_to_le16(ref_div);
268                         spc1_ptr->usFbDiv = cpu_to_le16(fb_div);
269                         spc1_ptr->ucFracFbDiv = frac_fb_div;
270                         spc1_ptr->ucPostDiv = post_div;
271                         spc1_ptr->ucPpll =
272                             radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
273                         spc1_ptr->ucCRTC = radeon_crtc->crtc_id;
274                         spc1_ptr->ucRefDivSrc = 1;
275                         break;
276                 case 2:
277                         spc2_ptr =
278                             (PIXEL_CLOCK_PARAMETERS_V2 *) & args.sPCLKInput;
279                         spc2_ptr->usPixelClock = cpu_to_le16(sclock);
280                         spc2_ptr->usRefDiv = cpu_to_le16(ref_div);
281                         spc2_ptr->usFbDiv = cpu_to_le16(fb_div);
282                         spc2_ptr->ucFracFbDiv = frac_fb_div;
283                         spc2_ptr->ucPostDiv = post_div;
284                         spc2_ptr->ucPpll =
285                             radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
286                         spc2_ptr->ucCRTC = radeon_crtc->crtc_id;
287                         spc2_ptr->ucRefDivSrc = 1;
288                         break;
289                 case 3:
290                         if (!encoder)
291                                 return;
292                         spc3_ptr =
293                             (PIXEL_CLOCK_PARAMETERS_V3 *) & args.sPCLKInput;
294                         spc3_ptr->usPixelClock = cpu_to_le16(sclock);
295                         spc3_ptr->usRefDiv = cpu_to_le16(ref_div);
296                         spc3_ptr->usFbDiv = cpu_to_le16(fb_div);
297                         spc3_ptr->ucFracFbDiv = frac_fb_div;
298                         spc3_ptr->ucPostDiv = post_div;
299                         spc3_ptr->ucPpll =
300                             radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1;
301                         spc3_ptr->ucMiscInfo = (radeon_crtc->crtc_id << 2);
302                         spc3_ptr->ucTransmitterId = radeon_encoder->encoder_id;
303                         spc3_ptr->ucEncoderMode =
304                             atombios_get_encoder_mode(encoder);
305                         break;
306                 default:
307                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
308                         return;
309                 }
310                 break;
311         default:
312                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
313                 return;
314         }
315
316         printk("executing set pll\n");
317         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
318 }
319
320 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
321                            struct drm_framebuffer *old_fb)
322 {
323         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
324         struct drm_device *dev = crtc->dev;
325         struct radeon_device *rdev = dev->dev_private;
326         struct radeon_framebuffer *radeon_fb;
327         struct drm_gem_object *obj;
328         struct drm_radeon_gem_object *obj_priv;
329         uint64_t fb_location;
330         uint32_t fb_format, fb_pitch_pixels, tiling_flags;
331
332         if (!crtc->fb)
333                 return -EINVAL;
334
335         radeon_fb = to_radeon_framebuffer(crtc->fb);
336
337         obj = radeon_fb->obj;
338         obj_priv = obj->driver_private;
339
340         if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &fb_location)) {
341                 return -EINVAL;
342         }
343
344         switch (crtc->fb->bits_per_pixel) {
345         case 15:
346                 fb_format =
347                     AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
348                     AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
349                 break;
350         case 16:
351                 fb_format =
352                     AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
353                     AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
354                 break;
355         case 24:
356         case 32:
357                 fb_format =
358                     AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
359                     AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
360                 break;
361         default:
362                 DRM_ERROR("Unsupported screen depth %d\n",
363                           crtc->fb->bits_per_pixel);
364                 return -EINVAL;
365         }
366
367         radeon_object_get_tiling_flags(obj->driver_private,
368                                        &tiling_flags, NULL);
369         if (tiling_flags & RADEON_TILING_MACRO)
370                 fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
371
372         if (tiling_flags & RADEON_TILING_MICRO)
373                 fb_format |= AVIVO_D1GRPH_TILED;
374
375         if (radeon_crtc->crtc_id == 0)
376                 WREG32(AVIVO_D1VGA_CONTROL, 0);
377         else
378                 WREG32(AVIVO_D2VGA_CONTROL, 0);
379         WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
380                (u32) fb_location);
381         WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
382                radeon_crtc->crtc_offset, (u32) fb_location);
383         WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
384
385         WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
386         WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
387         WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
388         WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
389         WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width);
390         WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height);
391
392         fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8);
393         WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
394         WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
395
396         WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
397                crtc->mode.vdisplay);
398         x &= ~3;
399         y &= ~1;
400         WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
401                (x << 16) | y);
402         WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
403                (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay);
404
405         if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE)
406                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
407                        AVIVO_D1MODE_INTERLEAVE_EN);
408         else
409                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
410
411         if (old_fb && old_fb != crtc->fb) {
412                 radeon_fb = to_radeon_framebuffer(old_fb);
413                 radeon_gem_object_unpin(radeon_fb->obj);
414         }
415         return 0;
416 }
417
418 int atombios_crtc_mode_set(struct drm_crtc *crtc,
419                            struct drm_display_mode *mode,
420                            struct drm_display_mode *adjusted_mode,
421                            int x, int y, struct drm_framebuffer *old_fb)
422 {
423         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
424         struct drm_device *dev = crtc->dev;
425         struct radeon_device *rdev = dev->dev_private;
426         struct drm_encoder *encoder;
427         SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing;
428
429         /* TODO color tiling */
430         memset(&crtc_timing, 0, sizeof(crtc_timing));
431
432         /* TODO tv */
433         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
434
435         }
436
437         crtc_timing.ucCRTC = radeon_crtc->crtc_id;
438         crtc_timing.usH_Total = adjusted_mode->crtc_htotal;
439         crtc_timing.usH_Disp = adjusted_mode->crtc_hdisplay;
440         crtc_timing.usH_SyncStart = adjusted_mode->crtc_hsync_start;
441         crtc_timing.usH_SyncWidth =
442             adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
443
444         crtc_timing.usV_Total = adjusted_mode->crtc_vtotal;
445         crtc_timing.usV_Disp = adjusted_mode->crtc_vdisplay;
446         crtc_timing.usV_SyncStart = adjusted_mode->crtc_vsync_start;
447         crtc_timing.usV_SyncWidth =
448             adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
449
450         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
451                 crtc_timing.susModeMiscInfo.usAccess |= ATOM_VSYNC_POLARITY;
452
453         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
454                 crtc_timing.susModeMiscInfo.usAccess |= ATOM_HSYNC_POLARITY;
455
456         if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC)
457                 crtc_timing.susModeMiscInfo.usAccess |= ATOM_COMPOSITESYNC;
458
459         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
460                 crtc_timing.susModeMiscInfo.usAccess |= ATOM_INTERLACE;
461
462         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
463                 crtc_timing.susModeMiscInfo.usAccess |= ATOM_DOUBLE_CLOCK_MODE;
464
465         atombios_crtc_set_pll(crtc, adjusted_mode);
466         atombios_crtc_set_timing(crtc, &crtc_timing);
467
468         if (ASIC_IS_AVIVO(rdev))
469                 atombios_crtc_set_base(crtc, x, y, old_fb);
470         else {
471                 if (radeon_crtc->crtc_id == 0) {
472                         SET_CRTC_USING_DTD_TIMING_PARAMETERS crtc_dtd_timing;
473                         memset(&crtc_dtd_timing, 0, sizeof(crtc_dtd_timing));
474
475                         /* setup FP shadow regs on R4xx */
476                         crtc_dtd_timing.ucCRTC = radeon_crtc->crtc_id;
477                         crtc_dtd_timing.usH_Size = adjusted_mode->crtc_hdisplay;
478                         crtc_dtd_timing.usV_Size = adjusted_mode->crtc_vdisplay;
479                         crtc_dtd_timing.usH_Blanking_Time =
480                             adjusted_mode->crtc_hblank_end -
481                             adjusted_mode->crtc_hdisplay;
482                         crtc_dtd_timing.usV_Blanking_Time =
483                             adjusted_mode->crtc_vblank_end -
484                             adjusted_mode->crtc_vdisplay;
485                         crtc_dtd_timing.usH_SyncOffset =
486                             adjusted_mode->crtc_hsync_start -
487                             adjusted_mode->crtc_hdisplay;
488                         crtc_dtd_timing.usV_SyncOffset =
489                             adjusted_mode->crtc_vsync_start -
490                             adjusted_mode->crtc_vdisplay;
491                         crtc_dtd_timing.usH_SyncWidth =
492                             adjusted_mode->crtc_hsync_end -
493                             adjusted_mode->crtc_hsync_start;
494                         crtc_dtd_timing.usV_SyncWidth =
495                             adjusted_mode->crtc_vsync_end -
496                             adjusted_mode->crtc_vsync_start;
497                         /* crtc_dtd_timing.ucH_Border = adjusted_mode->crtc_hborder; */
498                         /* crtc_dtd_timing.ucV_Border = adjusted_mode->crtc_vborder; */
499
500                         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
501                                 crtc_dtd_timing.susModeMiscInfo.usAccess |=
502                                     ATOM_VSYNC_POLARITY;
503
504                         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
505                                 crtc_dtd_timing.susModeMiscInfo.usAccess |=
506                                     ATOM_HSYNC_POLARITY;
507
508                         if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC)
509                                 crtc_dtd_timing.susModeMiscInfo.usAccess |=
510                                     ATOM_COMPOSITESYNC;
511
512                         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
513                                 crtc_dtd_timing.susModeMiscInfo.usAccess |=
514                                     ATOM_INTERLACE;
515
516                         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
517                                 crtc_dtd_timing.susModeMiscInfo.usAccess |=
518                                     ATOM_DOUBLE_CLOCK_MODE;
519
520                         atombios_set_crtc_dtd_timing(crtc, &crtc_dtd_timing);
521                 }
522                 radeon_crtc_set_base(crtc, x, y, old_fb);
523                 radeon_legacy_atom_set_surface(crtc);
524         }
525         return 0;
526 }
527
528 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
529                                      struct drm_display_mode *mode,
530                                      struct drm_display_mode *adjusted_mode)
531 {
532         return true;
533 }
534
535 static void atombios_crtc_prepare(struct drm_crtc *crtc)
536 {
537         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
538         atombios_lock_crtc(crtc, 1);
539 }
540
541 static void atombios_crtc_commit(struct drm_crtc *crtc)
542 {
543         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
544         atombios_lock_crtc(crtc, 0);
545 }
546
547 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
548         .dpms = atombios_crtc_dpms,
549         .mode_fixup = atombios_crtc_mode_fixup,
550         .mode_set = atombios_crtc_mode_set,
551         .mode_set_base = atombios_crtc_set_base,
552         .prepare = atombios_crtc_prepare,
553         .commit = atombios_crtc_commit,
554 };
555
556 void radeon_atombios_init_crtc(struct drm_device *dev,
557                                struct radeon_crtc *radeon_crtc)
558 {
559         if (radeon_crtc->crtc_id == 1)
560                 radeon_crtc->crtc_offset =
561                     AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
562         drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
563 }
564
565 void radeon_init_disp_bw_avivo(struct drm_device *dev,
566                                struct drm_display_mode *mode1,
567                                uint32_t pixel_bytes1,
568                                struct drm_display_mode *mode2,
569                                uint32_t pixel_bytes2)
570 {
571         struct radeon_device *rdev = dev->dev_private;
572         fixed20_12 min_mem_eff;
573         fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff;
574         fixed20_12 sclk_ff, mclk_ff;
575         uint32_t dc_lb_memory_split, temp;
576
577         min_mem_eff.full = rfixed_const_8(0);
578         if (rdev->disp_priority == 2) {
579                 uint32_t mc_init_misc_lat_timer = 0;
580                 if (rdev->family == CHIP_RV515)
581                         mc_init_misc_lat_timer =
582                             RREG32_MC(RV515_MC_INIT_MISC_LAT_TIMER);
583                 else if (rdev->family == CHIP_RS690)
584                         mc_init_misc_lat_timer =
585                             RREG32_MC(RS690_MC_INIT_MISC_LAT_TIMER);
586
587                 mc_init_misc_lat_timer &=
588                     ~(R300_MC_DISP1R_INIT_LAT_MASK <<
589                       R300_MC_DISP1R_INIT_LAT_SHIFT);
590                 mc_init_misc_lat_timer &=
591                     ~(R300_MC_DISP0R_INIT_LAT_MASK <<
592                       R300_MC_DISP0R_INIT_LAT_SHIFT);
593
594                 if (mode2)
595                         mc_init_misc_lat_timer |=
596                             (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
597                 if (mode1)
598                         mc_init_misc_lat_timer |=
599                             (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
600
601                 if (rdev->family == CHIP_RV515)
602                         WREG32_MC(RV515_MC_INIT_MISC_LAT_TIMER,
603                                   mc_init_misc_lat_timer);
604                 else if (rdev->family == CHIP_RS690)
605                         WREG32_MC(RS690_MC_INIT_MISC_LAT_TIMER,
606                                   mc_init_misc_lat_timer);
607         }
608
609         /*
610          * determine is there is enough bw for current mode
611          */
612         temp_ff.full = rfixed_const(100);
613         mclk_ff.full = rfixed_const(rdev->clock.default_mclk);
614         mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
615         sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
616         sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
617
618         temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
619         temp_ff.full = rfixed_const(temp);
620         mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
621         mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
622
623         pix_clk.full = 0;
624         pix_clk2.full = 0;
625         peak_disp_bw.full = 0;
626         if (mode1) {
627                 temp_ff.full = rfixed_const(1000);
628                 pix_clk.full = rfixed_const(mode1->clock);      /* convert to fixed point */
629                 pix_clk.full = rfixed_div(pix_clk, temp_ff);
630                 temp_ff.full = rfixed_const(pixel_bytes1);
631                 peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
632         }
633         if (mode2) {
634                 temp_ff.full = rfixed_const(1000);
635                 pix_clk2.full = rfixed_const(mode2->clock);     /* convert to fixed point */
636                 pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
637                 temp_ff.full = rfixed_const(pixel_bytes2);
638                 peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
639         }
640
641         if (peak_disp_bw.full >= mem_bw.full) {
642                 DRM_ERROR
643                     ("You may not have enough display bandwidth for current mode\n"
644                      "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
645                 printk("peak disp bw %d, mem_bw %d\n",
646                        rfixed_trunc(peak_disp_bw), rfixed_trunc(mem_bw));
647         }
648
649         /*
650          * Line Buffer Setup
651          * There is a single line buffer shared by both display controllers.
652          * DC_LB_MEMORY_SPLIT controls how that line buffer is shared between the display
653          * controllers.  The paritioning can either be done manually or via one of four
654          * preset allocations specified in bits 1:0:
655          * 0 - line buffer is divided in half and shared between each display controller
656          * 1 - D1 gets 3/4 of the line buffer, D2 gets 1/4
657          * 2 - D1 gets the whole buffer
658          * 3 - D1 gets 1/4 of the line buffer, D2 gets 3/4
659          * Setting bit 2 of DC_LB_MEMORY_SPLIT controls switches to manual allocation mode.
660          * In manual allocation mode, D1 always starts at 0, D1 end/2 is specified in bits
661          * 14:4; D2 allocation follows D1.
662          */
663
664         /* is auto or manual better ? */
665         dc_lb_memory_split =
666             RREG32(AVIVO_DC_LB_MEMORY_SPLIT) & ~AVIVO_DC_LB_MEMORY_SPLIT_MASK;
667         dc_lb_memory_split &= ~AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE;
668 #if 1
669         /* auto */
670         if (mode1 && mode2) {
671                 if (mode1->hdisplay > mode2->hdisplay) {
672                         if (mode1->hdisplay > 2560)
673                                 dc_lb_memory_split |=
674                                     AVIVO_DC_LB_MEMORY_SPLIT_D1_3Q_D2_1Q;
675                         else
676                                 dc_lb_memory_split |=
677                                     AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
678                 } else if (mode2->hdisplay > mode1->hdisplay) {
679                         if (mode2->hdisplay > 2560)
680                                 dc_lb_memory_split |=
681                                     AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
682                         else
683                                 dc_lb_memory_split |=
684                                     AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
685                 } else
686                         dc_lb_memory_split |=
687                             AVIVO_DC_LB_MEMORY_SPLIT_D1HALF_D2HALF;
688         } else if (mode1) {
689                 dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_D1_ONLY;
690         } else if (mode2) {
691                 dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_D1_1Q_D2_3Q;
692         }
693 #else
694         /* manual */
695         dc_lb_memory_split |= AVIVO_DC_LB_MEMORY_SPLIT_SHIFT_MODE;
696         dc_lb_memory_split &=
697             ~(AVIVO_DC_LB_DISP1_END_ADR_MASK <<
698               AVIVO_DC_LB_DISP1_END_ADR_SHIFT);
699         if (mode1) {
700                 dc_lb_memory_split |=
701                     ((((mode1->hdisplay / 2) + 64) & AVIVO_DC_LB_DISP1_END_ADR_MASK)
702                      << AVIVO_DC_LB_DISP1_END_ADR_SHIFT);
703         } else if (mode2) {
704                 dc_lb_memory_split |= (0 << AVIVO_DC_LB_DISP1_END_ADR_SHIFT);
705         }
706 #endif
707         WREG32(AVIVO_DC_LB_MEMORY_SPLIT, dc_lb_memory_split);
708 }