drm/radeon: fix ordering in pll picking on dce4+
[linux-2.6.git] / drivers / gpu / drm / radeon / atombios_crtc.c
1 /*
2  * Copyright 2007-8 Advanced Micro Devices, Inc.
3  * Copyright 2008 Red Hat Inc.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining a
6  * copy of this software and associated documentation files (the "Software"),
7  * to deal in the Software without restriction, including without limitation
8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9  * and/or sell copies of the Software, and to permit persons to whom the
10  * Software is furnished to do so, subject to the following conditions:
11  *
12  * The above copyright notice and this permission notice shall be included in
13  * all copies or substantial portions of the Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21  * OTHER DEALINGS IN THE SOFTWARE.
22  *
23  * Authors: Dave Airlie
24  *          Alex Deucher
25  */
26 #include <drm/drmP.h>
27 #include <drm/drm_crtc_helper.h>
28 #include <drm/radeon_drm.h>
29 #include <drm/drm_fixed.h>
30 #include "radeon.h"
31 #include "atom.h"
32 #include "atom-bits.h"
33
34 static void atombios_overscan_setup(struct drm_crtc *crtc,
35                                     struct drm_display_mode *mode,
36                                     struct drm_display_mode *adjusted_mode)
37 {
38         struct drm_device *dev = crtc->dev;
39         struct radeon_device *rdev = dev->dev_private;
40         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
41         SET_CRTC_OVERSCAN_PS_ALLOCATION args;
42         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan);
43         int a1, a2;
44
45         memset(&args, 0, sizeof(args));
46
47         args.ucCRTC = radeon_crtc->crtc_id;
48
49         switch (radeon_crtc->rmx_type) {
50         case RMX_CENTER:
51                 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
52                 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2);
53                 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
54                 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2);
55                 break;
56         case RMX_ASPECT:
57                 a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay;
58                 a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay;
59
60                 if (a1 > a2) {
61                         args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
62                         args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2);
63                 } else if (a2 > a1) {
64                         args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
65                         args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2);
66                 }
67                 break;
68         case RMX_FULL:
69         default:
70                 args.usOverscanRight = cpu_to_le16(radeon_crtc->h_border);
71                 args.usOverscanLeft = cpu_to_le16(radeon_crtc->h_border);
72                 args.usOverscanBottom = cpu_to_le16(radeon_crtc->v_border);
73                 args.usOverscanTop = cpu_to_le16(radeon_crtc->v_border);
74                 break;
75         }
76         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
77 }
78
79 static void atombios_scaler_setup(struct drm_crtc *crtc)
80 {
81         struct drm_device *dev = crtc->dev;
82         struct radeon_device *rdev = dev->dev_private;
83         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
84         ENABLE_SCALER_PS_ALLOCATION args;
85         int index = GetIndexIntoMasterTable(COMMAND, EnableScaler);
86
87         /* fixme - fill in enc_priv for atom dac */
88         enum radeon_tv_std tv_std = TV_STD_NTSC;
89         bool is_tv = false, is_cv = false;
90         struct drm_encoder *encoder;
91
92         if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id)
93                 return;
94
95         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
96                 /* find tv std */
97                 if (encoder->crtc == crtc) {
98                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
99                         if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) {
100                                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
101                                 tv_std = tv_dac->tv_std;
102                                 is_tv = true;
103                         }
104                 }
105         }
106
107         memset(&args, 0, sizeof(args));
108
109         args.ucScaler = radeon_crtc->crtc_id;
110
111         if (is_tv) {
112                 switch (tv_std) {
113                 case TV_STD_NTSC:
114                 default:
115                         args.ucTVStandard = ATOM_TV_NTSC;
116                         break;
117                 case TV_STD_PAL:
118                         args.ucTVStandard = ATOM_TV_PAL;
119                         break;
120                 case TV_STD_PAL_M:
121                         args.ucTVStandard = ATOM_TV_PALM;
122                         break;
123                 case TV_STD_PAL_60:
124                         args.ucTVStandard = ATOM_TV_PAL60;
125                         break;
126                 case TV_STD_NTSC_J:
127                         args.ucTVStandard = ATOM_TV_NTSCJ;
128                         break;
129                 case TV_STD_SCART_PAL:
130                         args.ucTVStandard = ATOM_TV_PAL; /* ??? */
131                         break;
132                 case TV_STD_SECAM:
133                         args.ucTVStandard = ATOM_TV_SECAM;
134                         break;
135                 case TV_STD_PAL_CN:
136                         args.ucTVStandard = ATOM_TV_PALCN;
137                         break;
138                 }
139                 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
140         } else if (is_cv) {
141                 args.ucTVStandard = ATOM_TV_CV;
142                 args.ucEnable = SCALER_ENABLE_MULTITAP_MODE;
143         } else {
144                 switch (radeon_crtc->rmx_type) {
145                 case RMX_FULL:
146                         args.ucEnable = ATOM_SCALER_EXPANSION;
147                         break;
148                 case RMX_CENTER:
149                         args.ucEnable = ATOM_SCALER_CENTER;
150                         break;
151                 case RMX_ASPECT:
152                         args.ucEnable = ATOM_SCALER_EXPANSION;
153                         break;
154                 default:
155                         if (ASIC_IS_AVIVO(rdev))
156                                 args.ucEnable = ATOM_SCALER_DISABLE;
157                         else
158                                 args.ucEnable = ATOM_SCALER_CENTER;
159                         break;
160                 }
161         }
162         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
163         if ((is_tv || is_cv)
164             && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) {
165                 atom_rv515_force_tv_scaler(rdev, radeon_crtc);
166         }
167 }
168
169 static void atombios_lock_crtc(struct drm_crtc *crtc, int lock)
170 {
171         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
172         struct drm_device *dev = crtc->dev;
173         struct radeon_device *rdev = dev->dev_private;
174         int index =
175             GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters);
176         ENABLE_CRTC_PS_ALLOCATION args;
177
178         memset(&args, 0, sizeof(args));
179
180         args.ucCRTC = radeon_crtc->crtc_id;
181         args.ucEnable = lock;
182
183         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
184 }
185
186 static void atombios_enable_crtc(struct drm_crtc *crtc, int state)
187 {
188         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
189         struct drm_device *dev = crtc->dev;
190         struct radeon_device *rdev = dev->dev_private;
191         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC);
192         ENABLE_CRTC_PS_ALLOCATION args;
193
194         memset(&args, 0, sizeof(args));
195
196         args.ucCRTC = radeon_crtc->crtc_id;
197         args.ucEnable = state;
198
199         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
200 }
201
202 static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state)
203 {
204         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
205         struct drm_device *dev = crtc->dev;
206         struct radeon_device *rdev = dev->dev_private;
207         int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq);
208         ENABLE_CRTC_PS_ALLOCATION args;
209
210         memset(&args, 0, sizeof(args));
211
212         args.ucCRTC = radeon_crtc->crtc_id;
213         args.ucEnable = state;
214
215         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
216 }
217
218 static void atombios_blank_crtc(struct drm_crtc *crtc, int state)
219 {
220         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
221         struct drm_device *dev = crtc->dev;
222         struct radeon_device *rdev = dev->dev_private;
223         int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC);
224         BLANK_CRTC_PS_ALLOCATION args;
225
226         memset(&args, 0, sizeof(args));
227
228         args.ucCRTC = radeon_crtc->crtc_id;
229         args.ucBlanking = state;
230
231         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
232 }
233
234 static void atombios_powergate_crtc(struct drm_crtc *crtc, int state)
235 {
236         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
237         struct drm_device *dev = crtc->dev;
238         struct radeon_device *rdev = dev->dev_private;
239         int index = GetIndexIntoMasterTable(COMMAND, EnableDispPowerGating);
240         ENABLE_DISP_POWER_GATING_PARAMETERS_V2_1 args;
241
242         memset(&args, 0, sizeof(args));
243
244         args.ucDispPipeId = radeon_crtc->crtc_id;
245         args.ucEnable = state;
246
247         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
248 }
249
250 void atombios_crtc_dpms(struct drm_crtc *crtc, int mode)
251 {
252         struct drm_device *dev = crtc->dev;
253         struct radeon_device *rdev = dev->dev_private;
254         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
255
256         switch (mode) {
257         case DRM_MODE_DPMS_ON:
258                 radeon_crtc->enabled = true;
259                 /* adjust pm to dpms changes BEFORE enabling crtcs */
260                 radeon_pm_compute_clocks(rdev);
261                 if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set)
262                         atombios_powergate_crtc(crtc, ATOM_DISABLE);
263                 atombios_enable_crtc(crtc, ATOM_ENABLE);
264                 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
265                         atombios_enable_crtc_memreq(crtc, ATOM_ENABLE);
266                 atombios_blank_crtc(crtc, ATOM_DISABLE);
267                 drm_vblank_post_modeset(dev, radeon_crtc->crtc_id);
268                 radeon_crtc_load_lut(crtc);
269                 break;
270         case DRM_MODE_DPMS_STANDBY:
271         case DRM_MODE_DPMS_SUSPEND:
272         case DRM_MODE_DPMS_OFF:
273                 drm_vblank_pre_modeset(dev, radeon_crtc->crtc_id);
274                 if (radeon_crtc->enabled)
275                         atombios_blank_crtc(crtc, ATOM_ENABLE);
276                 if (ASIC_IS_DCE3(rdev) && !ASIC_IS_DCE6(rdev))
277                         atombios_enable_crtc_memreq(crtc, ATOM_DISABLE);
278                 atombios_enable_crtc(crtc, ATOM_DISABLE);
279                 radeon_crtc->enabled = false;
280                 if (ASIC_IS_DCE6(rdev) && !radeon_crtc->in_mode_set)
281                         atombios_powergate_crtc(crtc, ATOM_ENABLE);
282                 /* adjust pm to dpms changes AFTER disabling crtcs */
283                 radeon_pm_compute_clocks(rdev);
284                 break;
285         }
286 }
287
288 static void
289 atombios_set_crtc_dtd_timing(struct drm_crtc *crtc,
290                              struct drm_display_mode *mode)
291 {
292         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
293         struct drm_device *dev = crtc->dev;
294         struct radeon_device *rdev = dev->dev_private;
295         SET_CRTC_USING_DTD_TIMING_PARAMETERS args;
296         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming);
297         u16 misc = 0;
298
299         memset(&args, 0, sizeof(args));
300         args.usH_Size = cpu_to_le16(mode->crtc_hdisplay - (radeon_crtc->h_border * 2));
301         args.usH_Blanking_Time =
302                 cpu_to_le16(mode->crtc_hblank_end - mode->crtc_hdisplay + (radeon_crtc->h_border * 2));
303         args.usV_Size = cpu_to_le16(mode->crtc_vdisplay - (radeon_crtc->v_border * 2));
304         args.usV_Blanking_Time =
305                 cpu_to_le16(mode->crtc_vblank_end - mode->crtc_vdisplay + (radeon_crtc->v_border * 2));
306         args.usH_SyncOffset =
307                 cpu_to_le16(mode->crtc_hsync_start - mode->crtc_hdisplay + radeon_crtc->h_border);
308         args.usH_SyncWidth =
309                 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
310         args.usV_SyncOffset =
311                 cpu_to_le16(mode->crtc_vsync_start - mode->crtc_vdisplay + radeon_crtc->v_border);
312         args.usV_SyncWidth =
313                 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
314         args.ucH_Border = radeon_crtc->h_border;
315         args.ucV_Border = radeon_crtc->v_border;
316
317         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
318                 misc |= ATOM_VSYNC_POLARITY;
319         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
320                 misc |= ATOM_HSYNC_POLARITY;
321         if (mode->flags & DRM_MODE_FLAG_CSYNC)
322                 misc |= ATOM_COMPOSITESYNC;
323         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
324                 misc |= ATOM_INTERLACE;
325         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
326                 misc |= ATOM_DOUBLE_CLOCK_MODE;
327
328         args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
329         args.ucCRTC = radeon_crtc->crtc_id;
330
331         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
332 }
333
334 static void atombios_crtc_set_timing(struct drm_crtc *crtc,
335                                      struct drm_display_mode *mode)
336 {
337         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
338         struct drm_device *dev = crtc->dev;
339         struct radeon_device *rdev = dev->dev_private;
340         SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION args;
341         int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing);
342         u16 misc = 0;
343
344         memset(&args, 0, sizeof(args));
345         args.usH_Total = cpu_to_le16(mode->crtc_htotal);
346         args.usH_Disp = cpu_to_le16(mode->crtc_hdisplay);
347         args.usH_SyncStart = cpu_to_le16(mode->crtc_hsync_start);
348         args.usH_SyncWidth =
349                 cpu_to_le16(mode->crtc_hsync_end - mode->crtc_hsync_start);
350         args.usV_Total = cpu_to_le16(mode->crtc_vtotal);
351         args.usV_Disp = cpu_to_le16(mode->crtc_vdisplay);
352         args.usV_SyncStart = cpu_to_le16(mode->crtc_vsync_start);
353         args.usV_SyncWidth =
354                 cpu_to_le16(mode->crtc_vsync_end - mode->crtc_vsync_start);
355
356         args.ucOverscanRight = radeon_crtc->h_border;
357         args.ucOverscanLeft = radeon_crtc->h_border;
358         args.ucOverscanBottom = radeon_crtc->v_border;
359         args.ucOverscanTop = radeon_crtc->v_border;
360
361         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
362                 misc |= ATOM_VSYNC_POLARITY;
363         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
364                 misc |= ATOM_HSYNC_POLARITY;
365         if (mode->flags & DRM_MODE_FLAG_CSYNC)
366                 misc |= ATOM_COMPOSITESYNC;
367         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
368                 misc |= ATOM_INTERLACE;
369         if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
370                 misc |= ATOM_DOUBLE_CLOCK_MODE;
371
372         args.susModeMiscInfo.usAccess = cpu_to_le16(misc);
373         args.ucCRTC = radeon_crtc->crtc_id;
374
375         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
376 }
377
378 static void atombios_disable_ss(struct radeon_device *rdev, int pll_id)
379 {
380         u32 ss_cntl;
381
382         if (ASIC_IS_DCE4(rdev)) {
383                 switch (pll_id) {
384                 case ATOM_PPLL1:
385                         ss_cntl = RREG32(EVERGREEN_P1PLL_SS_CNTL);
386                         ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
387                         WREG32(EVERGREEN_P1PLL_SS_CNTL, ss_cntl);
388                         break;
389                 case ATOM_PPLL2:
390                         ss_cntl = RREG32(EVERGREEN_P2PLL_SS_CNTL);
391                         ss_cntl &= ~EVERGREEN_PxPLL_SS_EN;
392                         WREG32(EVERGREEN_P2PLL_SS_CNTL, ss_cntl);
393                         break;
394                 case ATOM_DCPLL:
395                 case ATOM_PPLL_INVALID:
396                         return;
397                 }
398         } else if (ASIC_IS_AVIVO(rdev)) {
399                 switch (pll_id) {
400                 case ATOM_PPLL1:
401                         ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL);
402                         ss_cntl &= ~1;
403                         WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl);
404                         break;
405                 case ATOM_PPLL2:
406                         ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL);
407                         ss_cntl &= ~1;
408                         WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl);
409                         break;
410                 case ATOM_DCPLL:
411                 case ATOM_PPLL_INVALID:
412                         return;
413                 }
414         }
415 }
416
417
418 union atom_enable_ss {
419         ENABLE_LVDS_SS_PARAMETERS lvds_ss;
420         ENABLE_LVDS_SS_PARAMETERS_V2 lvds_ss_2;
421         ENABLE_SPREAD_SPECTRUM_ON_PPLL_PS_ALLOCATION v1;
422         ENABLE_SPREAD_SPECTRUM_ON_PPLL_V2 v2;
423         ENABLE_SPREAD_SPECTRUM_ON_PPLL_V3 v3;
424 };
425
426 static void atombios_crtc_program_ss(struct radeon_device *rdev,
427                                      int enable,
428                                      int pll_id,
429                                      int crtc_id,
430                                      struct radeon_atom_ss *ss)
431 {
432         unsigned i;
433         int index = GetIndexIntoMasterTable(COMMAND, EnableSpreadSpectrumOnPPLL);
434         union atom_enable_ss args;
435
436         if (!enable) {
437                 for (i = 0; i < rdev->num_crtc; i++) {
438                         if (rdev->mode_info.crtcs[i] &&
439                             rdev->mode_info.crtcs[i]->enabled &&
440                             i != crtc_id &&
441                             pll_id == rdev->mode_info.crtcs[i]->pll_id) {
442                                 /* one other crtc is using this pll don't turn
443                                  * off spread spectrum as it might turn off
444                                  * display on active crtc
445                                  */
446                                 return;
447                         }
448                 }
449         }
450
451         memset(&args, 0, sizeof(args));
452
453         if (ASIC_IS_DCE5(rdev)) {
454                 args.v3.usSpreadSpectrumAmountFrac = cpu_to_le16(0);
455                 args.v3.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
456                 switch (pll_id) {
457                 case ATOM_PPLL1:
458                         args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P1PLL;
459                         args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
460                         args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
461                         break;
462                 case ATOM_PPLL2:
463                         args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_P2PLL;
464                         args.v3.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
465                         args.v3.usSpreadSpectrumStep = cpu_to_le16(ss->step);
466                         break;
467                 case ATOM_DCPLL:
468                         args.v3.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V3_DCPLL;
469                         args.v3.usSpreadSpectrumAmount = cpu_to_le16(0);
470                         args.v3.usSpreadSpectrumStep = cpu_to_le16(0);
471                         break;
472                 case ATOM_PPLL_INVALID:
473                         return;
474                 }
475                 args.v3.ucEnable = enable;
476                 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE61(rdev))
477                         args.v3.ucEnable = ATOM_DISABLE;
478         } else if (ASIC_IS_DCE4(rdev)) {
479                 args.v2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
480                 args.v2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
481                 switch (pll_id) {
482                 case ATOM_PPLL1:
483                         args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P1PLL;
484                         args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
485                         args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
486                         break;
487                 case ATOM_PPLL2:
488                         args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_P2PLL;
489                         args.v2.usSpreadSpectrumAmount = cpu_to_le16(ss->amount);
490                         args.v2.usSpreadSpectrumStep = cpu_to_le16(ss->step);
491                         break;
492                 case ATOM_DCPLL:
493                         args.v2.ucSpreadSpectrumType |= ATOM_PPLL_SS_TYPE_V2_DCPLL;
494                         args.v2.usSpreadSpectrumAmount = cpu_to_le16(0);
495                         args.v2.usSpreadSpectrumStep = cpu_to_le16(0);
496                         break;
497                 case ATOM_PPLL_INVALID:
498                         return;
499                 }
500                 args.v2.ucEnable = enable;
501                 if ((ss->percentage == 0) || (ss->type & ATOM_EXTERNAL_SS_MASK) || ASIC_IS_DCE41(rdev))
502                         args.v2.ucEnable = ATOM_DISABLE;
503         } else if (ASIC_IS_DCE3(rdev)) {
504                 args.v1.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
505                 args.v1.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
506                 args.v1.ucSpreadSpectrumStep = ss->step;
507                 args.v1.ucSpreadSpectrumDelay = ss->delay;
508                 args.v1.ucSpreadSpectrumRange = ss->range;
509                 args.v1.ucPpll = pll_id;
510                 args.v1.ucEnable = enable;
511         } else if (ASIC_IS_AVIVO(rdev)) {
512                 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
513                     (ss->type & ATOM_EXTERNAL_SS_MASK)) {
514                         atombios_disable_ss(rdev, pll_id);
515                         return;
516                 }
517                 args.lvds_ss_2.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
518                 args.lvds_ss_2.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
519                 args.lvds_ss_2.ucSpreadSpectrumStep = ss->step;
520                 args.lvds_ss_2.ucSpreadSpectrumDelay = ss->delay;
521                 args.lvds_ss_2.ucSpreadSpectrumRange = ss->range;
522                 args.lvds_ss_2.ucEnable = enable;
523         } else {
524                 if ((enable == ATOM_DISABLE) || (ss->percentage == 0) ||
525                     (ss->type & ATOM_EXTERNAL_SS_MASK)) {
526                         atombios_disable_ss(rdev, pll_id);
527                         return;
528                 }
529                 args.lvds_ss.usSpreadSpectrumPercentage = cpu_to_le16(ss->percentage);
530                 args.lvds_ss.ucSpreadSpectrumType = ss->type & ATOM_SS_CENTRE_SPREAD_MODE_MASK;
531                 args.lvds_ss.ucSpreadSpectrumStepSize_Delay = (ss->step & 3) << 2;
532                 args.lvds_ss.ucSpreadSpectrumStepSize_Delay |= (ss->delay & 7) << 4;
533                 args.lvds_ss.ucEnable = enable;
534         }
535         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
536 }
537
538 union adjust_pixel_clock {
539         ADJUST_DISPLAY_PLL_PS_ALLOCATION v1;
540         ADJUST_DISPLAY_PLL_PS_ALLOCATION_V3 v3;
541 };
542
543 static u32 atombios_adjust_pll(struct drm_crtc *crtc,
544                                struct drm_display_mode *mode,
545                                struct radeon_pll *pll,
546                                bool ss_enabled,
547                                struct radeon_atom_ss *ss)
548 {
549         struct drm_device *dev = crtc->dev;
550         struct radeon_device *rdev = dev->dev_private;
551         struct drm_encoder *encoder = NULL;
552         struct radeon_encoder *radeon_encoder = NULL;
553         struct drm_connector *connector = NULL;
554         u32 adjusted_clock = mode->clock;
555         int encoder_mode = 0;
556         u32 dp_clock = mode->clock;
557         int bpc = 8;
558         bool is_duallink = false;
559
560         /* reset the pll flags */
561         pll->flags = 0;
562
563         if (ASIC_IS_AVIVO(rdev)) {
564                 if ((rdev->family == CHIP_RS600) ||
565                     (rdev->family == CHIP_RS690) ||
566                     (rdev->family == CHIP_RS740))
567                         pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
568                                        RADEON_PLL_PREFER_CLOSEST_LOWER);
569
570                 if (ASIC_IS_DCE32(rdev) && mode->clock > 200000)        /* range limits??? */
571                         pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
572                 else
573                         pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
574
575                 if (rdev->family < CHIP_RV770)
576                         pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
577                 /* use frac fb div on APUs */
578                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
579                         pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
580         } else {
581                 pll->flags |= RADEON_PLL_LEGACY;
582
583                 if (mode->clock > 200000)       /* range limits??? */
584                         pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
585                 else
586                         pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
587         }
588
589         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
590                 if (encoder->crtc == crtc) {
591                         radeon_encoder = to_radeon_encoder(encoder);
592                         connector = radeon_get_connector_for_encoder(encoder);
593                         /* if (connector && connector->display_info.bpc)
594                                 bpc = connector->display_info.bpc; */
595                         encoder_mode = atombios_get_encoder_mode(encoder);
596                         is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
597                         if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
598                             (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
599                                 if (connector) {
600                                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
601                                         struct radeon_connector_atom_dig *dig_connector =
602                                                 radeon_connector->con_priv;
603
604                                         dp_clock = dig_connector->dp_clock;
605                                 }
606                         }
607
608                         /* use recommended ref_div for ss */
609                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
610                                 if (ss_enabled) {
611                                         if (ss->refdiv) {
612                                                 pll->flags |= RADEON_PLL_USE_REF_DIV;
613                                                 pll->reference_div = ss->refdiv;
614                                                 if (ASIC_IS_AVIVO(rdev))
615                                                         pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
616                                         }
617                                 }
618                         }
619
620                         if (ASIC_IS_AVIVO(rdev)) {
621                                 /* DVO wants 2x pixel clock if the DVO chip is in 12 bit mode */
622                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1)
623                                         adjusted_clock = mode->clock * 2;
624                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
625                                         pll->flags |= RADEON_PLL_PREFER_CLOSEST_LOWER;
626                                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
627                                         pll->flags |= RADEON_PLL_IS_LCD;
628                         } else {
629                                 if (encoder->encoder_type != DRM_MODE_ENCODER_DAC)
630                                         pll->flags |= RADEON_PLL_NO_ODD_POST_DIV;
631                                 if (encoder->encoder_type == DRM_MODE_ENCODER_LVDS)
632                                         pll->flags |= RADEON_PLL_USE_REF_DIV;
633                         }
634                         break;
635                 }
636         }
637
638         /* DCE3+ has an AdjustDisplayPll that will adjust the pixel clock
639          * accordingly based on the encoder/transmitter to work around
640          * special hw requirements.
641          */
642         if (ASIC_IS_DCE3(rdev)) {
643                 union adjust_pixel_clock args;
644                 u8 frev, crev;
645                 int index;
646
647                 index = GetIndexIntoMasterTable(COMMAND, AdjustDisplayPll);
648                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
649                                            &crev))
650                         return adjusted_clock;
651
652                 memset(&args, 0, sizeof(args));
653
654                 switch (frev) {
655                 case 1:
656                         switch (crev) {
657                         case 1:
658                         case 2:
659                                 args.v1.usPixelClock = cpu_to_le16(mode->clock / 10);
660                                 args.v1.ucTransmitterID = radeon_encoder->encoder_id;
661                                 args.v1.ucEncodeMode = encoder_mode;
662                                 if (ss_enabled && ss->percentage)
663                                         args.v1.ucConfig |=
664                                                 ADJUST_DISPLAY_CONFIG_SS_ENABLE;
665
666                                 atom_execute_table(rdev->mode_info.atom_context,
667                                                    index, (uint32_t *)&args);
668                                 adjusted_clock = le16_to_cpu(args.v1.usPixelClock) * 10;
669                                 break;
670                         case 3:
671                                 args.v3.sInput.usPixelClock = cpu_to_le16(mode->clock / 10);
672                                 args.v3.sInput.ucTransmitterID = radeon_encoder->encoder_id;
673                                 args.v3.sInput.ucEncodeMode = encoder_mode;
674                                 args.v3.sInput.ucDispPllConfig = 0;
675                                 if (ss_enabled && ss->percentage)
676                                         args.v3.sInput.ucDispPllConfig |=
677                                                 DISPPLL_CONFIG_SS_ENABLE;
678                                 if (ENCODER_MODE_IS_DP(encoder_mode)) {
679                                         args.v3.sInput.ucDispPllConfig |=
680                                                 DISPPLL_CONFIG_COHERENT_MODE;
681                                         /* 16200 or 27000 */
682                                         args.v3.sInput.usPixelClock = cpu_to_le16(dp_clock / 10);
683                                 } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
684                                         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
685                                         if (encoder_mode == ATOM_ENCODER_MODE_HDMI)
686                                                 /* deep color support */
687                                                 args.v3.sInput.usPixelClock =
688                                                         cpu_to_le16((mode->clock * bpc / 8) / 10);
689                                         if (dig->coherent_mode)
690                                                 args.v3.sInput.ucDispPllConfig |=
691                                                         DISPPLL_CONFIG_COHERENT_MODE;
692                                         if (is_duallink)
693                                                 args.v3.sInput.ucDispPllConfig |=
694                                                         DISPPLL_CONFIG_DUAL_LINK;
695                                 }
696                                 if (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
697                                     ENCODER_OBJECT_ID_NONE)
698                                         args.v3.sInput.ucExtTransmitterID =
699                                                 radeon_encoder_get_dp_bridge_encoder_id(encoder);
700                                 else
701                                         args.v3.sInput.ucExtTransmitterID = 0;
702
703                                 atom_execute_table(rdev->mode_info.atom_context,
704                                                    index, (uint32_t *)&args);
705                                 adjusted_clock = le32_to_cpu(args.v3.sOutput.ulDispPllFreq) * 10;
706                                 if (args.v3.sOutput.ucRefDiv) {
707                                         pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
708                                         pll->flags |= RADEON_PLL_USE_REF_DIV;
709                                         pll->reference_div = args.v3.sOutput.ucRefDiv;
710                                 }
711                                 if (args.v3.sOutput.ucPostDiv) {
712                                         pll->flags |= RADEON_PLL_USE_FRAC_FB_DIV;
713                                         pll->flags |= RADEON_PLL_USE_POST_DIV;
714                                         pll->post_div = args.v3.sOutput.ucPostDiv;
715                                 }
716                                 break;
717                         default:
718                                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
719                                 return adjusted_clock;
720                         }
721                         break;
722                 default:
723                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
724                         return adjusted_clock;
725                 }
726         }
727         return adjusted_clock;
728 }
729
730 union set_pixel_clock {
731         SET_PIXEL_CLOCK_PS_ALLOCATION base;
732         PIXEL_CLOCK_PARAMETERS v1;
733         PIXEL_CLOCK_PARAMETERS_V2 v2;
734         PIXEL_CLOCK_PARAMETERS_V3 v3;
735         PIXEL_CLOCK_PARAMETERS_V5 v5;
736         PIXEL_CLOCK_PARAMETERS_V6 v6;
737 };
738
739 /* on DCE5, make sure the voltage is high enough to support the
740  * required disp clk.
741  */
742 static void atombios_crtc_set_disp_eng_pll(struct radeon_device *rdev,
743                                     u32 dispclk)
744 {
745         u8 frev, crev;
746         int index;
747         union set_pixel_clock args;
748
749         memset(&args, 0, sizeof(args));
750
751         index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
752         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
753                                    &crev))
754                 return;
755
756         switch (frev) {
757         case 1:
758                 switch (crev) {
759                 case 5:
760                         /* if the default dcpll clock is specified,
761                          * SetPixelClock provides the dividers
762                          */
763                         args.v5.ucCRTC = ATOM_CRTC_INVALID;
764                         args.v5.usPixelClock = cpu_to_le16(dispclk);
765                         args.v5.ucPpll = ATOM_DCPLL;
766                         break;
767                 case 6:
768                         /* if the default dcpll clock is specified,
769                          * SetPixelClock provides the dividers
770                          */
771                         args.v6.ulDispEngClkFreq = cpu_to_le32(dispclk);
772                         if (ASIC_IS_DCE61(rdev))
773                                 args.v6.ucPpll = ATOM_EXT_PLL1;
774                         else if (ASIC_IS_DCE6(rdev))
775                                 args.v6.ucPpll = ATOM_PPLL0;
776                         else
777                                 args.v6.ucPpll = ATOM_DCPLL;
778                         break;
779                 default:
780                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
781                         return;
782                 }
783                 break;
784         default:
785                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
786                 return;
787         }
788         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
789 }
790
791 static void atombios_crtc_program_pll(struct drm_crtc *crtc,
792                                       u32 crtc_id,
793                                       int pll_id,
794                                       u32 encoder_mode,
795                                       u32 encoder_id,
796                                       u32 clock,
797                                       u32 ref_div,
798                                       u32 fb_div,
799                                       u32 frac_fb_div,
800                                       u32 post_div,
801                                       int bpc,
802                                       bool ss_enabled,
803                                       struct radeon_atom_ss *ss)
804 {
805         struct drm_device *dev = crtc->dev;
806         struct radeon_device *rdev = dev->dev_private;
807         u8 frev, crev;
808         int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock);
809         union set_pixel_clock args;
810
811         memset(&args, 0, sizeof(args));
812
813         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev,
814                                    &crev))
815                 return;
816
817         switch (frev) {
818         case 1:
819                 switch (crev) {
820                 case 1:
821                         if (clock == ATOM_DISABLE)
822                                 return;
823                         args.v1.usPixelClock = cpu_to_le16(clock / 10);
824                         args.v1.usRefDiv = cpu_to_le16(ref_div);
825                         args.v1.usFbDiv = cpu_to_le16(fb_div);
826                         args.v1.ucFracFbDiv = frac_fb_div;
827                         args.v1.ucPostDiv = post_div;
828                         args.v1.ucPpll = pll_id;
829                         args.v1.ucCRTC = crtc_id;
830                         args.v1.ucRefDivSrc = 1;
831                         break;
832                 case 2:
833                         args.v2.usPixelClock = cpu_to_le16(clock / 10);
834                         args.v2.usRefDiv = cpu_to_le16(ref_div);
835                         args.v2.usFbDiv = cpu_to_le16(fb_div);
836                         args.v2.ucFracFbDiv = frac_fb_div;
837                         args.v2.ucPostDiv = post_div;
838                         args.v2.ucPpll = pll_id;
839                         args.v2.ucCRTC = crtc_id;
840                         args.v2.ucRefDivSrc = 1;
841                         break;
842                 case 3:
843                         args.v3.usPixelClock = cpu_to_le16(clock / 10);
844                         args.v3.usRefDiv = cpu_to_le16(ref_div);
845                         args.v3.usFbDiv = cpu_to_le16(fb_div);
846                         args.v3.ucFracFbDiv = frac_fb_div;
847                         args.v3.ucPostDiv = post_div;
848                         args.v3.ucPpll = pll_id;
849                         args.v3.ucMiscInfo = (pll_id << 2);
850                         if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
851                                 args.v3.ucMiscInfo |= PIXEL_CLOCK_MISC_REF_DIV_SRC;
852                         args.v3.ucTransmitterId = encoder_id;
853                         args.v3.ucEncoderMode = encoder_mode;
854                         break;
855                 case 5:
856                         args.v5.ucCRTC = crtc_id;
857                         args.v5.usPixelClock = cpu_to_le16(clock / 10);
858                         args.v5.ucRefDiv = ref_div;
859                         args.v5.usFbDiv = cpu_to_le16(fb_div);
860                         args.v5.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
861                         args.v5.ucPostDiv = post_div;
862                         args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
863                         if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
864                                 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
865                         switch (bpc) {
866                         case 8:
867                         default:
868                                 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
869                                 break;
870                         case 10:
871                                 args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
872                                 break;
873                         }
874                         args.v5.ucTransmitterID = encoder_id;
875                         args.v5.ucEncoderMode = encoder_mode;
876                         args.v5.ucPpll = pll_id;
877                         break;
878                 case 6:
879                         args.v6.ulDispEngClkFreq = cpu_to_le32(crtc_id << 24 | clock / 10);
880                         args.v6.ucRefDiv = ref_div;
881                         args.v6.usFbDiv = cpu_to_le16(fb_div);
882                         args.v6.ulFbDivDecFrac = cpu_to_le32(frac_fb_div * 100000);
883                         args.v6.ucPostDiv = post_div;
884                         args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
885                         if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
886                                 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
887                         switch (bpc) {
888                         case 8:
889                         default:
890                                 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
891                                 break;
892                         case 10:
893                                 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP;
894                                 break;
895                         case 12:
896                                 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP;
897                                 break;
898                         case 16:
899                                 args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
900                                 break;
901                         }
902                         args.v6.ucTransmitterID = encoder_id;
903                         args.v6.ucEncoderMode = encoder_mode;
904                         args.v6.ucPpll = pll_id;
905                         break;
906                 default:
907                         DRM_ERROR("Unknown table version %d %d\n", frev, crev);
908                         return;
909                 }
910                 break;
911         default:
912                 DRM_ERROR("Unknown table version %d %d\n", frev, crev);
913                 return;
914         }
915
916         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
917 }
918
919 static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
920 {
921         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
922         struct drm_device *dev = crtc->dev;
923         struct radeon_device *rdev = dev->dev_private;
924         struct drm_encoder *encoder = NULL;
925         struct radeon_encoder *radeon_encoder = NULL;
926         u32 pll_clock = mode->clock;
927         u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0;
928         struct radeon_pll *pll;
929         u32 adjusted_clock;
930         int encoder_mode = 0;
931         struct radeon_atom_ss ss;
932         bool ss_enabled = false;
933         int bpc = 8;
934
935         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
936                 if (encoder->crtc == crtc) {
937                         radeon_encoder = to_radeon_encoder(encoder);
938                         encoder_mode = atombios_get_encoder_mode(encoder);
939                         break;
940                 }
941         }
942
943         if (!radeon_encoder)
944                 return;
945
946         switch (radeon_crtc->pll_id) {
947         case ATOM_PPLL1:
948                 pll = &rdev->clock.p1pll;
949                 break;
950         case ATOM_PPLL2:
951                 pll = &rdev->clock.p2pll;
952                 break;
953         case ATOM_DCPLL:
954         case ATOM_PPLL_INVALID:
955         default:
956                 pll = &rdev->clock.dcpll;
957                 break;
958         }
959
960         if ((radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
961             (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
962                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
963                 struct drm_connector *connector =
964                         radeon_get_connector_for_encoder(encoder);
965                 struct radeon_connector *radeon_connector =
966                         to_radeon_connector(connector);
967                 struct radeon_connector_atom_dig *dig_connector =
968                         radeon_connector->con_priv;
969                 int dp_clock;
970
971                 /* if (connector->display_info.bpc)
972                         bpc = connector->display_info.bpc; */
973
974                 switch (encoder_mode) {
975                 case ATOM_ENCODER_MODE_DP_MST:
976                 case ATOM_ENCODER_MODE_DP:
977                         /* DP/eDP */
978                         dp_clock = dig_connector->dp_clock / 10;
979                         if (ASIC_IS_DCE4(rdev))
980                                 ss_enabled =
981                                         radeon_atombios_get_asic_ss_info(rdev, &ss,
982                                                                          ASIC_INTERNAL_SS_ON_DP,
983                                                                          dp_clock);
984                         else {
985                                 if (dp_clock == 16200) {
986                                         ss_enabled =
987                                                 radeon_atombios_get_ppll_ss_info(rdev, &ss,
988                                                                                  ATOM_DP_SS_ID2);
989                                         if (!ss_enabled)
990                                                 ss_enabled =
991                                                         radeon_atombios_get_ppll_ss_info(rdev, &ss,
992                                                                                          ATOM_DP_SS_ID1);
993                                 } else
994                                         ss_enabled =
995                                                 radeon_atombios_get_ppll_ss_info(rdev, &ss,
996                                                                                  ATOM_DP_SS_ID1);
997                         }
998                         break;
999                 case ATOM_ENCODER_MODE_LVDS:
1000                         if (ASIC_IS_DCE4(rdev))
1001                                 ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
1002                                                                               dig->lcd_ss_id,
1003                                                                               mode->clock / 10);
1004                         else
1005                                 ss_enabled = radeon_atombios_get_ppll_ss_info(rdev, &ss,
1006                                                                               dig->lcd_ss_id);
1007                         break;
1008                 case ATOM_ENCODER_MODE_DVI:
1009                         if (ASIC_IS_DCE4(rdev))
1010                                 ss_enabled =
1011                                         radeon_atombios_get_asic_ss_info(rdev, &ss,
1012                                                                          ASIC_INTERNAL_SS_ON_TMDS,
1013                                                                          mode->clock / 10);
1014                         break;
1015                 case ATOM_ENCODER_MODE_HDMI:
1016                         if (ASIC_IS_DCE4(rdev))
1017                                 ss_enabled =
1018                                         radeon_atombios_get_asic_ss_info(rdev, &ss,
1019                                                                          ASIC_INTERNAL_SS_ON_HDMI,
1020                                                                          mode->clock / 10);
1021                         break;
1022                 default:
1023                         break;
1024                 }
1025         }
1026
1027         /* adjust pixel clock as needed */
1028         adjusted_clock = atombios_adjust_pll(crtc, mode, pll, ss_enabled, &ss);
1029
1030         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1031                 /* TV seems to prefer the legacy algo on some boards */
1032                 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
1033                                           &ref_div, &post_div);
1034         else if (ASIC_IS_AVIVO(rdev))
1035                 radeon_compute_pll_avivo(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
1036                                          &ref_div, &post_div);
1037         else
1038                 radeon_compute_pll_legacy(pll, adjusted_clock, &pll_clock, &fb_div, &frac_fb_div,
1039                                           &ref_div, &post_div);
1040
1041         atombios_crtc_program_ss(rdev, ATOM_DISABLE, radeon_crtc->pll_id, radeon_crtc->crtc_id, &ss);
1042
1043         atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1044                                   encoder_mode, radeon_encoder->encoder_id, mode->clock,
1045                                   ref_div, fb_div, frac_fb_div, post_div, bpc, ss_enabled, &ss);
1046
1047         if (ss_enabled) {
1048                 /* calculate ss amount and step size */
1049                 if (ASIC_IS_DCE4(rdev)) {
1050                         u32 step_size;
1051                         u32 amount = (((fb_div * 10) + frac_fb_div) * ss.percentage) / 10000;
1052                         ss.amount = (amount / 10) & ATOM_PPLL_SS_AMOUNT_V2_FBDIV_MASK;
1053                         ss.amount |= ((amount - (amount / 10)) << ATOM_PPLL_SS_AMOUNT_V2_NFRAC_SHIFT) &
1054                                 ATOM_PPLL_SS_AMOUNT_V2_NFRAC_MASK;
1055                         if (ss.type & ATOM_PPLL_SS_TYPE_V2_CENTRE_SPREAD)
1056                                 step_size = (4 * amount * ref_div * (ss.rate * 2048)) /
1057                                         (125 * 25 * pll->reference_freq / 100);
1058                         else
1059                                 step_size = (2 * amount * ref_div * (ss.rate * 2048)) /
1060                                         (125 * 25 * pll->reference_freq / 100);
1061                         ss.step = step_size;
1062                 }
1063
1064                 atombios_crtc_program_ss(rdev, ATOM_ENABLE, radeon_crtc->pll_id, radeon_crtc->crtc_id, &ss);
1065         }
1066 }
1067
1068 static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
1069                                  struct drm_framebuffer *fb,
1070                                  int x, int y, int atomic)
1071 {
1072         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1073         struct drm_device *dev = crtc->dev;
1074         struct radeon_device *rdev = dev->dev_private;
1075         struct radeon_framebuffer *radeon_fb;
1076         struct drm_framebuffer *target_fb;
1077         struct drm_gem_object *obj;
1078         struct radeon_bo *rbo;
1079         uint64_t fb_location;
1080         uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1081         unsigned bankw, bankh, mtaspect, tile_split;
1082         u32 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
1083         u32 tmp, viewport_w, viewport_h;
1084         int r;
1085
1086         /* no fb bound */
1087         if (!atomic && !crtc->fb) {
1088                 DRM_DEBUG_KMS("No FB bound\n");
1089                 return 0;
1090         }
1091
1092         if (atomic) {
1093                 radeon_fb = to_radeon_framebuffer(fb);
1094                 target_fb = fb;
1095         }
1096         else {
1097                 radeon_fb = to_radeon_framebuffer(crtc->fb);
1098                 target_fb = crtc->fb;
1099         }
1100
1101         /* If atomic, assume fb object is pinned & idle & fenced and
1102          * just update base pointers
1103          */
1104         obj = radeon_fb->obj;
1105         rbo = gem_to_radeon_bo(obj);
1106         r = radeon_bo_reserve(rbo, false);
1107         if (unlikely(r != 0))
1108                 return r;
1109
1110         if (atomic)
1111                 fb_location = radeon_bo_gpu_offset(rbo);
1112         else {
1113                 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1114                 if (unlikely(r != 0)) {
1115                         radeon_bo_unreserve(rbo);
1116                         return -EINVAL;
1117                 }
1118         }
1119
1120         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1121         radeon_bo_unreserve(rbo);
1122
1123         switch (target_fb->bits_per_pixel) {
1124         case 8:
1125                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP) |
1126                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
1127                 break;
1128         case 15:
1129                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1130                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
1131                 break;
1132         case 16:
1133                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP) |
1134                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
1135 #ifdef __BIG_ENDIAN
1136                 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
1137 #endif
1138                 break;
1139         case 24:
1140         case 32:
1141                 fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
1142                              EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
1143 #ifdef __BIG_ENDIAN
1144                 fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
1145 #endif
1146                 break;
1147         default:
1148                 DRM_ERROR("Unsupported screen depth %d\n",
1149                           target_fb->bits_per_pixel);
1150                 return -EINVAL;
1151         }
1152
1153         if (tiling_flags & RADEON_TILING_MACRO) {
1154                 if (rdev->family >= CHIP_CAYMAN)
1155                         tmp = rdev->config.cayman.tile_config;
1156                 else
1157                         tmp = rdev->config.evergreen.tile_config;
1158
1159                 switch ((tmp & 0xf0) >> 4) {
1160                 case 0: /* 4 banks */
1161                         fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_4_BANK);
1162                         break;
1163                 case 1: /* 8 banks */
1164                 default:
1165                         fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_8_BANK);
1166                         break;
1167                 case 2: /* 16 banks */
1168                         fb_format |= EVERGREEN_GRPH_NUM_BANKS(EVERGREEN_ADDR_SURF_16_BANK);
1169                         break;
1170                 }
1171
1172                 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_2D_TILED_THIN1);
1173
1174                 evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split);
1175                 fb_format |= EVERGREEN_GRPH_TILE_SPLIT(tile_split);
1176                 fb_format |= EVERGREEN_GRPH_BANK_WIDTH(bankw);
1177                 fb_format |= EVERGREEN_GRPH_BANK_HEIGHT(bankh);
1178                 fb_format |= EVERGREEN_GRPH_MACRO_TILE_ASPECT(mtaspect);
1179         } else if (tiling_flags & RADEON_TILING_MICRO)
1180                 fb_format |= EVERGREEN_GRPH_ARRAY_MODE(EVERGREEN_GRPH_ARRAY_1D_TILED_THIN1);
1181
1182         switch (radeon_crtc->crtc_id) {
1183         case 0:
1184                 WREG32(AVIVO_D1VGA_CONTROL, 0);
1185                 break;
1186         case 1:
1187                 WREG32(AVIVO_D2VGA_CONTROL, 0);
1188                 break;
1189         case 2:
1190                 WREG32(EVERGREEN_D3VGA_CONTROL, 0);
1191                 break;
1192         case 3:
1193                 WREG32(EVERGREEN_D4VGA_CONTROL, 0);
1194                 break;
1195         case 4:
1196                 WREG32(EVERGREEN_D5VGA_CONTROL, 0);
1197                 break;
1198         case 5:
1199                 WREG32(EVERGREEN_D6VGA_CONTROL, 0);
1200                 break;
1201         default:
1202                 break;
1203         }
1204
1205         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1206                upper_32_bits(fb_location));
1207         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
1208                upper_32_bits(fb_location));
1209         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1210                (u32)fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1211         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1212                (u32) fb_location & EVERGREEN_GRPH_SURFACE_ADDRESS_MASK);
1213         WREG32(EVERGREEN_GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1214         WREG32(EVERGREEN_GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1215
1216         WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1217         WREG32(EVERGREEN_GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1218         WREG32(EVERGREEN_GRPH_X_START + radeon_crtc->crtc_offset, 0);
1219         WREG32(EVERGREEN_GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1220         WREG32(EVERGREEN_GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1221         WREG32(EVERGREEN_GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1222
1223         fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1224         WREG32(EVERGREEN_GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1225         WREG32(EVERGREEN_GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1226
1227         WREG32(EVERGREEN_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1228                target_fb->height);
1229         x &= ~3;
1230         y &= ~1;
1231         WREG32(EVERGREEN_VIEWPORT_START + radeon_crtc->crtc_offset,
1232                (x << 16) | y);
1233         viewport_w = crtc->mode.hdisplay;
1234         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1235         WREG32(EVERGREEN_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1236                (viewport_w << 16) | viewport_h);
1237
1238         /* pageflip setup */
1239         /* make sure flip is at vb rather than hb */
1240         tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1241         tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1242         WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1243
1244         /* set pageflip to happen anywhere in vblank interval */
1245         WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1246
1247         if (!atomic && fb && fb != crtc->fb) {
1248                 radeon_fb = to_radeon_framebuffer(fb);
1249                 rbo = gem_to_radeon_bo(radeon_fb->obj);
1250                 r = radeon_bo_reserve(rbo, false);
1251                 if (unlikely(r != 0))
1252                         return r;
1253                 radeon_bo_unpin(rbo);
1254                 radeon_bo_unreserve(rbo);
1255         }
1256
1257         /* Bytes per pixel may have changed */
1258         radeon_bandwidth_update(rdev);
1259
1260         return 0;
1261 }
1262
1263 static int avivo_crtc_do_set_base(struct drm_crtc *crtc,
1264                                   struct drm_framebuffer *fb,
1265                                   int x, int y, int atomic)
1266 {
1267         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1268         struct drm_device *dev = crtc->dev;
1269         struct radeon_device *rdev = dev->dev_private;
1270         struct radeon_framebuffer *radeon_fb;
1271         struct drm_gem_object *obj;
1272         struct radeon_bo *rbo;
1273         struct drm_framebuffer *target_fb;
1274         uint64_t fb_location;
1275         uint32_t fb_format, fb_pitch_pixels, tiling_flags;
1276         u32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE;
1277         u32 tmp, viewport_w, viewport_h;
1278         int r;
1279
1280         /* no fb bound */
1281         if (!atomic && !crtc->fb) {
1282                 DRM_DEBUG_KMS("No FB bound\n");
1283                 return 0;
1284         }
1285
1286         if (atomic) {
1287                 radeon_fb = to_radeon_framebuffer(fb);
1288                 target_fb = fb;
1289         }
1290         else {
1291                 radeon_fb = to_radeon_framebuffer(crtc->fb);
1292                 target_fb = crtc->fb;
1293         }
1294
1295         obj = radeon_fb->obj;
1296         rbo = gem_to_radeon_bo(obj);
1297         r = radeon_bo_reserve(rbo, false);
1298         if (unlikely(r != 0))
1299                 return r;
1300
1301         /* If atomic, assume fb object is pinned & idle & fenced and
1302          * just update base pointers
1303          */
1304         if (atomic)
1305                 fb_location = radeon_bo_gpu_offset(rbo);
1306         else {
1307                 r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location);
1308                 if (unlikely(r != 0)) {
1309                         radeon_bo_unreserve(rbo);
1310                         return -EINVAL;
1311                 }
1312         }
1313         radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL);
1314         radeon_bo_unreserve(rbo);
1315
1316         switch (target_fb->bits_per_pixel) {
1317         case 8:
1318                 fb_format =
1319                     AVIVO_D1GRPH_CONTROL_DEPTH_8BPP |
1320                     AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
1321                 break;
1322         case 15:
1323                 fb_format =
1324                     AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1325                     AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
1326                 break;
1327         case 16:
1328                 fb_format =
1329                     AVIVO_D1GRPH_CONTROL_DEPTH_16BPP |
1330                     AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
1331 #ifdef __BIG_ENDIAN
1332                 fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
1333 #endif
1334                 break;
1335         case 24:
1336         case 32:
1337                 fb_format =
1338                     AVIVO_D1GRPH_CONTROL_DEPTH_32BPP |
1339                     AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
1340 #ifdef __BIG_ENDIAN
1341                 fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
1342 #endif
1343                 break;
1344         default:
1345                 DRM_ERROR("Unsupported screen depth %d\n",
1346                           target_fb->bits_per_pixel);
1347                 return -EINVAL;
1348         }
1349
1350         if (rdev->family >= CHIP_R600) {
1351                 if (tiling_flags & RADEON_TILING_MACRO)
1352                         fb_format |= R600_D1GRPH_ARRAY_MODE_2D_TILED_THIN1;
1353                 else if (tiling_flags & RADEON_TILING_MICRO)
1354                         fb_format |= R600_D1GRPH_ARRAY_MODE_1D_TILED_THIN1;
1355         } else {
1356                 if (tiling_flags & RADEON_TILING_MACRO)
1357                         fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE;
1358
1359                 if (tiling_flags & RADEON_TILING_MICRO)
1360                         fb_format |= AVIVO_D1GRPH_TILED;
1361         }
1362
1363         if (radeon_crtc->crtc_id == 0)
1364                 WREG32(AVIVO_D1VGA_CONTROL, 0);
1365         else
1366                 WREG32(AVIVO_D2VGA_CONTROL, 0);
1367
1368         if (rdev->family >= CHIP_RV770) {
1369                 if (radeon_crtc->crtc_id) {
1370                         WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1371                         WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1372                 } else {
1373                         WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1374                         WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH, upper_32_bits(fb_location));
1375                 }
1376         }
1377         WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
1378                (u32) fb_location);
1379         WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS +
1380                radeon_crtc->crtc_offset, (u32) fb_location);
1381         WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format);
1382         if (rdev->family >= CHIP_R600)
1383                 WREG32(R600_D1GRPH_SWAP_CONTROL + radeon_crtc->crtc_offset, fb_swap);
1384
1385         WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0);
1386         WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0);
1387         WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0);
1388         WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0);
1389         WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, target_fb->width);
1390         WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, target_fb->height);
1391
1392         fb_pitch_pixels = target_fb->pitches[0] / (target_fb->bits_per_pixel / 8);
1393         WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels);
1394         WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1);
1395
1396         WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset,
1397                target_fb->height);
1398         x &= ~3;
1399         y &= ~1;
1400         WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset,
1401                (x << 16) | y);
1402         viewport_w = crtc->mode.hdisplay;
1403         viewport_h = (crtc->mode.vdisplay + 1) & ~1;
1404         WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset,
1405                (viewport_w << 16) | viewport_h);
1406
1407         /* pageflip setup */
1408         /* make sure flip is at vb rather than hb */
1409         tmp = RREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
1410         tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN;
1411         WREG32(AVIVO_D1GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
1412
1413         /* set pageflip to happen anywhere in vblank interval */
1414         WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
1415
1416         if (!atomic && fb && fb != crtc->fb) {
1417                 radeon_fb = to_radeon_framebuffer(fb);
1418                 rbo = gem_to_radeon_bo(radeon_fb->obj);
1419                 r = radeon_bo_reserve(rbo, false);
1420                 if (unlikely(r != 0))
1421                         return r;
1422                 radeon_bo_unpin(rbo);
1423                 radeon_bo_unreserve(rbo);
1424         }
1425
1426         /* Bytes per pixel may have changed */
1427         radeon_bandwidth_update(rdev);
1428
1429         return 0;
1430 }
1431
1432 int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
1433                            struct drm_framebuffer *old_fb)
1434 {
1435         struct drm_device *dev = crtc->dev;
1436         struct radeon_device *rdev = dev->dev_private;
1437
1438         if (ASIC_IS_DCE4(rdev))
1439                 return dce4_crtc_do_set_base(crtc, old_fb, x, y, 0);
1440         else if (ASIC_IS_AVIVO(rdev))
1441                 return avivo_crtc_do_set_base(crtc, old_fb, x, y, 0);
1442         else
1443                 return radeon_crtc_do_set_base(crtc, old_fb, x, y, 0);
1444 }
1445
1446 int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
1447                                   struct drm_framebuffer *fb,
1448                                   int x, int y, enum mode_set_atomic state)
1449 {
1450        struct drm_device *dev = crtc->dev;
1451        struct radeon_device *rdev = dev->dev_private;
1452
1453         if (ASIC_IS_DCE4(rdev))
1454                 return dce4_crtc_do_set_base(crtc, fb, x, y, 1);
1455         else if (ASIC_IS_AVIVO(rdev))
1456                 return avivo_crtc_do_set_base(crtc, fb, x, y, 1);
1457         else
1458                 return radeon_crtc_do_set_base(crtc, fb, x, y, 1);
1459 }
1460
1461 /* properly set additional regs when using atombios */
1462 static void radeon_legacy_atom_fixup(struct drm_crtc *crtc)
1463 {
1464         struct drm_device *dev = crtc->dev;
1465         struct radeon_device *rdev = dev->dev_private;
1466         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1467         u32 disp_merge_cntl;
1468
1469         switch (radeon_crtc->crtc_id) {
1470         case 0:
1471                 disp_merge_cntl = RREG32(RADEON_DISP_MERGE_CNTL);
1472                 disp_merge_cntl &= ~RADEON_DISP_RGB_OFFSET_EN;
1473                 WREG32(RADEON_DISP_MERGE_CNTL, disp_merge_cntl);
1474                 break;
1475         case 1:
1476                 disp_merge_cntl = RREG32(RADEON_DISP2_MERGE_CNTL);
1477                 disp_merge_cntl &= ~RADEON_DISP2_RGB_OFFSET_EN;
1478                 WREG32(RADEON_DISP2_MERGE_CNTL, disp_merge_cntl);
1479                 WREG32(RADEON_FP_H2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_H_SYNC_STRT_WID));
1480                 WREG32(RADEON_FP_V2_SYNC_STRT_WID,   RREG32(RADEON_CRTC2_V_SYNC_STRT_WID));
1481                 break;
1482         }
1483 }
1484
1485 static int radeon_atom_pick_pll(struct drm_crtc *crtc)
1486 {
1487         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1488         struct drm_device *dev = crtc->dev;
1489         struct radeon_device *rdev = dev->dev_private;
1490         struct drm_encoder *test_encoder;
1491         struct drm_crtc *test_crtc;
1492         uint32_t pll_in_use = 0;
1493
1494         if (ASIC_IS_DCE61(rdev)) {
1495                 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1496                         if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1497                                 struct radeon_encoder *test_radeon_encoder =
1498                                         to_radeon_encoder(test_encoder);
1499                                 struct radeon_encoder_atom_dig *dig =
1500                                         test_radeon_encoder->enc_priv;
1501
1502                                 if ((test_radeon_encoder->encoder_id ==
1503                                      ENCODER_OBJECT_ID_INTERNAL_UNIPHY) &&
1504                                     (dig->linkb == false)) /* UNIPHY A uses PPLL2 */
1505                                         return ATOM_PPLL2;
1506                         }
1507                 }
1508                 /* UNIPHY B/C/D/E/F */
1509                 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1510                         struct radeon_crtc *radeon_test_crtc;
1511
1512                         if (crtc == test_crtc)
1513                                 continue;
1514
1515                         radeon_test_crtc = to_radeon_crtc(test_crtc);
1516                         if ((radeon_test_crtc->pll_id == ATOM_PPLL0) ||
1517                             (radeon_test_crtc->pll_id == ATOM_PPLL1))
1518                                 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1519                 }
1520                 if (!(pll_in_use & 4))
1521                         return ATOM_PPLL0;
1522                 return ATOM_PPLL1;
1523         } else if (ASIC_IS_DCE4(rdev)) {
1524                 list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
1525                         if (test_encoder->crtc && (test_encoder->crtc == crtc)) {
1526                                 /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock,
1527                                  * depending on the asic:
1528                                  * DCE4: PPLL or ext clock
1529                                  * DCE5: DCPLL or ext clock
1530                                  *
1531                                  * Setting ATOM_PPLL_INVALID will cause SetPixelClock to skip
1532                                  * PPLL/DCPLL programming and only program the DP DTO for the
1533                                  * crtc virtual pixel clock.
1534                                  */
1535                                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_encoder))) {
1536                                         if (rdev->clock.dp_extclk)
1537                                                 return ATOM_PPLL_INVALID;
1538                                         else if (ASIC_IS_DCE6(rdev))
1539                                                 return ATOM_PPLL0;
1540                                         else if (ASIC_IS_DCE5(rdev))
1541                                                 return ATOM_DCPLL;
1542                                 }
1543                         }
1544                 }
1545
1546                 /* otherwise, pick one of the plls */
1547                 list_for_each_entry(test_crtc, &dev->mode_config.crtc_list, head) {
1548                         struct radeon_crtc *radeon_test_crtc;
1549
1550                         if (crtc == test_crtc)
1551                                 continue;
1552
1553                         radeon_test_crtc = to_radeon_crtc(test_crtc);
1554                         if ((radeon_test_crtc->pll_id >= ATOM_PPLL1) &&
1555                             (radeon_test_crtc->pll_id <= ATOM_PPLL2))
1556                                 pll_in_use |= (1 << radeon_test_crtc->pll_id);
1557                 }
1558                 if (!(pll_in_use & 1))
1559                         return ATOM_PPLL1;
1560                 return ATOM_PPLL2;
1561         } else
1562                 return radeon_crtc->crtc_id;
1563
1564 }
1565
1566 void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev)
1567 {
1568         /* always set DCPLL */
1569         if (ASIC_IS_DCE6(rdev))
1570                 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
1571         else if (ASIC_IS_DCE4(rdev)) {
1572                 struct radeon_atom_ss ss;
1573                 bool ss_enabled = radeon_atombios_get_asic_ss_info(rdev, &ss,
1574                                                                    ASIC_INTERNAL_SS_ON_DCPLL,
1575                                                                    rdev->clock.default_dispclk);
1576                 if (ss_enabled)
1577                         atombios_crtc_program_ss(rdev, ATOM_DISABLE, ATOM_DCPLL, -1, &ss);
1578                 /* XXX: DCE5, make sure voltage, dispclk is high enough */
1579                 atombios_crtc_set_disp_eng_pll(rdev, rdev->clock.default_dispclk);
1580                 if (ss_enabled)
1581                         atombios_crtc_program_ss(rdev, ATOM_ENABLE, ATOM_DCPLL, -1, &ss);
1582         }
1583
1584 }
1585
1586 int atombios_crtc_mode_set(struct drm_crtc *crtc,
1587                            struct drm_display_mode *mode,
1588                            struct drm_display_mode *adjusted_mode,
1589                            int x, int y, struct drm_framebuffer *old_fb)
1590 {
1591         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1592         struct drm_device *dev = crtc->dev;
1593         struct radeon_device *rdev = dev->dev_private;
1594         struct drm_encoder *encoder;
1595         bool is_tvcv = false;
1596
1597         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1598                 /* find tv std */
1599                 if (encoder->crtc == crtc) {
1600                         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1601                         if (radeon_encoder->active_device &
1602                             (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
1603                                 is_tvcv = true;
1604                 }
1605         }
1606
1607         atombios_crtc_set_pll(crtc, adjusted_mode);
1608
1609         if (ASIC_IS_DCE4(rdev))
1610                 atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1611         else if (ASIC_IS_AVIVO(rdev)) {
1612                 if (is_tvcv)
1613                         atombios_crtc_set_timing(crtc, adjusted_mode);
1614                 else
1615                         atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1616         } else {
1617                 atombios_crtc_set_timing(crtc, adjusted_mode);
1618                 if (radeon_crtc->crtc_id == 0)
1619                         atombios_set_crtc_dtd_timing(crtc, adjusted_mode);
1620                 radeon_legacy_atom_fixup(crtc);
1621         }
1622         atombios_crtc_set_base(crtc, x, y, old_fb);
1623         atombios_overscan_setup(crtc, mode, adjusted_mode);
1624         atombios_scaler_setup(crtc);
1625         return 0;
1626 }
1627
1628 static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
1629                                      struct drm_display_mode *mode,
1630                                      struct drm_display_mode *adjusted_mode)
1631 {
1632         if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode))
1633                 return false;
1634         return true;
1635 }
1636
1637 static void atombios_crtc_prepare(struct drm_crtc *crtc)
1638 {
1639         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1640         struct drm_device *dev = crtc->dev;
1641         struct radeon_device *rdev = dev->dev_private;
1642
1643         radeon_crtc->in_mode_set = true;
1644         /* pick pll */
1645         radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
1646
1647         /* disable crtc pair power gating before programming */
1648         if (ASIC_IS_DCE6(rdev))
1649                 atombios_powergate_crtc(crtc, ATOM_DISABLE);
1650
1651         atombios_lock_crtc(crtc, ATOM_ENABLE);
1652         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1653 }
1654
1655 static void atombios_crtc_commit(struct drm_crtc *crtc)
1656 {
1657         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1658
1659         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
1660         atombios_lock_crtc(crtc, ATOM_DISABLE);
1661         radeon_crtc->in_mode_set = false;
1662 }
1663
1664 static void atombios_crtc_disable(struct drm_crtc *crtc)
1665 {
1666         struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1667         struct drm_device *dev = crtc->dev;
1668         struct radeon_device *rdev = dev->dev_private;
1669         struct radeon_atom_ss ss;
1670         int i;
1671
1672         atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
1673
1674         for (i = 0; i < rdev->num_crtc; i++) {
1675                 if (rdev->mode_info.crtcs[i] &&
1676                     rdev->mode_info.crtcs[i]->enabled &&
1677                     i != radeon_crtc->crtc_id &&
1678                     radeon_crtc->pll_id == rdev->mode_info.crtcs[i]->pll_id) {
1679                         /* one other crtc is using this pll don't turn
1680                          * off the pll
1681                          */
1682                         goto done;
1683                 }
1684         }
1685
1686         switch (radeon_crtc->pll_id) {
1687         case ATOM_PPLL1:
1688         case ATOM_PPLL2:
1689                 /* disable the ppll */
1690                 atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1691                                           0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
1692                 break;
1693         case ATOM_PPLL0:
1694                 /* disable the ppll */
1695                 if (ASIC_IS_DCE61(rdev))
1696                         atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
1697                                                   0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
1698                 break;
1699         default:
1700                 break;
1701         }
1702 done:
1703         radeon_crtc->pll_id = -1;
1704 }
1705
1706 static const struct drm_crtc_helper_funcs atombios_helper_funcs = {
1707         .dpms = atombios_crtc_dpms,
1708         .mode_fixup = atombios_crtc_mode_fixup,
1709         .mode_set = atombios_crtc_mode_set,
1710         .mode_set_base = atombios_crtc_set_base,
1711         .mode_set_base_atomic = atombios_crtc_set_base_atomic,
1712         .prepare = atombios_crtc_prepare,
1713         .commit = atombios_crtc_commit,
1714         .load_lut = radeon_crtc_load_lut,
1715         .disable = atombios_crtc_disable,
1716 };
1717
1718 void radeon_atombios_init_crtc(struct drm_device *dev,
1719                                struct radeon_crtc *radeon_crtc)
1720 {
1721         struct radeon_device *rdev = dev->dev_private;
1722
1723         if (ASIC_IS_DCE4(rdev)) {
1724                 switch (radeon_crtc->crtc_id) {
1725                 case 0:
1726                 default:
1727                         radeon_crtc->crtc_offset = EVERGREEN_CRTC0_REGISTER_OFFSET;
1728                         break;
1729                 case 1:
1730                         radeon_crtc->crtc_offset = EVERGREEN_CRTC1_REGISTER_OFFSET;
1731                         break;
1732                 case 2:
1733                         radeon_crtc->crtc_offset = EVERGREEN_CRTC2_REGISTER_OFFSET;
1734                         break;
1735                 case 3:
1736                         radeon_crtc->crtc_offset = EVERGREEN_CRTC3_REGISTER_OFFSET;
1737                         break;
1738                 case 4:
1739                         radeon_crtc->crtc_offset = EVERGREEN_CRTC4_REGISTER_OFFSET;
1740                         break;
1741                 case 5:
1742                         radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET;
1743                         break;
1744                 }
1745         } else {
1746                 if (radeon_crtc->crtc_id == 1)
1747                         radeon_crtc->crtc_offset =
1748                                 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL;
1749                 else
1750                         radeon_crtc->crtc_offset = 0;
1751         }
1752         radeon_crtc->pll_id = -1;
1753         drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs);
1754 }