Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/linville/wirel...
[linux-2.6.git] / drivers / gpu / drm / nouveau / nv40_graph.c
1 /*
2  * Copyright (C) 2007 Ben Skeggs.
3  * All Rights Reserved.
4  *
5  * Permission is hereby granted, free of charge, to any person obtaining
6  * a copy of this software and associated documentation files (the
7  * "Software"), to deal in the Software without restriction, including
8  * without limitation the rights to use, copy, modify, merge, publish,
9  * distribute, sublicense, and/or sell copies of the Software, and to
10  * permit persons to whom the Software is furnished to do so, subject to
11  * the following conditions:
12  *
13  * The above copyright notice and this permission notice (including the
14  * next paragraph) shall be included in all copies or substantial
15  * portions of the Software.
16  *
17  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
20  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
21  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
22  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24  *
25  */
26
27 #include "drmP.h"
28 #include "drm.h"
29 #include "nouveau_drv.h"
30 #include "nouveau_grctx.h"
31
32 static int nv40_graph_register(struct drm_device *);
33 static void nv40_graph_isr(struct drm_device *);
34
35 struct nouveau_channel *
36 nv40_graph_channel(struct drm_device *dev)
37 {
38         struct drm_nouveau_private *dev_priv = dev->dev_private;
39         uint32_t inst;
40         int i;
41
42         inst = nv_rd32(dev, NV40_PGRAPH_CTXCTL_CUR);
43         if (!(inst & NV40_PGRAPH_CTXCTL_CUR_LOADED))
44                 return NULL;
45         inst = (inst & NV40_PGRAPH_CTXCTL_CUR_INSTANCE) << 4;
46
47         for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
48                 struct nouveau_channel *chan = dev_priv->channels.ptr[i];
49
50                 if (chan && chan->ramin_grctx &&
51                     chan->ramin_grctx->pinst == inst)
52                         return chan;
53         }
54
55         return NULL;
56 }
57
58 int
59 nv40_graph_create_context(struct nouveau_channel *chan)
60 {
61         struct drm_device *dev = chan->dev;
62         struct drm_nouveau_private *dev_priv = dev->dev_private;
63         struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
64         struct nouveau_grctx ctx = {};
65         unsigned long flags;
66         int ret;
67
68         ret = nouveau_gpuobj_new(dev, chan, pgraph->grctx_size, 16,
69                                  NVOBJ_FLAG_ZERO_ALLOC, &chan->ramin_grctx);
70         if (ret)
71                 return ret;
72
73         /* Initialise default context values */
74         ctx.dev = chan->dev;
75         ctx.mode = NOUVEAU_GRCTX_VALS;
76         ctx.data = chan->ramin_grctx;
77         nv40_grctx_init(&ctx);
78
79         nv_wo32(chan->ramin_grctx, 0, chan->ramin_grctx->pinst);
80
81         /* init grctx pointer in ramfc, and on PFIFO if channel is
82          * already active there
83          */
84         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
85         nv_wo32(chan->ramfc, 0x38, chan->ramin_grctx->pinst >> 4);
86         nv_mask(dev, 0x002500, 0x00000001, 0x00000000);
87         if ((nv_rd32(dev, 0x003204) & 0x0000001f) == chan->id)
88                 nv_wr32(dev, 0x0032e0, chan->ramin_grctx->pinst >> 4);
89         nv_mask(dev, 0x002500, 0x00000001, 0x00000001);
90         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
91         return 0;
92 }
93
94 void
95 nv40_graph_destroy_context(struct nouveau_channel *chan)
96 {
97         struct drm_device *dev = chan->dev;
98         struct drm_nouveau_private *dev_priv = dev->dev_private;
99         struct nouveau_pgraph_engine *pgraph = &dev_priv->engine.graph;
100         unsigned long flags;
101
102         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
103         pgraph->fifo_access(dev, false);
104
105         /* Unload the context if it's the currently active one */
106         if (pgraph->channel(dev) == chan)
107                 pgraph->unload_context(dev);
108
109         pgraph->fifo_access(dev, true);
110         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
111
112         /* Free the context resources */
113         nouveau_gpuobj_ref(NULL, &chan->ramin_grctx);
114 }
115
116 static int
117 nv40_graph_transfer_context(struct drm_device *dev, uint32_t inst, int save)
118 {
119         uint32_t old_cp, tv = 1000, tmp;
120         int i;
121
122         old_cp = nv_rd32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER);
123         nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
124
125         tmp  = nv_rd32(dev, NV40_PGRAPH_CTXCTL_0310);
126         tmp |= save ? NV40_PGRAPH_CTXCTL_0310_XFER_SAVE :
127                       NV40_PGRAPH_CTXCTL_0310_XFER_LOAD;
128         nv_wr32(dev, NV40_PGRAPH_CTXCTL_0310, tmp);
129
130         tmp  = nv_rd32(dev, NV40_PGRAPH_CTXCTL_0304);
131         tmp |= NV40_PGRAPH_CTXCTL_0304_XFER_CTX;
132         nv_wr32(dev, NV40_PGRAPH_CTXCTL_0304, tmp);
133
134         nouveau_wait_for_idle(dev);
135
136         for (i = 0; i < tv; i++) {
137                 if (nv_rd32(dev, NV40_PGRAPH_CTXCTL_030C) == 0)
138                         break;
139         }
140
141         nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, old_cp);
142
143         if (i == tv) {
144                 uint32_t ucstat = nv_rd32(dev, NV40_PGRAPH_CTXCTL_UCODE_STAT);
145                 NV_ERROR(dev, "Failed: Instance=0x%08x Save=%d\n", inst, save);
146                 NV_ERROR(dev, "IP: 0x%02x, Opcode: 0x%08x\n",
147                          ucstat >> NV40_PGRAPH_CTXCTL_UCODE_STAT_IP_SHIFT,
148                          ucstat  & NV40_PGRAPH_CTXCTL_UCODE_STAT_OP_MASK);
149                 NV_ERROR(dev, "0x40030C = 0x%08x\n",
150                          nv_rd32(dev, NV40_PGRAPH_CTXCTL_030C));
151                 return -EBUSY;
152         }
153
154         return 0;
155 }
156
157 /* Restore the context for a specific channel into PGRAPH */
158 int
159 nv40_graph_load_context(struct nouveau_channel *chan)
160 {
161         struct drm_device *dev = chan->dev;
162         uint32_t inst;
163         int ret;
164
165         if (!chan->ramin_grctx)
166                 return -EINVAL;
167         inst = chan->ramin_grctx->pinst >> 4;
168
169         ret = nv40_graph_transfer_context(dev, inst, 0);
170         if (ret)
171                 return ret;
172
173         /* 0x40032C, no idea of it's exact function.  Could simply be a
174          * record of the currently active PGRAPH context.  It's currently
175          * unknown as to what bit 24 does.  The nv ddx has it set, so we will
176          * set it here too.
177          */
178         nv_wr32(dev, NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
179         nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR,
180                  (inst & NV40_PGRAPH_CTXCTL_CUR_INSTANCE) |
181                   NV40_PGRAPH_CTXCTL_CUR_LOADED);
182         /* 0x32E0 records the instance address of the active FIFO's PGRAPH
183          * context.  If at any time this doesn't match 0x40032C, you will
184          * recieve PGRAPH_INTR_CONTEXT_SWITCH
185          */
186         nv_wr32(dev, NV40_PFIFO_GRCTX_INSTANCE, inst);
187         return 0;
188 }
189
190 int
191 nv40_graph_unload_context(struct drm_device *dev)
192 {
193         uint32_t inst;
194         int ret;
195
196         inst = nv_rd32(dev, NV40_PGRAPH_CTXCTL_CUR);
197         if (!(inst & NV40_PGRAPH_CTXCTL_CUR_LOADED))
198                 return 0;
199         inst &= NV40_PGRAPH_CTXCTL_CUR_INSTANCE;
200
201         ret = nv40_graph_transfer_context(dev, inst, 1);
202
203         nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, inst);
204         return ret;
205 }
206
207 void
208 nv40_graph_set_tile_region(struct drm_device *dev, int i)
209 {
210         struct drm_nouveau_private *dev_priv = dev->dev_private;
211         struct nouveau_tile_reg *tile = &dev_priv->tile.reg[i];
212
213         switch (dev_priv->chipset) {
214         case 0x40:
215         case 0x41: /* guess */
216         case 0x42:
217         case 0x43:
218         case 0x45: /* guess */
219         case 0x4e:
220                 nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);
221                 nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit);
222                 nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr);
223                 nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tile->pitch);
224                 nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit);
225                 nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr);
226                 break;
227         case 0x44:
228         case 0x4a:
229                 nv_wr32(dev, NV20_PGRAPH_TSIZE(i), tile->pitch);
230                 nv_wr32(dev, NV20_PGRAPH_TLIMIT(i), tile->limit);
231                 nv_wr32(dev, NV20_PGRAPH_TILE(i), tile->addr);
232                 break;
233         case 0x46:
234         case 0x47:
235         case 0x49:
236         case 0x4b:
237         case 0x4c:
238         case 0x67:
239         default:
240                 nv_wr32(dev, NV47_PGRAPH_TSIZE(i), tile->pitch);
241                 nv_wr32(dev, NV47_PGRAPH_TLIMIT(i), tile->limit);
242                 nv_wr32(dev, NV47_PGRAPH_TILE(i), tile->addr);
243                 nv_wr32(dev, NV40_PGRAPH_TSIZE1(i), tile->pitch);
244                 nv_wr32(dev, NV40_PGRAPH_TLIMIT1(i), tile->limit);
245                 nv_wr32(dev, NV40_PGRAPH_TILE1(i), tile->addr);
246                 break;
247         }
248 }
249
250 /*
251  * G70          0x47
252  * G71          0x49
253  * NV45         0x48
254  * G72[M]       0x46
255  * G73          0x4b
256  * C51_G7X      0x4c
257  * C51          0x4e
258  */
259 int
260 nv40_graph_init(struct drm_device *dev)
261 {
262         struct drm_nouveau_private *dev_priv =
263                 (struct drm_nouveau_private *)dev->dev_private;
264         struct nouveau_fb_engine *pfb = &dev_priv->engine.fb;
265         struct nouveau_grctx ctx = {};
266         uint32_t vramsz, *cp;
267         int ret, i, j;
268
269         nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) &
270                         ~NV_PMC_ENABLE_PGRAPH);
271         nv_wr32(dev, NV03_PMC_ENABLE, nv_rd32(dev, NV03_PMC_ENABLE) |
272                          NV_PMC_ENABLE_PGRAPH);
273
274         cp = kmalloc(sizeof(*cp) * 256, GFP_KERNEL);
275         if (!cp)
276                 return -ENOMEM;
277
278         ctx.dev = dev;
279         ctx.mode = NOUVEAU_GRCTX_PROG;
280         ctx.data = cp;
281         ctx.ctxprog_max = 256;
282         nv40_grctx_init(&ctx);
283         dev_priv->engine.graph.grctx_size = ctx.ctxvals_pos * 4;
284
285         nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
286         for (i = 0; i < ctx.ctxprog_len; i++)
287                 nv_wr32(dev, NV40_PGRAPH_CTXCTL_UCODE_DATA, cp[i]);
288
289         kfree(cp);
290
291         ret = nv40_graph_register(dev);
292         if (ret)
293                 return ret;
294
295         /* No context present currently */
296         nv_wr32(dev, NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
297
298         nouveau_irq_register(dev, 12, nv40_graph_isr);
299         nv_wr32(dev, NV03_PGRAPH_INTR   , 0xFFFFFFFF);
300         nv_wr32(dev, NV40_PGRAPH_INTR_EN, 0xFFFFFFFF);
301
302         nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0xFFFFFFFF);
303         nv_wr32(dev, NV04_PGRAPH_DEBUG_0, 0x00000000);
304         nv_wr32(dev, NV04_PGRAPH_DEBUG_1, 0x401287c0);
305         nv_wr32(dev, NV04_PGRAPH_DEBUG_3, 0xe0de8055);
306         nv_wr32(dev, NV10_PGRAPH_DEBUG_4, 0x00008000);
307         nv_wr32(dev, NV04_PGRAPH_LIMIT_VIOL_PIX, 0x00be3c5f);
308
309         nv_wr32(dev, NV10_PGRAPH_CTX_CONTROL, 0x10010100);
310         nv_wr32(dev, NV10_PGRAPH_STATE      , 0xFFFFFFFF);
311
312         j = nv_rd32(dev, 0x1540) & 0xff;
313         if (j) {
314                 for (i = 0; !(j & 1); j >>= 1, i++)
315                         ;
316                 nv_wr32(dev, 0x405000, i);
317         }
318
319         if (dev_priv->chipset == 0x40) {
320                 nv_wr32(dev, 0x4009b0, 0x83280fff);
321                 nv_wr32(dev, 0x4009b4, 0x000000a0);
322         } else {
323                 nv_wr32(dev, 0x400820, 0x83280eff);
324                 nv_wr32(dev, 0x400824, 0x000000a0);
325         }
326
327         switch (dev_priv->chipset) {
328         case 0x40:
329         case 0x45:
330                 nv_wr32(dev, 0x4009b8, 0x0078e366);
331                 nv_wr32(dev, 0x4009bc, 0x0000014c);
332                 break;
333         case 0x41:
334         case 0x42: /* pciid also 0x00Cx */
335         /* case 0x0120: XXX (pciid) */
336                 nv_wr32(dev, 0x400828, 0x007596ff);
337                 nv_wr32(dev, 0x40082c, 0x00000108);
338                 break;
339         case 0x43:
340                 nv_wr32(dev, 0x400828, 0x0072cb77);
341                 nv_wr32(dev, 0x40082c, 0x00000108);
342                 break;
343         case 0x44:
344         case 0x46: /* G72 */
345         case 0x4a:
346         case 0x4c: /* G7x-based C51 */
347         case 0x4e:
348                 nv_wr32(dev, 0x400860, 0);
349                 nv_wr32(dev, 0x400864, 0);
350                 break;
351         case 0x47: /* G70 */
352         case 0x49: /* G71 */
353         case 0x4b: /* G73 */
354                 nv_wr32(dev, 0x400828, 0x07830610);
355                 nv_wr32(dev, 0x40082c, 0x0000016A);
356                 break;
357         default:
358                 break;
359         }
360
361         nv_wr32(dev, 0x400b38, 0x2ffff800);
362         nv_wr32(dev, 0x400b3c, 0x00006000);
363
364         /* Tiling related stuff. */
365         switch (dev_priv->chipset) {
366         case 0x44:
367         case 0x4a:
368                 nv_wr32(dev, 0x400bc4, 0x1003d888);
369                 nv_wr32(dev, 0x400bbc, 0xb7a7b500);
370                 break;
371         case 0x46:
372                 nv_wr32(dev, 0x400bc4, 0x0000e024);
373                 nv_wr32(dev, 0x400bbc, 0xb7a7b520);
374                 break;
375         case 0x4c:
376         case 0x4e:
377         case 0x67:
378                 nv_wr32(dev, 0x400bc4, 0x1003d888);
379                 nv_wr32(dev, 0x400bbc, 0xb7a7b540);
380                 break;
381         default:
382                 break;
383         }
384
385         /* Turn all the tiling regions off. */
386         for (i = 0; i < pfb->num_tiles; i++)
387                 nv40_graph_set_tile_region(dev, i);
388
389         /* begin RAM config */
390         vramsz = pci_resource_len(dev->pdev, 0) - 1;
391         switch (dev_priv->chipset) {
392         case 0x40:
393                 nv_wr32(dev, 0x4009A4, nv_rd32(dev, NV04_PFB_CFG0));
394                 nv_wr32(dev, 0x4009A8, nv_rd32(dev, NV04_PFB_CFG1));
395                 nv_wr32(dev, 0x4069A4, nv_rd32(dev, NV04_PFB_CFG0));
396                 nv_wr32(dev, 0x4069A8, nv_rd32(dev, NV04_PFB_CFG1));
397                 nv_wr32(dev, 0x400820, 0);
398                 nv_wr32(dev, 0x400824, 0);
399                 nv_wr32(dev, 0x400864, vramsz);
400                 nv_wr32(dev, 0x400868, vramsz);
401                 break;
402         default:
403                 switch (dev_priv->chipset) {
404                 case 0x41:
405                 case 0x42:
406                 case 0x43:
407                 case 0x45:
408                 case 0x4e:
409                 case 0x44:
410                 case 0x4a:
411                         nv_wr32(dev, 0x4009F0, nv_rd32(dev, NV04_PFB_CFG0));
412                         nv_wr32(dev, 0x4009F4, nv_rd32(dev, NV04_PFB_CFG1));
413                         break;
414                 default:
415                         nv_wr32(dev, 0x400DF0, nv_rd32(dev, NV04_PFB_CFG0));
416                         nv_wr32(dev, 0x400DF4, nv_rd32(dev, NV04_PFB_CFG1));
417                         break;
418                 }
419                 nv_wr32(dev, 0x4069F0, nv_rd32(dev, NV04_PFB_CFG0));
420                 nv_wr32(dev, 0x4069F4, nv_rd32(dev, NV04_PFB_CFG1));
421                 nv_wr32(dev, 0x400840, 0);
422                 nv_wr32(dev, 0x400844, 0);
423                 nv_wr32(dev, 0x4008A0, vramsz);
424                 nv_wr32(dev, 0x4008A4, vramsz);
425                 break;
426         }
427
428         return 0;
429 }
430
431 void nv40_graph_takedown(struct drm_device *dev)
432 {
433         nouveau_irq_unregister(dev, 12);
434 }
435
436 static int
437 nv40_graph_register(struct drm_device *dev)
438 {
439         struct drm_nouveau_private *dev_priv = dev->dev_private;
440
441         if (dev_priv->engine.graph.registered)
442                 return 0;
443
444         NVOBJ_CLASS(dev, 0x506e, SW); /* nvsw */
445         NVOBJ_CLASS(dev, 0x0030, GR); /* null */
446         NVOBJ_CLASS(dev, 0x0039, GR); /* m2mf */
447         NVOBJ_CLASS(dev, 0x004a, GR); /* gdirect */
448         NVOBJ_CLASS(dev, 0x009f, GR); /* imageblit (nv12) */
449         NVOBJ_CLASS(dev, 0x008a, GR); /* ifc */
450         NVOBJ_CLASS(dev, 0x0089, GR); /* sifm */
451         NVOBJ_CLASS(dev, 0x3089, GR); /* sifm (nv40) */
452         NVOBJ_CLASS(dev, 0x0062, GR); /* surf2d */
453         NVOBJ_CLASS(dev, 0x3062, GR); /* surf2d (nv40) */
454         NVOBJ_CLASS(dev, 0x0043, GR); /* rop */
455         NVOBJ_CLASS(dev, 0x0012, GR); /* beta1 */
456         NVOBJ_CLASS(dev, 0x0072, GR); /* beta4 */
457         NVOBJ_CLASS(dev, 0x0019, GR); /* cliprect */
458         NVOBJ_CLASS(dev, 0x0044, GR); /* pattern */
459         NVOBJ_CLASS(dev, 0x309e, GR); /* swzsurf */
460
461         /* curie */
462         if (nv44_graph_class(dev))
463                 NVOBJ_CLASS(dev, 0x4497, GR);
464         else
465                 NVOBJ_CLASS(dev, 0x4097, GR);
466
467         /* nvsw */
468         NVOBJ_CLASS(dev, 0x506e, SW);
469         NVOBJ_MTHD (dev, 0x506e, 0x0500, nv04_graph_mthd_page_flip);
470
471         dev_priv->engine.graph.registered = true;
472         return 0;
473 }
474
475 static int
476 nv40_graph_isr_chid(struct drm_device *dev, u32 inst)
477 {
478         struct drm_nouveau_private *dev_priv = dev->dev_private;
479         struct nouveau_channel *chan;
480         unsigned long flags;
481         int i;
482
483         spin_lock_irqsave(&dev_priv->channels.lock, flags);
484         for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
485                 chan = dev_priv->channels.ptr[i];
486                 if (!chan || !chan->ramin_grctx)
487                         continue;
488
489                 if (inst == chan->ramin_grctx->pinst)
490                         break;
491         }
492         spin_unlock_irqrestore(&dev_priv->channels.lock, flags);
493         return i;
494 }
495
496 static void
497 nv40_graph_isr(struct drm_device *dev)
498 {
499         u32 stat;
500
501         while ((stat = nv_rd32(dev, NV03_PGRAPH_INTR))) {
502                 u32 nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
503                 u32 nstatus = nv_rd32(dev, NV03_PGRAPH_NSTATUS);
504                 u32 inst = (nv_rd32(dev, 0x40032c) & 0x000fffff) << 4;
505                 u32 chid = nv40_graph_isr_chid(dev, inst);
506                 u32 addr = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
507                 u32 subc = (addr & 0x00070000) >> 16;
508                 u32 mthd = (addr & 0x00001ffc);
509                 u32 data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
510                 u32 class = nv_rd32(dev, 0x400160 + subc * 4) & 0xffff;
511                 u32 show = stat;
512
513                 if (stat & NV_PGRAPH_INTR_ERROR) {
514                         if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
515                                 if (!nouveau_gpuobj_mthd_call2(dev, chid, class, mthd, data))
516                                         show &= ~NV_PGRAPH_INTR_ERROR;
517                         } else
518                         if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) {
519                                 nv_mask(dev, 0x402000, 0, 0);
520                         }
521                 }
522
523                 nv_wr32(dev, NV03_PGRAPH_INTR, stat);
524                 nv_wr32(dev, NV04_PGRAPH_FIFO, 0x00000001);
525
526                 if (show && nouveau_ratelimit()) {
527                         NV_INFO(dev, "PGRAPH -");
528                         nouveau_bitfield_print(nv10_graph_intr, show);
529                         printk(" nsource:");
530                         nouveau_bitfield_print(nv04_graph_nsource, nsource);
531                         printk(" nstatus:");
532                         nouveau_bitfield_print(nv10_graph_nstatus, nstatus);
533                         printk("\n");
534                         NV_INFO(dev, "PGRAPH - ch %d (0x%08x) subc %d "
535                                      "class 0x%04x mthd 0x%04x data 0x%08x\n",
536                                 chid, inst, subc, class, mthd, data);
537                 }
538         }
539 }