Merge branch 'x86-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
[linux-2.6.git] / drivers / gpu / drm / nouveau / nouveau_dp.c
1 /*
2  * Copyright 2009 Red Hat Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  * Authors: Ben Skeggs
23  */
24
25 #include "drmP.h"
26 #include "nouveau_drv.h"
27 #include "nouveau_i2c.h"
28 #include "nouveau_encoder.h"
29
30 static int
31 auxch_rd(struct drm_encoder *encoder, int address, uint8_t *buf, int size)
32 {
33         struct drm_device *dev = encoder->dev;
34         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
35         struct nouveau_i2c_chan *auxch;
36         int ret;
37
38         auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
39         if (!auxch)
40                 return -ENODEV;
41
42         ret = nouveau_dp_auxch(auxch, 9, address, buf, size);
43         if (ret)
44                 return ret;
45
46         return 0;
47 }
48
49 static int
50 auxch_wr(struct drm_encoder *encoder, int address, uint8_t *buf, int size)
51 {
52         struct drm_device *dev = encoder->dev;
53         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
54         struct nouveau_i2c_chan *auxch;
55         int ret;
56
57         auxch = nouveau_i2c_find(dev, nv_encoder->dcb->i2c_index);
58         if (!auxch)
59                 return -ENODEV;
60
61         ret = nouveau_dp_auxch(auxch, 8, address, buf, size);
62         return ret;
63 }
64
65 static int
66 nouveau_dp_lane_count_set(struct drm_encoder *encoder, uint8_t cmd)
67 {
68         struct drm_device *dev = encoder->dev;
69         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
70         uint32_t tmp;
71         int or = nv_encoder->or, link = !(nv_encoder->dcb->sorconf.link & 1);
72
73         tmp  = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
74         tmp &= ~(NV50_SOR_DP_CTRL_ENHANCED_FRAME_ENABLED |
75                  NV50_SOR_DP_CTRL_LANE_MASK);
76         tmp |= ((1 << (cmd & DP_LANE_COUNT_MASK)) - 1) << 16;
77         if (cmd & DP_LANE_COUNT_ENHANCED_FRAME_EN)
78                 tmp |= NV50_SOR_DP_CTRL_ENHANCED_FRAME_ENABLED;
79         nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
80
81         return auxch_wr(encoder, DP_LANE_COUNT_SET, &cmd, 1);
82 }
83
84 static int
85 nouveau_dp_link_bw_set(struct drm_encoder *encoder, uint8_t cmd)
86 {
87         struct drm_device *dev = encoder->dev;
88         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
89         uint32_t tmp;
90         int reg = 0x614300 + (nv_encoder->or * 0x800);
91
92         tmp  = nv_rd32(dev, reg);
93         tmp &= 0xfff3ffff;
94         if (cmd == DP_LINK_BW_2_7)
95                 tmp |= 0x00040000;
96         nv_wr32(dev, reg, tmp);
97
98         return auxch_wr(encoder, DP_LINK_BW_SET, &cmd, 1);
99 }
100
101 static int
102 nouveau_dp_link_train_set(struct drm_encoder *encoder, int pattern)
103 {
104         struct drm_device *dev = encoder->dev;
105         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
106         uint32_t tmp;
107         uint8_t cmd;
108         int or = nv_encoder->or, link = !(nv_encoder->dcb->sorconf.link & 1);
109         int ret;
110
111         tmp  = nv_rd32(dev, NV50_SOR_DP_CTRL(or, link));
112         tmp &= ~NV50_SOR_DP_CTRL_TRAINING_PATTERN;
113         tmp |= (pattern << 24);
114         nv_wr32(dev, NV50_SOR_DP_CTRL(or, link), tmp);
115
116         ret = auxch_rd(encoder, DP_TRAINING_PATTERN_SET, &cmd, 1);
117         if (ret)
118                 return ret;
119         cmd &= ~DP_TRAINING_PATTERN_MASK;
120         cmd |= (pattern & DP_TRAINING_PATTERN_MASK);
121         return auxch_wr(encoder, DP_TRAINING_PATTERN_SET, &cmd, 1);
122 }
123
124 static int
125 nouveau_dp_max_voltage_swing(struct drm_encoder *encoder)
126 {
127         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
128         struct drm_device *dev = encoder->dev;
129         struct bit_displayport_encoder_table_entry *dpse;
130         struct bit_displayport_encoder_table *dpe;
131         int i, dpe_headerlen, max_vs = 0;
132
133         dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
134         if (!dpe)
135                 return false;
136         dpse = (void *)((char *)dpe + dpe_headerlen);
137
138         for (i = 0; i < dpe_headerlen; i++, dpse++) {
139                 if (dpse->vs_level > max_vs)
140                         max_vs = dpse->vs_level;
141         }
142
143         return max_vs;
144 }
145
146 static int
147 nouveau_dp_max_pre_emphasis(struct drm_encoder *encoder, int vs)
148 {
149         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
150         struct drm_device *dev = encoder->dev;
151         struct bit_displayport_encoder_table_entry *dpse;
152         struct bit_displayport_encoder_table *dpe;
153         int i, dpe_headerlen, max_pre = 0;
154
155         dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
156         if (!dpe)
157                 return false;
158         dpse = (void *)((char *)dpe + dpe_headerlen);
159
160         for (i = 0; i < dpe_headerlen; i++, dpse++) {
161                 if (dpse->vs_level != vs)
162                         continue;
163
164                 if (dpse->pre_level > max_pre)
165                         max_pre = dpse->pre_level;
166         }
167
168         return max_pre;
169 }
170
171 static bool
172 nouveau_dp_link_train_adjust(struct drm_encoder *encoder, uint8_t *config)
173 {
174         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
175         struct drm_device *dev = encoder->dev;
176         struct bit_displayport_encoder_table_entry *dpse;
177         struct bit_displayport_encoder_table *dpe;
178         int ret, i, dpe_headerlen, vs = 0, pre = 0;
179         uint8_t request[2];
180
181         dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
182         if (!dpe)
183                 return false;
184         dpse = (void *)((char *)dpe + dpe_headerlen);
185
186         ret = auxch_rd(encoder, DP_ADJUST_REQUEST_LANE0_1, request, 2);
187         if (ret)
188                 return false;
189
190         NV_DEBUG(dev, "\t\tadjust 0x%02x 0x%02x\n", request[0], request[1]);
191
192         /* Keep all lanes at the same level.. */
193         for (i = 0; i < nv_encoder->dp.link_nr; i++) {
194                 int lane_req = (request[i >> 1] >> ((i & 1) << 2)) & 0xf;
195                 int lane_vs = lane_req & 3;
196                 int lane_pre = (lane_req >> 2) & 3;
197
198                 if (lane_vs > vs)
199                         vs = lane_vs;
200                 if (lane_pre > pre)
201                         pre = lane_pre;
202         }
203
204         if (vs >= nouveau_dp_max_voltage_swing(encoder)) {
205                 vs  = nouveau_dp_max_voltage_swing(encoder);
206                 vs |= 4;
207         }
208
209         if (pre >= nouveau_dp_max_pre_emphasis(encoder, vs & 3)) {
210                 pre  = nouveau_dp_max_pre_emphasis(encoder, vs & 3);
211                 pre |= 4;
212         }
213
214         /* Update the configuration for all lanes.. */
215         for (i = 0; i < nv_encoder->dp.link_nr; i++)
216                 config[i] = (pre << 3) | vs;
217
218         return true;
219 }
220
221 static bool
222 nouveau_dp_link_train_commit(struct drm_encoder *encoder, uint8_t *config)
223 {
224         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
225         struct drm_device *dev = encoder->dev;
226         struct bit_displayport_encoder_table_entry *dpse;
227         struct bit_displayport_encoder_table *dpe;
228         int or = nv_encoder->or, link = !(nv_encoder->dcb->sorconf.link & 1);
229         int dpe_headerlen, ret, i;
230
231         NV_DEBUG(dev, "\t\tconfig 0x%02x 0x%02x 0x%02x 0x%02x\n",
232                  config[0], config[1], config[2], config[3]);
233
234         dpe = nouveau_bios_dp_table(dev, nv_encoder->dcb, &dpe_headerlen);
235         if (!dpe)
236                 return false;
237         dpse = (void *)((char *)dpe + dpe_headerlen);
238
239         for (i = 0; i < dpe->record_nr; i++, dpse++) {
240                 if (dpse->vs_level == (config[0] & 3) &&
241                     dpse->pre_level == ((config[0] >> 3) & 3))
242                         break;
243         }
244         BUG_ON(i == dpe->record_nr);
245
246         for (i = 0; i < nv_encoder->dp.link_nr; i++) {
247                 const int shift[4] = { 16, 8, 0, 24 };
248                 uint32_t mask = 0xff << shift[i];
249                 uint32_t reg0, reg1, reg2;
250
251                 reg0  = nv_rd32(dev, NV50_SOR_DP_UNK118(or, link)) & ~mask;
252                 reg0 |= (dpse->reg0 << shift[i]);
253                 reg1  = nv_rd32(dev, NV50_SOR_DP_UNK120(or, link)) & ~mask;
254                 reg1 |= (dpse->reg1 << shift[i]);
255                 reg2  = nv_rd32(dev, NV50_SOR_DP_UNK130(or, link)) & 0xffff00ff;
256                 reg2 |= (dpse->reg2 << 8);
257                 nv_wr32(dev, NV50_SOR_DP_UNK118(or, link), reg0);
258                 nv_wr32(dev, NV50_SOR_DP_UNK120(or, link), reg1);
259                 nv_wr32(dev, NV50_SOR_DP_UNK130(or, link), reg2);
260         }
261
262         ret = auxch_wr(encoder, DP_TRAINING_LANE0_SET, config, 4);
263         if (ret)
264                 return false;
265
266         return true;
267 }
268
269 bool
270 nouveau_dp_link_train(struct drm_encoder *encoder)
271 {
272         struct drm_device *dev = encoder->dev;
273         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
274         uint8_t config[4];
275         uint8_t status[3];
276         bool cr_done, cr_max_vs, eq_done;
277         int ret = 0, i, tries, voltage;
278
279         NV_DEBUG(dev, "link training!!\n");
280 train:
281         cr_done = eq_done = false;
282
283         /* set link configuration */
284         NV_DEBUG(dev, "\tbegin train: bw %d, lanes %d\n",
285                  nv_encoder->dp.link_bw, nv_encoder->dp.link_nr);
286
287         ret = nouveau_dp_link_bw_set(encoder, nv_encoder->dp.link_bw);
288         if (ret)
289                 return false;
290
291         config[0] = nv_encoder->dp.link_nr;
292         if (nv_encoder->dp.dpcd_version >= 0x11)
293                 config[0] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
294
295         ret = nouveau_dp_lane_count_set(encoder, config[0]);
296         if (ret)
297                 return false;
298
299         /* clock recovery */
300         NV_DEBUG(dev, "\tbegin cr\n");
301         ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_1);
302         if (ret)
303                 goto stop;
304
305         tries = 0;
306         voltage = -1;
307         memset(config, 0x00, sizeof(config));
308         for (;;) {
309                 if (!nouveau_dp_link_train_commit(encoder, config))
310                         break;
311
312                 udelay(100);
313
314                 ret = auxch_rd(encoder, DP_LANE0_1_STATUS, status, 2);
315                 if (ret)
316                         break;
317                 NV_DEBUG(dev, "\t\tstatus: 0x%02x 0x%02x\n",
318                          status[0], status[1]);
319
320                 cr_done = true;
321                 cr_max_vs = false;
322                 for (i = 0; i < nv_encoder->dp.link_nr; i++) {
323                         int lane = (status[i >> 1] >> ((i & 1) * 4)) & 0xf;
324
325                         if (!(lane & DP_LANE_CR_DONE)) {
326                                 cr_done = false;
327                                 if (config[i] & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED)
328                                         cr_max_vs = true;
329                                 break;
330                         }
331                 }
332
333                 if ((config[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) {
334                         voltage = config[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
335                         tries = 0;
336                 }
337
338                 if (cr_done || cr_max_vs || (++tries == 5))
339                         break;
340
341                 if (!nouveau_dp_link_train_adjust(encoder, config))
342                         break;
343         }
344
345         if (!cr_done)
346                 goto stop;
347
348         /* channel equalisation */
349         NV_DEBUG(dev, "\tbegin eq\n");
350         ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_2);
351         if (ret)
352                 goto stop;
353
354         for (tries = 0; tries <= 5; tries++) {
355                 udelay(400);
356
357                 ret = auxch_rd(encoder, DP_LANE0_1_STATUS, status, 3);
358                 if (ret)
359                         break;
360                 NV_DEBUG(dev, "\t\tstatus: 0x%02x 0x%02x\n",
361                          status[0], status[1]);
362
363                 eq_done = true;
364                 if (!(status[2] & DP_INTERLANE_ALIGN_DONE))
365                         eq_done = false;
366
367                 for (i = 0; eq_done && i < nv_encoder->dp.link_nr; i++) {
368                         int lane = (status[i >> 1] >> ((i & 1) * 4)) & 0xf;
369
370                         if (!(lane & DP_LANE_CR_DONE)) {
371                                 cr_done = false;
372                                 break;
373                         }
374
375                         if (!(lane & DP_LANE_CHANNEL_EQ_DONE) ||
376                             !(lane & DP_LANE_SYMBOL_LOCKED)) {
377                                 eq_done = false;
378                                 break;
379                         }
380                 }
381
382                 if (eq_done || !cr_done)
383                         break;
384
385                 if (!nouveau_dp_link_train_adjust(encoder, config) ||
386                     !nouveau_dp_link_train_commit(encoder, config))
387                         break;
388         }
389
390 stop:
391         /* end link training */
392         ret = nouveau_dp_link_train_set(encoder, DP_TRAINING_PATTERN_DISABLE);
393         if (ret)
394                 return false;
395
396         /* retry at a lower setting, if possible */
397         if (!ret && !(eq_done && cr_done)) {
398                 NV_DEBUG(dev, "\twe failed\n");
399                 if (nv_encoder->dp.link_bw != DP_LINK_BW_1_62) {
400                         NV_DEBUG(dev, "retry link training at low rate\n");
401                         nv_encoder->dp.link_bw = DP_LINK_BW_1_62;
402                         goto train;
403                 }
404         }
405
406         return eq_done;
407 }
408
409 bool
410 nouveau_dp_detect(struct drm_encoder *encoder)
411 {
412         struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
413         struct drm_device *dev = encoder->dev;
414         uint8_t dpcd[4];
415         int ret;
416
417         ret = auxch_rd(encoder, 0x0000, dpcd, 4);
418         if (ret)
419                 return false;
420
421         NV_DEBUG(dev, "encoder: link_bw %d, link_nr %d\n"
422                       "display: link_bw %d, link_nr %d version 0x%02x\n",
423                  nv_encoder->dcb->dpconf.link_bw,
424                  nv_encoder->dcb->dpconf.link_nr,
425                  dpcd[1], dpcd[2] & 0x0f, dpcd[0]);
426
427         nv_encoder->dp.dpcd_version = dpcd[0];
428
429         nv_encoder->dp.link_bw = dpcd[1];
430         if (nv_encoder->dp.link_bw != DP_LINK_BW_1_62 &&
431             !nv_encoder->dcb->dpconf.link_bw)
432                 nv_encoder->dp.link_bw = DP_LINK_BW_1_62;
433
434         nv_encoder->dp.link_nr = dpcd[2] & 0xf;
435         if (nv_encoder->dp.link_nr > nv_encoder->dcb->dpconf.link_nr)
436                 nv_encoder->dp.link_nr = nv_encoder->dcb->dpconf.link_nr;
437
438         return true;
439 }
440
441 int
442 nouveau_dp_auxch(struct nouveau_i2c_chan *auxch, int cmd, int addr,
443                  uint8_t *data, int data_nr)
444 {
445         struct drm_device *dev = auxch->dev;
446         uint32_t tmp, ctrl, stat = 0, data32[4] = {};
447         int ret = 0, i, index = auxch->rd;
448
449         NV_DEBUG(dev, "ch %d cmd %d addr 0x%x len %d\n", index, cmd, addr, data_nr);
450
451         tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd));
452         nv_wr32(dev, NV50_AUXCH_CTRL(auxch->rd), tmp | 0x00100000);
453         tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd));
454         if (!(tmp & 0x01000000)) {
455                 NV_ERROR(dev, "expected bit 24 == 1, got 0x%08x\n", tmp);
456                 ret = -EIO;
457                 goto out;
458         }
459
460         for (i = 0; i < 3; i++) {
461                 tmp = nv_rd32(dev, NV50_AUXCH_STAT(auxch->rd));
462                 if (tmp & NV50_AUXCH_STAT_STATE_READY)
463                         break;
464                 udelay(100);
465         }
466
467         if (i == 3) {
468                 ret = -EBUSY;
469                 goto out;
470         }
471
472         if (!(cmd & 1)) {
473                 memcpy(data32, data, data_nr);
474                 for (i = 0; i < 4; i++) {
475                         NV_DEBUG(dev, "wr %d: 0x%08x\n", i, data32[i]);
476                         nv_wr32(dev, NV50_AUXCH_DATA_OUT(index, i), data32[i]);
477                 }
478         }
479
480         nv_wr32(dev, NV50_AUXCH_ADDR(index), addr);
481         ctrl  = nv_rd32(dev, NV50_AUXCH_CTRL(index));
482         ctrl &= ~(NV50_AUXCH_CTRL_CMD | NV50_AUXCH_CTRL_LEN);
483         ctrl |= (cmd << NV50_AUXCH_CTRL_CMD_SHIFT);
484         ctrl |= ((data_nr - 1) << NV50_AUXCH_CTRL_LEN_SHIFT);
485
486         for (;;) {
487                 nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl | 0x80000000);
488                 nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl);
489                 nv_wr32(dev, NV50_AUXCH_CTRL(index), ctrl | 0x00010000);
490                 if (!nv_wait(NV50_AUXCH_CTRL(index), 0x00010000, 0x00000000)) {
491                         NV_ERROR(dev, "expected bit 16 == 0, got 0x%08x\n",
492                                  nv_rd32(dev, NV50_AUXCH_CTRL(index)));
493                         return -EBUSY;
494                 }
495
496                 udelay(400);
497
498                 stat = nv_rd32(dev, NV50_AUXCH_STAT(index));
499                 if ((stat & NV50_AUXCH_STAT_REPLY_AUX) !=
500                             NV50_AUXCH_STAT_REPLY_AUX_DEFER)
501                         break;
502         }
503
504         if (cmd & 1) {
505                 for (i = 0; i < 4; i++) {
506                         data32[i] = nv_rd32(dev, NV50_AUXCH_DATA_IN(index, i));
507                         NV_DEBUG(dev, "rd %d: 0x%08x\n", i, data32[i]);
508                 }
509                 memcpy(data, data32, data_nr);
510         }
511
512 out:
513         tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd));
514         nv_wr32(dev, NV50_AUXCH_CTRL(auxch->rd), tmp & ~0x00100000);
515         tmp = nv_rd32(dev, NV50_AUXCH_CTRL(auxch->rd));
516         if (tmp & 0x01000000) {
517                 NV_ERROR(dev, "expected bit 24 == 0, got 0x%08x\n", tmp);
518                 ret = -EIO;
519         }
520
521         udelay(400);
522
523         return ret ? ret : (stat & NV50_AUXCH_STAT_REPLY);
524 }
525
526 int
527 nouveau_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
528                       uint8_t write_byte, uint8_t *read_byte)
529 {
530         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
531         struct nouveau_i2c_chan *auxch = (struct nouveau_i2c_chan *)adapter;
532         struct drm_device *dev = auxch->dev;
533         int ret = 0, cmd, addr = algo_data->address;
534         uint8_t *buf;
535
536         if (mode == MODE_I2C_READ) {
537                 cmd = AUX_I2C_READ;
538                 buf = read_byte;
539         } else {
540                 cmd = (mode & MODE_I2C_READ) ? AUX_I2C_READ : AUX_I2C_WRITE;
541                 buf = &write_byte;
542         }
543
544         if (!(mode & MODE_I2C_STOP))
545                 cmd |= AUX_I2C_MOT;
546
547         if (mode & MODE_I2C_START)
548                 return 1;
549
550         for (;;) {
551                 ret = nouveau_dp_auxch(auxch, cmd, addr, buf, 1);
552                 if (ret < 0)
553                         return ret;
554
555                 switch (ret & NV50_AUXCH_STAT_REPLY_I2C) {
556                 case NV50_AUXCH_STAT_REPLY_I2C_ACK:
557                         return 1;
558                 case NV50_AUXCH_STAT_REPLY_I2C_NACK:
559                         return -EREMOTEIO;
560                 case NV50_AUXCH_STAT_REPLY_I2C_DEFER:
561                         udelay(100);
562                         break;
563                 default:
564                         NV_ERROR(dev, "invalid auxch status: 0x%08x\n", ret);
565                         return -EREMOTEIO;
566                 }
567         }
568 }
569