drm: Make drm_local_map use a resource_size_t offset
[linux-2.6.git] / drivers / gpu / drm / mga / mga_dma.c
1 /* mga_dma.c -- DMA support for mga g200/g400 -*- linux-c -*-
2  * Created: Mon Dec 13 01:50:01 1999 by jhartmann@precisioninsight.com
3  *
4  * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5  * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
6  * All Rights Reserved.
7  *
8  * Permission is hereby granted, free of charge, to any person obtaining a
9  * copy of this software and associated documentation files (the "Software"),
10  * to deal in the Software without restriction, including without limitation
11  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12  * and/or sell copies of the Software, and to permit persons to whom the
13  * Software is furnished to do so, subject to the following conditions:
14  *
15  * The above copyright notice and this permission notice (including the next
16  * paragraph) shall be included in all copies or substantial portions of the
17  * Software.
18  *
19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
22  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25  * DEALINGS IN THE SOFTWARE.
26  */
27
28 /**
29  * \file mga_dma.c
30  * DMA support for MGA G200 / G400.
31  *
32  * \author Rickard E. (Rik) Faith <faith@valinux.com>
33  * \author Jeff Hartmann <jhartmann@valinux.com>
34  * \author Keith Whitwell <keith@tungstengraphics.com>
35  * \author Gareth Hughes <gareth@valinux.com>
36  */
37
38 #include "drmP.h"
39 #include "drm.h"
40 #include "drm_sarea.h"
41 #include "mga_drm.h"
42 #include "mga_drv.h"
43
44 #define MGA_DEFAULT_USEC_TIMEOUT        10000
45 #define MGA_FREELIST_DEBUG              0
46
47 #define MINIMAL_CLEANUP 0
48 #define FULL_CLEANUP 1
49 static int mga_do_cleanup_dma(struct drm_device *dev, int full_cleanup);
50
51 /* ================================================================
52  * Engine control
53  */
54
55 int mga_do_wait_for_idle(drm_mga_private_t * dev_priv)
56 {
57         u32 status = 0;
58         int i;
59         DRM_DEBUG("\n");
60
61         for (i = 0; i < dev_priv->usec_timeout; i++) {
62                 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
63                 if (status == MGA_ENDPRDMASTS) {
64                         MGA_WRITE8(MGA_CRTC_INDEX, 0);
65                         return 0;
66                 }
67                 DRM_UDELAY(1);
68         }
69
70 #if MGA_DMA_DEBUG
71         DRM_ERROR("failed!\n");
72         DRM_INFO("   status=0x%08x\n", status);
73 #endif
74         return -EBUSY;
75 }
76
77 static int mga_do_dma_reset(drm_mga_private_t * dev_priv)
78 {
79         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
80         drm_mga_primary_buffer_t *primary = &dev_priv->prim;
81
82         DRM_DEBUG("\n");
83
84         /* The primary DMA stream should look like new right about now.
85          */
86         primary->tail = 0;
87         primary->space = primary->size;
88         primary->last_flush = 0;
89
90         sarea_priv->last_wrap = 0;
91
92         /* FIXME: Reset counters, buffer ages etc...
93          */
94
95         /* FIXME: What else do we need to reinitialize?  WARP stuff?
96          */
97
98         return 0;
99 }
100
101 /* ================================================================
102  * Primary DMA stream
103  */
104
105 void mga_do_dma_flush(drm_mga_private_t * dev_priv)
106 {
107         drm_mga_primary_buffer_t *primary = &dev_priv->prim;
108         u32 head, tail;
109         u32 status = 0;
110         int i;
111         DMA_LOCALS;
112         DRM_DEBUG("\n");
113
114         /* We need to wait so that we can do an safe flush */
115         for (i = 0; i < dev_priv->usec_timeout; i++) {
116                 status = MGA_READ(MGA_STATUS) & MGA_ENGINE_IDLE_MASK;
117                 if (status == MGA_ENDPRDMASTS)
118                         break;
119                 DRM_UDELAY(1);
120         }
121
122         if (primary->tail == primary->last_flush) {
123                 DRM_DEBUG("   bailing out...\n");
124                 return;
125         }
126
127         tail = primary->tail + dev_priv->primary->offset;
128
129         /* We need to pad the stream between flushes, as the card
130          * actually (partially?) reads the first of these commands.
131          * See page 4-16 in the G400 manual, middle of the page or so.
132          */
133         BEGIN_DMA(1);
134
135         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
136                   MGA_DMAPAD, 0x00000000,
137                   MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
138
139         ADVANCE_DMA();
140
141         primary->last_flush = primary->tail;
142
143         head = MGA_READ(MGA_PRIMADDRESS);
144
145         if (head <= tail) {
146                 primary->space = primary->size - primary->tail;
147         } else {
148                 primary->space = head - tail;
149         }
150
151         DRM_DEBUG("   head = 0x%06lx\n", (unsigned long)(head - dev_priv->primary->offset));
152         DRM_DEBUG("   tail = 0x%06lx\n", (unsigned long)(tail - dev_priv->primary->offset));
153         DRM_DEBUG("  space = 0x%06x\n", primary->space);
154
155         mga_flush_write_combine();
156         MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access);
157
158         DRM_DEBUG("done.\n");
159 }
160
161 void mga_do_dma_wrap_start(drm_mga_private_t * dev_priv)
162 {
163         drm_mga_primary_buffer_t *primary = &dev_priv->prim;
164         u32 head, tail;
165         DMA_LOCALS;
166         DRM_DEBUG("\n");
167
168         BEGIN_DMA_WRAP();
169
170         DMA_BLOCK(MGA_DMAPAD, 0x00000000,
171                   MGA_DMAPAD, 0x00000000,
172                   MGA_DMAPAD, 0x00000000, MGA_DMAPAD, 0x00000000);
173
174         ADVANCE_DMA();
175
176         tail = primary->tail + dev_priv->primary->offset;
177
178         primary->tail = 0;
179         primary->last_flush = 0;
180         primary->last_wrap++;
181
182         head = MGA_READ(MGA_PRIMADDRESS);
183
184         if (head == dev_priv->primary->offset) {
185                 primary->space = primary->size;
186         } else {
187                 primary->space = head - dev_priv->primary->offset;
188         }
189
190         DRM_DEBUG("   head = 0x%06lx\n", (unsigned long)(head - dev_priv->primary->offset));
191         DRM_DEBUG("   tail = 0x%06x\n", primary->tail);
192         DRM_DEBUG("   wrap = %d\n", primary->last_wrap);
193         DRM_DEBUG("  space = 0x%06x\n", primary->space);
194
195         mga_flush_write_combine();
196         MGA_WRITE(MGA_PRIMEND, tail | dev_priv->dma_access);
197
198         set_bit(0, &primary->wrapped);
199         DRM_DEBUG("done.\n");
200 }
201
202 void mga_do_dma_wrap_end(drm_mga_private_t * dev_priv)
203 {
204         drm_mga_primary_buffer_t *primary = &dev_priv->prim;
205         drm_mga_sarea_t *sarea_priv = dev_priv->sarea_priv;
206         u32 head = dev_priv->primary->offset;
207         DRM_DEBUG("\n");
208
209         sarea_priv->last_wrap++;
210         DRM_DEBUG("   wrap = %d\n", sarea_priv->last_wrap);
211
212         mga_flush_write_combine();
213         MGA_WRITE(MGA_PRIMADDRESS, head | MGA_DMA_GENERAL);
214
215         clear_bit(0, &primary->wrapped);
216         DRM_DEBUG("done.\n");
217 }
218
219 /* ================================================================
220  * Freelist management
221  */
222
223 #define MGA_BUFFER_USED         ~0
224 #define MGA_BUFFER_FREE         0
225
226 #if MGA_FREELIST_DEBUG
227 static void mga_freelist_print(struct drm_device * dev)
228 {
229         drm_mga_private_t *dev_priv = dev->dev_private;
230         drm_mga_freelist_t *entry;
231
232         DRM_INFO("\n");
233         DRM_INFO("current dispatch: last=0x%x done=0x%x\n",
234                  dev_priv->sarea_priv->last_dispatch,
235                  (unsigned int)(MGA_READ(MGA_PRIMADDRESS) -
236                                 dev_priv->primary->offset));
237         DRM_INFO("current freelist:\n");
238
239         for (entry = dev_priv->head->next; entry; entry = entry->next) {
240                 DRM_INFO("   %p   idx=%2d  age=0x%x 0x%06lx\n",
241                          entry, entry->buf->idx, entry->age.head,
242                          (unsigned long)(entry->age.head - dev_priv->primary->offset));
243         }
244         DRM_INFO("\n");
245 }
246 #endif
247
248 static int mga_freelist_init(struct drm_device * dev, drm_mga_private_t * dev_priv)
249 {
250         struct drm_device_dma *dma = dev->dma;
251         struct drm_buf *buf;
252         drm_mga_buf_priv_t *buf_priv;
253         drm_mga_freelist_t *entry;
254         int i;
255         DRM_DEBUG("count=%d\n", dma->buf_count);
256
257         dev_priv->head = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
258         if (dev_priv->head == NULL)
259                 return -ENOMEM;
260
261         memset(dev_priv->head, 0, sizeof(drm_mga_freelist_t));
262         SET_AGE(&dev_priv->head->age, MGA_BUFFER_USED, 0);
263
264         for (i = 0; i < dma->buf_count; i++) {
265                 buf = dma->buflist[i];
266                 buf_priv = buf->dev_private;
267
268                 entry = drm_alloc(sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
269                 if (entry == NULL)
270                         return -ENOMEM;
271
272                 memset(entry, 0, sizeof(drm_mga_freelist_t));
273
274                 entry->next = dev_priv->head->next;
275                 entry->prev = dev_priv->head;
276                 SET_AGE(&entry->age, MGA_BUFFER_FREE, 0);
277                 entry->buf = buf;
278
279                 if (dev_priv->head->next != NULL)
280                         dev_priv->head->next->prev = entry;
281                 if (entry->next == NULL)
282                         dev_priv->tail = entry;
283
284                 buf_priv->list_entry = entry;
285                 buf_priv->discard = 0;
286                 buf_priv->dispatched = 0;
287
288                 dev_priv->head->next = entry;
289         }
290
291         return 0;
292 }
293
294 static void mga_freelist_cleanup(struct drm_device * dev)
295 {
296         drm_mga_private_t *dev_priv = dev->dev_private;
297         drm_mga_freelist_t *entry;
298         drm_mga_freelist_t *next;
299         DRM_DEBUG("\n");
300
301         entry = dev_priv->head;
302         while (entry) {
303                 next = entry->next;
304                 drm_free(entry, sizeof(drm_mga_freelist_t), DRM_MEM_DRIVER);
305                 entry = next;
306         }
307
308         dev_priv->head = dev_priv->tail = NULL;
309 }
310
311 #if 0
312 /* FIXME: Still needed?
313  */
314 static void mga_freelist_reset(struct drm_device * dev)
315 {
316         struct drm_device_dma *dma = dev->dma;
317         struct drm_buf *buf;
318         drm_mga_buf_priv_t *buf_priv;
319         int i;
320
321         for (i = 0; i < dma->buf_count; i++) {
322                 buf = dma->buflist[i];
323                 buf_priv = buf->dev_private;
324                 SET_AGE(&buf_priv->list_entry->age, MGA_BUFFER_FREE, 0);
325         }
326 }
327 #endif
328
329 static struct drm_buf *mga_freelist_get(struct drm_device * dev)
330 {
331         drm_mga_private_t *dev_priv = dev->dev_private;
332         drm_mga_freelist_t *next;
333         drm_mga_freelist_t *prev;
334         drm_mga_freelist_t *tail = dev_priv->tail;
335         u32 head, wrap;
336         DRM_DEBUG("\n");
337
338         head = MGA_READ(MGA_PRIMADDRESS);
339         wrap = dev_priv->sarea_priv->last_wrap;
340
341         DRM_DEBUG("   tail=0x%06lx %d\n",
342                   tail->age.head ?
343                   (unsigned long)(tail->age.head - dev_priv->primary->offset) : 0,
344                   tail->age.wrap);
345         DRM_DEBUG("   head=0x%06lx %d\n",
346                   (unsigned long)(head - dev_priv->primary->offset), wrap);
347
348         if (TEST_AGE(&tail->age, head, wrap)) {
349                 prev = dev_priv->tail->prev;
350                 next = dev_priv->tail;
351                 prev->next = NULL;
352                 next->prev = next->next = NULL;
353                 dev_priv->tail = prev;
354                 SET_AGE(&next->age, MGA_BUFFER_USED, 0);
355                 return next->buf;
356         }
357
358         DRM_DEBUG("returning NULL!\n");
359         return NULL;
360 }
361
362 int mga_freelist_put(struct drm_device * dev, struct drm_buf * buf)
363 {
364         drm_mga_private_t *dev_priv = dev->dev_private;
365         drm_mga_buf_priv_t *buf_priv = buf->dev_private;
366         drm_mga_freelist_t *head, *entry, *prev;
367
368         DRM_DEBUG("age=0x%06lx wrap=%d\n",
369                   (unsigned long)(buf_priv->list_entry->age.head -
370                                   dev_priv->primary->offset),
371                   buf_priv->list_entry->age.wrap);
372
373         entry = buf_priv->list_entry;
374         head = dev_priv->head;
375
376         if (buf_priv->list_entry->age.head == MGA_BUFFER_USED) {
377                 SET_AGE(&entry->age, MGA_BUFFER_FREE, 0);
378                 prev = dev_priv->tail;
379                 prev->next = entry;
380                 entry->prev = prev;
381                 entry->next = NULL;
382         } else {
383                 prev = head->next;
384                 head->next = entry;
385                 prev->prev = entry;
386                 entry->prev = head;
387                 entry->next = prev;
388         }
389
390         return 0;
391 }
392
393 /* ================================================================
394  * DMA initialization, cleanup
395  */
396
397 int mga_driver_load(struct drm_device * dev, unsigned long flags)
398 {
399         drm_mga_private_t *dev_priv;
400         int ret;
401
402         dev_priv = drm_alloc(sizeof(drm_mga_private_t), DRM_MEM_DRIVER);
403         if (!dev_priv)
404                 return -ENOMEM;
405
406         dev->dev_private = (void *)dev_priv;
407         memset(dev_priv, 0, sizeof(drm_mga_private_t));
408
409         dev_priv->usec_timeout = MGA_DEFAULT_USEC_TIMEOUT;
410         dev_priv->chipset = flags;
411
412         dev_priv->mmio_base = drm_get_resource_start(dev, 1);
413         dev_priv->mmio_size = drm_get_resource_len(dev, 1);
414
415         dev->counters += 3;
416         dev->types[6] = _DRM_STAT_IRQ;
417         dev->types[7] = _DRM_STAT_PRIMARY;
418         dev->types[8] = _DRM_STAT_SECONDARY;
419
420         ret = drm_vblank_init(dev, 1);
421
422         if (ret) {
423                 (void) mga_driver_unload(dev);
424                 return ret;
425         }
426
427         return 0;
428 }
429
430 #if __OS_HAS_AGP
431 /**
432  * Bootstrap the driver for AGP DMA.
433  *
434  * \todo
435  * Investigate whether there is any benifit to storing the WARP microcode in
436  * AGP memory.  If not, the microcode may as well always be put in PCI
437  * memory.
438  *
439  * \todo
440  * This routine needs to set dma_bs->agp_mode to the mode actually configured
441  * in the hardware.  Looking just at the Linux AGP driver code, I don't see
442  * an easy way to determine this.
443  *
444  * \sa mga_do_dma_bootstrap, mga_do_pci_dma_bootstrap
445  */
446 static int mga_do_agp_dma_bootstrap(struct drm_device * dev,
447                                     drm_mga_dma_bootstrap_t * dma_bs)
448 {
449         drm_mga_private_t *const dev_priv =
450             (drm_mga_private_t *) dev->dev_private;
451         unsigned int warp_size = mga_warp_microcode_size(dev_priv);
452         int err;
453         unsigned offset;
454         const unsigned secondary_size = dma_bs->secondary_bin_count
455             * dma_bs->secondary_bin_size;
456         const unsigned agp_size = (dma_bs->agp_size << 20);
457         struct drm_buf_desc req;
458         struct drm_agp_mode mode;
459         struct drm_agp_info info;
460         struct drm_agp_buffer agp_req;
461         struct drm_agp_binding bind_req;
462
463         /* Acquire AGP. */
464         err = drm_agp_acquire(dev);
465         if (err) {
466                 DRM_ERROR("Unable to acquire AGP: %d\n", err);
467                 return err;
468         }
469
470         err = drm_agp_info(dev, &info);
471         if (err) {
472                 DRM_ERROR("Unable to get AGP info: %d\n", err);
473                 return err;
474         }
475
476         mode.mode = (info.mode & ~0x07) | dma_bs->agp_mode;
477         err = drm_agp_enable(dev, mode);
478         if (err) {
479                 DRM_ERROR("Unable to enable AGP (mode = 0x%lx)\n", mode.mode);
480                 return err;
481         }
482
483         /* In addition to the usual AGP mode configuration, the G200 AGP cards
484          * need to have the AGP mode "manually" set.
485          */
486
487         if (dev_priv->chipset == MGA_CARD_TYPE_G200) {
488                 if (mode.mode & 0x02) {
489                         MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_ENABLE);
490                 } else {
491                         MGA_WRITE(MGA_AGP_PLL, MGA_AGP2XPLL_DISABLE);
492                 }
493         }
494
495         /* Allocate and bind AGP memory. */
496         agp_req.size = agp_size;
497         agp_req.type = 0;
498         err = drm_agp_alloc(dev, &agp_req);
499         if (err) {
500                 dev_priv->agp_size = 0;
501                 DRM_ERROR("Unable to allocate %uMB AGP memory\n",
502                           dma_bs->agp_size);
503                 return err;
504         }
505
506         dev_priv->agp_size = agp_size;
507         dev_priv->agp_handle = agp_req.handle;
508
509         bind_req.handle = agp_req.handle;
510         bind_req.offset = 0;
511         err = drm_agp_bind(dev, &bind_req);
512         if (err) {
513                 DRM_ERROR("Unable to bind AGP memory: %d\n", err);
514                 return err;
515         }
516
517         /* Make drm_addbufs happy by not trying to create a mapping for less
518          * than a page.
519          */
520         if (warp_size < PAGE_SIZE)
521                 warp_size = PAGE_SIZE;
522
523         offset = 0;
524         err = drm_addmap(dev, offset, warp_size,
525                          _DRM_AGP, _DRM_READ_ONLY, &dev_priv->warp);
526         if (err) {
527                 DRM_ERROR("Unable to map WARP microcode: %d\n", err);
528                 return err;
529         }
530
531         offset += warp_size;
532         err = drm_addmap(dev, offset, dma_bs->primary_size,
533                          _DRM_AGP, _DRM_READ_ONLY, &dev_priv->primary);
534         if (err) {
535                 DRM_ERROR("Unable to map primary DMA region: %d\n", err);
536                 return err;
537         }
538
539         offset += dma_bs->primary_size;
540         err = drm_addmap(dev, offset, secondary_size,
541                          _DRM_AGP, 0, &dev->agp_buffer_map);
542         if (err) {
543                 DRM_ERROR("Unable to map secondary DMA region: %d\n", err);
544                 return err;
545         }
546
547         (void)memset(&req, 0, sizeof(req));
548         req.count = dma_bs->secondary_bin_count;
549         req.size = dma_bs->secondary_bin_size;
550         req.flags = _DRM_AGP_BUFFER;
551         req.agp_start = offset;
552
553         err = drm_addbufs_agp(dev, &req);
554         if (err) {
555                 DRM_ERROR("Unable to add secondary DMA buffers: %d\n", err);
556                 return err;
557         }
558
559         {
560                 struct drm_map_list *_entry;
561                 unsigned long agp_token = 0;
562
563                 list_for_each_entry(_entry, &dev->maplist, head) {
564                         if (_entry->map == dev->agp_buffer_map)
565                                 agp_token = _entry->user_token;
566                 }
567                 if (!agp_token)
568                         return -EFAULT;
569
570                 dev->agp_buffer_token = agp_token;
571         }
572
573         offset += secondary_size;
574         err = drm_addmap(dev, offset, agp_size - offset,
575                          _DRM_AGP, 0, &dev_priv->agp_textures);
576         if (err) {
577                 DRM_ERROR("Unable to map AGP texture region %d\n", err);
578                 return err;
579         }
580
581         drm_core_ioremap(dev_priv->warp, dev);
582         drm_core_ioremap(dev_priv->primary, dev);
583         drm_core_ioremap(dev->agp_buffer_map, dev);
584
585         if (!dev_priv->warp->handle ||
586             !dev_priv->primary->handle || !dev->agp_buffer_map->handle) {
587                 DRM_ERROR("failed to ioremap agp regions! (%p, %p, %p)\n",
588                           dev_priv->warp->handle, dev_priv->primary->handle,
589                           dev->agp_buffer_map->handle);
590                 return -ENOMEM;
591         }
592
593         dev_priv->dma_access = MGA_PAGPXFER;
594         dev_priv->wagp_enable = MGA_WAGP_ENABLE;
595
596         DRM_INFO("Initialized card for AGP DMA.\n");
597         return 0;
598 }
599 #else
600 static int mga_do_agp_dma_bootstrap(struct drm_device * dev,
601                                     drm_mga_dma_bootstrap_t * dma_bs)
602 {
603         return -EINVAL;
604 }
605 #endif
606
607 /**
608  * Bootstrap the driver for PCI DMA.
609  *
610  * \todo
611  * The algorithm for decreasing the size of the primary DMA buffer could be
612  * better.  The size should be rounded up to the nearest page size, then
613  * decrease the request size by a single page each pass through the loop.
614  *
615  * \todo
616  * Determine whether the maximum address passed to drm_pci_alloc is correct.
617  * The same goes for drm_addbufs_pci.
618  *
619  * \sa mga_do_dma_bootstrap, mga_do_agp_dma_bootstrap
620  */
621 static int mga_do_pci_dma_bootstrap(struct drm_device * dev,
622                                     drm_mga_dma_bootstrap_t * dma_bs)
623 {
624         drm_mga_private_t *const dev_priv =
625             (drm_mga_private_t *) dev->dev_private;
626         unsigned int warp_size = mga_warp_microcode_size(dev_priv);
627         unsigned int primary_size;
628         unsigned int bin_count;
629         int err;
630         struct drm_buf_desc req;
631
632         if (dev->dma == NULL) {
633                 DRM_ERROR("dev->dma is NULL\n");
634                 return -EFAULT;
635         }
636
637         /* Make drm_addbufs happy by not trying to create a mapping for less
638          * than a page.
639          */
640         if (warp_size < PAGE_SIZE)
641                 warp_size = PAGE_SIZE;
642
643         /* The proper alignment is 0x100 for this mapping */
644         err = drm_addmap(dev, 0, warp_size, _DRM_CONSISTENT,
645                          _DRM_READ_ONLY, &dev_priv->warp);
646         if (err != 0) {
647                 DRM_ERROR("Unable to create mapping for WARP microcode: %d\n",
648                           err);
649                 return err;
650         }
651
652         /* Other than the bottom two bits being used to encode other
653          * information, there don't appear to be any restrictions on the
654          * alignment of the primary or secondary DMA buffers.
655          */
656
657         for (primary_size = dma_bs->primary_size; primary_size != 0;
658              primary_size >>= 1) {
659                 /* The proper alignment for this mapping is 0x04 */
660                 err = drm_addmap(dev, 0, primary_size, _DRM_CONSISTENT,
661                                  _DRM_READ_ONLY, &dev_priv->primary);
662                 if (!err)
663                         break;
664         }
665
666         if (err != 0) {
667                 DRM_ERROR("Unable to allocate primary DMA region: %d\n", err);
668                 return -ENOMEM;
669         }
670
671         if (dev_priv->primary->size != dma_bs->primary_size) {
672                 DRM_INFO("Primary DMA buffer size reduced from %u to %u.\n",
673                          dma_bs->primary_size,
674                          (unsigned)dev_priv->primary->size);
675                 dma_bs->primary_size = dev_priv->primary->size;
676         }
677
678         for (bin_count = dma_bs->secondary_bin_count; bin_count > 0;
679              bin_count--) {
680                 (void)memset(&req, 0, sizeof(req));
681                 req.count = bin_count;
682                 req.size = dma_bs->secondary_bin_size;
683
684                 err = drm_addbufs_pci(dev, &req);
685                 if (!err) {
686                         break;
687                 }
688         }
689
690         if (bin_count == 0) {
691                 DRM_ERROR("Unable to add secondary DMA buffers: %d\n", err);
692                 return err;
693         }
694
695         if (bin_count != dma_bs->secondary_bin_count) {
696                 DRM_INFO("Secondary PCI DMA buffer bin count reduced from %u "
697                          "to %u.\n", dma_bs->secondary_bin_count, bin_count);
698
699                 dma_bs->secondary_bin_count = bin_count;
700         }
701
702         dev_priv->dma_access = 0;
703         dev_priv->wagp_enable = 0;
704
705         dma_bs->agp_mode = 0;
706
707         DRM_INFO("Initialized card for PCI DMA.\n");
708         return 0;
709 }
710
711 static int mga_do_dma_bootstrap(struct drm_device * dev,
712                                 drm_mga_dma_bootstrap_t * dma_bs)
713 {
714         const int is_agp = (dma_bs->agp_mode != 0) && drm_device_is_agp(dev);
715         int err;
716         drm_mga_private_t *const dev_priv =
717             (drm_mga_private_t *) dev->dev_private;
718
719         dev_priv->used_new_dma_init = 1;
720
721         /* The first steps are the same for both PCI and AGP based DMA.  Map
722          * the cards MMIO registers and map a status page.
723          */
724         err = drm_addmap(dev, dev_priv->mmio_base, dev_priv->mmio_size,
725                          _DRM_REGISTERS, _DRM_READ_ONLY, &dev_priv->mmio);
726         if (err) {
727                 DRM_ERROR("Unable to map MMIO region: %d\n", err);
728                 return err;
729         }
730
731         err = drm_addmap(dev, 0, SAREA_MAX, _DRM_SHM,
732                          _DRM_READ_ONLY | _DRM_LOCKED | _DRM_KERNEL,
733                          &dev_priv->status);
734         if (err) {
735                 DRM_ERROR("Unable to map status region: %d\n", err);
736                 return err;
737         }
738
739         /* The DMA initialization procedure is slightly different for PCI and
740          * AGP cards.  AGP cards just allocate a large block of AGP memory and
741          * carve off portions of it for internal uses.  The remaining memory
742          * is returned to user-mode to be used for AGP textures.
743          */
744         if (is_agp) {
745                 err = mga_do_agp_dma_bootstrap(dev, dma_bs);
746         }
747
748         /* If we attempted to initialize the card for AGP DMA but failed,
749          * clean-up any mess that may have been created.
750          */
751
752         if (err) {
753                 mga_do_cleanup_dma(dev, MINIMAL_CLEANUP);
754         }
755
756         /* Not only do we want to try and initialized PCI cards for PCI DMA,
757          * but we also try to initialized AGP cards that could not be
758          * initialized for AGP DMA.  This covers the case where we have an AGP
759          * card in a system with an unsupported AGP chipset.  In that case the
760          * card will be detected as AGP, but we won't be able to allocate any
761          * AGP memory, etc.
762          */
763
764         if (!is_agp || err) {
765                 err = mga_do_pci_dma_bootstrap(dev, dma_bs);
766         }
767
768         return err;
769 }
770
771 int mga_dma_bootstrap(struct drm_device *dev, void *data,
772                       struct drm_file *file_priv)
773 {
774         drm_mga_dma_bootstrap_t *bootstrap = data;
775         int err;
776         static const int modes[] = { 0, 1, 2, 2, 4, 4, 4, 4 };
777         const drm_mga_private_t *const dev_priv =
778                 (drm_mga_private_t *) dev->dev_private;
779
780         err = mga_do_dma_bootstrap(dev, bootstrap);
781         if (err) {
782                 mga_do_cleanup_dma(dev, FULL_CLEANUP);
783                 return err;
784         }
785
786         if (dev_priv->agp_textures != NULL) {
787                 bootstrap->texture_handle = dev_priv->agp_textures->offset;
788                 bootstrap->texture_size = dev_priv->agp_textures->size;
789         } else {
790                 bootstrap->texture_handle = 0;
791                 bootstrap->texture_size = 0;
792         }
793
794         bootstrap->agp_mode = modes[bootstrap->agp_mode & 0x07];
795
796         return err;
797 }
798
799 static int mga_do_init_dma(struct drm_device * dev, drm_mga_init_t * init)
800 {
801         drm_mga_private_t *dev_priv;
802         int ret;
803         DRM_DEBUG("\n");
804
805         dev_priv = dev->dev_private;
806
807         if (init->sgram) {
808                 dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_BLK;
809         } else {
810                 dev_priv->clear_cmd = MGA_DWGCTL_CLEAR | MGA_ATYPE_RSTR;
811         }
812         dev_priv->maccess = init->maccess;
813
814         dev_priv->fb_cpp = init->fb_cpp;
815         dev_priv->front_offset = init->front_offset;
816         dev_priv->front_pitch = init->front_pitch;
817         dev_priv->back_offset = init->back_offset;
818         dev_priv->back_pitch = init->back_pitch;
819
820         dev_priv->depth_cpp = init->depth_cpp;
821         dev_priv->depth_offset = init->depth_offset;
822         dev_priv->depth_pitch = init->depth_pitch;
823
824         /* FIXME: Need to support AGP textures...
825          */
826         dev_priv->texture_offset = init->texture_offset[0];
827         dev_priv->texture_size = init->texture_size[0];
828
829         dev_priv->sarea = drm_getsarea(dev);
830         if (!dev_priv->sarea) {
831                 DRM_ERROR("failed to find sarea!\n");
832                 return -EINVAL;
833         }
834
835         if (!dev_priv->used_new_dma_init) {
836
837                 dev_priv->dma_access = MGA_PAGPXFER;
838                 dev_priv->wagp_enable = MGA_WAGP_ENABLE;
839
840                 dev_priv->status = drm_core_findmap(dev, init->status_offset);
841                 if (!dev_priv->status) {
842                         DRM_ERROR("failed to find status page!\n");
843                         return -EINVAL;
844                 }
845                 dev_priv->mmio = drm_core_findmap(dev, init->mmio_offset);
846                 if (!dev_priv->mmio) {
847                         DRM_ERROR("failed to find mmio region!\n");
848                         return -EINVAL;
849                 }
850                 dev_priv->warp = drm_core_findmap(dev, init->warp_offset);
851                 if (!dev_priv->warp) {
852                         DRM_ERROR("failed to find warp microcode region!\n");
853                         return -EINVAL;
854                 }
855                 dev_priv->primary = drm_core_findmap(dev, init->primary_offset);
856                 if (!dev_priv->primary) {
857                         DRM_ERROR("failed to find primary dma region!\n");
858                         return -EINVAL;
859                 }
860                 dev->agp_buffer_token = init->buffers_offset;
861                 dev->agp_buffer_map =
862                     drm_core_findmap(dev, init->buffers_offset);
863                 if (!dev->agp_buffer_map) {
864                         DRM_ERROR("failed to find dma buffer region!\n");
865                         return -EINVAL;
866                 }
867
868                 drm_core_ioremap(dev_priv->warp, dev);
869                 drm_core_ioremap(dev_priv->primary, dev);
870                 drm_core_ioremap(dev->agp_buffer_map, dev);
871         }
872
873         dev_priv->sarea_priv =
874             (drm_mga_sarea_t *) ((u8 *) dev_priv->sarea->handle +
875                                  init->sarea_priv_offset);
876
877         if (!dev_priv->warp->handle ||
878             !dev_priv->primary->handle ||
879             ((dev_priv->dma_access != 0) &&
880              ((dev->agp_buffer_map == NULL) ||
881               (dev->agp_buffer_map->handle == NULL)))) {
882                 DRM_ERROR("failed to ioremap agp regions!\n");
883                 return -ENOMEM;
884         }
885
886         ret = mga_warp_install_microcode(dev_priv);
887         if (ret < 0) {
888                 DRM_ERROR("failed to install WARP ucode!: %d\n", ret);
889                 return ret;
890         }
891
892         ret = mga_warp_init(dev_priv);
893         if (ret < 0) {
894                 DRM_ERROR("failed to init WARP engine!: %d\n", ret);
895                 return ret;
896         }
897
898         dev_priv->prim.status = (u32 *) dev_priv->status->handle;
899
900         mga_do_wait_for_idle(dev_priv);
901
902         /* Init the primary DMA registers.
903          */
904         MGA_WRITE(MGA_PRIMADDRESS, dev_priv->primary->offset | MGA_DMA_GENERAL);
905 #if 0
906         MGA_WRITE(MGA_PRIMPTR, virt_to_bus((void *)dev_priv->prim.status) | MGA_PRIMPTREN0 |    /* Soft trap, SECEND, SETUPEND */
907                   MGA_PRIMPTREN1);      /* DWGSYNC */
908 #endif
909
910         dev_priv->prim.start = (u8 *) dev_priv->primary->handle;
911         dev_priv->prim.end = ((u8 *) dev_priv->primary->handle
912                               + dev_priv->primary->size);
913         dev_priv->prim.size = dev_priv->primary->size;
914
915         dev_priv->prim.tail = 0;
916         dev_priv->prim.space = dev_priv->prim.size;
917         dev_priv->prim.wrapped = 0;
918
919         dev_priv->prim.last_flush = 0;
920         dev_priv->prim.last_wrap = 0;
921
922         dev_priv->prim.high_mark = 256 * DMA_BLOCK_SIZE;
923
924         dev_priv->prim.status[0] = dev_priv->primary->offset;
925         dev_priv->prim.status[1] = 0;
926
927         dev_priv->sarea_priv->last_wrap = 0;
928         dev_priv->sarea_priv->last_frame.head = 0;
929         dev_priv->sarea_priv->last_frame.wrap = 0;
930
931         if (mga_freelist_init(dev, dev_priv) < 0) {
932                 DRM_ERROR("could not initialize freelist\n");
933                 return -ENOMEM;
934         }
935
936         return 0;
937 }
938
939 static int mga_do_cleanup_dma(struct drm_device *dev, int full_cleanup)
940 {
941         int err = 0;
942         DRM_DEBUG("\n");
943
944         /* Make sure interrupts are disabled here because the uninstall ioctl
945          * may not have been called from userspace and after dev_private
946          * is freed, it's too late.
947          */
948         if (dev->irq_enabled)
949                 drm_irq_uninstall(dev);
950
951         if (dev->dev_private) {
952                 drm_mga_private_t *dev_priv = dev->dev_private;
953
954                 if ((dev_priv->warp != NULL)
955                     && (dev_priv->warp->type != _DRM_CONSISTENT))
956                         drm_core_ioremapfree(dev_priv->warp, dev);
957
958                 if ((dev_priv->primary != NULL)
959                     && (dev_priv->primary->type != _DRM_CONSISTENT))
960                         drm_core_ioremapfree(dev_priv->primary, dev);
961
962                 if (dev->agp_buffer_map != NULL)
963                         drm_core_ioremapfree(dev->agp_buffer_map, dev);
964
965                 if (dev_priv->used_new_dma_init) {
966 #if __OS_HAS_AGP
967                         if (dev_priv->agp_handle != 0) {
968                                 struct drm_agp_binding unbind_req;
969                                 struct drm_agp_buffer free_req;
970
971                                 unbind_req.handle = dev_priv->agp_handle;
972                                 drm_agp_unbind(dev, &unbind_req);
973
974                                 free_req.handle = dev_priv->agp_handle;
975                                 drm_agp_free(dev, &free_req);
976
977                                 dev_priv->agp_textures = NULL;
978                                 dev_priv->agp_size = 0;
979                                 dev_priv->agp_handle = 0;
980                         }
981
982                         if ((dev->agp != NULL) && dev->agp->acquired) {
983                                 err = drm_agp_release(dev);
984                         }
985 #endif
986                 }
987
988                 dev_priv->warp = NULL;
989                 dev_priv->primary = NULL;
990                 dev_priv->sarea = NULL;
991                 dev_priv->sarea_priv = NULL;
992                 dev->agp_buffer_map = NULL;
993
994                 if (full_cleanup) {
995                         dev_priv->mmio = NULL;
996                         dev_priv->status = NULL;
997                         dev_priv->used_new_dma_init = 0;
998                 }
999
1000                 memset(&dev_priv->prim, 0, sizeof(dev_priv->prim));
1001                 dev_priv->warp_pipe = 0;
1002                 memset(dev_priv->warp_pipe_phys, 0,
1003                        sizeof(dev_priv->warp_pipe_phys));
1004
1005                 if (dev_priv->head != NULL) {
1006                         mga_freelist_cleanup(dev);
1007                 }
1008         }
1009
1010         return err;
1011 }
1012
1013 int mga_dma_init(struct drm_device *dev, void *data,
1014                  struct drm_file *file_priv)
1015 {
1016         drm_mga_init_t *init = data;
1017         int err;
1018
1019         LOCK_TEST_WITH_RETURN(dev, file_priv);
1020
1021         switch (init->func) {
1022         case MGA_INIT_DMA:
1023                 err = mga_do_init_dma(dev, init);
1024                 if (err) {
1025                         (void)mga_do_cleanup_dma(dev, FULL_CLEANUP);
1026                 }
1027                 return err;
1028         case MGA_CLEANUP_DMA:
1029                 return mga_do_cleanup_dma(dev, FULL_CLEANUP);
1030         }
1031
1032         return -EINVAL;
1033 }
1034
1035 /* ================================================================
1036  * Primary DMA stream management
1037  */
1038
1039 int mga_dma_flush(struct drm_device *dev, void *data,
1040                   struct drm_file *file_priv)
1041 {
1042         drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1043         struct drm_lock *lock = data;
1044
1045         LOCK_TEST_WITH_RETURN(dev, file_priv);
1046
1047         DRM_DEBUG("%s%s%s\n",
1048                   (lock->flags & _DRM_LOCK_FLUSH) ? "flush, " : "",
1049                   (lock->flags & _DRM_LOCK_FLUSH_ALL) ? "flush all, " : "",
1050                   (lock->flags & _DRM_LOCK_QUIESCENT) ? "idle, " : "");
1051
1052         WRAP_WAIT_WITH_RETURN(dev_priv);
1053
1054         if (lock->flags & (_DRM_LOCK_FLUSH | _DRM_LOCK_FLUSH_ALL)) {
1055                 mga_do_dma_flush(dev_priv);
1056         }
1057
1058         if (lock->flags & _DRM_LOCK_QUIESCENT) {
1059 #if MGA_DMA_DEBUG
1060                 int ret = mga_do_wait_for_idle(dev_priv);
1061                 if (ret < 0)
1062                         DRM_INFO("-EBUSY\n");
1063                 return ret;
1064 #else
1065                 return mga_do_wait_for_idle(dev_priv);
1066 #endif
1067         } else {
1068                 return 0;
1069         }
1070 }
1071
1072 int mga_dma_reset(struct drm_device *dev, void *data,
1073                   struct drm_file *file_priv)
1074 {
1075         drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1076
1077         LOCK_TEST_WITH_RETURN(dev, file_priv);
1078
1079         return mga_do_dma_reset(dev_priv);
1080 }
1081
1082 /* ================================================================
1083  * DMA buffer management
1084  */
1085
1086 static int mga_dma_get_buffers(struct drm_device * dev,
1087                                struct drm_file *file_priv, struct drm_dma * d)
1088 {
1089         struct drm_buf *buf;
1090         int i;
1091
1092         for (i = d->granted_count; i < d->request_count; i++) {
1093                 buf = mga_freelist_get(dev);
1094                 if (!buf)
1095                         return -EAGAIN;
1096
1097                 buf->file_priv = file_priv;
1098
1099                 if (DRM_COPY_TO_USER(&d->request_indices[i],
1100                                      &buf->idx, sizeof(buf->idx)))
1101                         return -EFAULT;
1102                 if (DRM_COPY_TO_USER(&d->request_sizes[i],
1103                                      &buf->total, sizeof(buf->total)))
1104                         return -EFAULT;
1105
1106                 d->granted_count++;
1107         }
1108         return 0;
1109 }
1110
1111 int mga_dma_buffers(struct drm_device *dev, void *data,
1112                     struct drm_file *file_priv)
1113 {
1114         struct drm_device_dma *dma = dev->dma;
1115         drm_mga_private_t *dev_priv = (drm_mga_private_t *) dev->dev_private;
1116         struct drm_dma *d = data;
1117         int ret = 0;
1118
1119         LOCK_TEST_WITH_RETURN(dev, file_priv);
1120
1121         /* Please don't send us buffers.
1122          */
1123         if (d->send_count != 0) {
1124                 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1125                           DRM_CURRENTPID, d->send_count);
1126                 return -EINVAL;
1127         }
1128
1129         /* We'll send you buffers.
1130          */
1131         if (d->request_count < 0 || d->request_count > dma->buf_count) {
1132                 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1133                           DRM_CURRENTPID, d->request_count, dma->buf_count);
1134                 return -EINVAL;
1135         }
1136
1137         WRAP_TEST_WITH_RETURN(dev_priv);
1138
1139         d->granted_count = 0;
1140
1141         if (d->request_count) {
1142                 ret = mga_dma_get_buffers(dev, file_priv, d);
1143         }
1144
1145         return ret;
1146 }
1147
1148 /**
1149  * Called just before the module is unloaded.
1150  */
1151 int mga_driver_unload(struct drm_device * dev)
1152 {
1153         drm_free(dev->dev_private, sizeof(drm_mga_private_t), DRM_MEM_DRIVER);
1154         dev->dev_private = NULL;
1155
1156         return 0;
1157 }
1158
1159 /**
1160  * Called when the last opener of the device is closed.
1161  */
1162 void mga_driver_lastclose(struct drm_device * dev)
1163 {
1164         mga_do_cleanup_dma(dev, FULL_CLEANUP);
1165 }
1166
1167 int mga_driver_dma_quiescent(struct drm_device * dev)
1168 {
1169         drm_mga_private_t *dev_priv = dev->dev_private;
1170         return mga_do_wait_for_idle(dev_priv);
1171 }