drm/i915: Workaround erratum on i830 for TAIL pointer within last 2 cachelines
[linux-2.6.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2  * Copyright © 2008-2010 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Authors:
24  *    Eric Anholt <eric@anholt.net>
25  *    Zou Nan hai <nanhai.zou@intel.com>
26  *    Xiang Hai hao<haihao.xiang@intel.com>
27  *
28  */
29
30 #include "drmP.h"
31 #include "drm.h"
32 #include "i915_drv.h"
33 #include "i915_drm.h"
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36
37 static u32 i915_gem_get_seqno(struct drm_device *dev)
38 {
39         drm_i915_private_t *dev_priv = dev->dev_private;
40         u32 seqno;
41
42         seqno = dev_priv->next_seqno;
43
44         /* reserve 0 for non-seqno */
45         if (++dev_priv->next_seqno == 0)
46                 dev_priv->next_seqno = 1;
47
48         return seqno;
49 }
50
51 static void
52 render_ring_flush(struct intel_ring_buffer *ring,
53                   u32   invalidate_domains,
54                   u32   flush_domains)
55 {
56         struct drm_device *dev = ring->dev;
57         drm_i915_private_t *dev_priv = dev->dev_private;
58         u32 cmd;
59
60 #if WATCH_EXEC
61         DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
62                   invalidate_domains, flush_domains);
63 #endif
64
65         trace_i915_gem_request_flush(dev, dev_priv->next_seqno,
66                                      invalidate_domains, flush_domains);
67
68         if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
69                 /*
70                  * read/write caches:
71                  *
72                  * I915_GEM_DOMAIN_RENDER is always invalidated, but is
73                  * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
74                  * also flushed at 2d versus 3d pipeline switches.
75                  *
76                  * read-only caches:
77                  *
78                  * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
79                  * MI_READ_FLUSH is set, and is always flushed on 965.
80                  *
81                  * I915_GEM_DOMAIN_COMMAND may not exist?
82                  *
83                  * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
84                  * invalidated when MI_EXE_FLUSH is set.
85                  *
86                  * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
87                  * invalidated with every MI_FLUSH.
88                  *
89                  * TLBs:
90                  *
91                  * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
92                  * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
93                  * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
94                  * are flushed at any MI_FLUSH.
95                  */
96
97                 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
98                 if ((invalidate_domains|flush_domains) &
99                     I915_GEM_DOMAIN_RENDER)
100                         cmd &= ~MI_NO_WRITE_FLUSH;
101                 if (INTEL_INFO(dev)->gen < 4) {
102                         /*
103                          * On the 965, the sampler cache always gets flushed
104                          * and this bit is reserved.
105                          */
106                         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
107                                 cmd |= MI_READ_FLUSH;
108                 }
109                 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
110                         cmd |= MI_EXE_FLUSH;
111
112                 if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
113                     (IS_G4X(dev) || IS_GEN5(dev)))
114                         cmd |= MI_INVALIDATE_ISP;
115
116 #if WATCH_EXEC
117                 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
118 #endif
119                 if (intel_ring_begin(ring, 2) == 0) {
120                         intel_ring_emit(ring, cmd);
121                         intel_ring_emit(ring, MI_NOOP);
122                         intel_ring_advance(ring);
123                 }
124         }
125 }
126
127 static void ring_write_tail(struct intel_ring_buffer *ring,
128                             u32 value)
129 {
130         drm_i915_private_t *dev_priv = ring->dev->dev_private;
131         I915_WRITE_TAIL(ring, value);
132 }
133
134 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
135 {
136         drm_i915_private_t *dev_priv = ring->dev->dev_private;
137         u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
138                         RING_ACTHD(ring->mmio_base) : ACTHD;
139
140         return I915_READ(acthd_reg);
141 }
142
143 static int init_ring_common(struct intel_ring_buffer *ring)
144 {
145         drm_i915_private_t *dev_priv = ring->dev->dev_private;
146         struct drm_i915_gem_object *obj = ring->obj;
147         u32 head;
148
149         /* Stop the ring if it's running. */
150         I915_WRITE_CTL(ring, 0);
151         I915_WRITE_HEAD(ring, 0);
152         ring->write_tail(ring, 0);
153
154         /* Initialize the ring. */
155         I915_WRITE_START(ring, obj->gtt_offset);
156         head = I915_READ_HEAD(ring) & HEAD_ADDR;
157
158         /* G45 ring initialization fails to reset head to zero */
159         if (head != 0) {
160                 DRM_DEBUG_KMS("%s head not reset to zero "
161                               "ctl %08x head %08x tail %08x start %08x\n",
162                               ring->name,
163                               I915_READ_CTL(ring),
164                               I915_READ_HEAD(ring),
165                               I915_READ_TAIL(ring),
166                               I915_READ_START(ring));
167
168                 I915_WRITE_HEAD(ring, 0);
169
170                 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
171                         DRM_ERROR("failed to set %s head to zero "
172                                   "ctl %08x head %08x tail %08x start %08x\n",
173                                   ring->name,
174                                   I915_READ_CTL(ring),
175                                   I915_READ_HEAD(ring),
176                                   I915_READ_TAIL(ring),
177                                   I915_READ_START(ring));
178                 }
179         }
180
181         I915_WRITE_CTL(ring,
182                         ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
183                         | RING_REPORT_64K | RING_VALID);
184
185         /* If the head is still not zero, the ring is dead */
186         if ((I915_READ_CTL(ring) & RING_VALID) == 0 ||
187             I915_READ_START(ring) != obj->gtt_offset ||
188             (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) {
189                 DRM_ERROR("%s initialization failed "
190                                 "ctl %08x head %08x tail %08x start %08x\n",
191                                 ring->name,
192                                 I915_READ_CTL(ring),
193                                 I915_READ_HEAD(ring),
194                                 I915_READ_TAIL(ring),
195                                 I915_READ_START(ring));
196                 return -EIO;
197         }
198
199         if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
200                 i915_kernel_lost_context(ring->dev);
201         else {
202                 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
203                 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
204                 ring->space = ring->head - (ring->tail + 8);
205                 if (ring->space < 0)
206                         ring->space += ring->size;
207         }
208
209         return 0;
210 }
211
212 /*
213  * 965+ support PIPE_CONTROL commands, which provide finer grained control
214  * over cache flushing.
215  */
216 struct pipe_control {
217         struct drm_i915_gem_object *obj;
218         volatile u32 *cpu_page;
219         u32 gtt_offset;
220 };
221
222 static int
223 init_pipe_control(struct intel_ring_buffer *ring)
224 {
225         struct pipe_control *pc;
226         struct drm_i915_gem_object *obj;
227         int ret;
228
229         if (ring->private)
230                 return 0;
231
232         pc = kmalloc(sizeof(*pc), GFP_KERNEL);
233         if (!pc)
234                 return -ENOMEM;
235
236         obj = i915_gem_alloc_object(ring->dev, 4096);
237         if (obj == NULL) {
238                 DRM_ERROR("Failed to allocate seqno page\n");
239                 ret = -ENOMEM;
240                 goto err;
241         }
242         obj->agp_type = AGP_USER_CACHED_MEMORY;
243
244         ret = i915_gem_object_pin(obj, 4096, true);
245         if (ret)
246                 goto err_unref;
247
248         pc->gtt_offset = obj->gtt_offset;
249         pc->cpu_page =  kmap(obj->pages[0]);
250         if (pc->cpu_page == NULL)
251                 goto err_unpin;
252
253         pc->obj = obj;
254         ring->private = pc;
255         return 0;
256
257 err_unpin:
258         i915_gem_object_unpin(obj);
259 err_unref:
260         drm_gem_object_unreference(&obj->base);
261 err:
262         kfree(pc);
263         return ret;
264 }
265
266 static void
267 cleanup_pipe_control(struct intel_ring_buffer *ring)
268 {
269         struct pipe_control *pc = ring->private;
270         struct drm_i915_gem_object *obj;
271
272         if (!ring->private)
273                 return;
274
275         obj = pc->obj;
276         kunmap(obj->pages[0]);
277         i915_gem_object_unpin(obj);
278         drm_gem_object_unreference(&obj->base);
279
280         kfree(pc);
281         ring->private = NULL;
282 }
283
284 static int init_render_ring(struct intel_ring_buffer *ring)
285 {
286         struct drm_device *dev = ring->dev;
287         struct drm_i915_private *dev_priv = dev->dev_private;
288         int ret = init_ring_common(ring);
289
290         if (INTEL_INFO(dev)->gen > 3) {
291                 int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
292                 if (IS_GEN6(dev))
293                         mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
294                 I915_WRITE(MI_MODE, mode);
295         }
296
297         if (INTEL_INFO(dev)->gen >= 6) {
298         } else if (IS_GEN5(dev)) {
299                 ret = init_pipe_control(ring);
300                 if (ret)
301                         return ret;
302         }
303
304         return ret;
305 }
306
307 static void render_ring_cleanup(struct intel_ring_buffer *ring)
308 {
309         if (!ring->private)
310                 return;
311
312         cleanup_pipe_control(ring);
313 }
314
315 static void
316 update_semaphore(struct intel_ring_buffer *ring, int i, u32 seqno)
317 {
318         struct drm_device *dev = ring->dev;
319         struct drm_i915_private *dev_priv = dev->dev_private;
320         int id;
321
322         /*
323          * cs -> 1 = vcs, 0 = bcs
324          * vcs -> 1 = bcs, 0 = cs,
325          * bcs -> 1 = cs, 0 = vcs.
326          */
327         id = ring - dev_priv->ring;
328         id += 2 - i;
329         id %= 3;
330
331         intel_ring_emit(ring,
332                         MI_SEMAPHORE_MBOX |
333                         MI_SEMAPHORE_REGISTER |
334                         MI_SEMAPHORE_UPDATE);
335         intel_ring_emit(ring, seqno);
336         intel_ring_emit(ring,
337                         RING_SYNC_0(dev_priv->ring[id].mmio_base) + 4*i);
338 }
339
340 static int
341 gen6_add_request(struct intel_ring_buffer *ring,
342                  u32 *result)
343 {
344         u32 seqno;
345         int ret;
346
347         ret = intel_ring_begin(ring, 10);
348         if (ret)
349                 return ret;
350
351         seqno = i915_gem_get_seqno(ring->dev);
352         update_semaphore(ring, 0, seqno);
353         update_semaphore(ring, 1, seqno);
354
355         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
356         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
357         intel_ring_emit(ring, seqno);
358         intel_ring_emit(ring, MI_USER_INTERRUPT);
359         intel_ring_advance(ring);
360
361         *result = seqno;
362         return 0;
363 }
364
365 int
366 intel_ring_sync(struct intel_ring_buffer *ring,
367                 struct intel_ring_buffer *to,
368                 u32 seqno)
369 {
370         int ret;
371
372         ret = intel_ring_begin(ring, 4);
373         if (ret)
374                 return ret;
375
376         intel_ring_emit(ring,
377                         MI_SEMAPHORE_MBOX |
378                         MI_SEMAPHORE_REGISTER |
379                         intel_ring_sync_index(ring, to) << 17 |
380                         MI_SEMAPHORE_COMPARE);
381         intel_ring_emit(ring, seqno);
382         intel_ring_emit(ring, 0);
383         intel_ring_emit(ring, MI_NOOP);
384         intel_ring_advance(ring);
385
386         return 0;
387 }
388
389 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
390 do {                                                                    \
391         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |           \
392                  PIPE_CONTROL_DEPTH_STALL | 2);                         \
393         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
394         intel_ring_emit(ring__, 0);                                                     \
395         intel_ring_emit(ring__, 0);                                                     \
396 } while (0)
397
398 static int
399 pc_render_add_request(struct intel_ring_buffer *ring,
400                       u32 *result)
401 {
402         struct drm_device *dev = ring->dev;
403         u32 seqno = i915_gem_get_seqno(dev);
404         struct pipe_control *pc = ring->private;
405         u32 scratch_addr = pc->gtt_offset + 128;
406         int ret;
407
408         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
409          * incoherent with writes to memory, i.e. completely fubar,
410          * so we need to use PIPE_NOTIFY instead.
411          *
412          * However, we also need to workaround the qword write
413          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
414          * memory before requesting an interrupt.
415          */
416         ret = intel_ring_begin(ring, 32);
417         if (ret)
418                 return ret;
419
420         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
421                         PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH);
422         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
423         intel_ring_emit(ring, seqno);
424         intel_ring_emit(ring, 0);
425         PIPE_CONTROL_FLUSH(ring, scratch_addr);
426         scratch_addr += 128; /* write to separate cachelines */
427         PIPE_CONTROL_FLUSH(ring, scratch_addr);
428         scratch_addr += 128;
429         PIPE_CONTROL_FLUSH(ring, scratch_addr);
430         scratch_addr += 128;
431         PIPE_CONTROL_FLUSH(ring, scratch_addr);
432         scratch_addr += 128;
433         PIPE_CONTROL_FLUSH(ring, scratch_addr);
434         scratch_addr += 128;
435         PIPE_CONTROL_FLUSH(ring, scratch_addr);
436         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
437                         PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
438                         PIPE_CONTROL_NOTIFY);
439         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
440         intel_ring_emit(ring, seqno);
441         intel_ring_emit(ring, 0);
442         intel_ring_advance(ring);
443
444         *result = seqno;
445         return 0;
446 }
447
448 static int
449 render_ring_add_request(struct intel_ring_buffer *ring,
450                         u32 *result)
451 {
452         struct drm_device *dev = ring->dev;
453         u32 seqno = i915_gem_get_seqno(dev);
454         int ret;
455
456         ret = intel_ring_begin(ring, 4);
457         if (ret)
458                 return ret;
459
460         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
461         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
462         intel_ring_emit(ring, seqno);
463         intel_ring_emit(ring, MI_USER_INTERRUPT);
464         intel_ring_advance(ring);
465
466         *result = seqno;
467         return 0;
468 }
469
470 static u32
471 ring_get_seqno(struct intel_ring_buffer *ring)
472 {
473         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
474 }
475
476 static u32
477 pc_render_get_seqno(struct intel_ring_buffer *ring)
478 {
479         struct pipe_control *pc = ring->private;
480         return pc->cpu_page[0];
481 }
482
483 static bool
484 render_ring_get_irq(struct intel_ring_buffer *ring)
485 {
486         struct drm_device *dev = ring->dev;
487
488         if (!dev->irq_enabled)
489                 return false;
490
491         if (atomic_inc_return(&ring->irq_refcount) == 1) {
492                 drm_i915_private_t *dev_priv = dev->dev_private;
493                 unsigned long irqflags;
494
495                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
496                 if (HAS_PCH_SPLIT(dev))
497                         ironlake_enable_graphics_irq(dev_priv,
498                                                      GT_PIPE_NOTIFY | GT_USER_INTERRUPT);
499                 else
500                         i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
501                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
502         }
503
504         return true;
505 }
506
507 static void
508 render_ring_put_irq(struct intel_ring_buffer *ring)
509 {
510         struct drm_device *dev = ring->dev;
511
512         if (atomic_dec_and_test(&ring->irq_refcount)) {
513                 drm_i915_private_t *dev_priv = dev->dev_private;
514                 unsigned long irqflags;
515
516                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
517                 if (HAS_PCH_SPLIT(dev))
518                         ironlake_disable_graphics_irq(dev_priv,
519                                                       GT_USER_INTERRUPT |
520                                                       GT_PIPE_NOTIFY);
521                 else
522                         i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
523                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
524         }
525 }
526
527 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
528 {
529         drm_i915_private_t *dev_priv = ring->dev->dev_private;
530         u32 mmio = IS_GEN6(ring->dev) ?
531                 RING_HWS_PGA_GEN6(ring->mmio_base) :
532                 RING_HWS_PGA(ring->mmio_base);
533         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
534         POSTING_READ(mmio);
535 }
536
537 static void
538 bsd_ring_flush(struct intel_ring_buffer *ring,
539                u32     invalidate_domains,
540                u32     flush_domains)
541 {
542         if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
543                 return;
544
545         if (intel_ring_begin(ring, 2) == 0) {
546                 intel_ring_emit(ring, MI_FLUSH);
547                 intel_ring_emit(ring, MI_NOOP);
548                 intel_ring_advance(ring);
549         }
550 }
551
552 static int
553 ring_add_request(struct intel_ring_buffer *ring,
554                  u32 *result)
555 {
556         u32 seqno;
557         int ret;
558
559         ret = intel_ring_begin(ring, 4);
560         if (ret)
561                 return ret;
562
563         seqno = i915_gem_get_seqno(ring->dev);
564
565         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
566         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
567         intel_ring_emit(ring, seqno);
568         intel_ring_emit(ring, MI_USER_INTERRUPT);
569         intel_ring_advance(ring);
570
571         DRM_DEBUG_DRIVER("%s %d\n", ring->name, seqno);
572         *result = seqno;
573         return 0;
574 }
575
576 static bool
577 ring_get_irq(struct intel_ring_buffer *ring, u32 flag)
578 {
579         struct drm_device *dev = ring->dev;
580
581         if (!dev->irq_enabled)
582                return false;
583
584         if (atomic_inc_return(&ring->irq_refcount) == 1) {
585                 drm_i915_private_t *dev_priv = dev->dev_private;
586                 unsigned long irqflags;
587
588                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
589                 ironlake_enable_graphics_irq(dev_priv, flag);
590                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
591         }
592
593         return true;
594 }
595
596 static void
597 ring_put_irq(struct intel_ring_buffer *ring, u32 flag)
598 {
599         struct drm_device *dev = ring->dev;
600
601         if (atomic_dec_and_test(&ring->irq_refcount)) {
602                 drm_i915_private_t *dev_priv = dev->dev_private;
603                 unsigned long irqflags;
604
605                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
606                 ironlake_disable_graphics_irq(dev_priv, flag);
607                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
608         }
609 }
610
611 static bool
612 bsd_ring_get_irq(struct intel_ring_buffer *ring)
613 {
614         return ring_get_irq(ring, GT_BSD_USER_INTERRUPT);
615 }
616 static void
617 bsd_ring_put_irq(struct intel_ring_buffer *ring)
618 {
619         ring_put_irq(ring, GT_BSD_USER_INTERRUPT);
620 }
621
622 static int
623 ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
624 {
625         int ret;
626
627         ret = intel_ring_begin(ring, 2);
628         if (ret)
629                 return ret;
630
631         intel_ring_emit(ring,
632                         MI_BATCH_BUFFER_START | (2 << 6) |
633                         MI_BATCH_NON_SECURE_I965);
634         intel_ring_emit(ring, offset);
635         intel_ring_advance(ring);
636
637         return 0;
638 }
639
640 static int
641 render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
642                                 u32 offset, u32 len)
643 {
644         struct drm_device *dev = ring->dev;
645         drm_i915_private_t *dev_priv = dev->dev_private;
646         int ret;
647
648         trace_i915_gem_request_submit(dev, dev_priv->next_seqno + 1);
649
650         if (IS_I830(dev) || IS_845G(dev)) {
651                 ret = intel_ring_begin(ring, 4);
652                 if (ret)
653                         return ret;
654
655                 intel_ring_emit(ring, MI_BATCH_BUFFER);
656                 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
657                 intel_ring_emit(ring, offset + len - 8);
658                 intel_ring_emit(ring, 0);
659         } else {
660                 ret = intel_ring_begin(ring, 2);
661                 if (ret)
662                         return ret;
663
664                 if (INTEL_INFO(dev)->gen >= 4) {
665                         intel_ring_emit(ring,
666                                         MI_BATCH_BUFFER_START | (2 << 6) |
667                                         MI_BATCH_NON_SECURE_I965);
668                         intel_ring_emit(ring, offset);
669                 } else {
670                         intel_ring_emit(ring,
671                                         MI_BATCH_BUFFER_START | (2 << 6));
672                         intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
673                 }
674         }
675         intel_ring_advance(ring);
676
677         return 0;
678 }
679
680 static void cleanup_status_page(struct intel_ring_buffer *ring)
681 {
682         drm_i915_private_t *dev_priv = ring->dev->dev_private;
683         struct drm_i915_gem_object *obj;
684
685         obj = ring->status_page.obj;
686         if (obj == NULL)
687                 return;
688
689         kunmap(obj->pages[0]);
690         i915_gem_object_unpin(obj);
691         drm_gem_object_unreference(&obj->base);
692         ring->status_page.obj = NULL;
693
694         memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
695 }
696
697 static int init_status_page(struct intel_ring_buffer *ring)
698 {
699         struct drm_device *dev = ring->dev;
700         drm_i915_private_t *dev_priv = dev->dev_private;
701         struct drm_i915_gem_object *obj;
702         int ret;
703
704         obj = i915_gem_alloc_object(dev, 4096);
705         if (obj == NULL) {
706                 DRM_ERROR("Failed to allocate status page\n");
707                 ret = -ENOMEM;
708                 goto err;
709         }
710         obj->agp_type = AGP_USER_CACHED_MEMORY;
711
712         ret = i915_gem_object_pin(obj, 4096, true);
713         if (ret != 0) {
714                 goto err_unref;
715         }
716
717         ring->status_page.gfx_addr = obj->gtt_offset;
718         ring->status_page.page_addr = kmap(obj->pages[0]);
719         if (ring->status_page.page_addr == NULL) {
720                 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
721                 goto err_unpin;
722         }
723         ring->status_page.obj = obj;
724         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
725
726         intel_ring_setup_status_page(ring);
727         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
728                         ring->name, ring->status_page.gfx_addr);
729
730         return 0;
731
732 err_unpin:
733         i915_gem_object_unpin(obj);
734 err_unref:
735         drm_gem_object_unreference(&obj->base);
736 err:
737         return ret;
738 }
739
740 int intel_init_ring_buffer(struct drm_device *dev,
741                            struct intel_ring_buffer *ring)
742 {
743         struct drm_i915_gem_object *obj;
744         int ret;
745
746         ring->dev = dev;
747         INIT_LIST_HEAD(&ring->active_list);
748         INIT_LIST_HEAD(&ring->request_list);
749         INIT_LIST_HEAD(&ring->gpu_write_list);
750
751         if (I915_NEED_GFX_HWS(dev)) {
752                 ret = init_status_page(ring);
753                 if (ret)
754                         return ret;
755         }
756
757         obj = i915_gem_alloc_object(dev, ring->size);
758         if (obj == NULL) {
759                 DRM_ERROR("Failed to allocate ringbuffer\n");
760                 ret = -ENOMEM;
761                 goto err_hws;
762         }
763
764         ring->obj = obj;
765
766         ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
767         if (ret)
768                 goto err_unref;
769
770         ring->map.size = ring->size;
771         ring->map.offset = dev->agp->base + obj->gtt_offset;
772         ring->map.type = 0;
773         ring->map.flags = 0;
774         ring->map.mtrr = 0;
775
776         drm_core_ioremap_wc(&ring->map, dev);
777         if (ring->map.handle == NULL) {
778                 DRM_ERROR("Failed to map ringbuffer.\n");
779                 ret = -EINVAL;
780                 goto err_unpin;
781         }
782
783         ring->virtual_start = ring->map.handle;
784         ret = ring->init(ring);
785         if (ret)
786                 goto err_unmap;
787
788         /* Workaround an erratum on the i830 which causes a hang if
789          * the TAIL pointer points to within the last 2 cachelines
790          * of the buffer.
791          */
792         ring->effective_size = ring->size;
793         if (IS_I830(ring->dev))
794                 ring->effective_size -= 128;
795
796         return 0;
797
798 err_unmap:
799         drm_core_ioremapfree(&ring->map, dev);
800 err_unpin:
801         i915_gem_object_unpin(obj);
802 err_unref:
803         drm_gem_object_unreference(&obj->base);
804         ring->obj = NULL;
805 err_hws:
806         cleanup_status_page(ring);
807         return ret;
808 }
809
810 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
811 {
812         struct drm_i915_private *dev_priv;
813         int ret;
814
815         if (ring->obj == NULL)
816                 return;
817
818         /* Disable the ring buffer. The ring must be idle at this point */
819         dev_priv = ring->dev->dev_private;
820         ret = intel_wait_ring_buffer(ring, ring->size - 8);
821         I915_WRITE_CTL(ring, 0);
822
823         drm_core_ioremapfree(&ring->map, ring->dev);
824
825         i915_gem_object_unpin(ring->obj);
826         drm_gem_object_unreference(&ring->obj->base);
827         ring->obj = NULL;
828
829         if (ring->cleanup)
830                 ring->cleanup(ring);
831
832         cleanup_status_page(ring);
833 }
834
835 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
836 {
837         unsigned int *virt;
838         int rem = ring->size - ring->tail;
839
840         if (ring->space < rem) {
841                 int ret = intel_wait_ring_buffer(ring, rem);
842                 if (ret)
843                         return ret;
844         }
845
846         virt = (unsigned int *)(ring->virtual_start + ring->tail);
847         rem /= 8;
848         while (rem--) {
849                 *virt++ = MI_NOOP;
850                 *virt++ = MI_NOOP;
851         }
852
853         ring->tail = 0;
854         ring->space = ring->head - 8;
855
856         return 0;
857 }
858
859 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
860 {
861         struct drm_device *dev = ring->dev;
862         struct drm_i915_private *dev_priv = dev->dev_private;
863         unsigned long end;
864         u32 head;
865
866         trace_i915_ring_wait_begin (dev);
867         end = jiffies + 3 * HZ;
868         do {
869                 /* If the reported head position has wrapped or hasn't advanced,
870                  * fallback to the slow and accurate path.
871                  */
872                 head = intel_read_status_page(ring, 4);
873                 if (head < ring->actual_head)
874                         head = I915_READ_HEAD(ring);
875                 ring->actual_head = head;
876                 ring->head = head & HEAD_ADDR;
877                 ring->space = ring->head - (ring->tail + 8);
878                 if (ring->space < 0)
879                         ring->space += ring->size;
880                 if (ring->space >= n) {
881                         trace_i915_ring_wait_end(dev);
882                         return 0;
883                 }
884
885                 if (dev->primary->master) {
886                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
887                         if (master_priv->sarea_priv)
888                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
889                 }
890
891                 msleep(1);
892                 if (atomic_read(&dev_priv->mm.wedged))
893                         return -EAGAIN;
894         } while (!time_after(jiffies, end));
895         trace_i915_ring_wait_end (dev);
896         return -EBUSY;
897 }
898
899 int intel_ring_begin(struct intel_ring_buffer *ring,
900                      int num_dwords)
901 {
902         int n = 4*num_dwords;
903         int ret;
904
905         if (unlikely(ring->tail + n > ring->effective_size)) {
906                 ret = intel_wrap_ring_buffer(ring);
907                 if (unlikely(ret))
908                         return ret;
909         }
910
911         if (unlikely(ring->space < n)) {
912                 ret = intel_wait_ring_buffer(ring, n);
913                 if (unlikely(ret))
914                         return ret;
915         }
916
917         ring->space -= n;
918         return 0;
919 }
920
921 void intel_ring_advance(struct intel_ring_buffer *ring)
922 {
923         ring->tail &= ring->size - 1;
924         ring->write_tail(ring, ring->tail);
925 }
926
927 static const struct intel_ring_buffer render_ring = {
928         .name                   = "render ring",
929         .id                     = RING_RENDER,
930         .mmio_base              = RENDER_RING_BASE,
931         .size                   = 32 * PAGE_SIZE,
932         .init                   = init_render_ring,
933         .write_tail             = ring_write_tail,
934         .flush                  = render_ring_flush,
935         .add_request            = render_ring_add_request,
936         .get_seqno              = ring_get_seqno,
937         .irq_get                = render_ring_get_irq,
938         .irq_put                = render_ring_put_irq,
939         .dispatch_execbuffer    = render_ring_dispatch_execbuffer,
940        .cleanup                 = render_ring_cleanup,
941 };
942
943 /* ring buffer for bit-stream decoder */
944
945 static const struct intel_ring_buffer bsd_ring = {
946         .name                   = "bsd ring",
947         .id                     = RING_BSD,
948         .mmio_base              = BSD_RING_BASE,
949         .size                   = 32 * PAGE_SIZE,
950         .init                   = init_ring_common,
951         .write_tail             = ring_write_tail,
952         .flush                  = bsd_ring_flush,
953         .add_request            = ring_add_request,
954         .get_seqno              = ring_get_seqno,
955         .irq_get                = bsd_ring_get_irq,
956         .irq_put                = bsd_ring_put_irq,
957         .dispatch_execbuffer    = ring_dispatch_execbuffer,
958 };
959
960
961 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
962                                      u32 value)
963 {
964        drm_i915_private_t *dev_priv = ring->dev->dev_private;
965
966        /* Every tail move must follow the sequence below */
967        I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
968                GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
969                GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
970        I915_WRITE(GEN6_BSD_RNCID, 0x0);
971
972        if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
973                                GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
974                        50))
975                DRM_ERROR("timed out waiting for IDLE Indicator\n");
976
977        I915_WRITE_TAIL(ring, value);
978        I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
979                GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
980                GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
981 }
982
983 static void gen6_ring_flush(struct intel_ring_buffer *ring,
984                             u32 invalidate_domains,
985                             u32 flush_domains)
986 {
987         if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
988                 return;
989
990         if (intel_ring_begin(ring, 4) == 0) {
991                 intel_ring_emit(ring, MI_FLUSH_DW);
992                 intel_ring_emit(ring, 0);
993                 intel_ring_emit(ring, 0);
994                 intel_ring_emit(ring, 0);
995                 intel_ring_advance(ring);
996         }
997 }
998
999 static int
1000 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1001                               u32 offset, u32 len)
1002 {
1003        int ret;
1004
1005        ret = intel_ring_begin(ring, 2);
1006        if (ret)
1007                return ret;
1008
1009        intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1010        /* bit0-7 is the length on GEN6+ */
1011        intel_ring_emit(ring, offset);
1012        intel_ring_advance(ring);
1013
1014        return 0;
1015 }
1016
1017 static bool
1018 gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring)
1019 {
1020         return ring_get_irq(ring, GT_GEN6_BSD_USER_INTERRUPT);
1021 }
1022
1023 static void
1024 gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring)
1025 {
1026         ring_put_irq(ring, GT_GEN6_BSD_USER_INTERRUPT);
1027 }
1028
1029 /* ring buffer for Video Codec for Gen6+ */
1030 static const struct intel_ring_buffer gen6_bsd_ring = {
1031         .name                   = "gen6 bsd ring",
1032         .id                     = RING_BSD,
1033         .mmio_base              = GEN6_BSD_RING_BASE,
1034         .size                   = 32 * PAGE_SIZE,
1035         .init                   = init_ring_common,
1036         .write_tail             = gen6_bsd_ring_write_tail,
1037         .flush                  = gen6_ring_flush,
1038         .add_request            = gen6_add_request,
1039         .get_seqno              = ring_get_seqno,
1040         .irq_get                = gen6_bsd_ring_get_irq,
1041         .irq_put                = gen6_bsd_ring_put_irq,
1042         .dispatch_execbuffer    = gen6_ring_dispatch_execbuffer,
1043 };
1044
1045 /* Blitter support (SandyBridge+) */
1046
1047 static bool
1048 blt_ring_get_irq(struct intel_ring_buffer *ring)
1049 {
1050         return ring_get_irq(ring, GT_BLT_USER_INTERRUPT);
1051 }
1052
1053 static void
1054 blt_ring_put_irq(struct intel_ring_buffer *ring)
1055 {
1056         ring_put_irq(ring, GT_BLT_USER_INTERRUPT);
1057 }
1058
1059
1060 /* Workaround for some stepping of SNB,
1061  * each time when BLT engine ring tail moved,
1062  * the first command in the ring to be parsed
1063  * should be MI_BATCH_BUFFER_START
1064  */
1065 #define NEED_BLT_WORKAROUND(dev) \
1066         (IS_GEN6(dev) && (dev->pdev->revision < 8))
1067
1068 static inline struct drm_i915_gem_object *
1069 to_blt_workaround(struct intel_ring_buffer *ring)
1070 {
1071         return ring->private;
1072 }
1073
1074 static int blt_ring_init(struct intel_ring_buffer *ring)
1075 {
1076         if (NEED_BLT_WORKAROUND(ring->dev)) {
1077                 struct drm_i915_gem_object *obj;
1078                 u32 *ptr;
1079                 int ret;
1080
1081                 obj = i915_gem_alloc_object(ring->dev, 4096);
1082                 if (obj == NULL)
1083                         return -ENOMEM;
1084
1085                 ret = i915_gem_object_pin(obj, 4096, true);
1086                 if (ret) {
1087                         drm_gem_object_unreference(&obj->base);
1088                         return ret;
1089                 }
1090
1091                 ptr = kmap(obj->pages[0]);
1092                 *ptr++ = MI_BATCH_BUFFER_END;
1093                 *ptr++ = MI_NOOP;
1094                 kunmap(obj->pages[0]);
1095
1096                 ret = i915_gem_object_set_to_gtt_domain(obj, false);
1097                 if (ret) {
1098                         i915_gem_object_unpin(obj);
1099                         drm_gem_object_unreference(&obj->base);
1100                         return ret;
1101                 }
1102
1103                 ring->private = obj;
1104         }
1105
1106         return init_ring_common(ring);
1107 }
1108
1109 static int blt_ring_begin(struct intel_ring_buffer *ring,
1110                           int num_dwords)
1111 {
1112         if (ring->private) {
1113                 int ret = intel_ring_begin(ring, num_dwords+2);
1114                 if (ret)
1115                         return ret;
1116
1117                 intel_ring_emit(ring, MI_BATCH_BUFFER_START);
1118                 intel_ring_emit(ring, to_blt_workaround(ring)->gtt_offset);
1119
1120                 return 0;
1121         } else
1122                 return intel_ring_begin(ring, 4);
1123 }
1124
1125 static void blt_ring_flush(struct intel_ring_buffer *ring,
1126                            u32 invalidate_domains,
1127                            u32 flush_domains)
1128 {
1129         if ((flush_domains & I915_GEM_DOMAIN_RENDER) == 0)
1130                 return;
1131
1132         if (blt_ring_begin(ring, 4) == 0) {
1133                 intel_ring_emit(ring, MI_FLUSH_DW);
1134                 intel_ring_emit(ring, 0);
1135                 intel_ring_emit(ring, 0);
1136                 intel_ring_emit(ring, 0);
1137                 intel_ring_advance(ring);
1138         }
1139 }
1140
1141 static void blt_ring_cleanup(struct intel_ring_buffer *ring)
1142 {
1143         if (!ring->private)
1144                 return;
1145
1146         i915_gem_object_unpin(ring->private);
1147         drm_gem_object_unreference(ring->private);
1148         ring->private = NULL;
1149 }
1150
1151 static const struct intel_ring_buffer gen6_blt_ring = {
1152        .name                    = "blt ring",
1153        .id                      = RING_BLT,
1154        .mmio_base               = BLT_RING_BASE,
1155        .size                    = 32 * PAGE_SIZE,
1156        .init                    = blt_ring_init,
1157        .write_tail              = ring_write_tail,
1158        .flush                   = blt_ring_flush,
1159        .add_request             = gen6_add_request,
1160        .get_seqno               = ring_get_seqno,
1161        .irq_get                 = blt_ring_get_irq,
1162        .irq_put                 = blt_ring_put_irq,
1163        .dispatch_execbuffer     = gen6_ring_dispatch_execbuffer,
1164        .cleanup                 = blt_ring_cleanup,
1165 };
1166
1167 int intel_init_render_ring_buffer(struct drm_device *dev)
1168 {
1169         drm_i915_private_t *dev_priv = dev->dev_private;
1170         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1171
1172         *ring = render_ring;
1173         if (INTEL_INFO(dev)->gen >= 6) {
1174                 ring->add_request = gen6_add_request;
1175         } else if (IS_GEN5(dev)) {
1176                 ring->add_request = pc_render_add_request;
1177                 ring->get_seqno = pc_render_get_seqno;
1178         }
1179
1180         if (!I915_NEED_GFX_HWS(dev)) {
1181                 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1182                 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1183         }
1184
1185         return intel_init_ring_buffer(dev, ring);
1186 }
1187
1188 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1189 {
1190         drm_i915_private_t *dev_priv = dev->dev_private;
1191         struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1192
1193         if (IS_GEN6(dev))
1194                 *ring = gen6_bsd_ring;
1195         else
1196                 *ring = bsd_ring;
1197
1198         return intel_init_ring_buffer(dev, ring);
1199 }
1200
1201 int intel_init_blt_ring_buffer(struct drm_device *dev)
1202 {
1203         drm_i915_private_t *dev_priv = dev->dev_private;
1204         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1205
1206         *ring = gen6_blt_ring;
1207
1208         return intel_init_ring_buffer(dev, ring);
1209 }