drm/i915: Work around gen7 BLT ring synchronization issues.
[linux-2.6.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2  * Copyright © 2008-2010 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Authors:
24  *    Eric Anholt <eric@anholt.net>
25  *    Zou Nan hai <nanhai.zou@intel.com>
26  *    Xiang Hai hao<haihao.xiang@intel.com>
27  *
28  */
29
30 #include "drmP.h"
31 #include "drm.h"
32 #include "i915_drv.h"
33 #include "i915_drm.h"
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36
37 /*
38  * 965+ support PIPE_CONTROL commands, which provide finer grained control
39  * over cache flushing.
40  */
41 struct pipe_control {
42         struct drm_i915_gem_object *obj;
43         volatile u32 *cpu_page;
44         u32 gtt_offset;
45 };
46
47 static inline int ring_space(struct intel_ring_buffer *ring)
48 {
49         int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
50         if (space < 0)
51                 space += ring->size;
52         return space;
53 }
54
55 static u32 i915_gem_get_seqno(struct drm_device *dev)
56 {
57         drm_i915_private_t *dev_priv = dev->dev_private;
58         u32 seqno;
59
60         seqno = dev_priv->next_seqno;
61
62         /* reserve 0 for non-seqno */
63         if (++dev_priv->next_seqno == 0)
64                 dev_priv->next_seqno = 1;
65
66         return seqno;
67 }
68
69 static int
70 render_ring_flush(struct intel_ring_buffer *ring,
71                   u32   invalidate_domains,
72                   u32   flush_domains)
73 {
74         struct drm_device *dev = ring->dev;
75         u32 cmd;
76         int ret;
77
78         /*
79          * read/write caches:
80          *
81          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
82          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
83          * also flushed at 2d versus 3d pipeline switches.
84          *
85          * read-only caches:
86          *
87          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
88          * MI_READ_FLUSH is set, and is always flushed on 965.
89          *
90          * I915_GEM_DOMAIN_COMMAND may not exist?
91          *
92          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
93          * invalidated when MI_EXE_FLUSH is set.
94          *
95          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
96          * invalidated with every MI_FLUSH.
97          *
98          * TLBs:
99          *
100          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
101          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
102          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
103          * are flushed at any MI_FLUSH.
104          */
105
106         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
107         if ((invalidate_domains|flush_domains) &
108             I915_GEM_DOMAIN_RENDER)
109                 cmd &= ~MI_NO_WRITE_FLUSH;
110         if (INTEL_INFO(dev)->gen < 4) {
111                 /*
112                  * On the 965, the sampler cache always gets flushed
113                  * and this bit is reserved.
114                  */
115                 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
116                         cmd |= MI_READ_FLUSH;
117         }
118         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
119                 cmd |= MI_EXE_FLUSH;
120
121         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
122             (IS_G4X(dev) || IS_GEN5(dev)))
123                 cmd |= MI_INVALIDATE_ISP;
124
125         ret = intel_ring_begin(ring, 2);
126         if (ret)
127                 return ret;
128
129         intel_ring_emit(ring, cmd);
130         intel_ring_emit(ring, MI_NOOP);
131         intel_ring_advance(ring);
132
133         return 0;
134 }
135
136 /**
137  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
138  * implementing two workarounds on gen6.  From section 1.4.7.1
139  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
140  *
141  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
142  * produced by non-pipelined state commands), software needs to first
143  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
144  * 0.
145  *
146  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
147  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
148  *
149  * And the workaround for these two requires this workaround first:
150  *
151  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
152  * BEFORE the pipe-control with a post-sync op and no write-cache
153  * flushes.
154  *
155  * And this last workaround is tricky because of the requirements on
156  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
157  * volume 2 part 1:
158  *
159  *     "1 of the following must also be set:
160  *      - Render Target Cache Flush Enable ([12] of DW1)
161  *      - Depth Cache Flush Enable ([0] of DW1)
162  *      - Stall at Pixel Scoreboard ([1] of DW1)
163  *      - Depth Stall ([13] of DW1)
164  *      - Post-Sync Operation ([13] of DW1)
165  *      - Notify Enable ([8] of DW1)"
166  *
167  * The cache flushes require the workaround flush that triggered this
168  * one, so we can't use it.  Depth stall would trigger the same.
169  * Post-sync nonzero is what triggered this second workaround, so we
170  * can't use that one either.  Notify enable is IRQs, which aren't
171  * really our business.  That leaves only stall at scoreboard.
172  */
173 static int
174 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
175 {
176         struct pipe_control *pc = ring->private;
177         u32 scratch_addr = pc->gtt_offset + 128;
178         int ret;
179
180
181         ret = intel_ring_begin(ring, 6);
182         if (ret)
183                 return ret;
184
185         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
186         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
187                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
188         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
189         intel_ring_emit(ring, 0); /* low dword */
190         intel_ring_emit(ring, 0); /* high dword */
191         intel_ring_emit(ring, MI_NOOP);
192         intel_ring_advance(ring);
193
194         ret = intel_ring_begin(ring, 6);
195         if (ret)
196                 return ret;
197
198         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
199         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
200         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
201         intel_ring_emit(ring, 0);
202         intel_ring_emit(ring, 0);
203         intel_ring_emit(ring, MI_NOOP);
204         intel_ring_advance(ring);
205
206         return 0;
207 }
208
209 static int
210 gen6_render_ring_flush(struct intel_ring_buffer *ring,
211                          u32 invalidate_domains, u32 flush_domains)
212 {
213         u32 flags = 0;
214         struct pipe_control *pc = ring->private;
215         u32 scratch_addr = pc->gtt_offset + 128;
216         int ret;
217
218         /* Force SNB workarounds for PIPE_CONTROL flushes */
219         intel_emit_post_sync_nonzero_flush(ring);
220
221         /* Just flush everything.  Experiments have shown that reducing the
222          * number of bits based on the write domains has little performance
223          * impact.
224          */
225         flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
226         flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
227         flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
228         flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
229         flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
230         flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
231         flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
232
233         ret = intel_ring_begin(ring, 6);
234         if (ret)
235                 return ret;
236
237         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
238         intel_ring_emit(ring, flags);
239         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
240         intel_ring_emit(ring, 0); /* lower dword */
241         intel_ring_emit(ring, 0); /* uppwer dword */
242         intel_ring_emit(ring, MI_NOOP);
243         intel_ring_advance(ring);
244
245         return 0;
246 }
247
248 static void ring_write_tail(struct intel_ring_buffer *ring,
249                             u32 value)
250 {
251         drm_i915_private_t *dev_priv = ring->dev->dev_private;
252         I915_WRITE_TAIL(ring, value);
253 }
254
255 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
256 {
257         drm_i915_private_t *dev_priv = ring->dev->dev_private;
258         u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
259                         RING_ACTHD(ring->mmio_base) : ACTHD;
260
261         return I915_READ(acthd_reg);
262 }
263
264 static int init_ring_common(struct intel_ring_buffer *ring)
265 {
266         drm_i915_private_t *dev_priv = ring->dev->dev_private;
267         struct drm_i915_gem_object *obj = ring->obj;
268         u32 head;
269
270         /* Stop the ring if it's running. */
271         I915_WRITE_CTL(ring, 0);
272         I915_WRITE_HEAD(ring, 0);
273         ring->write_tail(ring, 0);
274
275         /* Initialize the ring. */
276         I915_WRITE_START(ring, obj->gtt_offset);
277         head = I915_READ_HEAD(ring) & HEAD_ADDR;
278
279         /* G45 ring initialization fails to reset head to zero */
280         if (head != 0) {
281                 DRM_DEBUG_KMS("%s head not reset to zero "
282                               "ctl %08x head %08x tail %08x start %08x\n",
283                               ring->name,
284                               I915_READ_CTL(ring),
285                               I915_READ_HEAD(ring),
286                               I915_READ_TAIL(ring),
287                               I915_READ_START(ring));
288
289                 I915_WRITE_HEAD(ring, 0);
290
291                 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
292                         DRM_ERROR("failed to set %s head to zero "
293                                   "ctl %08x head %08x tail %08x start %08x\n",
294                                   ring->name,
295                                   I915_READ_CTL(ring),
296                                   I915_READ_HEAD(ring),
297                                   I915_READ_TAIL(ring),
298                                   I915_READ_START(ring));
299                 }
300         }
301
302         I915_WRITE_CTL(ring,
303                         ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
304                         | RING_REPORT_64K | RING_VALID);
305
306         /* If the head is still not zero, the ring is dead */
307         if ((I915_READ_CTL(ring) & RING_VALID) == 0 ||
308             I915_READ_START(ring) != obj->gtt_offset ||
309             (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) {
310                 DRM_ERROR("%s initialization failed "
311                                 "ctl %08x head %08x tail %08x start %08x\n",
312                                 ring->name,
313                                 I915_READ_CTL(ring),
314                                 I915_READ_HEAD(ring),
315                                 I915_READ_TAIL(ring),
316                                 I915_READ_START(ring));
317                 return -EIO;
318         }
319
320         if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
321                 i915_kernel_lost_context(ring->dev);
322         else {
323                 ring->head = I915_READ_HEAD(ring);
324                 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
325                 ring->space = ring_space(ring);
326         }
327
328         return 0;
329 }
330
331 static int
332 init_pipe_control(struct intel_ring_buffer *ring)
333 {
334         struct pipe_control *pc;
335         struct drm_i915_gem_object *obj;
336         int ret;
337
338         if (ring->private)
339                 return 0;
340
341         pc = kmalloc(sizeof(*pc), GFP_KERNEL);
342         if (!pc)
343                 return -ENOMEM;
344
345         obj = i915_gem_alloc_object(ring->dev, 4096);
346         if (obj == NULL) {
347                 DRM_ERROR("Failed to allocate seqno page\n");
348                 ret = -ENOMEM;
349                 goto err;
350         }
351
352         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
353
354         ret = i915_gem_object_pin(obj, 4096, true);
355         if (ret)
356                 goto err_unref;
357
358         pc->gtt_offset = obj->gtt_offset;
359         pc->cpu_page =  kmap(obj->pages[0]);
360         if (pc->cpu_page == NULL)
361                 goto err_unpin;
362
363         pc->obj = obj;
364         ring->private = pc;
365         return 0;
366
367 err_unpin:
368         i915_gem_object_unpin(obj);
369 err_unref:
370         drm_gem_object_unreference(&obj->base);
371 err:
372         kfree(pc);
373         return ret;
374 }
375
376 static void
377 cleanup_pipe_control(struct intel_ring_buffer *ring)
378 {
379         struct pipe_control *pc = ring->private;
380         struct drm_i915_gem_object *obj;
381
382         if (!ring->private)
383                 return;
384
385         obj = pc->obj;
386         kunmap(obj->pages[0]);
387         i915_gem_object_unpin(obj);
388         drm_gem_object_unreference(&obj->base);
389
390         kfree(pc);
391         ring->private = NULL;
392 }
393
394 static int init_render_ring(struct intel_ring_buffer *ring)
395 {
396         struct drm_device *dev = ring->dev;
397         struct drm_i915_private *dev_priv = dev->dev_private;
398         int ret = init_ring_common(ring);
399
400         if (INTEL_INFO(dev)->gen > 3) {
401                 int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
402                 if (IS_GEN6(dev) || IS_GEN7(dev))
403                         mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
404                 I915_WRITE(MI_MODE, mode);
405                 if (IS_GEN7(dev))
406                         I915_WRITE(GFX_MODE_GEN7,
407                                    GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
408                                    GFX_MODE_ENABLE(GFX_REPLAY_MODE));
409         }
410
411         if (INTEL_INFO(dev)->gen >= 5) {
412                 ret = init_pipe_control(ring);
413                 if (ret)
414                         return ret;
415         }
416
417         if (INTEL_INFO(dev)->gen >= 6) {
418                 I915_WRITE(INSTPM,
419                            INSTPM_FORCE_ORDERING << 16 | INSTPM_FORCE_ORDERING);
420         }
421
422         return ret;
423 }
424
425 static void render_ring_cleanup(struct intel_ring_buffer *ring)
426 {
427         if (!ring->private)
428                 return;
429
430         cleanup_pipe_control(ring);
431 }
432
433 static void
434 update_mboxes(struct intel_ring_buffer *ring,
435             u32 seqno,
436             u32 mmio_offset)
437 {
438         intel_ring_emit(ring, MI_SEMAPHORE_MBOX |
439                               MI_SEMAPHORE_GLOBAL_GTT |
440                               MI_SEMAPHORE_REGISTER |
441                               MI_SEMAPHORE_UPDATE);
442         intel_ring_emit(ring, seqno);
443         intel_ring_emit(ring, mmio_offset);
444 }
445
446 /**
447  * gen6_add_request - Update the semaphore mailbox registers
448  * 
449  * @ring - ring that is adding a request
450  * @seqno - return seqno stuck into the ring
451  *
452  * Update the mailbox registers in the *other* rings with the current seqno.
453  * This acts like a signal in the canonical semaphore.
454  */
455 static int
456 gen6_add_request(struct intel_ring_buffer *ring,
457                  u32 *seqno)
458 {
459         u32 mbox1_reg;
460         u32 mbox2_reg;
461         int ret;
462
463         ret = intel_ring_begin(ring, 10);
464         if (ret)
465                 return ret;
466
467         mbox1_reg = ring->signal_mbox[0];
468         mbox2_reg = ring->signal_mbox[1];
469
470         *seqno = i915_gem_get_seqno(ring->dev);
471
472         update_mboxes(ring, *seqno, mbox1_reg);
473         update_mboxes(ring, *seqno, mbox2_reg);
474         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
475         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
476         intel_ring_emit(ring, *seqno);
477         intel_ring_emit(ring, MI_USER_INTERRUPT);
478         intel_ring_advance(ring);
479
480         return 0;
481 }
482
483 /**
484  * intel_ring_sync - sync the waiter to the signaller on seqno
485  *
486  * @waiter - ring that is waiting
487  * @signaller - ring which has, or will signal
488  * @seqno - seqno which the waiter will block on
489  */
490 static int
491 intel_ring_sync(struct intel_ring_buffer *waiter,
492                 struct intel_ring_buffer *signaller,
493                 int ring,
494                 u32 seqno)
495 {
496         int ret;
497         u32 dw1 = MI_SEMAPHORE_MBOX |
498                   MI_SEMAPHORE_COMPARE |
499                   MI_SEMAPHORE_REGISTER;
500
501         ret = intel_ring_begin(waiter, 4);
502         if (ret)
503                 return ret;
504
505         intel_ring_emit(waiter, dw1 | signaller->semaphore_register[ring]);
506         intel_ring_emit(waiter, seqno);
507         intel_ring_emit(waiter, 0);
508         intel_ring_emit(waiter, MI_NOOP);
509         intel_ring_advance(waiter);
510
511         return 0;
512 }
513
514 /* VCS->RCS (RVSYNC) or BCS->RCS (RBSYNC) */
515 int
516 render_ring_sync_to(struct intel_ring_buffer *waiter,
517                     struct intel_ring_buffer *signaller,
518                     u32 seqno)
519 {
520         WARN_ON(signaller->semaphore_register[RCS] == MI_SEMAPHORE_SYNC_INVALID);
521         return intel_ring_sync(waiter,
522                                signaller,
523                                RCS,
524                                seqno);
525 }
526
527 /* RCS->VCS (VRSYNC) or BCS->VCS (VBSYNC) */
528 int
529 gen6_bsd_ring_sync_to(struct intel_ring_buffer *waiter,
530                       struct intel_ring_buffer *signaller,
531                       u32 seqno)
532 {
533         WARN_ON(signaller->semaphore_register[VCS] == MI_SEMAPHORE_SYNC_INVALID);
534         return intel_ring_sync(waiter,
535                                signaller,
536                                VCS,
537                                seqno);
538 }
539
540 /* RCS->BCS (BRSYNC) or VCS->BCS (BVSYNC) */
541 int
542 gen6_blt_ring_sync_to(struct intel_ring_buffer *waiter,
543                       struct intel_ring_buffer *signaller,
544                       u32 seqno)
545 {
546         WARN_ON(signaller->semaphore_register[BCS] == MI_SEMAPHORE_SYNC_INVALID);
547         return intel_ring_sync(waiter,
548                                signaller,
549                                BCS,
550                                seqno);
551 }
552
553
554
555 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
556 do {                                                                    \
557         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
558                  PIPE_CONTROL_DEPTH_STALL);                             \
559         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
560         intel_ring_emit(ring__, 0);                                                     \
561         intel_ring_emit(ring__, 0);                                                     \
562 } while (0)
563
564 static int
565 pc_render_add_request(struct intel_ring_buffer *ring,
566                       u32 *result)
567 {
568         struct drm_device *dev = ring->dev;
569         u32 seqno = i915_gem_get_seqno(dev);
570         struct pipe_control *pc = ring->private;
571         u32 scratch_addr = pc->gtt_offset + 128;
572         int ret;
573
574         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
575          * incoherent with writes to memory, i.e. completely fubar,
576          * so we need to use PIPE_NOTIFY instead.
577          *
578          * However, we also need to workaround the qword write
579          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
580          * memory before requesting an interrupt.
581          */
582         ret = intel_ring_begin(ring, 32);
583         if (ret)
584                 return ret;
585
586         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
587                         PIPE_CONTROL_WRITE_FLUSH |
588                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
589         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
590         intel_ring_emit(ring, seqno);
591         intel_ring_emit(ring, 0);
592         PIPE_CONTROL_FLUSH(ring, scratch_addr);
593         scratch_addr += 128; /* write to separate cachelines */
594         PIPE_CONTROL_FLUSH(ring, scratch_addr);
595         scratch_addr += 128;
596         PIPE_CONTROL_FLUSH(ring, scratch_addr);
597         scratch_addr += 128;
598         PIPE_CONTROL_FLUSH(ring, scratch_addr);
599         scratch_addr += 128;
600         PIPE_CONTROL_FLUSH(ring, scratch_addr);
601         scratch_addr += 128;
602         PIPE_CONTROL_FLUSH(ring, scratch_addr);
603         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
604                         PIPE_CONTROL_WRITE_FLUSH |
605                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
606                         PIPE_CONTROL_NOTIFY);
607         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
608         intel_ring_emit(ring, seqno);
609         intel_ring_emit(ring, 0);
610         intel_ring_advance(ring);
611
612         *result = seqno;
613         return 0;
614 }
615
616 static int
617 render_ring_add_request(struct intel_ring_buffer *ring,
618                         u32 *result)
619 {
620         struct drm_device *dev = ring->dev;
621         u32 seqno = i915_gem_get_seqno(dev);
622         int ret;
623
624         ret = intel_ring_begin(ring, 4);
625         if (ret)
626                 return ret;
627
628         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
629         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
630         intel_ring_emit(ring, seqno);
631         intel_ring_emit(ring, MI_USER_INTERRUPT);
632         intel_ring_advance(ring);
633
634         *result = seqno;
635         return 0;
636 }
637
638 static u32
639 ring_get_seqno(struct intel_ring_buffer *ring)
640 {
641         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
642 }
643
644 static u32
645 pc_render_get_seqno(struct intel_ring_buffer *ring)
646 {
647         struct pipe_control *pc = ring->private;
648         return pc->cpu_page[0];
649 }
650
651 static void
652 ironlake_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
653 {
654         dev_priv->gt_irq_mask &= ~mask;
655         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
656         POSTING_READ(GTIMR);
657 }
658
659 static void
660 ironlake_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
661 {
662         dev_priv->gt_irq_mask |= mask;
663         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
664         POSTING_READ(GTIMR);
665 }
666
667 static void
668 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
669 {
670         dev_priv->irq_mask &= ~mask;
671         I915_WRITE(IMR, dev_priv->irq_mask);
672         POSTING_READ(IMR);
673 }
674
675 static void
676 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
677 {
678         dev_priv->irq_mask |= mask;
679         I915_WRITE(IMR, dev_priv->irq_mask);
680         POSTING_READ(IMR);
681 }
682
683 static bool
684 render_ring_get_irq(struct intel_ring_buffer *ring)
685 {
686         struct drm_device *dev = ring->dev;
687         drm_i915_private_t *dev_priv = dev->dev_private;
688
689         if (!dev->irq_enabled)
690                 return false;
691
692         spin_lock(&ring->irq_lock);
693         if (ring->irq_refcount++ == 0) {
694                 if (HAS_PCH_SPLIT(dev))
695                         ironlake_enable_irq(dev_priv,
696                                             GT_PIPE_NOTIFY | GT_USER_INTERRUPT);
697                 else
698                         i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
699         }
700         spin_unlock(&ring->irq_lock);
701
702         return true;
703 }
704
705 static void
706 render_ring_put_irq(struct intel_ring_buffer *ring)
707 {
708         struct drm_device *dev = ring->dev;
709         drm_i915_private_t *dev_priv = dev->dev_private;
710
711         spin_lock(&ring->irq_lock);
712         if (--ring->irq_refcount == 0) {
713                 if (HAS_PCH_SPLIT(dev))
714                         ironlake_disable_irq(dev_priv,
715                                              GT_USER_INTERRUPT |
716                                              GT_PIPE_NOTIFY);
717                 else
718                         i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
719         }
720         spin_unlock(&ring->irq_lock);
721 }
722
723 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
724 {
725         struct drm_device *dev = ring->dev;
726         drm_i915_private_t *dev_priv = ring->dev->dev_private;
727         u32 mmio = 0;
728
729         /* The ring status page addresses are no longer next to the rest of
730          * the ring registers as of gen7.
731          */
732         if (IS_GEN7(dev)) {
733                 switch (ring->id) {
734                 case RING_RENDER:
735                         mmio = RENDER_HWS_PGA_GEN7;
736                         break;
737                 case RING_BLT:
738                         mmio = BLT_HWS_PGA_GEN7;
739                         break;
740                 case RING_BSD:
741                         mmio = BSD_HWS_PGA_GEN7;
742                         break;
743                 }
744         } else if (IS_GEN6(ring->dev)) {
745                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
746         } else {
747                 mmio = RING_HWS_PGA(ring->mmio_base);
748         }
749
750         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
751         POSTING_READ(mmio);
752 }
753
754 static int
755 bsd_ring_flush(struct intel_ring_buffer *ring,
756                u32     invalidate_domains,
757                u32     flush_domains)
758 {
759         int ret;
760
761         ret = intel_ring_begin(ring, 2);
762         if (ret)
763                 return ret;
764
765         intel_ring_emit(ring, MI_FLUSH);
766         intel_ring_emit(ring, MI_NOOP);
767         intel_ring_advance(ring);
768         return 0;
769 }
770
771 static int
772 ring_add_request(struct intel_ring_buffer *ring,
773                  u32 *result)
774 {
775         u32 seqno;
776         int ret;
777
778         ret = intel_ring_begin(ring, 4);
779         if (ret)
780                 return ret;
781
782         seqno = i915_gem_get_seqno(ring->dev);
783
784         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
785         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
786         intel_ring_emit(ring, seqno);
787         intel_ring_emit(ring, MI_USER_INTERRUPT);
788         intel_ring_advance(ring);
789
790         *result = seqno;
791         return 0;
792 }
793
794 static bool
795 gen7_blt_ring_get_irq(struct intel_ring_buffer *ring)
796 {
797         /* The BLT ring on IVB appears to have broken synchronization
798          * between the seqno write and the interrupt, so that the
799          * interrupt appears first.  Returning false here makes
800          * i915_wait_request() do a polling loop, instead.
801          */
802         return false;
803 }
804
805 static bool
806 gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
807 {
808         struct drm_device *dev = ring->dev;
809         drm_i915_private_t *dev_priv = dev->dev_private;
810
811         if (!dev->irq_enabled)
812                return false;
813
814         spin_lock(&ring->irq_lock);
815         if (ring->irq_refcount++ == 0) {
816                 ring->irq_mask &= ~rflag;
817                 I915_WRITE_IMR(ring, ring->irq_mask);
818                 ironlake_enable_irq(dev_priv, gflag);
819         }
820         spin_unlock(&ring->irq_lock);
821
822         return true;
823 }
824
825 static void
826 gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
827 {
828         struct drm_device *dev = ring->dev;
829         drm_i915_private_t *dev_priv = dev->dev_private;
830
831         spin_lock(&ring->irq_lock);
832         if (--ring->irq_refcount == 0) {
833                 ring->irq_mask |= rflag;
834                 I915_WRITE_IMR(ring, ring->irq_mask);
835                 ironlake_disable_irq(dev_priv, gflag);
836         }
837         spin_unlock(&ring->irq_lock);
838 }
839
840 static bool
841 bsd_ring_get_irq(struct intel_ring_buffer *ring)
842 {
843         struct drm_device *dev = ring->dev;
844         drm_i915_private_t *dev_priv = dev->dev_private;
845
846         if (!dev->irq_enabled)
847                 return false;
848
849         spin_lock(&ring->irq_lock);
850         if (ring->irq_refcount++ == 0) {
851                 if (IS_G4X(dev))
852                         i915_enable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
853                 else
854                         ironlake_enable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
855         }
856         spin_unlock(&ring->irq_lock);
857
858         return true;
859 }
860 static void
861 bsd_ring_put_irq(struct intel_ring_buffer *ring)
862 {
863         struct drm_device *dev = ring->dev;
864         drm_i915_private_t *dev_priv = dev->dev_private;
865
866         spin_lock(&ring->irq_lock);
867         if (--ring->irq_refcount == 0) {
868                 if (IS_G4X(dev))
869                         i915_disable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
870                 else
871                         ironlake_disable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
872         }
873         spin_unlock(&ring->irq_lock);
874 }
875
876 static int
877 ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
878 {
879         int ret;
880
881         ret = intel_ring_begin(ring, 2);
882         if (ret)
883                 return ret;
884
885         intel_ring_emit(ring,
886                         MI_BATCH_BUFFER_START | (2 << 6) |
887                         MI_BATCH_NON_SECURE_I965);
888         intel_ring_emit(ring, offset);
889         intel_ring_advance(ring);
890
891         return 0;
892 }
893
894 static int
895 render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
896                                 u32 offset, u32 len)
897 {
898         struct drm_device *dev = ring->dev;
899         int ret;
900
901         if (IS_I830(dev) || IS_845G(dev)) {
902                 ret = intel_ring_begin(ring, 4);
903                 if (ret)
904                         return ret;
905
906                 intel_ring_emit(ring, MI_BATCH_BUFFER);
907                 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
908                 intel_ring_emit(ring, offset + len - 8);
909                 intel_ring_emit(ring, 0);
910         } else {
911                 ret = intel_ring_begin(ring, 2);
912                 if (ret)
913                         return ret;
914
915                 if (INTEL_INFO(dev)->gen >= 4) {
916                         intel_ring_emit(ring,
917                                         MI_BATCH_BUFFER_START | (2 << 6) |
918                                         MI_BATCH_NON_SECURE_I965);
919                         intel_ring_emit(ring, offset);
920                 } else {
921                         intel_ring_emit(ring,
922                                         MI_BATCH_BUFFER_START | (2 << 6));
923                         intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
924                 }
925         }
926         intel_ring_advance(ring);
927
928         return 0;
929 }
930
931 static void cleanup_status_page(struct intel_ring_buffer *ring)
932 {
933         drm_i915_private_t *dev_priv = ring->dev->dev_private;
934         struct drm_i915_gem_object *obj;
935
936         obj = ring->status_page.obj;
937         if (obj == NULL)
938                 return;
939
940         kunmap(obj->pages[0]);
941         i915_gem_object_unpin(obj);
942         drm_gem_object_unreference(&obj->base);
943         ring->status_page.obj = NULL;
944
945         memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
946 }
947
948 static int init_status_page(struct intel_ring_buffer *ring)
949 {
950         struct drm_device *dev = ring->dev;
951         drm_i915_private_t *dev_priv = dev->dev_private;
952         struct drm_i915_gem_object *obj;
953         int ret;
954
955         obj = i915_gem_alloc_object(dev, 4096);
956         if (obj == NULL) {
957                 DRM_ERROR("Failed to allocate status page\n");
958                 ret = -ENOMEM;
959                 goto err;
960         }
961
962         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
963
964         ret = i915_gem_object_pin(obj, 4096, true);
965         if (ret != 0) {
966                 goto err_unref;
967         }
968
969         ring->status_page.gfx_addr = obj->gtt_offset;
970         ring->status_page.page_addr = kmap(obj->pages[0]);
971         if (ring->status_page.page_addr == NULL) {
972                 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
973                 goto err_unpin;
974         }
975         ring->status_page.obj = obj;
976         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
977
978         intel_ring_setup_status_page(ring);
979         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
980                         ring->name, ring->status_page.gfx_addr);
981
982         return 0;
983
984 err_unpin:
985         i915_gem_object_unpin(obj);
986 err_unref:
987         drm_gem_object_unreference(&obj->base);
988 err:
989         return ret;
990 }
991
992 int intel_init_ring_buffer(struct drm_device *dev,
993                            struct intel_ring_buffer *ring)
994 {
995         struct drm_i915_gem_object *obj;
996         int ret;
997
998         ring->dev = dev;
999         INIT_LIST_HEAD(&ring->active_list);
1000         INIT_LIST_HEAD(&ring->request_list);
1001         INIT_LIST_HEAD(&ring->gpu_write_list);
1002
1003         init_waitqueue_head(&ring->irq_queue);
1004         spin_lock_init(&ring->irq_lock);
1005         ring->irq_mask = ~0;
1006
1007         if (I915_NEED_GFX_HWS(dev)) {
1008                 ret = init_status_page(ring);
1009                 if (ret)
1010                         return ret;
1011         }
1012
1013         obj = i915_gem_alloc_object(dev, ring->size);
1014         if (obj == NULL) {
1015                 DRM_ERROR("Failed to allocate ringbuffer\n");
1016                 ret = -ENOMEM;
1017                 goto err_hws;
1018         }
1019
1020         ring->obj = obj;
1021
1022         ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
1023         if (ret)
1024                 goto err_unref;
1025
1026         ring->map.size = ring->size;
1027         ring->map.offset = dev->agp->base + obj->gtt_offset;
1028         ring->map.type = 0;
1029         ring->map.flags = 0;
1030         ring->map.mtrr = 0;
1031
1032         drm_core_ioremap_wc(&ring->map, dev);
1033         if (ring->map.handle == NULL) {
1034                 DRM_ERROR("Failed to map ringbuffer.\n");
1035                 ret = -EINVAL;
1036                 goto err_unpin;
1037         }
1038
1039         ring->virtual_start = ring->map.handle;
1040         ret = ring->init(ring);
1041         if (ret)
1042                 goto err_unmap;
1043
1044         /* Workaround an erratum on the i830 which causes a hang if
1045          * the TAIL pointer points to within the last 2 cachelines
1046          * of the buffer.
1047          */
1048         ring->effective_size = ring->size;
1049         if (IS_I830(ring->dev))
1050                 ring->effective_size -= 128;
1051
1052         return 0;
1053
1054 err_unmap:
1055         drm_core_ioremapfree(&ring->map, dev);
1056 err_unpin:
1057         i915_gem_object_unpin(obj);
1058 err_unref:
1059         drm_gem_object_unreference(&obj->base);
1060         ring->obj = NULL;
1061 err_hws:
1062         cleanup_status_page(ring);
1063         return ret;
1064 }
1065
1066 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1067 {
1068         struct drm_i915_private *dev_priv;
1069         int ret;
1070
1071         if (ring->obj == NULL)
1072                 return;
1073
1074         /* Disable the ring buffer. The ring must be idle at this point */
1075         dev_priv = ring->dev->dev_private;
1076         ret = intel_wait_ring_idle(ring);
1077         if (ret)
1078                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1079                           ring->name, ret);
1080
1081         I915_WRITE_CTL(ring, 0);
1082
1083         drm_core_ioremapfree(&ring->map, ring->dev);
1084
1085         i915_gem_object_unpin(ring->obj);
1086         drm_gem_object_unreference(&ring->obj->base);
1087         ring->obj = NULL;
1088
1089         if (ring->cleanup)
1090                 ring->cleanup(ring);
1091
1092         cleanup_status_page(ring);
1093 }
1094
1095 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1096 {
1097         unsigned int *virt;
1098         int rem = ring->size - ring->tail;
1099
1100         if (ring->space < rem) {
1101                 int ret = intel_wait_ring_buffer(ring, rem);
1102                 if (ret)
1103                         return ret;
1104         }
1105
1106         virt = (unsigned int *)(ring->virtual_start + ring->tail);
1107         rem /= 8;
1108         while (rem--) {
1109                 *virt++ = MI_NOOP;
1110                 *virt++ = MI_NOOP;
1111         }
1112
1113         ring->tail = 0;
1114         ring->space = ring_space(ring);
1115
1116         return 0;
1117 }
1118
1119 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
1120 {
1121         struct drm_device *dev = ring->dev;
1122         struct drm_i915_private *dev_priv = dev->dev_private;
1123         unsigned long end;
1124         u32 head;
1125
1126         /* If the reported head position has wrapped or hasn't advanced,
1127          * fallback to the slow and accurate path.
1128          */
1129         head = intel_read_status_page(ring, 4);
1130         if (head > ring->head) {
1131                 ring->head = head;
1132                 ring->space = ring_space(ring);
1133                 if (ring->space >= n)
1134                         return 0;
1135         }
1136
1137         trace_i915_ring_wait_begin(ring);
1138         end = jiffies + 3 * HZ;
1139         do {
1140                 ring->head = I915_READ_HEAD(ring);
1141                 ring->space = ring_space(ring);
1142                 if (ring->space >= n) {
1143                         trace_i915_ring_wait_end(ring);
1144                         return 0;
1145                 }
1146
1147                 if (dev->primary->master) {
1148                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1149                         if (master_priv->sarea_priv)
1150                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1151                 }
1152
1153                 msleep(1);
1154                 if (atomic_read(&dev_priv->mm.wedged))
1155                         return -EAGAIN;
1156         } while (!time_after(jiffies, end));
1157         trace_i915_ring_wait_end(ring);
1158         return -EBUSY;
1159 }
1160
1161 int intel_ring_begin(struct intel_ring_buffer *ring,
1162                      int num_dwords)
1163 {
1164         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1165         int n = 4*num_dwords;
1166         int ret;
1167
1168         if (unlikely(atomic_read(&dev_priv->mm.wedged)))
1169                 return -EIO;
1170
1171         if (unlikely(ring->tail + n > ring->effective_size)) {
1172                 ret = intel_wrap_ring_buffer(ring);
1173                 if (unlikely(ret))
1174                         return ret;
1175         }
1176
1177         if (unlikely(ring->space < n)) {
1178                 ret = intel_wait_ring_buffer(ring, n);
1179                 if (unlikely(ret))
1180                         return ret;
1181         }
1182
1183         ring->space -= n;
1184         return 0;
1185 }
1186
1187 void intel_ring_advance(struct intel_ring_buffer *ring)
1188 {
1189         ring->tail &= ring->size - 1;
1190         ring->write_tail(ring, ring->tail);
1191 }
1192
1193 static const struct intel_ring_buffer render_ring = {
1194         .name                   = "render ring",
1195         .id                     = RING_RENDER,
1196         .mmio_base              = RENDER_RING_BASE,
1197         .size                   = 32 * PAGE_SIZE,
1198         .init                   = init_render_ring,
1199         .write_tail             = ring_write_tail,
1200         .flush                  = render_ring_flush,
1201         .add_request            = render_ring_add_request,
1202         .get_seqno              = ring_get_seqno,
1203         .irq_get                = render_ring_get_irq,
1204         .irq_put                = render_ring_put_irq,
1205         .dispatch_execbuffer    = render_ring_dispatch_execbuffer,
1206         .cleanup                = render_ring_cleanup,
1207         .sync_to                = render_ring_sync_to,
1208         .semaphore_register     = {MI_SEMAPHORE_SYNC_INVALID,
1209                                    MI_SEMAPHORE_SYNC_RV,
1210                                    MI_SEMAPHORE_SYNC_RB},
1211         .signal_mbox            = {GEN6_VRSYNC, GEN6_BRSYNC},
1212 };
1213
1214 /* ring buffer for bit-stream decoder */
1215
1216 static const struct intel_ring_buffer bsd_ring = {
1217         .name                   = "bsd ring",
1218         .id                     = RING_BSD,
1219         .mmio_base              = BSD_RING_BASE,
1220         .size                   = 32 * PAGE_SIZE,
1221         .init                   = init_ring_common,
1222         .write_tail             = ring_write_tail,
1223         .flush                  = bsd_ring_flush,
1224         .add_request            = ring_add_request,
1225         .get_seqno              = ring_get_seqno,
1226         .irq_get                = bsd_ring_get_irq,
1227         .irq_put                = bsd_ring_put_irq,
1228         .dispatch_execbuffer    = ring_dispatch_execbuffer,
1229 };
1230
1231
1232 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1233                                      u32 value)
1234 {
1235         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1236
1237        /* Every tail move must follow the sequence below */
1238         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1239                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1240                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
1241         I915_WRITE(GEN6_BSD_RNCID, 0x0);
1242
1243         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1244                 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
1245                 50))
1246         DRM_ERROR("timed out waiting for IDLE Indicator\n");
1247
1248         I915_WRITE_TAIL(ring, value);
1249         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1250                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1251                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
1252 }
1253
1254 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1255                            u32 invalidate, u32 flush)
1256 {
1257         uint32_t cmd;
1258         int ret;
1259
1260         ret = intel_ring_begin(ring, 4);
1261         if (ret)
1262                 return ret;
1263
1264         cmd = MI_FLUSH_DW;
1265         if (invalidate & I915_GEM_GPU_DOMAINS)
1266                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1267         intel_ring_emit(ring, cmd);
1268         intel_ring_emit(ring, 0);
1269         intel_ring_emit(ring, 0);
1270         intel_ring_emit(ring, MI_NOOP);
1271         intel_ring_advance(ring);
1272         return 0;
1273 }
1274
1275 static int
1276 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1277                               u32 offset, u32 len)
1278 {
1279         int ret;
1280
1281         ret = intel_ring_begin(ring, 2);
1282         if (ret)
1283                 return ret;
1284
1285         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1286         /* bit0-7 is the length on GEN6+ */
1287         intel_ring_emit(ring, offset);
1288         intel_ring_advance(ring);
1289
1290         return 0;
1291 }
1292
1293 static bool
1294 gen6_render_ring_get_irq(struct intel_ring_buffer *ring)
1295 {
1296         return gen6_ring_get_irq(ring,
1297                                  GT_USER_INTERRUPT,
1298                                  GEN6_RENDER_USER_INTERRUPT);
1299 }
1300
1301 static void
1302 gen6_render_ring_put_irq(struct intel_ring_buffer *ring)
1303 {
1304         return gen6_ring_put_irq(ring,
1305                                  GT_USER_INTERRUPT,
1306                                  GEN6_RENDER_USER_INTERRUPT);
1307 }
1308
1309 static bool
1310 gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring)
1311 {
1312         return gen6_ring_get_irq(ring,
1313                                  GT_GEN6_BSD_USER_INTERRUPT,
1314                                  GEN6_BSD_USER_INTERRUPT);
1315 }
1316
1317 static void
1318 gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring)
1319 {
1320         return gen6_ring_put_irq(ring,
1321                                  GT_GEN6_BSD_USER_INTERRUPT,
1322                                  GEN6_BSD_USER_INTERRUPT);
1323 }
1324
1325 /* ring buffer for Video Codec for Gen6+ */
1326 static const struct intel_ring_buffer gen6_bsd_ring = {
1327         .name                   = "gen6 bsd ring",
1328         .id                     = RING_BSD,
1329         .mmio_base              = GEN6_BSD_RING_BASE,
1330         .size                   = 32 * PAGE_SIZE,
1331         .init                   = init_ring_common,
1332         .write_tail             = gen6_bsd_ring_write_tail,
1333         .flush                  = gen6_ring_flush,
1334         .add_request            = gen6_add_request,
1335         .get_seqno              = ring_get_seqno,
1336         .irq_get                = gen6_bsd_ring_get_irq,
1337         .irq_put                = gen6_bsd_ring_put_irq,
1338         .dispatch_execbuffer    = gen6_ring_dispatch_execbuffer,
1339         .sync_to                = gen6_bsd_ring_sync_to,
1340         .semaphore_register     = {MI_SEMAPHORE_SYNC_VR,
1341                                    MI_SEMAPHORE_SYNC_INVALID,
1342                                    MI_SEMAPHORE_SYNC_VB},
1343         .signal_mbox            = {GEN6_RVSYNC, GEN6_BVSYNC},
1344 };
1345
1346 /* Blitter support (SandyBridge+) */
1347
1348 static bool
1349 blt_ring_get_irq(struct intel_ring_buffer *ring)
1350 {
1351         return gen6_ring_get_irq(ring,
1352                                  GT_BLT_USER_INTERRUPT,
1353                                  GEN6_BLITTER_USER_INTERRUPT);
1354 }
1355
1356 static void
1357 blt_ring_put_irq(struct intel_ring_buffer *ring)
1358 {
1359         gen6_ring_put_irq(ring,
1360                           GT_BLT_USER_INTERRUPT,
1361                           GEN6_BLITTER_USER_INTERRUPT);
1362 }
1363
1364
1365 /* Workaround for some stepping of SNB,
1366  * each time when BLT engine ring tail moved,
1367  * the first command in the ring to be parsed
1368  * should be MI_BATCH_BUFFER_START
1369  */
1370 #define NEED_BLT_WORKAROUND(dev) \
1371         (IS_GEN6(dev) && (dev->pdev->revision < 8))
1372
1373 static inline struct drm_i915_gem_object *
1374 to_blt_workaround(struct intel_ring_buffer *ring)
1375 {
1376         return ring->private;
1377 }
1378
1379 static int blt_ring_init(struct intel_ring_buffer *ring)
1380 {
1381         if (NEED_BLT_WORKAROUND(ring->dev)) {
1382                 struct drm_i915_gem_object *obj;
1383                 u32 *ptr;
1384                 int ret;
1385
1386                 obj = i915_gem_alloc_object(ring->dev, 4096);
1387                 if (obj == NULL)
1388                         return -ENOMEM;
1389
1390                 ret = i915_gem_object_pin(obj, 4096, true);
1391                 if (ret) {
1392                         drm_gem_object_unreference(&obj->base);
1393                         return ret;
1394                 }
1395
1396                 ptr = kmap(obj->pages[0]);
1397                 *ptr++ = MI_BATCH_BUFFER_END;
1398                 *ptr++ = MI_NOOP;
1399                 kunmap(obj->pages[0]);
1400
1401                 ret = i915_gem_object_set_to_gtt_domain(obj, false);
1402                 if (ret) {
1403                         i915_gem_object_unpin(obj);
1404                         drm_gem_object_unreference(&obj->base);
1405                         return ret;
1406                 }
1407
1408                 ring->private = obj;
1409         }
1410
1411         return init_ring_common(ring);
1412 }
1413
1414 static int blt_ring_begin(struct intel_ring_buffer *ring,
1415                           int num_dwords)
1416 {
1417         if (ring->private) {
1418                 int ret = intel_ring_begin(ring, num_dwords+2);
1419                 if (ret)
1420                         return ret;
1421
1422                 intel_ring_emit(ring, MI_BATCH_BUFFER_START);
1423                 intel_ring_emit(ring, to_blt_workaround(ring)->gtt_offset);
1424
1425                 return 0;
1426         } else
1427                 return intel_ring_begin(ring, 4);
1428 }
1429
1430 static int blt_ring_flush(struct intel_ring_buffer *ring,
1431                           u32 invalidate, u32 flush)
1432 {
1433         uint32_t cmd;
1434         int ret;
1435
1436         ret = blt_ring_begin(ring, 4);
1437         if (ret)
1438                 return ret;
1439
1440         cmd = MI_FLUSH_DW;
1441         if (invalidate & I915_GEM_DOMAIN_RENDER)
1442                 cmd |= MI_INVALIDATE_TLB;
1443         intel_ring_emit(ring, cmd);
1444         intel_ring_emit(ring, 0);
1445         intel_ring_emit(ring, 0);
1446         intel_ring_emit(ring, MI_NOOP);
1447         intel_ring_advance(ring);
1448         return 0;
1449 }
1450
1451 static void blt_ring_cleanup(struct intel_ring_buffer *ring)
1452 {
1453         if (!ring->private)
1454                 return;
1455
1456         i915_gem_object_unpin(ring->private);
1457         drm_gem_object_unreference(ring->private);
1458         ring->private = NULL;
1459 }
1460
1461 static const struct intel_ring_buffer gen6_blt_ring = {
1462         .name                   = "blt ring",
1463         .id                     = RING_BLT,
1464         .mmio_base              = BLT_RING_BASE,
1465         .size                   = 32 * PAGE_SIZE,
1466         .init                   = blt_ring_init,
1467         .write_tail             = ring_write_tail,
1468         .flush                  = blt_ring_flush,
1469         .add_request            = gen6_add_request,
1470         .get_seqno              = ring_get_seqno,
1471         .irq_get                = blt_ring_get_irq,
1472         .irq_put                = blt_ring_put_irq,
1473         .dispatch_execbuffer    = gen6_ring_dispatch_execbuffer,
1474         .cleanup                = blt_ring_cleanup,
1475         .sync_to                = gen6_blt_ring_sync_to,
1476         .semaphore_register     = {MI_SEMAPHORE_SYNC_BR,
1477                                    MI_SEMAPHORE_SYNC_BV,
1478                                    MI_SEMAPHORE_SYNC_INVALID},
1479         .signal_mbox            = {GEN6_RBSYNC, GEN6_VBSYNC},
1480 };
1481
1482 int intel_init_render_ring_buffer(struct drm_device *dev)
1483 {
1484         drm_i915_private_t *dev_priv = dev->dev_private;
1485         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1486
1487         *ring = render_ring;
1488         if (INTEL_INFO(dev)->gen >= 6) {
1489                 ring->add_request = gen6_add_request;
1490                 ring->flush = gen6_render_ring_flush;
1491                 ring->irq_get = gen6_render_ring_get_irq;
1492                 ring->irq_put = gen6_render_ring_put_irq;
1493         } else if (IS_GEN5(dev)) {
1494                 ring->add_request = pc_render_add_request;
1495                 ring->get_seqno = pc_render_get_seqno;
1496         }
1497
1498         if (!I915_NEED_GFX_HWS(dev)) {
1499                 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1500                 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1501         }
1502
1503         return intel_init_ring_buffer(dev, ring);
1504 }
1505
1506 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1507 {
1508         drm_i915_private_t *dev_priv = dev->dev_private;
1509         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1510
1511         *ring = render_ring;
1512         if (INTEL_INFO(dev)->gen >= 6) {
1513                 ring->add_request = gen6_add_request;
1514                 ring->irq_get = gen6_render_ring_get_irq;
1515                 ring->irq_put = gen6_render_ring_put_irq;
1516         } else if (IS_GEN5(dev)) {
1517                 ring->add_request = pc_render_add_request;
1518                 ring->get_seqno = pc_render_get_seqno;
1519         }
1520
1521         if (!I915_NEED_GFX_HWS(dev))
1522                 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1523
1524         ring->dev = dev;
1525         INIT_LIST_HEAD(&ring->active_list);
1526         INIT_LIST_HEAD(&ring->request_list);
1527         INIT_LIST_HEAD(&ring->gpu_write_list);
1528
1529         ring->size = size;
1530         ring->effective_size = ring->size;
1531         if (IS_I830(ring->dev))
1532                 ring->effective_size -= 128;
1533
1534         ring->map.offset = start;
1535         ring->map.size = size;
1536         ring->map.type = 0;
1537         ring->map.flags = 0;
1538         ring->map.mtrr = 0;
1539
1540         drm_core_ioremap_wc(&ring->map, dev);
1541         if (ring->map.handle == NULL) {
1542                 DRM_ERROR("can not ioremap virtual address for"
1543                           " ring buffer\n");
1544                 return -ENOMEM;
1545         }
1546
1547         ring->virtual_start = (void __force __iomem *)ring->map.handle;
1548         return 0;
1549 }
1550
1551 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1552 {
1553         drm_i915_private_t *dev_priv = dev->dev_private;
1554         struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1555
1556         if (IS_GEN6(dev) || IS_GEN7(dev))
1557                 *ring = gen6_bsd_ring;
1558         else
1559                 *ring = bsd_ring;
1560
1561         return intel_init_ring_buffer(dev, ring);
1562 }
1563
1564 int intel_init_blt_ring_buffer(struct drm_device *dev)
1565 {
1566         drm_i915_private_t *dev_priv = dev->dev_private;
1567         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1568
1569         *ring = gen6_blt_ring;
1570
1571         if (IS_GEN7(dev))
1572                 ring->irq_get = gen7_blt_ring_get_irq;
1573
1574         return intel_init_ring_buffer(dev, ring);
1575 }