drm/i915: Set the Stencil Cache eviction policy to non-LRA mode.
[linux-2.6.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2  * Copyright © 2008-2010 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Authors:
24  *    Eric Anholt <eric@anholt.net>
25  *    Zou Nan hai <nanhai.zou@intel.com>
26  *    Xiang Hai hao<haihao.xiang@intel.com>
27  *
28  */
29
30 #include "drmP.h"
31 #include "drm.h"
32 #include "i915_drv.h"
33 #include "i915_drm.h"
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36
37 /*
38  * 965+ support PIPE_CONTROL commands, which provide finer grained control
39  * over cache flushing.
40  */
41 struct pipe_control {
42         struct drm_i915_gem_object *obj;
43         volatile u32 *cpu_page;
44         u32 gtt_offset;
45 };
46
47 static inline int ring_space(struct intel_ring_buffer *ring)
48 {
49         int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
50         if (space < 0)
51                 space += ring->size;
52         return space;
53 }
54
55 static int
56 render_ring_flush(struct intel_ring_buffer *ring,
57                   u32   invalidate_domains,
58                   u32   flush_domains)
59 {
60         struct drm_device *dev = ring->dev;
61         u32 cmd;
62         int ret;
63
64         /*
65          * read/write caches:
66          *
67          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
68          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
69          * also flushed at 2d versus 3d pipeline switches.
70          *
71          * read-only caches:
72          *
73          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
74          * MI_READ_FLUSH is set, and is always flushed on 965.
75          *
76          * I915_GEM_DOMAIN_COMMAND may not exist?
77          *
78          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
79          * invalidated when MI_EXE_FLUSH is set.
80          *
81          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
82          * invalidated with every MI_FLUSH.
83          *
84          * TLBs:
85          *
86          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
87          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
88          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
89          * are flushed at any MI_FLUSH.
90          */
91
92         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
93         if ((invalidate_domains|flush_domains) &
94             I915_GEM_DOMAIN_RENDER)
95                 cmd &= ~MI_NO_WRITE_FLUSH;
96         if (INTEL_INFO(dev)->gen < 4) {
97                 /*
98                  * On the 965, the sampler cache always gets flushed
99                  * and this bit is reserved.
100                  */
101                 if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
102                         cmd |= MI_READ_FLUSH;
103         }
104         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
105                 cmd |= MI_EXE_FLUSH;
106
107         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
108             (IS_G4X(dev) || IS_GEN5(dev)))
109                 cmd |= MI_INVALIDATE_ISP;
110
111         ret = intel_ring_begin(ring, 2);
112         if (ret)
113                 return ret;
114
115         intel_ring_emit(ring, cmd);
116         intel_ring_emit(ring, MI_NOOP);
117         intel_ring_advance(ring);
118
119         return 0;
120 }
121
122 /**
123  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
124  * implementing two workarounds on gen6.  From section 1.4.7.1
125  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
126  *
127  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
128  * produced by non-pipelined state commands), software needs to first
129  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
130  * 0.
131  *
132  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
133  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
134  *
135  * And the workaround for these two requires this workaround first:
136  *
137  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
138  * BEFORE the pipe-control with a post-sync op and no write-cache
139  * flushes.
140  *
141  * And this last workaround is tricky because of the requirements on
142  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
143  * volume 2 part 1:
144  *
145  *     "1 of the following must also be set:
146  *      - Render Target Cache Flush Enable ([12] of DW1)
147  *      - Depth Cache Flush Enable ([0] of DW1)
148  *      - Stall at Pixel Scoreboard ([1] of DW1)
149  *      - Depth Stall ([13] of DW1)
150  *      - Post-Sync Operation ([13] of DW1)
151  *      - Notify Enable ([8] of DW1)"
152  *
153  * The cache flushes require the workaround flush that triggered this
154  * one, so we can't use it.  Depth stall would trigger the same.
155  * Post-sync nonzero is what triggered this second workaround, so we
156  * can't use that one either.  Notify enable is IRQs, which aren't
157  * really our business.  That leaves only stall at scoreboard.
158  */
159 static int
160 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
161 {
162         struct pipe_control *pc = ring->private;
163         u32 scratch_addr = pc->gtt_offset + 128;
164         int ret;
165
166
167         ret = intel_ring_begin(ring, 6);
168         if (ret)
169                 return ret;
170
171         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
172         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
173                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
174         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
175         intel_ring_emit(ring, 0); /* low dword */
176         intel_ring_emit(ring, 0); /* high dword */
177         intel_ring_emit(ring, MI_NOOP);
178         intel_ring_advance(ring);
179
180         ret = intel_ring_begin(ring, 6);
181         if (ret)
182                 return ret;
183
184         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
185         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
186         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
187         intel_ring_emit(ring, 0);
188         intel_ring_emit(ring, 0);
189         intel_ring_emit(ring, MI_NOOP);
190         intel_ring_advance(ring);
191
192         return 0;
193 }
194
195 static int
196 gen6_render_ring_flush(struct intel_ring_buffer *ring,
197                          u32 invalidate_domains, u32 flush_domains)
198 {
199         u32 flags = 0;
200         struct pipe_control *pc = ring->private;
201         u32 scratch_addr = pc->gtt_offset + 128;
202         int ret;
203
204         /* Force SNB workarounds for PIPE_CONTROL flushes */
205         intel_emit_post_sync_nonzero_flush(ring);
206
207         /* Just flush everything.  Experiments have shown that reducing the
208          * number of bits based on the write domains has little performance
209          * impact.
210          */
211         flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
212         flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
213         flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
214         flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
215         flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
216         flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
217         flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
218
219         ret = intel_ring_begin(ring, 6);
220         if (ret)
221                 return ret;
222
223         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
224         intel_ring_emit(ring, flags);
225         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
226         intel_ring_emit(ring, 0); /* lower dword */
227         intel_ring_emit(ring, 0); /* uppwer dword */
228         intel_ring_emit(ring, MI_NOOP);
229         intel_ring_advance(ring);
230
231         return 0;
232 }
233
234 static void ring_write_tail(struct intel_ring_buffer *ring,
235                             u32 value)
236 {
237         drm_i915_private_t *dev_priv = ring->dev->dev_private;
238         I915_WRITE_TAIL(ring, value);
239 }
240
241 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
242 {
243         drm_i915_private_t *dev_priv = ring->dev->dev_private;
244         u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
245                         RING_ACTHD(ring->mmio_base) : ACTHD;
246
247         return I915_READ(acthd_reg);
248 }
249
250 static int init_ring_common(struct intel_ring_buffer *ring)
251 {
252         drm_i915_private_t *dev_priv = ring->dev->dev_private;
253         struct drm_i915_gem_object *obj = ring->obj;
254         u32 head;
255
256         /* Stop the ring if it's running. */
257         I915_WRITE_CTL(ring, 0);
258         I915_WRITE_HEAD(ring, 0);
259         ring->write_tail(ring, 0);
260
261         /* Initialize the ring. */
262         I915_WRITE_START(ring, obj->gtt_offset);
263         head = I915_READ_HEAD(ring) & HEAD_ADDR;
264
265         /* G45 ring initialization fails to reset head to zero */
266         if (head != 0) {
267                 DRM_DEBUG_KMS("%s head not reset to zero "
268                               "ctl %08x head %08x tail %08x start %08x\n",
269                               ring->name,
270                               I915_READ_CTL(ring),
271                               I915_READ_HEAD(ring),
272                               I915_READ_TAIL(ring),
273                               I915_READ_START(ring));
274
275                 I915_WRITE_HEAD(ring, 0);
276
277                 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
278                         DRM_ERROR("failed to set %s head to zero "
279                                   "ctl %08x head %08x tail %08x start %08x\n",
280                                   ring->name,
281                                   I915_READ_CTL(ring),
282                                   I915_READ_HEAD(ring),
283                                   I915_READ_TAIL(ring),
284                                   I915_READ_START(ring));
285                 }
286         }
287
288         I915_WRITE_CTL(ring,
289                         ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
290                         | RING_VALID);
291
292         /* If the head is still not zero, the ring is dead */
293         if ((I915_READ_CTL(ring) & RING_VALID) == 0 ||
294             I915_READ_START(ring) != obj->gtt_offset ||
295             (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) {
296                 DRM_ERROR("%s initialization failed "
297                                 "ctl %08x head %08x tail %08x start %08x\n",
298                                 ring->name,
299                                 I915_READ_CTL(ring),
300                                 I915_READ_HEAD(ring),
301                                 I915_READ_TAIL(ring),
302                                 I915_READ_START(ring));
303                 return -EIO;
304         }
305
306         if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
307                 i915_kernel_lost_context(ring->dev);
308         else {
309                 ring->head = I915_READ_HEAD(ring);
310                 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
311                 ring->space = ring_space(ring);
312         }
313
314         return 0;
315 }
316
317 static int
318 init_pipe_control(struct intel_ring_buffer *ring)
319 {
320         struct pipe_control *pc;
321         struct drm_i915_gem_object *obj;
322         int ret;
323
324         if (ring->private)
325                 return 0;
326
327         pc = kmalloc(sizeof(*pc), GFP_KERNEL);
328         if (!pc)
329                 return -ENOMEM;
330
331         obj = i915_gem_alloc_object(ring->dev, 4096);
332         if (obj == NULL) {
333                 DRM_ERROR("Failed to allocate seqno page\n");
334                 ret = -ENOMEM;
335                 goto err;
336         }
337
338         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
339
340         ret = i915_gem_object_pin(obj, 4096, true);
341         if (ret)
342                 goto err_unref;
343
344         pc->gtt_offset = obj->gtt_offset;
345         pc->cpu_page =  kmap(obj->pages[0]);
346         if (pc->cpu_page == NULL)
347                 goto err_unpin;
348
349         pc->obj = obj;
350         ring->private = pc;
351         return 0;
352
353 err_unpin:
354         i915_gem_object_unpin(obj);
355 err_unref:
356         drm_gem_object_unreference(&obj->base);
357 err:
358         kfree(pc);
359         return ret;
360 }
361
362 static void
363 cleanup_pipe_control(struct intel_ring_buffer *ring)
364 {
365         struct pipe_control *pc = ring->private;
366         struct drm_i915_gem_object *obj;
367
368         if (!ring->private)
369                 return;
370
371         obj = pc->obj;
372         kunmap(obj->pages[0]);
373         i915_gem_object_unpin(obj);
374         drm_gem_object_unreference(&obj->base);
375
376         kfree(pc);
377         ring->private = NULL;
378 }
379
380 static int init_render_ring(struct intel_ring_buffer *ring)
381 {
382         struct drm_device *dev = ring->dev;
383         struct drm_i915_private *dev_priv = dev->dev_private;
384         int ret = init_ring_common(ring);
385
386         if (INTEL_INFO(dev)->gen > 3) {
387                 int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
388                 I915_WRITE(MI_MODE, mode);
389                 if (IS_GEN7(dev))
390                         I915_WRITE(GFX_MODE_GEN7,
391                                    GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
392                                    GFX_MODE_ENABLE(GFX_REPLAY_MODE));
393         }
394
395         if (INTEL_INFO(dev)->gen >= 5) {
396                 ret = init_pipe_control(ring);
397                 if (ret)
398                         return ret;
399         }
400
401         if (INTEL_INFO(dev)->gen >= 6) {
402                 I915_WRITE(INSTPM,
403                            INSTPM_FORCE_ORDERING << 16 | INSTPM_FORCE_ORDERING);
404
405                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
406                  * "If this bit is set, STCunit will have LRA as replacement
407                  *  policy. [...] This bit must be reset.  LRA replacement
408                  *  policy is not supported."
409                  */
410                 I915_WRITE(CACHE_MODE_0,
411                            CM0_STC_EVICT_DISABLE_LRA_SNB << CM0_MASK_SHIFT);
412         }
413
414         return ret;
415 }
416
417 static void render_ring_cleanup(struct intel_ring_buffer *ring)
418 {
419         if (!ring->private)
420                 return;
421
422         cleanup_pipe_control(ring);
423 }
424
425 static void
426 update_mboxes(struct intel_ring_buffer *ring,
427             u32 seqno,
428             u32 mmio_offset)
429 {
430         intel_ring_emit(ring, MI_SEMAPHORE_MBOX |
431                               MI_SEMAPHORE_GLOBAL_GTT |
432                               MI_SEMAPHORE_REGISTER |
433                               MI_SEMAPHORE_UPDATE);
434         intel_ring_emit(ring, seqno);
435         intel_ring_emit(ring, mmio_offset);
436 }
437
438 /**
439  * gen6_add_request - Update the semaphore mailbox registers
440  * 
441  * @ring - ring that is adding a request
442  * @seqno - return seqno stuck into the ring
443  *
444  * Update the mailbox registers in the *other* rings with the current seqno.
445  * This acts like a signal in the canonical semaphore.
446  */
447 static int
448 gen6_add_request(struct intel_ring_buffer *ring,
449                  u32 *seqno)
450 {
451         u32 mbox1_reg;
452         u32 mbox2_reg;
453         int ret;
454
455         ret = intel_ring_begin(ring, 10);
456         if (ret)
457                 return ret;
458
459         mbox1_reg = ring->signal_mbox[0];
460         mbox2_reg = ring->signal_mbox[1];
461
462         *seqno = i915_gem_next_request_seqno(ring);
463
464         update_mboxes(ring, *seqno, mbox1_reg);
465         update_mboxes(ring, *seqno, mbox2_reg);
466         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
467         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
468         intel_ring_emit(ring, *seqno);
469         intel_ring_emit(ring, MI_USER_INTERRUPT);
470         intel_ring_advance(ring);
471
472         return 0;
473 }
474
475 /**
476  * intel_ring_sync - sync the waiter to the signaller on seqno
477  *
478  * @waiter - ring that is waiting
479  * @signaller - ring which has, or will signal
480  * @seqno - seqno which the waiter will block on
481  */
482 static int
483 intel_ring_sync(struct intel_ring_buffer *waiter,
484                 struct intel_ring_buffer *signaller,
485                 int ring,
486                 u32 seqno)
487 {
488         int ret;
489         u32 dw1 = MI_SEMAPHORE_MBOX |
490                   MI_SEMAPHORE_COMPARE |
491                   MI_SEMAPHORE_REGISTER;
492
493         ret = intel_ring_begin(waiter, 4);
494         if (ret)
495                 return ret;
496
497         intel_ring_emit(waiter, dw1 | signaller->semaphore_register[ring]);
498         intel_ring_emit(waiter, seqno);
499         intel_ring_emit(waiter, 0);
500         intel_ring_emit(waiter, MI_NOOP);
501         intel_ring_advance(waiter);
502
503         return 0;
504 }
505
506 /* VCS->RCS (RVSYNC) or BCS->RCS (RBSYNC) */
507 int
508 render_ring_sync_to(struct intel_ring_buffer *waiter,
509                     struct intel_ring_buffer *signaller,
510                     u32 seqno)
511 {
512         WARN_ON(signaller->semaphore_register[RCS] == MI_SEMAPHORE_SYNC_INVALID);
513         return intel_ring_sync(waiter,
514                                signaller,
515                                RCS,
516                                seqno);
517 }
518
519 /* RCS->VCS (VRSYNC) or BCS->VCS (VBSYNC) */
520 int
521 gen6_bsd_ring_sync_to(struct intel_ring_buffer *waiter,
522                       struct intel_ring_buffer *signaller,
523                       u32 seqno)
524 {
525         WARN_ON(signaller->semaphore_register[VCS] == MI_SEMAPHORE_SYNC_INVALID);
526         return intel_ring_sync(waiter,
527                                signaller,
528                                VCS,
529                                seqno);
530 }
531
532 /* RCS->BCS (BRSYNC) or VCS->BCS (BVSYNC) */
533 int
534 gen6_blt_ring_sync_to(struct intel_ring_buffer *waiter,
535                       struct intel_ring_buffer *signaller,
536                       u32 seqno)
537 {
538         WARN_ON(signaller->semaphore_register[BCS] == MI_SEMAPHORE_SYNC_INVALID);
539         return intel_ring_sync(waiter,
540                                signaller,
541                                BCS,
542                                seqno);
543 }
544
545
546
547 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
548 do {                                                                    \
549         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
550                  PIPE_CONTROL_DEPTH_STALL);                             \
551         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
552         intel_ring_emit(ring__, 0);                                                     \
553         intel_ring_emit(ring__, 0);                                                     \
554 } while (0)
555
556 static int
557 pc_render_add_request(struct intel_ring_buffer *ring,
558                       u32 *result)
559 {
560         u32 seqno = i915_gem_next_request_seqno(ring);
561         struct pipe_control *pc = ring->private;
562         u32 scratch_addr = pc->gtt_offset + 128;
563         int ret;
564
565         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
566          * incoherent with writes to memory, i.e. completely fubar,
567          * so we need to use PIPE_NOTIFY instead.
568          *
569          * However, we also need to workaround the qword write
570          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
571          * memory before requesting an interrupt.
572          */
573         ret = intel_ring_begin(ring, 32);
574         if (ret)
575                 return ret;
576
577         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
578                         PIPE_CONTROL_WRITE_FLUSH |
579                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
580         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
581         intel_ring_emit(ring, seqno);
582         intel_ring_emit(ring, 0);
583         PIPE_CONTROL_FLUSH(ring, scratch_addr);
584         scratch_addr += 128; /* write to separate cachelines */
585         PIPE_CONTROL_FLUSH(ring, scratch_addr);
586         scratch_addr += 128;
587         PIPE_CONTROL_FLUSH(ring, scratch_addr);
588         scratch_addr += 128;
589         PIPE_CONTROL_FLUSH(ring, scratch_addr);
590         scratch_addr += 128;
591         PIPE_CONTROL_FLUSH(ring, scratch_addr);
592         scratch_addr += 128;
593         PIPE_CONTROL_FLUSH(ring, scratch_addr);
594
595         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
596                         PIPE_CONTROL_WRITE_FLUSH |
597                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
598                         PIPE_CONTROL_NOTIFY);
599         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
600         intel_ring_emit(ring, seqno);
601         intel_ring_emit(ring, 0);
602         intel_ring_advance(ring);
603
604         *result = seqno;
605         return 0;
606 }
607
608 static int
609 render_ring_add_request(struct intel_ring_buffer *ring,
610                         u32 *result)
611 {
612         u32 seqno = i915_gem_next_request_seqno(ring);
613         int ret;
614
615         ret = intel_ring_begin(ring, 4);
616         if (ret)
617                 return ret;
618
619         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
620         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
621         intel_ring_emit(ring, seqno);
622         intel_ring_emit(ring, MI_USER_INTERRUPT);
623         intel_ring_advance(ring);
624
625         *result = seqno;
626         return 0;
627 }
628
629 static u32
630 gen6_ring_get_seqno(struct intel_ring_buffer *ring)
631 {
632         struct drm_device *dev = ring->dev;
633
634         /* Workaround to force correct ordering between irq and seqno writes on
635          * ivb (and maybe also on snb) by reading from a CS register (like
636          * ACTHD) before reading the status page. */
637         if (IS_GEN6(dev) || IS_GEN7(dev))
638                 intel_ring_get_active_head(ring);
639         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
640 }
641
642 static u32
643 ring_get_seqno(struct intel_ring_buffer *ring)
644 {
645         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
646 }
647
648 static u32
649 pc_render_get_seqno(struct intel_ring_buffer *ring)
650 {
651         struct pipe_control *pc = ring->private;
652         return pc->cpu_page[0];
653 }
654
655 static void
656 ironlake_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
657 {
658         dev_priv->gt_irq_mask &= ~mask;
659         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
660         POSTING_READ(GTIMR);
661 }
662
663 static void
664 ironlake_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
665 {
666         dev_priv->gt_irq_mask |= mask;
667         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
668         POSTING_READ(GTIMR);
669 }
670
671 static void
672 i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
673 {
674         dev_priv->irq_mask &= ~mask;
675         I915_WRITE(IMR, dev_priv->irq_mask);
676         POSTING_READ(IMR);
677 }
678
679 static void
680 i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
681 {
682         dev_priv->irq_mask |= mask;
683         I915_WRITE(IMR, dev_priv->irq_mask);
684         POSTING_READ(IMR);
685 }
686
687 static bool
688 render_ring_get_irq(struct intel_ring_buffer *ring)
689 {
690         struct drm_device *dev = ring->dev;
691         drm_i915_private_t *dev_priv = dev->dev_private;
692
693         if (!dev->irq_enabled)
694                 return false;
695
696         spin_lock(&ring->irq_lock);
697         if (ring->irq_refcount++ == 0) {
698                 if (HAS_PCH_SPLIT(dev))
699                         ironlake_enable_irq(dev_priv,
700                                             GT_PIPE_NOTIFY | GT_USER_INTERRUPT);
701                 else
702                         i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
703         }
704         spin_unlock(&ring->irq_lock);
705
706         return true;
707 }
708
709 static void
710 render_ring_put_irq(struct intel_ring_buffer *ring)
711 {
712         struct drm_device *dev = ring->dev;
713         drm_i915_private_t *dev_priv = dev->dev_private;
714
715         spin_lock(&ring->irq_lock);
716         if (--ring->irq_refcount == 0) {
717                 if (HAS_PCH_SPLIT(dev))
718                         ironlake_disable_irq(dev_priv,
719                                              GT_USER_INTERRUPT |
720                                              GT_PIPE_NOTIFY);
721                 else
722                         i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
723         }
724         spin_unlock(&ring->irq_lock);
725 }
726
727 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
728 {
729         struct drm_device *dev = ring->dev;
730         drm_i915_private_t *dev_priv = ring->dev->dev_private;
731         u32 mmio = 0;
732
733         /* The ring status page addresses are no longer next to the rest of
734          * the ring registers as of gen7.
735          */
736         if (IS_GEN7(dev)) {
737                 switch (ring->id) {
738                 case RCS:
739                         mmio = RENDER_HWS_PGA_GEN7;
740                         break;
741                 case BCS:
742                         mmio = BLT_HWS_PGA_GEN7;
743                         break;
744                 case VCS:
745                         mmio = BSD_HWS_PGA_GEN7;
746                         break;
747                 }
748         } else if (IS_GEN6(ring->dev)) {
749                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
750         } else {
751                 mmio = RING_HWS_PGA(ring->mmio_base);
752         }
753
754         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
755         POSTING_READ(mmio);
756 }
757
758 static int
759 bsd_ring_flush(struct intel_ring_buffer *ring,
760                u32     invalidate_domains,
761                u32     flush_domains)
762 {
763         int ret;
764
765         ret = intel_ring_begin(ring, 2);
766         if (ret)
767                 return ret;
768
769         intel_ring_emit(ring, MI_FLUSH);
770         intel_ring_emit(ring, MI_NOOP);
771         intel_ring_advance(ring);
772         return 0;
773 }
774
775 static int
776 ring_add_request(struct intel_ring_buffer *ring,
777                  u32 *result)
778 {
779         u32 seqno;
780         int ret;
781
782         ret = intel_ring_begin(ring, 4);
783         if (ret)
784                 return ret;
785
786         seqno = i915_gem_next_request_seqno(ring);
787
788         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
789         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
790         intel_ring_emit(ring, seqno);
791         intel_ring_emit(ring, MI_USER_INTERRUPT);
792         intel_ring_advance(ring);
793
794         *result = seqno;
795         return 0;
796 }
797
798 static bool
799 gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
800 {
801         struct drm_device *dev = ring->dev;
802         drm_i915_private_t *dev_priv = dev->dev_private;
803
804         if (!dev->irq_enabled)
805                return false;
806
807         /* It looks like we need to prevent the gt from suspending while waiting
808          * for an notifiy irq, otherwise irqs seem to get lost on at least the
809          * blt/bsd rings on ivb. */
810         gen6_gt_force_wake_get(dev_priv);
811
812         spin_lock(&ring->irq_lock);
813         if (ring->irq_refcount++ == 0) {
814                 ring->irq_mask &= ~rflag;
815                 I915_WRITE_IMR(ring, ring->irq_mask);
816                 ironlake_enable_irq(dev_priv, gflag);
817         }
818         spin_unlock(&ring->irq_lock);
819
820         return true;
821 }
822
823 static void
824 gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
825 {
826         struct drm_device *dev = ring->dev;
827         drm_i915_private_t *dev_priv = dev->dev_private;
828
829         spin_lock(&ring->irq_lock);
830         if (--ring->irq_refcount == 0) {
831                 ring->irq_mask |= rflag;
832                 I915_WRITE_IMR(ring, ring->irq_mask);
833                 ironlake_disable_irq(dev_priv, gflag);
834         }
835         spin_unlock(&ring->irq_lock);
836
837         gen6_gt_force_wake_put(dev_priv);
838 }
839
840 static bool
841 bsd_ring_get_irq(struct intel_ring_buffer *ring)
842 {
843         struct drm_device *dev = ring->dev;
844         drm_i915_private_t *dev_priv = dev->dev_private;
845
846         if (!dev->irq_enabled)
847                 return false;
848
849         spin_lock(&ring->irq_lock);
850         if (ring->irq_refcount++ == 0) {
851                 if (IS_G4X(dev))
852                         i915_enable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
853                 else
854                         ironlake_enable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
855         }
856         spin_unlock(&ring->irq_lock);
857
858         return true;
859 }
860 static void
861 bsd_ring_put_irq(struct intel_ring_buffer *ring)
862 {
863         struct drm_device *dev = ring->dev;
864         drm_i915_private_t *dev_priv = dev->dev_private;
865
866         spin_lock(&ring->irq_lock);
867         if (--ring->irq_refcount == 0) {
868                 if (IS_G4X(dev))
869                         i915_disable_irq(dev_priv, I915_BSD_USER_INTERRUPT);
870                 else
871                         ironlake_disable_irq(dev_priv, GT_BSD_USER_INTERRUPT);
872         }
873         spin_unlock(&ring->irq_lock);
874 }
875
876 static int
877 ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
878 {
879         int ret;
880
881         ret = intel_ring_begin(ring, 2);
882         if (ret)
883                 return ret;
884
885         intel_ring_emit(ring,
886                         MI_BATCH_BUFFER_START | (2 << 6) |
887                         MI_BATCH_NON_SECURE_I965);
888         intel_ring_emit(ring, offset);
889         intel_ring_advance(ring);
890
891         return 0;
892 }
893
894 static int
895 render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
896                                 u32 offset, u32 len)
897 {
898         struct drm_device *dev = ring->dev;
899         int ret;
900
901         if (IS_I830(dev) || IS_845G(dev)) {
902                 ret = intel_ring_begin(ring, 4);
903                 if (ret)
904                         return ret;
905
906                 intel_ring_emit(ring, MI_BATCH_BUFFER);
907                 intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
908                 intel_ring_emit(ring, offset + len - 8);
909                 intel_ring_emit(ring, 0);
910         } else {
911                 ret = intel_ring_begin(ring, 2);
912                 if (ret)
913                         return ret;
914
915                 if (INTEL_INFO(dev)->gen >= 4) {
916                         intel_ring_emit(ring,
917                                         MI_BATCH_BUFFER_START | (2 << 6) |
918                                         MI_BATCH_NON_SECURE_I965);
919                         intel_ring_emit(ring, offset);
920                 } else {
921                         intel_ring_emit(ring,
922                                         MI_BATCH_BUFFER_START | (2 << 6));
923                         intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
924                 }
925         }
926         intel_ring_advance(ring);
927
928         return 0;
929 }
930
931 static void cleanup_status_page(struct intel_ring_buffer *ring)
932 {
933         drm_i915_private_t *dev_priv = ring->dev->dev_private;
934         struct drm_i915_gem_object *obj;
935
936         obj = ring->status_page.obj;
937         if (obj == NULL)
938                 return;
939
940         kunmap(obj->pages[0]);
941         i915_gem_object_unpin(obj);
942         drm_gem_object_unreference(&obj->base);
943         ring->status_page.obj = NULL;
944
945         memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
946 }
947
948 static int init_status_page(struct intel_ring_buffer *ring)
949 {
950         struct drm_device *dev = ring->dev;
951         drm_i915_private_t *dev_priv = dev->dev_private;
952         struct drm_i915_gem_object *obj;
953         int ret;
954
955         obj = i915_gem_alloc_object(dev, 4096);
956         if (obj == NULL) {
957                 DRM_ERROR("Failed to allocate status page\n");
958                 ret = -ENOMEM;
959                 goto err;
960         }
961
962         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
963
964         ret = i915_gem_object_pin(obj, 4096, true);
965         if (ret != 0) {
966                 goto err_unref;
967         }
968
969         ring->status_page.gfx_addr = obj->gtt_offset;
970         ring->status_page.page_addr = kmap(obj->pages[0]);
971         if (ring->status_page.page_addr == NULL) {
972                 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
973                 goto err_unpin;
974         }
975         ring->status_page.obj = obj;
976         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
977
978         intel_ring_setup_status_page(ring);
979         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
980                         ring->name, ring->status_page.gfx_addr);
981
982         return 0;
983
984 err_unpin:
985         i915_gem_object_unpin(obj);
986 err_unref:
987         drm_gem_object_unreference(&obj->base);
988 err:
989         return ret;
990 }
991
992 int intel_init_ring_buffer(struct drm_device *dev,
993                            struct intel_ring_buffer *ring)
994 {
995         struct drm_i915_gem_object *obj;
996         int ret;
997
998         ring->dev = dev;
999         INIT_LIST_HEAD(&ring->active_list);
1000         INIT_LIST_HEAD(&ring->request_list);
1001         INIT_LIST_HEAD(&ring->gpu_write_list);
1002
1003         init_waitqueue_head(&ring->irq_queue);
1004         spin_lock_init(&ring->irq_lock);
1005         ring->irq_mask = ~0;
1006
1007         if (I915_NEED_GFX_HWS(dev)) {
1008                 ret = init_status_page(ring);
1009                 if (ret)
1010                         return ret;
1011         }
1012
1013         obj = i915_gem_alloc_object(dev, ring->size);
1014         if (obj == NULL) {
1015                 DRM_ERROR("Failed to allocate ringbuffer\n");
1016                 ret = -ENOMEM;
1017                 goto err_hws;
1018         }
1019
1020         ring->obj = obj;
1021
1022         ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
1023         if (ret)
1024                 goto err_unref;
1025
1026         ring->map.size = ring->size;
1027         ring->map.offset = dev->agp->base + obj->gtt_offset;
1028         ring->map.type = 0;
1029         ring->map.flags = 0;
1030         ring->map.mtrr = 0;
1031
1032         drm_core_ioremap_wc(&ring->map, dev);
1033         if (ring->map.handle == NULL) {
1034                 DRM_ERROR("Failed to map ringbuffer.\n");
1035                 ret = -EINVAL;
1036                 goto err_unpin;
1037         }
1038
1039         ring->virtual_start = ring->map.handle;
1040         ret = ring->init(ring);
1041         if (ret)
1042                 goto err_unmap;
1043
1044         /* Workaround an erratum on the i830 which causes a hang if
1045          * the TAIL pointer points to within the last 2 cachelines
1046          * of the buffer.
1047          */
1048         ring->effective_size = ring->size;
1049         if (IS_I830(ring->dev) || IS_845G(ring->dev))
1050                 ring->effective_size -= 128;
1051
1052         return 0;
1053
1054 err_unmap:
1055         drm_core_ioremapfree(&ring->map, dev);
1056 err_unpin:
1057         i915_gem_object_unpin(obj);
1058 err_unref:
1059         drm_gem_object_unreference(&obj->base);
1060         ring->obj = NULL;
1061 err_hws:
1062         cleanup_status_page(ring);
1063         return ret;
1064 }
1065
1066 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1067 {
1068         struct drm_i915_private *dev_priv;
1069         int ret;
1070
1071         if (ring->obj == NULL)
1072                 return;
1073
1074         /* Disable the ring buffer. The ring must be idle at this point */
1075         dev_priv = ring->dev->dev_private;
1076         ret = intel_wait_ring_idle(ring);
1077         if (ret)
1078                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1079                           ring->name, ret);
1080
1081         I915_WRITE_CTL(ring, 0);
1082
1083         drm_core_ioremapfree(&ring->map, ring->dev);
1084
1085         i915_gem_object_unpin(ring->obj);
1086         drm_gem_object_unreference(&ring->obj->base);
1087         ring->obj = NULL;
1088
1089         if (ring->cleanup)
1090                 ring->cleanup(ring);
1091
1092         cleanup_status_page(ring);
1093 }
1094
1095 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1096 {
1097         unsigned int *virt;
1098         int rem = ring->size - ring->tail;
1099
1100         if (ring->space < rem) {
1101                 int ret = intel_wait_ring_buffer(ring, rem);
1102                 if (ret)
1103                         return ret;
1104         }
1105
1106         virt = (unsigned int *)(ring->virtual_start + ring->tail);
1107         rem /= 8;
1108         while (rem--) {
1109                 *virt++ = MI_NOOP;
1110                 *virt++ = MI_NOOP;
1111         }
1112
1113         ring->tail = 0;
1114         ring->space = ring_space(ring);
1115
1116         return 0;
1117 }
1118
1119 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1120 {
1121         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1122         bool was_interruptible;
1123         int ret;
1124
1125         /* XXX As we have not yet audited all the paths to check that
1126          * they are ready for ERESTARTSYS from intel_ring_begin, do not
1127          * allow us to be interruptible by a signal.
1128          */
1129         was_interruptible = dev_priv->mm.interruptible;
1130         dev_priv->mm.interruptible = false;
1131
1132         ret = i915_wait_request(ring, seqno, true);
1133
1134         dev_priv->mm.interruptible = was_interruptible;
1135
1136         return ret;
1137 }
1138
1139 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1140 {
1141         struct drm_i915_gem_request *request;
1142         u32 seqno = 0;
1143         int ret;
1144
1145         i915_gem_retire_requests_ring(ring);
1146
1147         if (ring->last_retired_head != -1) {
1148                 ring->head = ring->last_retired_head;
1149                 ring->last_retired_head = -1;
1150                 ring->space = ring_space(ring);
1151                 if (ring->space >= n)
1152                         return 0;
1153         }
1154
1155         list_for_each_entry(request, &ring->request_list, list) {
1156                 int space;
1157
1158                 if (request->tail == -1)
1159                         continue;
1160
1161                 space = request->tail - (ring->tail + 8);
1162                 if (space < 0)
1163                         space += ring->size;
1164                 if (space >= n) {
1165                         seqno = request->seqno;
1166                         break;
1167                 }
1168
1169                 /* Consume this request in case we need more space than
1170                  * is available and so need to prevent a race between
1171                  * updating last_retired_head and direct reads of
1172                  * I915_RING_HEAD. It also provides a nice sanity check.
1173                  */
1174                 request->tail = -1;
1175         }
1176
1177         if (seqno == 0)
1178                 return -ENOSPC;
1179
1180         ret = intel_ring_wait_seqno(ring, seqno);
1181         if (ret)
1182                 return ret;
1183
1184         if (WARN_ON(ring->last_retired_head == -1))
1185                 return -ENOSPC;
1186
1187         ring->head = ring->last_retired_head;
1188         ring->last_retired_head = -1;
1189         ring->space = ring_space(ring);
1190         if (WARN_ON(ring->space < n))
1191                 return -ENOSPC;
1192
1193         return 0;
1194 }
1195
1196 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
1197 {
1198         struct drm_device *dev = ring->dev;
1199         struct drm_i915_private *dev_priv = dev->dev_private;
1200         unsigned long end;
1201         int ret;
1202
1203         ret = intel_ring_wait_request(ring, n);
1204         if (ret != -ENOSPC)
1205                 return ret;
1206
1207         trace_i915_ring_wait_begin(ring);
1208         if (drm_core_check_feature(dev, DRIVER_GEM))
1209                 /* With GEM the hangcheck timer should kick us out of the loop,
1210                  * leaving it early runs the risk of corrupting GEM state (due
1211                  * to running on almost untested codepaths). But on resume
1212                  * timers don't work yet, so prevent a complete hang in that
1213                  * case by choosing an insanely large timeout. */
1214                 end = jiffies + 60 * HZ;
1215         else
1216                 end = jiffies + 3 * HZ;
1217
1218         do {
1219                 ring->head = I915_READ_HEAD(ring);
1220                 ring->space = ring_space(ring);
1221                 if (ring->space >= n) {
1222                         trace_i915_ring_wait_end(ring);
1223                         return 0;
1224                 }
1225
1226                 if (dev->primary->master) {
1227                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1228                         if (master_priv->sarea_priv)
1229                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1230                 }
1231
1232                 msleep(1);
1233                 if (atomic_read(&dev_priv->mm.wedged))
1234                         return -EAGAIN;
1235         } while (!time_after(jiffies, end));
1236         trace_i915_ring_wait_end(ring);
1237         return -EBUSY;
1238 }
1239
1240 int intel_ring_begin(struct intel_ring_buffer *ring,
1241                      int num_dwords)
1242 {
1243         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1244         int n = 4*num_dwords;
1245         int ret;
1246
1247         if (unlikely(atomic_read(&dev_priv->mm.wedged)))
1248                 return -EIO;
1249
1250         if (unlikely(ring->tail + n > ring->effective_size)) {
1251                 ret = intel_wrap_ring_buffer(ring);
1252                 if (unlikely(ret))
1253                         return ret;
1254         }
1255
1256         if (unlikely(ring->space < n)) {
1257                 ret = intel_wait_ring_buffer(ring, n);
1258                 if (unlikely(ret))
1259                         return ret;
1260         }
1261
1262         ring->space -= n;
1263         return 0;
1264 }
1265
1266 void intel_ring_advance(struct intel_ring_buffer *ring)
1267 {
1268         ring->tail &= ring->size - 1;
1269         ring->write_tail(ring, ring->tail);
1270 }
1271
1272 static const struct intel_ring_buffer render_ring = {
1273         .name                   = "render ring",
1274         .id                     = RCS,
1275         .mmio_base              = RENDER_RING_BASE,
1276         .size                   = 32 * PAGE_SIZE,
1277         .init                   = init_render_ring,
1278         .write_tail             = ring_write_tail,
1279         .flush                  = render_ring_flush,
1280         .add_request            = render_ring_add_request,
1281         .get_seqno              = ring_get_seqno,
1282         .irq_get                = render_ring_get_irq,
1283         .irq_put                = render_ring_put_irq,
1284         .dispatch_execbuffer    = render_ring_dispatch_execbuffer,
1285         .cleanup                = render_ring_cleanup,
1286         .sync_to                = render_ring_sync_to,
1287         .semaphore_register     = {MI_SEMAPHORE_SYNC_INVALID,
1288                                    MI_SEMAPHORE_SYNC_RV,
1289                                    MI_SEMAPHORE_SYNC_RB},
1290         .signal_mbox            = {GEN6_VRSYNC, GEN6_BRSYNC},
1291 };
1292
1293 /* ring buffer for bit-stream decoder */
1294
1295 static const struct intel_ring_buffer bsd_ring = {
1296         .name                   = "bsd ring",
1297         .id                     = VCS,
1298         .mmio_base              = BSD_RING_BASE,
1299         .size                   = 32 * PAGE_SIZE,
1300         .init                   = init_ring_common,
1301         .write_tail             = ring_write_tail,
1302         .flush                  = bsd_ring_flush,
1303         .add_request            = ring_add_request,
1304         .get_seqno              = ring_get_seqno,
1305         .irq_get                = bsd_ring_get_irq,
1306         .irq_put                = bsd_ring_put_irq,
1307         .dispatch_execbuffer    = ring_dispatch_execbuffer,
1308 };
1309
1310
1311 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1312                                      u32 value)
1313 {
1314         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1315
1316        /* Every tail move must follow the sequence below */
1317         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1318                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1319                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
1320         I915_WRITE(GEN6_BSD_RNCID, 0x0);
1321
1322         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1323                 GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
1324                 50))
1325         DRM_ERROR("timed out waiting for IDLE Indicator\n");
1326
1327         I915_WRITE_TAIL(ring, value);
1328         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1329                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
1330                 GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
1331 }
1332
1333 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1334                            u32 invalidate, u32 flush)
1335 {
1336         uint32_t cmd;
1337         int ret;
1338
1339         ret = intel_ring_begin(ring, 4);
1340         if (ret)
1341                 return ret;
1342
1343         cmd = MI_FLUSH_DW;
1344         if (invalidate & I915_GEM_GPU_DOMAINS)
1345                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
1346         intel_ring_emit(ring, cmd);
1347         intel_ring_emit(ring, 0);
1348         intel_ring_emit(ring, 0);
1349         intel_ring_emit(ring, MI_NOOP);
1350         intel_ring_advance(ring);
1351         return 0;
1352 }
1353
1354 static int
1355 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1356                               u32 offset, u32 len)
1357 {
1358         int ret;
1359
1360         ret = intel_ring_begin(ring, 2);
1361         if (ret)
1362                 return ret;
1363
1364         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
1365         /* bit0-7 is the length on GEN6+ */
1366         intel_ring_emit(ring, offset);
1367         intel_ring_advance(ring);
1368
1369         return 0;
1370 }
1371
1372 static bool
1373 gen6_render_ring_get_irq(struct intel_ring_buffer *ring)
1374 {
1375         return gen6_ring_get_irq(ring,
1376                                  GT_USER_INTERRUPT,
1377                                  GEN6_RENDER_USER_INTERRUPT);
1378 }
1379
1380 static void
1381 gen6_render_ring_put_irq(struct intel_ring_buffer *ring)
1382 {
1383         return gen6_ring_put_irq(ring,
1384                                  GT_USER_INTERRUPT,
1385                                  GEN6_RENDER_USER_INTERRUPT);
1386 }
1387
1388 static bool
1389 gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring)
1390 {
1391         return gen6_ring_get_irq(ring,
1392                                  GT_GEN6_BSD_USER_INTERRUPT,
1393                                  GEN6_BSD_USER_INTERRUPT);
1394 }
1395
1396 static void
1397 gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring)
1398 {
1399         return gen6_ring_put_irq(ring,
1400                                  GT_GEN6_BSD_USER_INTERRUPT,
1401                                  GEN6_BSD_USER_INTERRUPT);
1402 }
1403
1404 /* ring buffer for Video Codec for Gen6+ */
1405 static const struct intel_ring_buffer gen6_bsd_ring = {
1406         .name                   = "gen6 bsd ring",
1407         .id                     = VCS,
1408         .mmio_base              = GEN6_BSD_RING_BASE,
1409         .size                   = 32 * PAGE_SIZE,
1410         .init                   = init_ring_common,
1411         .write_tail             = gen6_bsd_ring_write_tail,
1412         .flush                  = gen6_ring_flush,
1413         .add_request            = gen6_add_request,
1414         .get_seqno              = gen6_ring_get_seqno,
1415         .irq_get                = gen6_bsd_ring_get_irq,
1416         .irq_put                = gen6_bsd_ring_put_irq,
1417         .dispatch_execbuffer    = gen6_ring_dispatch_execbuffer,
1418         .sync_to                = gen6_bsd_ring_sync_to,
1419         .semaphore_register     = {MI_SEMAPHORE_SYNC_VR,
1420                                    MI_SEMAPHORE_SYNC_INVALID,
1421                                    MI_SEMAPHORE_SYNC_VB},
1422         .signal_mbox            = {GEN6_RVSYNC, GEN6_BVSYNC},
1423 };
1424
1425 /* Blitter support (SandyBridge+) */
1426
1427 static bool
1428 blt_ring_get_irq(struct intel_ring_buffer *ring)
1429 {
1430         return gen6_ring_get_irq(ring,
1431                                  GT_BLT_USER_INTERRUPT,
1432                                  GEN6_BLITTER_USER_INTERRUPT);
1433 }
1434
1435 static void
1436 blt_ring_put_irq(struct intel_ring_buffer *ring)
1437 {
1438         gen6_ring_put_irq(ring,
1439                           GT_BLT_USER_INTERRUPT,
1440                           GEN6_BLITTER_USER_INTERRUPT);
1441 }
1442
1443 static int blt_ring_flush(struct intel_ring_buffer *ring,
1444                           u32 invalidate, u32 flush)
1445 {
1446         uint32_t cmd;
1447         int ret;
1448
1449         ret = intel_ring_begin(ring, 4);
1450         if (ret)
1451                 return ret;
1452
1453         cmd = MI_FLUSH_DW;
1454         if (invalidate & I915_GEM_DOMAIN_RENDER)
1455                 cmd |= MI_INVALIDATE_TLB;
1456         intel_ring_emit(ring, cmd);
1457         intel_ring_emit(ring, 0);
1458         intel_ring_emit(ring, 0);
1459         intel_ring_emit(ring, MI_NOOP);
1460         intel_ring_advance(ring);
1461         return 0;
1462 }
1463
1464 static const struct intel_ring_buffer gen6_blt_ring = {
1465         .name                   = "blt ring",
1466         .id                     = BCS,
1467         .mmio_base              = BLT_RING_BASE,
1468         .size                   = 32 * PAGE_SIZE,
1469         .init                   = init_ring_common,
1470         .write_tail             = ring_write_tail,
1471         .flush                  = blt_ring_flush,
1472         .add_request            = gen6_add_request,
1473         .get_seqno              = gen6_ring_get_seqno,
1474         .irq_get                = blt_ring_get_irq,
1475         .irq_put                = blt_ring_put_irq,
1476         .dispatch_execbuffer    = gen6_ring_dispatch_execbuffer,
1477         .sync_to                = gen6_blt_ring_sync_to,
1478         .semaphore_register     = {MI_SEMAPHORE_SYNC_BR,
1479                                    MI_SEMAPHORE_SYNC_BV,
1480                                    MI_SEMAPHORE_SYNC_INVALID},
1481         .signal_mbox            = {GEN6_RBSYNC, GEN6_VBSYNC},
1482 };
1483
1484 int intel_init_render_ring_buffer(struct drm_device *dev)
1485 {
1486         drm_i915_private_t *dev_priv = dev->dev_private;
1487         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1488
1489         *ring = render_ring;
1490         if (INTEL_INFO(dev)->gen >= 6) {
1491                 ring->add_request = gen6_add_request;
1492                 ring->flush = gen6_render_ring_flush;
1493                 ring->irq_get = gen6_render_ring_get_irq;
1494                 ring->irq_put = gen6_render_ring_put_irq;
1495                 ring->get_seqno = gen6_ring_get_seqno;
1496         } else if (IS_GEN5(dev)) {
1497                 ring->add_request = pc_render_add_request;
1498                 ring->get_seqno = pc_render_get_seqno;
1499         }
1500
1501         if (!I915_NEED_GFX_HWS(dev)) {
1502                 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1503                 memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1504         }
1505
1506         return intel_init_ring_buffer(dev, ring);
1507 }
1508
1509 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1510 {
1511         drm_i915_private_t *dev_priv = dev->dev_private;
1512         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1513
1514         *ring = render_ring;
1515         if (INTEL_INFO(dev)->gen >= 6) {
1516                 ring->add_request = gen6_add_request;
1517                 ring->irq_get = gen6_render_ring_get_irq;
1518                 ring->irq_put = gen6_render_ring_put_irq;
1519         } else if (IS_GEN5(dev)) {
1520                 ring->add_request = pc_render_add_request;
1521                 ring->get_seqno = pc_render_get_seqno;
1522         }
1523
1524         if (!I915_NEED_GFX_HWS(dev))
1525                 ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1526
1527         ring->dev = dev;
1528         INIT_LIST_HEAD(&ring->active_list);
1529         INIT_LIST_HEAD(&ring->request_list);
1530         INIT_LIST_HEAD(&ring->gpu_write_list);
1531
1532         ring->size = size;
1533         ring->effective_size = ring->size;
1534         if (IS_I830(ring->dev))
1535                 ring->effective_size -= 128;
1536
1537         ring->map.offset = start;
1538         ring->map.size = size;
1539         ring->map.type = 0;
1540         ring->map.flags = 0;
1541         ring->map.mtrr = 0;
1542
1543         drm_core_ioremap_wc(&ring->map, dev);
1544         if (ring->map.handle == NULL) {
1545                 DRM_ERROR("can not ioremap virtual address for"
1546                           " ring buffer\n");
1547                 return -ENOMEM;
1548         }
1549
1550         ring->virtual_start = (void __force __iomem *)ring->map.handle;
1551         return 0;
1552 }
1553
1554 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1555 {
1556         drm_i915_private_t *dev_priv = dev->dev_private;
1557         struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1558
1559         if (IS_GEN6(dev) || IS_GEN7(dev))
1560                 *ring = gen6_bsd_ring;
1561         else
1562                 *ring = bsd_ring;
1563
1564         return intel_init_ring_buffer(dev, ring);
1565 }
1566
1567 int intel_init_blt_ring_buffer(struct drm_device *dev)
1568 {
1569         drm_i915_private_t *dev_priv = dev->dev_private;
1570         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1571
1572         *ring = gen6_blt_ring;
1573
1574         return intel_init_ring_buffer(dev, ring);
1575 }