99f2c96a9c70caf8715aa5ae06e151a54b419ff6
[linux-2.6.git] / drivers / gpu / drm / i915 / intel_ringbuffer.c
1 /*
2  * Copyright © 2008-2010 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Authors:
24  *    Eric Anholt <eric@anholt.net>
25  *    Zou Nan hai <nanhai.zou@intel.com>
26  *    Xiang Hai hao<haihao.xiang@intel.com>
27  *
28  */
29
30 #include "drmP.h"
31 #include "drm.h"
32 #include "i915_drv.h"
33 #include "i915_drm.h"
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36
37 static u32 i915_gem_get_seqno(struct drm_device *dev)
38 {
39         drm_i915_private_t *dev_priv = dev->dev_private;
40         u32 seqno;
41
42         seqno = dev_priv->next_seqno;
43
44         /* reserve 0 for non-seqno */
45         if (++dev_priv->next_seqno == 0)
46                 dev_priv->next_seqno = 1;
47
48         return seqno;
49 }
50
51 static void
52 render_ring_flush(struct intel_ring_buffer *ring,
53                   u32   invalidate_domains,
54                   u32   flush_domains)
55 {
56         struct drm_device *dev = ring->dev;
57         drm_i915_private_t *dev_priv = dev->dev_private;
58         u32 cmd;
59
60 #if WATCH_EXEC
61         DRM_INFO("%s: invalidate %08x flush %08x\n", __func__,
62                   invalidate_domains, flush_domains);
63 #endif
64
65         trace_i915_gem_request_flush(dev, dev_priv->next_seqno,
66                                      invalidate_domains, flush_domains);
67
68         if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) {
69                 /*
70                  * read/write caches:
71                  *
72                  * I915_GEM_DOMAIN_RENDER is always invalidated, but is
73                  * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
74                  * also flushed at 2d versus 3d pipeline switches.
75                  *
76                  * read-only caches:
77                  *
78                  * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
79                  * MI_READ_FLUSH is set, and is always flushed on 965.
80                  *
81                  * I915_GEM_DOMAIN_COMMAND may not exist?
82                  *
83                  * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
84                  * invalidated when MI_EXE_FLUSH is set.
85                  *
86                  * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
87                  * invalidated with every MI_FLUSH.
88                  *
89                  * TLBs:
90                  *
91                  * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
92                  * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
93                  * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
94                  * are flushed at any MI_FLUSH.
95                  */
96
97                 cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
98                 if ((invalidate_domains|flush_domains) &
99                     I915_GEM_DOMAIN_RENDER)
100                         cmd &= ~MI_NO_WRITE_FLUSH;
101                 if (INTEL_INFO(dev)->gen < 4) {
102                         /*
103                          * On the 965, the sampler cache always gets flushed
104                          * and this bit is reserved.
105                          */
106                         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
107                                 cmd |= MI_READ_FLUSH;
108                 }
109                 if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
110                         cmd |= MI_EXE_FLUSH;
111
112 #if WATCH_EXEC
113                 DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd);
114 #endif
115                 if (intel_ring_begin(ring, 2) == 0) {
116                         intel_ring_emit(ring, cmd);
117                         intel_ring_emit(ring, MI_NOOP);
118                         intel_ring_advance(ring);
119                 }
120         }
121 }
122
123 static void ring_write_tail(struct intel_ring_buffer *ring,
124                             u32 value)
125 {
126         drm_i915_private_t *dev_priv = ring->dev->dev_private;
127         I915_WRITE_TAIL(ring, value);
128 }
129
130 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
131 {
132         drm_i915_private_t *dev_priv = ring->dev->dev_private;
133         u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
134                         RING_ACTHD(ring->mmio_base) : ACTHD;
135
136         return I915_READ(acthd_reg);
137 }
138
139 static int init_ring_common(struct intel_ring_buffer *ring)
140 {
141         drm_i915_private_t *dev_priv = ring->dev->dev_private;
142         struct drm_i915_gem_object *obj_priv = to_intel_bo(ring->gem_object);
143         u32 head;
144
145         /* Stop the ring if it's running. */
146         I915_WRITE_CTL(ring, 0);
147         I915_WRITE_HEAD(ring, 0);
148         ring->write_tail(ring, 0);
149
150         /* Initialize the ring. */
151         I915_WRITE_START(ring, obj_priv->gtt_offset);
152         head = I915_READ_HEAD(ring) & HEAD_ADDR;
153
154         /* G45 ring initialization fails to reset head to zero */
155         if (head != 0) {
156                 DRM_ERROR("%s head not reset to zero "
157                                 "ctl %08x head %08x tail %08x start %08x\n",
158                                 ring->name,
159                                 I915_READ_CTL(ring),
160                                 I915_READ_HEAD(ring),
161                                 I915_READ_TAIL(ring),
162                                 I915_READ_START(ring));
163
164                 I915_WRITE_HEAD(ring, 0);
165
166                 DRM_ERROR("%s head forced to zero "
167                                 "ctl %08x head %08x tail %08x start %08x\n",
168                                 ring->name,
169                                 I915_READ_CTL(ring),
170                                 I915_READ_HEAD(ring),
171                                 I915_READ_TAIL(ring),
172                                 I915_READ_START(ring));
173         }
174
175         I915_WRITE_CTL(ring,
176                         ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
177                         | RING_REPORT_64K | RING_VALID);
178
179         /* If the head is still not zero, the ring is dead */
180         if ((I915_READ_CTL(ring) & RING_VALID) == 0 ||
181             I915_READ_START(ring) != obj_priv->gtt_offset ||
182             (I915_READ_HEAD(ring) & HEAD_ADDR) != 0) {
183                 if (IS_GEN6(ring->dev) && ring->dev->pdev->revision <= 8) {
184                         /* Early revisions of Sandybridge do not like
185                          * revealing the contents of the ring buffer
186                          * registers whilst idle. Fortunately, the
187                          * auto-reporting mechanism prevents most hangs,
188                          * but this will bite us eventually...
189                          */
190                         DRM_DEBUG("%s initialization failed "
191                                   "ctl %08x head %08x tail %08x start %08x. Ignoring, hope for the best!\n",
192                                   ring->name,
193                                   I915_READ_CTL(ring),
194                                   I915_READ_HEAD(ring),
195                                   I915_READ_TAIL(ring),
196                                   I915_READ_START(ring));
197                 } else {
198                         DRM_ERROR("%s initialization failed "
199                                   "ctl %08x head %08x tail %08x start %08x\n",
200                                   ring->name,
201                                   I915_READ_CTL(ring),
202                                   I915_READ_HEAD(ring),
203                                   I915_READ_TAIL(ring),
204                                   I915_READ_START(ring));
205                         return -EIO;
206                 }
207         }
208
209         if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
210                 i915_kernel_lost_context(ring->dev);
211         else {
212                 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
213                 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
214                 ring->space = ring->head - (ring->tail + 8);
215                 if (ring->space < 0)
216                         ring->space += ring->size;
217         }
218         return 0;
219 }
220
221 static int init_render_ring(struct intel_ring_buffer *ring)
222 {
223         struct drm_device *dev = ring->dev;
224         int ret = init_ring_common(ring);
225
226         if (INTEL_INFO(dev)->gen > 3) {
227                 drm_i915_private_t *dev_priv = dev->dev_private;
228                 int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
229                 if (IS_GEN6(dev))
230                         mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
231                 I915_WRITE(MI_MODE, mode);
232         }
233
234         return ret;
235 }
236
237 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
238 do {                                                                    \
239         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |           \
240                  PIPE_CONTROL_DEPTH_STALL | 2);                         \
241         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
242         intel_ring_emit(ring__, 0);                                                     \
243         intel_ring_emit(ring__, 0);                                                     \
244 } while (0)
245
246 /**
247  * Creates a new sequence number, emitting a write of it to the status page
248  * plus an interrupt, which will trigger i915_user_interrupt_handler.
249  *
250  * Must be called with struct_lock held.
251  *
252  * Returned sequence numbers are nonzero on success.
253  */
254 static int
255 render_ring_add_request(struct intel_ring_buffer *ring,
256                         u32 *result)
257 {
258         struct drm_device *dev = ring->dev;
259         drm_i915_private_t *dev_priv = dev->dev_private;
260         u32 seqno = i915_gem_get_seqno(dev);
261         int ret;
262
263         if (IS_GEN6(dev)) {
264                 ret = intel_ring_begin(ring, 6);
265                 if (ret)
266                     return ret;
267
268                 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | 3);
269                 intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE |
270                                 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_IS_FLUSH |
271                                 PIPE_CONTROL_NOTIFY);
272                 intel_ring_emit(ring, dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
273                 intel_ring_emit(ring, seqno);
274                 intel_ring_emit(ring, 0);
275                 intel_ring_emit(ring, 0);
276         } else if (HAS_PIPE_CONTROL(dev)) {
277                 u32 scratch_addr = dev_priv->seqno_gfx_addr + 128;
278
279                 /*
280                  * Workaround qword write incoherence by flushing the
281                  * PIPE_NOTIFY buffers out to memory before requesting
282                  * an interrupt.
283                  */
284                 ret = intel_ring_begin(ring, 32);
285                 if (ret)
286                         return ret;
287
288                 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
289                                 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH);
290                 intel_ring_emit(ring, dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
291                 intel_ring_emit(ring, seqno);
292                 intel_ring_emit(ring, 0);
293                 PIPE_CONTROL_FLUSH(ring, scratch_addr);
294                 scratch_addr += 128; /* write to separate cachelines */
295                 PIPE_CONTROL_FLUSH(ring, scratch_addr);
296                 scratch_addr += 128;
297                 PIPE_CONTROL_FLUSH(ring, scratch_addr);
298                 scratch_addr += 128;
299                 PIPE_CONTROL_FLUSH(ring, scratch_addr);
300                 scratch_addr += 128;
301                 PIPE_CONTROL_FLUSH(ring, scratch_addr);
302                 scratch_addr += 128;
303                 PIPE_CONTROL_FLUSH(ring, scratch_addr);
304                 intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
305                                 PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
306                                 PIPE_CONTROL_NOTIFY);
307                 intel_ring_emit(ring, dev_priv->seqno_gfx_addr | PIPE_CONTROL_GLOBAL_GTT);
308                 intel_ring_emit(ring, seqno);
309                 intel_ring_emit(ring, 0);
310         } else {
311                 ret = intel_ring_begin(ring, 4);
312                 if (ret)
313                     return ret;
314
315                 intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
316                 intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
317                 intel_ring_emit(ring, seqno);
318
319                 intel_ring_emit(ring, MI_USER_INTERRUPT);
320         }
321
322         intel_ring_advance(ring);
323         *result = seqno;
324         return 0;
325 }
326
327 static u32
328 render_ring_get_seqno(struct intel_ring_buffer *ring)
329 {
330         struct drm_device *dev = ring->dev;
331         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
332         if (HAS_PIPE_CONTROL(dev))
333                 return ((volatile u32 *)(dev_priv->seqno_page))[0];
334         else
335                 return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
336 }
337
338 static void
339 render_ring_get_user_irq(struct intel_ring_buffer *ring)
340 {
341         struct drm_device *dev = ring->dev;
342         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
343         unsigned long irqflags;
344
345         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
346         if (dev->irq_enabled && (++ring->user_irq_refcount == 1)) {
347                 if (HAS_PCH_SPLIT(dev))
348                         ironlake_enable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
349                 else
350                         i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
351         }
352         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
353 }
354
355 static void
356 render_ring_put_user_irq(struct intel_ring_buffer *ring)
357 {
358         struct drm_device *dev = ring->dev;
359         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
360         unsigned long irqflags;
361
362         spin_lock_irqsave(&dev_priv->user_irq_lock, irqflags);
363         BUG_ON(dev->irq_enabled && ring->user_irq_refcount <= 0);
364         if (dev->irq_enabled && (--ring->user_irq_refcount == 0)) {
365                 if (HAS_PCH_SPLIT(dev))
366                         ironlake_disable_graphics_irq(dev_priv, GT_PIPE_NOTIFY);
367                 else
368                         i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
369         }
370         spin_unlock_irqrestore(&dev_priv->user_irq_lock, irqflags);
371 }
372
373 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
374 {
375         drm_i915_private_t *dev_priv = ring->dev->dev_private;
376         u32 mmio = IS_GEN6(ring->dev) ?
377                 RING_HWS_PGA_GEN6(ring->mmio_base) :
378                 RING_HWS_PGA(ring->mmio_base);
379         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
380         POSTING_READ(mmio);
381 }
382
383 static void
384 bsd_ring_flush(struct intel_ring_buffer *ring,
385                u32     invalidate_domains,
386                u32     flush_domains)
387 {
388         if (intel_ring_begin(ring, 2) == 0) {
389                 intel_ring_emit(ring, MI_FLUSH);
390                 intel_ring_emit(ring, MI_NOOP);
391                 intel_ring_advance(ring);
392         }
393 }
394
395 static int
396 ring_add_request(struct intel_ring_buffer *ring,
397                  u32 *result)
398 {
399         u32 seqno;
400         int ret;
401
402         ret = intel_ring_begin(ring, 4);
403         if (ret)
404                 return ret;
405
406         seqno = i915_gem_get_seqno(ring->dev);
407
408         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
409         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
410         intel_ring_emit(ring, seqno);
411         intel_ring_emit(ring, MI_USER_INTERRUPT);
412         intel_ring_advance(ring);
413
414         DRM_DEBUG_DRIVER("%s %d\n", ring->name, seqno);
415         *result = seqno;
416         return 0;
417 }
418
419 static void
420 bsd_ring_get_user_irq(struct intel_ring_buffer *ring)
421 {
422         /* do nothing */
423 }
424 static void
425 bsd_ring_put_user_irq(struct intel_ring_buffer *ring)
426 {
427         /* do nothing */
428 }
429
430 static u32
431 ring_status_page_get_seqno(struct intel_ring_buffer *ring)
432 {
433         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
434 }
435
436 static int
437 ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
438                          struct drm_i915_gem_execbuffer2 *exec,
439                          struct drm_clip_rect *cliprects,
440                          uint64_t exec_offset)
441 {
442         uint32_t exec_start;
443         int ret;
444
445         exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
446
447         ret = intel_ring_begin(ring, 2);
448         if (ret)
449                 return ret;
450
451         intel_ring_emit(ring,
452                         MI_BATCH_BUFFER_START |
453                         (2 << 6) |
454                         MI_BATCH_NON_SECURE_I965);
455         intel_ring_emit(ring, exec_start);
456         intel_ring_advance(ring);
457
458         return 0;
459 }
460
461 static int
462 render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
463                                 struct drm_i915_gem_execbuffer2 *exec,
464                                 struct drm_clip_rect *cliprects,
465                                 uint64_t exec_offset)
466 {
467         struct drm_device *dev = ring->dev;
468         drm_i915_private_t *dev_priv = dev->dev_private;
469         int nbox = exec->num_cliprects;
470         uint32_t exec_start, exec_len;
471         int i, count, ret;
472
473         exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
474         exec_len = (uint32_t) exec->batch_len;
475
476         trace_i915_gem_request_submit(dev, dev_priv->next_seqno + 1);
477
478         count = nbox ? nbox : 1;
479         for (i = 0; i < count; i++) {
480                 if (i < nbox) {
481                         ret = i915_emit_box(dev, cliprects, i,
482                                             exec->DR1, exec->DR4);
483                         if (ret)
484                                 return ret;
485                 }
486
487                 if (IS_I830(dev) || IS_845G(dev)) {
488                         ret = intel_ring_begin(ring, 4);
489                         if (ret)
490                                 return ret;
491
492                         intel_ring_emit(ring, MI_BATCH_BUFFER);
493                         intel_ring_emit(ring, exec_start | MI_BATCH_NON_SECURE);
494                         intel_ring_emit(ring, exec_start + exec_len - 4);
495                         intel_ring_emit(ring, 0);
496                 } else {
497                         ret = intel_ring_begin(ring, 2);
498                         if (ret)
499                                 return ret;
500
501                         if (INTEL_INFO(dev)->gen >= 4) {
502                                 intel_ring_emit(ring,
503                                                 MI_BATCH_BUFFER_START | (2 << 6)
504                                                 | MI_BATCH_NON_SECURE_I965);
505                                 intel_ring_emit(ring, exec_start);
506                         } else {
507                                 intel_ring_emit(ring, MI_BATCH_BUFFER_START
508                                                 | (2 << 6));
509                                 intel_ring_emit(ring, exec_start |
510                                                 MI_BATCH_NON_SECURE);
511                         }
512                 }
513                 intel_ring_advance(ring);
514         }
515
516         if (IS_G4X(dev) || IS_GEN5(dev)) {
517                 if (intel_ring_begin(ring, 2) == 0) {
518                         intel_ring_emit(ring, MI_FLUSH |
519                                         MI_NO_WRITE_FLUSH |
520                                         MI_INVALIDATE_ISP );
521                         intel_ring_emit(ring, MI_NOOP);
522                         intel_ring_advance(ring);
523                 }
524         }
525         /* XXX breadcrumb */
526
527         return 0;
528 }
529
530 static void cleanup_status_page(struct intel_ring_buffer *ring)
531 {
532         drm_i915_private_t *dev_priv = ring->dev->dev_private;
533         struct drm_gem_object *obj;
534         struct drm_i915_gem_object *obj_priv;
535
536         obj = ring->status_page.obj;
537         if (obj == NULL)
538                 return;
539         obj_priv = to_intel_bo(obj);
540
541         kunmap(obj_priv->pages[0]);
542         i915_gem_object_unpin(obj);
543         drm_gem_object_unreference(obj);
544         ring->status_page.obj = NULL;
545
546         memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
547 }
548
549 static int init_status_page(struct intel_ring_buffer *ring)
550 {
551         struct drm_device *dev = ring->dev;
552         drm_i915_private_t *dev_priv = dev->dev_private;
553         struct drm_gem_object *obj;
554         struct drm_i915_gem_object *obj_priv;
555         int ret;
556
557         obj = i915_gem_alloc_object(dev, 4096);
558         if (obj == NULL) {
559                 DRM_ERROR("Failed to allocate status page\n");
560                 ret = -ENOMEM;
561                 goto err;
562         }
563         obj_priv = to_intel_bo(obj);
564         obj_priv->agp_type = AGP_USER_CACHED_MEMORY;
565
566         ret = i915_gem_object_pin(obj, 4096, true);
567         if (ret != 0) {
568                 goto err_unref;
569         }
570
571         ring->status_page.gfx_addr = obj_priv->gtt_offset;
572         ring->status_page.page_addr = kmap(obj_priv->pages[0]);
573         if (ring->status_page.page_addr == NULL) {
574                 memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
575                 goto err_unpin;
576         }
577         ring->status_page.obj = obj;
578         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
579
580         intel_ring_setup_status_page(ring);
581         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
582                         ring->name, ring->status_page.gfx_addr);
583
584         return 0;
585
586 err_unpin:
587         i915_gem_object_unpin(obj);
588 err_unref:
589         drm_gem_object_unreference(obj);
590 err:
591         return ret;
592 }
593
594 int intel_init_ring_buffer(struct drm_device *dev,
595                            struct intel_ring_buffer *ring)
596 {
597         struct drm_i915_gem_object *obj_priv;
598         struct drm_gem_object *obj;
599         int ret;
600
601         ring->dev = dev;
602         INIT_LIST_HEAD(&ring->active_list);
603         INIT_LIST_HEAD(&ring->request_list);
604         INIT_LIST_HEAD(&ring->gpu_write_list);
605
606         if (I915_NEED_GFX_HWS(dev)) {
607                 ret = init_status_page(ring);
608                 if (ret)
609                         return ret;
610         }
611
612         obj = i915_gem_alloc_object(dev, ring->size);
613         if (obj == NULL) {
614                 DRM_ERROR("Failed to allocate ringbuffer\n");
615                 ret = -ENOMEM;
616                 goto err_hws;
617         }
618
619         ring->gem_object = obj;
620
621         ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
622         if (ret)
623                 goto err_unref;
624
625         obj_priv = to_intel_bo(obj);
626         ring->map.size = ring->size;
627         ring->map.offset = dev->agp->base + obj_priv->gtt_offset;
628         ring->map.type = 0;
629         ring->map.flags = 0;
630         ring->map.mtrr = 0;
631
632         drm_core_ioremap_wc(&ring->map, dev);
633         if (ring->map.handle == NULL) {
634                 DRM_ERROR("Failed to map ringbuffer.\n");
635                 ret = -EINVAL;
636                 goto err_unpin;
637         }
638
639         ring->virtual_start = ring->map.handle;
640         ret = ring->init(ring);
641         if (ret)
642                 goto err_unmap;
643
644         return 0;
645
646 err_unmap:
647         drm_core_ioremapfree(&ring->map, dev);
648 err_unpin:
649         i915_gem_object_unpin(obj);
650 err_unref:
651         drm_gem_object_unreference(obj);
652         ring->gem_object = NULL;
653 err_hws:
654         cleanup_status_page(ring);
655         return ret;
656 }
657
658 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
659 {
660         struct drm_i915_private *dev_priv;
661         int ret;
662
663         if (ring->gem_object == NULL)
664                 return;
665
666         /* Disable the ring buffer. The ring must be idle at this point */
667         dev_priv = ring->dev->dev_private;
668         ret = intel_wait_ring_buffer(ring, ring->size - 8);
669         I915_WRITE_CTL(ring, 0);
670
671         drm_core_ioremapfree(&ring->map, ring->dev);
672
673         i915_gem_object_unpin(ring->gem_object);
674         drm_gem_object_unreference(ring->gem_object);
675         ring->gem_object = NULL;
676
677         if (ring->cleanup)
678                 ring->cleanup(ring);
679
680         cleanup_status_page(ring);
681 }
682
683 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
684 {
685         unsigned int *virt;
686         int rem;
687         rem = ring->size - ring->tail;
688
689         if (ring->space < rem) {
690                 int ret = intel_wait_ring_buffer(ring, rem);
691                 if (ret)
692                         return ret;
693         }
694
695         virt = (unsigned int *)(ring->virtual_start + ring->tail);
696         rem /= 8;
697         while (rem--) {
698                 *virt++ = MI_NOOP;
699                 *virt++ = MI_NOOP;
700         }
701
702         ring->tail = 0;
703         ring->space = ring->head - 8;
704
705         return 0;
706 }
707
708 int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
709 {
710         struct drm_device *dev = ring->dev;
711         struct drm_i915_private *dev_priv = dev->dev_private;
712         unsigned long end;
713         u32 head;
714
715         head = intel_read_status_page(ring, 4);
716         if (head) {
717                 ring->head = head & HEAD_ADDR;
718                 ring->space = ring->head - (ring->tail + 8);
719                 if (ring->space < 0)
720                         ring->space += ring->size;
721                 if (ring->space >= n)
722                         return 0;
723         }
724
725         trace_i915_ring_wait_begin (dev);
726         end = jiffies + 3 * HZ;
727         do {
728                 ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
729                 ring->space = ring->head - (ring->tail + 8);
730                 if (ring->space < 0)
731                         ring->space += ring->size;
732                 if (ring->space >= n) {
733                         trace_i915_ring_wait_end(dev);
734                         return 0;
735                 }
736
737                 if (dev->primary->master) {
738                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
739                         if (master_priv->sarea_priv)
740                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
741                 }
742
743                 msleep(1);
744                 if (atomic_read(&dev_priv->mm.wedged))
745                         return -EAGAIN;
746         } while (!time_after(jiffies, end));
747         trace_i915_ring_wait_end (dev);
748         return -EBUSY;
749 }
750
751 int intel_ring_begin(struct intel_ring_buffer *ring,
752                      int num_dwords)
753 {
754         int n = 4*num_dwords;
755         int ret;
756
757         if (unlikely(ring->tail + n > ring->size)) {
758                 ret = intel_wrap_ring_buffer(ring);
759                 if (unlikely(ret))
760                         return ret;
761         }
762
763         if (unlikely(ring->space < n)) {
764                 ret = intel_wait_ring_buffer(ring, n);
765                 if (unlikely(ret))
766                         return ret;
767         }
768
769         ring->space -= n;
770         return 0;
771 }
772
773 void intel_ring_advance(struct intel_ring_buffer *ring)
774 {
775         ring->tail &= ring->size - 1;
776         ring->write_tail(ring, ring->tail);
777 }
778
779 static const struct intel_ring_buffer render_ring = {
780         .name                   = "render ring",
781         .id                     = RING_RENDER,
782         .mmio_base              = RENDER_RING_BASE,
783         .size                   = 32 * PAGE_SIZE,
784         .init                   = init_render_ring,
785         .write_tail             = ring_write_tail,
786         .flush                  = render_ring_flush,
787         .add_request            = render_ring_add_request,
788         .get_seqno              = render_ring_get_seqno,
789         .user_irq_get           = render_ring_get_user_irq,
790         .user_irq_put           = render_ring_put_user_irq,
791         .dispatch_execbuffer    = render_ring_dispatch_execbuffer,
792 };
793
794 /* ring buffer for bit-stream decoder */
795
796 static const struct intel_ring_buffer bsd_ring = {
797         .name                   = "bsd ring",
798         .id                     = RING_BSD,
799         .mmio_base              = BSD_RING_BASE,
800         .size                   = 32 * PAGE_SIZE,
801         .init                   = init_ring_common,
802         .write_tail             = ring_write_tail,
803         .flush                  = bsd_ring_flush,
804         .add_request            = ring_add_request,
805         .get_seqno              = ring_status_page_get_seqno,
806         .user_irq_get           = bsd_ring_get_user_irq,
807         .user_irq_put           = bsd_ring_put_user_irq,
808         .dispatch_execbuffer    = ring_dispatch_execbuffer,
809 };
810
811
812 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
813                                      u32 value)
814 {
815        drm_i915_private_t *dev_priv = ring->dev->dev_private;
816
817        /* Every tail move must follow the sequence below */
818        I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
819                GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
820                GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
821        I915_WRITE(GEN6_BSD_RNCID, 0x0);
822
823        if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
824                                GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
825                        50))
826                DRM_ERROR("timed out waiting for IDLE Indicator\n");
827
828        I915_WRITE_TAIL(ring, value);
829        I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
830                GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
831                GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
832 }
833
834 static void gen6_ring_flush(struct intel_ring_buffer *ring,
835                             u32 invalidate_domains,
836                             u32 flush_domains)
837 {
838         if (intel_ring_begin(ring, 4) == 0) {
839                 intel_ring_emit(ring, MI_FLUSH_DW);
840                 intel_ring_emit(ring, 0);
841                 intel_ring_emit(ring, 0);
842                 intel_ring_emit(ring, 0);
843                 intel_ring_advance(ring);
844         }
845 }
846
847 static int
848 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
849                               struct drm_i915_gem_execbuffer2 *exec,
850                               struct drm_clip_rect *cliprects,
851                               uint64_t exec_offset)
852 {
853        uint32_t exec_start;
854        int ret;
855
856        exec_start = (uint32_t) exec_offset + exec->batch_start_offset;
857
858        ret = intel_ring_begin(ring, 2);
859        if (ret)
860                return ret;
861
862        intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
863        /* bit0-7 is the length on GEN6+ */
864        intel_ring_emit(ring, exec_start);
865        intel_ring_advance(ring);
866
867        return 0;
868 }
869
870 /* ring buffer for Video Codec for Gen6+ */
871 static const struct intel_ring_buffer gen6_bsd_ring = {
872        .name                    = "gen6 bsd ring",
873        .id                      = RING_BSD,
874        .mmio_base               = GEN6_BSD_RING_BASE,
875        .size                    = 32 * PAGE_SIZE,
876        .init                    = init_ring_common,
877        .write_tail              = gen6_bsd_ring_write_tail,
878        .flush                   = gen6_ring_flush,
879        .add_request             = ring_add_request,
880        .get_seqno               = ring_status_page_get_seqno,
881        .user_irq_get            = bsd_ring_get_user_irq,
882        .user_irq_put            = bsd_ring_put_user_irq,
883        .dispatch_execbuffer     = gen6_ring_dispatch_execbuffer,
884 };
885
886 /* Blitter support (SandyBridge+) */
887
888 static void
889 blt_ring_get_user_irq(struct intel_ring_buffer *ring)
890 {
891         /* do nothing */
892 }
893 static void
894 blt_ring_put_user_irq(struct intel_ring_buffer *ring)
895 {
896         /* do nothing */
897 }
898
899
900 /* Workaround for some stepping of SNB,
901  * each time when BLT engine ring tail moved,
902  * the first command in the ring to be parsed
903  * should be MI_BATCH_BUFFER_START
904  */
905 #define NEED_BLT_WORKAROUND(dev) \
906         (IS_GEN6(dev) && (dev->pdev->revision < 8))
907
908 static inline struct drm_i915_gem_object *
909 to_blt_workaround(struct intel_ring_buffer *ring)
910 {
911         return ring->private;
912 }
913
914 static int blt_ring_init(struct intel_ring_buffer *ring)
915 {
916         if (NEED_BLT_WORKAROUND(ring->dev)) {
917                 struct drm_i915_gem_object *obj;
918                 u32 *ptr;
919                 int ret;
920
921                 obj = to_intel_bo(i915_gem_alloc_object(ring->dev, 4096));
922                 if (obj == NULL)
923                         return -ENOMEM;
924
925                 ret = i915_gem_object_pin(&obj->base, 4096, true);
926                 if (ret) {
927                         drm_gem_object_unreference(&obj->base);
928                         return ret;
929                 }
930
931                 ptr = kmap(obj->pages[0]);
932                 *ptr++ = MI_BATCH_BUFFER_END;
933                 *ptr++ = MI_NOOP;
934                 kunmap(obj->pages[0]);
935
936                 ret = i915_gem_object_set_to_gtt_domain(&obj->base, false);
937                 if (ret) {
938                         i915_gem_object_unpin(&obj->base);
939                         drm_gem_object_unreference(&obj->base);
940                         return ret;
941                 }
942
943                 ring->private = obj;
944         }
945
946         return init_ring_common(ring);
947 }
948
949 static int blt_ring_begin(struct intel_ring_buffer *ring,
950                           int num_dwords)
951 {
952         if (ring->private) {
953                 int ret = intel_ring_begin(ring, num_dwords+2);
954                 if (ret)
955                         return ret;
956
957                 intel_ring_emit(ring, MI_BATCH_BUFFER_START);
958                 intel_ring_emit(ring, to_blt_workaround(ring)->gtt_offset);
959
960                 return 0;
961         } else
962                 return intel_ring_begin(ring, 4);
963 }
964
965 static void blt_ring_flush(struct intel_ring_buffer *ring,
966                            u32 invalidate_domains,
967                            u32 flush_domains)
968 {
969         if (blt_ring_begin(ring, 4) == 0) {
970                 intel_ring_emit(ring, MI_FLUSH_DW);
971                 intel_ring_emit(ring, 0);
972                 intel_ring_emit(ring, 0);
973                 intel_ring_emit(ring, 0);
974                 intel_ring_advance(ring);
975         }
976 }
977
978 static int
979 blt_ring_add_request(struct intel_ring_buffer *ring,
980                      u32 *result)
981 {
982         u32 seqno;
983         int ret;
984
985         ret = blt_ring_begin(ring, 4);
986         if (ret)
987                 return ret;
988
989         seqno = i915_gem_get_seqno(ring->dev);
990
991         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
992         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
993         intel_ring_emit(ring, seqno);
994         intel_ring_emit(ring, MI_USER_INTERRUPT);
995         intel_ring_advance(ring);
996
997         DRM_DEBUG_DRIVER("%s %d\n", ring->name, seqno);
998         *result = seqno;
999         return 0;
1000 }
1001
1002 static void blt_ring_cleanup(struct intel_ring_buffer *ring)
1003 {
1004         if (!ring->private)
1005                 return;
1006
1007         i915_gem_object_unpin(ring->private);
1008         drm_gem_object_unreference(ring->private);
1009         ring->private = NULL;
1010 }
1011
1012 static const struct intel_ring_buffer gen6_blt_ring = {
1013        .name                    = "blt ring",
1014        .id                      = RING_BLT,
1015        .mmio_base               = BLT_RING_BASE,
1016        .size                    = 32 * PAGE_SIZE,
1017        .init                    = blt_ring_init,
1018        .write_tail              = ring_write_tail,
1019        .flush                   = blt_ring_flush,
1020        .add_request             = blt_ring_add_request,
1021        .get_seqno               = ring_status_page_get_seqno,
1022        .user_irq_get            = blt_ring_get_user_irq,
1023        .user_irq_put            = blt_ring_put_user_irq,
1024        .dispatch_execbuffer     = gen6_ring_dispatch_execbuffer,
1025        .cleanup                 = blt_ring_cleanup,
1026 };
1027
1028 int intel_init_render_ring_buffer(struct drm_device *dev)
1029 {
1030         drm_i915_private_t *dev_priv = dev->dev_private;
1031
1032         dev_priv->render_ring = render_ring;
1033
1034         if (!I915_NEED_GFX_HWS(dev)) {
1035                 dev_priv->render_ring.status_page.page_addr
1036                         = dev_priv->status_page_dmah->vaddr;
1037                 memset(dev_priv->render_ring.status_page.page_addr,
1038                                 0, PAGE_SIZE);
1039         }
1040
1041         return intel_init_ring_buffer(dev, &dev_priv->render_ring);
1042 }
1043
1044 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1045 {
1046         drm_i915_private_t *dev_priv = dev->dev_private;
1047
1048         if (IS_GEN6(dev))
1049                 dev_priv->bsd_ring = gen6_bsd_ring;
1050         else
1051                 dev_priv->bsd_ring = bsd_ring;
1052
1053         return intel_init_ring_buffer(dev, &dev_priv->bsd_ring);
1054 }
1055
1056 int intel_init_blt_ring_buffer(struct drm_device *dev)
1057 {
1058         drm_i915_private_t *dev_priv = dev->dev_private;
1059
1060         dev_priv->blt_ring = gen6_blt_ring;
1061
1062         return intel_init_ring_buffer(dev, &dev_priv->blt_ring);
1063 }