drm/i915/dp: retry link status read 3 times on failure
[linux-2.6.git] / drivers / gpu / drm / i915 / intel_dp.c
1 /*
2  * Copyright © 2008 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Authors:
24  *    Keith Packard <keithp@keithp.com>
25  *
26  */
27
28 #include <linux/i2c.h>
29 #include <linux/slab.h>
30 #include "drmP.h"
31 #include "drm.h"
32 #include "drm_crtc.h"
33 #include "drm_crtc_helper.h"
34 #include "intel_drv.h"
35 #include "i915_drm.h"
36 #include "i915_drv.h"
37 #include "drm_dp_helper.h"
38
39
40 #define DP_LINK_STATUS_SIZE     6
41 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
42
43 #define DP_LINK_CONFIGURATION_SIZE      9
44
45 struct intel_dp {
46         struct intel_encoder base;
47         uint32_t output_reg;
48         uint32_t DP;
49         uint8_t  link_configuration[DP_LINK_CONFIGURATION_SIZE];
50         bool has_audio;
51         int force_audio;
52         uint32_t color_range;
53         int dpms_mode;
54         uint8_t link_bw;
55         uint8_t lane_count;
56         uint8_t dpcd[4];
57         struct i2c_adapter adapter;
58         struct i2c_algo_dp_aux_data algo;
59         bool is_pch_edp;
60         uint8_t train_set[4];
61         uint8_t link_status[DP_LINK_STATUS_SIZE];
62 };
63
64 /**
65  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
66  * @intel_dp: DP struct
67  *
68  * If a CPU or PCH DP output is attached to an eDP panel, this function
69  * will return true, and false otherwise.
70  */
71 static bool is_edp(struct intel_dp *intel_dp)
72 {
73         return intel_dp->base.type == INTEL_OUTPUT_EDP;
74 }
75
76 /**
77  * is_pch_edp - is the port on the PCH and attached to an eDP panel?
78  * @intel_dp: DP struct
79  *
80  * Returns true if the given DP struct corresponds to a PCH DP port attached
81  * to an eDP panel, false otherwise.  Helpful for determining whether we
82  * may need FDI resources for a given DP output or not.
83  */
84 static bool is_pch_edp(struct intel_dp *intel_dp)
85 {
86         return intel_dp->is_pch_edp;
87 }
88
89 static struct intel_dp *enc_to_intel_dp(struct drm_encoder *encoder)
90 {
91         return container_of(encoder, struct intel_dp, base.base);
92 }
93
94 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
95 {
96         return container_of(intel_attached_encoder(connector),
97                             struct intel_dp, base);
98 }
99
100 /**
101  * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
102  * @encoder: DRM encoder
103  *
104  * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
105  * by intel_display.c.
106  */
107 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
108 {
109         struct intel_dp *intel_dp;
110
111         if (!encoder)
112                 return false;
113
114         intel_dp = enc_to_intel_dp(encoder);
115
116         return is_pch_edp(intel_dp);
117 }
118
119 static void intel_dp_start_link_train(struct intel_dp *intel_dp);
120 static void intel_dp_complete_link_train(struct intel_dp *intel_dp);
121 static void intel_dp_link_down(struct intel_dp *intel_dp);
122
123 void
124 intel_edp_link_config (struct intel_encoder *intel_encoder,
125                        int *lane_num, int *link_bw)
126 {
127         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
128
129         *lane_num = intel_dp->lane_count;
130         if (intel_dp->link_bw == DP_LINK_BW_1_62)
131                 *link_bw = 162000;
132         else if (intel_dp->link_bw == DP_LINK_BW_2_7)
133                 *link_bw = 270000;
134 }
135
136 static int
137 intel_dp_max_lane_count(struct intel_dp *intel_dp)
138 {
139         int max_lane_count = 4;
140
141         if (intel_dp->dpcd[0] >= 0x11) {
142                 max_lane_count = intel_dp->dpcd[2] & 0x1f;
143                 switch (max_lane_count) {
144                 case 1: case 2: case 4:
145                         break;
146                 default:
147                         max_lane_count = 4;
148                 }
149         }
150         return max_lane_count;
151 }
152
153 static int
154 intel_dp_max_link_bw(struct intel_dp *intel_dp)
155 {
156         int max_link_bw = intel_dp->dpcd[1];
157
158         switch (max_link_bw) {
159         case DP_LINK_BW_1_62:
160         case DP_LINK_BW_2_7:
161                 break;
162         default:
163                 max_link_bw = DP_LINK_BW_1_62;
164                 break;
165         }
166         return max_link_bw;
167 }
168
169 static int
170 intel_dp_link_clock(uint8_t link_bw)
171 {
172         if (link_bw == DP_LINK_BW_2_7)
173                 return 270000;
174         else
175                 return 162000;
176 }
177
178 /* I think this is a fiction */
179 static int
180 intel_dp_link_required(struct drm_device *dev, struct intel_dp *intel_dp, int pixel_clock)
181 {
182         struct drm_i915_private *dev_priv = dev->dev_private;
183
184         if (is_edp(intel_dp))
185                 return (pixel_clock * dev_priv->edp.bpp + 7) / 8;
186         else
187                 return pixel_clock * 3;
188 }
189
190 static int
191 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
192 {
193         return (max_link_clock * max_lanes * 8) / 10;
194 }
195
196 static int
197 intel_dp_mode_valid(struct drm_connector *connector,
198                     struct drm_display_mode *mode)
199 {
200         struct intel_dp *intel_dp = intel_attached_dp(connector);
201         struct drm_device *dev = connector->dev;
202         struct drm_i915_private *dev_priv = dev->dev_private;
203         int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp));
204         int max_lanes = intel_dp_max_lane_count(intel_dp);
205
206         if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
207                 if (mode->hdisplay > dev_priv->panel_fixed_mode->hdisplay)
208                         return MODE_PANEL;
209
210                 if (mode->vdisplay > dev_priv->panel_fixed_mode->vdisplay)
211                         return MODE_PANEL;
212         }
213
214         /* only refuse the mode on non eDP since we have seen some weird eDP panels
215            which are outside spec tolerances but somehow work by magic */
216         if (!is_edp(intel_dp) &&
217             (intel_dp_link_required(connector->dev, intel_dp, mode->clock)
218              > intel_dp_max_data_rate(max_link_clock, max_lanes)))
219                 return MODE_CLOCK_HIGH;
220
221         if (mode->clock < 10000)
222                 return MODE_CLOCK_LOW;
223
224         return MODE_OK;
225 }
226
227 static uint32_t
228 pack_aux(uint8_t *src, int src_bytes)
229 {
230         int     i;
231         uint32_t v = 0;
232
233         if (src_bytes > 4)
234                 src_bytes = 4;
235         for (i = 0; i < src_bytes; i++)
236                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
237         return v;
238 }
239
240 static void
241 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
242 {
243         int i;
244         if (dst_bytes > 4)
245                 dst_bytes = 4;
246         for (i = 0; i < dst_bytes; i++)
247                 dst[i] = src >> ((3-i) * 8);
248 }
249
250 /* hrawclock is 1/4 the FSB frequency */
251 static int
252 intel_hrawclk(struct drm_device *dev)
253 {
254         struct drm_i915_private *dev_priv = dev->dev_private;
255         uint32_t clkcfg;
256
257         clkcfg = I915_READ(CLKCFG);
258         switch (clkcfg & CLKCFG_FSB_MASK) {
259         case CLKCFG_FSB_400:
260                 return 100;
261         case CLKCFG_FSB_533:
262                 return 133;
263         case CLKCFG_FSB_667:
264                 return 166;
265         case CLKCFG_FSB_800:
266                 return 200;
267         case CLKCFG_FSB_1067:
268                 return 266;
269         case CLKCFG_FSB_1333:
270                 return 333;
271         /* these two are just a guess; one of them might be right */
272         case CLKCFG_FSB_1600:
273         case CLKCFG_FSB_1600_ALT:
274                 return 400;
275         default:
276                 return 133;
277         }
278 }
279
280 static int
281 intel_dp_aux_ch(struct intel_dp *intel_dp,
282                 uint8_t *send, int send_bytes,
283                 uint8_t *recv, int recv_size)
284 {
285         uint32_t output_reg = intel_dp->output_reg;
286         struct drm_device *dev = intel_dp->base.base.dev;
287         struct drm_i915_private *dev_priv = dev->dev_private;
288         uint32_t ch_ctl = output_reg + 0x10;
289         uint32_t ch_data = ch_ctl + 4;
290         int i;
291         int recv_bytes;
292         uint32_t status;
293         uint32_t aux_clock_divider;
294         int try, precharge;
295
296         /* The clock divider is based off the hrawclk,
297          * and would like to run at 2MHz. So, take the
298          * hrawclk value and divide by 2 and use that
299          *
300          * Note that PCH attached eDP panels should use a 125MHz input
301          * clock divider.
302          */
303         if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
304                 if (IS_GEN6(dev))
305                         aux_clock_divider = 200; /* SNB eDP input clock at 400Mhz */
306                 else
307                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
308         } else if (HAS_PCH_SPLIT(dev))
309                 aux_clock_divider = 62; /* IRL input clock fixed at 125Mhz */
310         else
311                 aux_clock_divider = intel_hrawclk(dev) / 2;
312
313         if (IS_GEN6(dev))
314                 precharge = 3;
315         else
316                 precharge = 5;
317
318         if (I915_READ(ch_ctl) & DP_AUX_CH_CTL_SEND_BUSY) {
319                 DRM_ERROR("dp_aux_ch not started status 0x%08x\n",
320                           I915_READ(ch_ctl));
321                 return -EBUSY;
322         }
323
324         /* Must try at least 3 times according to DP spec */
325         for (try = 0; try < 5; try++) {
326                 /* Load the send data into the aux channel data registers */
327                 for (i = 0; i < send_bytes; i += 4)
328                         I915_WRITE(ch_data + i,
329                                    pack_aux(send + i, send_bytes - i));
330         
331                 /* Send the command and wait for it to complete */
332                 I915_WRITE(ch_ctl,
333                            DP_AUX_CH_CTL_SEND_BUSY |
334                            DP_AUX_CH_CTL_TIME_OUT_400us |
335                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
336                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
337                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
338                            DP_AUX_CH_CTL_DONE |
339                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
340                            DP_AUX_CH_CTL_RECEIVE_ERROR);
341                 for (;;) {
342                         status = I915_READ(ch_ctl);
343                         if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
344                                 break;
345                         udelay(100);
346                 }
347         
348                 /* Clear done status and any errors */
349                 I915_WRITE(ch_ctl,
350                            status |
351                            DP_AUX_CH_CTL_DONE |
352                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
353                            DP_AUX_CH_CTL_RECEIVE_ERROR);
354                 if (status & DP_AUX_CH_CTL_DONE)
355                         break;
356         }
357
358         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
359                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
360                 return -EBUSY;
361         }
362
363         /* Check for timeout or receive error.
364          * Timeouts occur when the sink is not connected
365          */
366         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
367                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
368                 return -EIO;
369         }
370
371         /* Timeouts occur when the device isn't connected, so they're
372          * "normal" -- don't fill the kernel log with these */
373         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
374                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
375                 return -ETIMEDOUT;
376         }
377
378         /* Unload any bytes sent back from the other side */
379         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
380                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
381         if (recv_bytes > recv_size)
382                 recv_bytes = recv_size;
383         
384         for (i = 0; i < recv_bytes; i += 4)
385                 unpack_aux(I915_READ(ch_data + i),
386                            recv + i, recv_bytes - i);
387
388         return recv_bytes;
389 }
390
391 /* Write data to the aux channel in native mode */
392 static int
393 intel_dp_aux_native_write(struct intel_dp *intel_dp,
394                           uint16_t address, uint8_t *send, int send_bytes)
395 {
396         int ret;
397         uint8_t msg[20];
398         int msg_bytes;
399         uint8_t ack;
400
401         if (send_bytes > 16)
402                 return -1;
403         msg[0] = AUX_NATIVE_WRITE << 4;
404         msg[1] = address >> 8;
405         msg[2] = address & 0xff;
406         msg[3] = send_bytes - 1;
407         memcpy(&msg[4], send, send_bytes);
408         msg_bytes = send_bytes + 4;
409         for (;;) {
410                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
411                 if (ret < 0)
412                         return ret;
413                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
414                         break;
415                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
416                         udelay(100);
417                 else
418                         return -EIO;
419         }
420         return send_bytes;
421 }
422
423 /* Write a single byte to the aux channel in native mode */
424 static int
425 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
426                             uint16_t address, uint8_t byte)
427 {
428         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
429 }
430
431 /* read bytes from a native aux channel */
432 static int
433 intel_dp_aux_native_read(struct intel_dp *intel_dp,
434                          uint16_t address, uint8_t *recv, int recv_bytes)
435 {
436         uint8_t msg[4];
437         int msg_bytes;
438         uint8_t reply[20];
439         int reply_bytes;
440         uint8_t ack;
441         int ret;
442
443         msg[0] = AUX_NATIVE_READ << 4;
444         msg[1] = address >> 8;
445         msg[2] = address & 0xff;
446         msg[3] = recv_bytes - 1;
447
448         msg_bytes = 4;
449         reply_bytes = recv_bytes + 1;
450
451         for (;;) {
452                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
453                                       reply, reply_bytes);
454                 if (ret == 0)
455                         return -EPROTO;
456                 if (ret < 0)
457                         return ret;
458                 ack = reply[0];
459                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
460                         memcpy(recv, reply + 1, ret - 1);
461                         return ret - 1;
462                 }
463                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
464                         udelay(100);
465                 else
466                         return -EIO;
467         }
468 }
469
470 static int
471 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
472                     uint8_t write_byte, uint8_t *read_byte)
473 {
474         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
475         struct intel_dp *intel_dp = container_of(adapter,
476                                                 struct intel_dp,
477                                                 adapter);
478         uint16_t address = algo_data->address;
479         uint8_t msg[5];
480         uint8_t reply[2];
481         unsigned retry;
482         int msg_bytes;
483         int reply_bytes;
484         int ret;
485
486         /* Set up the command byte */
487         if (mode & MODE_I2C_READ)
488                 msg[0] = AUX_I2C_READ << 4;
489         else
490                 msg[0] = AUX_I2C_WRITE << 4;
491
492         if (!(mode & MODE_I2C_STOP))
493                 msg[0] |= AUX_I2C_MOT << 4;
494
495         msg[1] = address >> 8;
496         msg[2] = address;
497
498         switch (mode) {
499         case MODE_I2C_WRITE:
500                 msg[3] = 0;
501                 msg[4] = write_byte;
502                 msg_bytes = 5;
503                 reply_bytes = 1;
504                 break;
505         case MODE_I2C_READ:
506                 msg[3] = 0;
507                 msg_bytes = 4;
508                 reply_bytes = 2;
509                 break;
510         default:
511                 msg_bytes = 3;
512                 reply_bytes = 1;
513                 break;
514         }
515
516         for (retry = 0; retry < 5; retry++) {
517                 ret = intel_dp_aux_ch(intel_dp,
518                                       msg, msg_bytes,
519                                       reply, reply_bytes);
520                 if (ret < 0) {
521                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
522                         return ret;
523                 }
524
525                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
526                 case AUX_NATIVE_REPLY_ACK:
527                         /* I2C-over-AUX Reply field is only valid
528                          * when paired with AUX ACK.
529                          */
530                         break;
531                 case AUX_NATIVE_REPLY_NACK:
532                         DRM_DEBUG_KMS("aux_ch native nack\n");
533                         return -EREMOTEIO;
534                 case AUX_NATIVE_REPLY_DEFER:
535                         udelay(100);
536                         continue;
537                 default:
538                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
539                                   reply[0]);
540                         return -EREMOTEIO;
541                 }
542
543                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
544                 case AUX_I2C_REPLY_ACK:
545                         if (mode == MODE_I2C_READ) {
546                                 *read_byte = reply[1];
547                         }
548                         return reply_bytes - 1;
549                 case AUX_I2C_REPLY_NACK:
550                         DRM_DEBUG_KMS("aux_i2c nack\n");
551                         return -EREMOTEIO;
552                 case AUX_I2C_REPLY_DEFER:
553                         DRM_DEBUG_KMS("aux_i2c defer\n");
554                         udelay(100);
555                         break;
556                 default:
557                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
558                         return -EREMOTEIO;
559                 }
560         }
561
562         DRM_ERROR("too many retries, giving up\n");
563         return -EREMOTEIO;
564 }
565
566 static int
567 intel_dp_i2c_init(struct intel_dp *intel_dp,
568                   struct intel_connector *intel_connector, const char *name)
569 {
570         DRM_DEBUG_KMS("i2c_init %s\n", name);
571         intel_dp->algo.running = false;
572         intel_dp->algo.address = 0;
573         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
574
575         memset(&intel_dp->adapter, '\0', sizeof (intel_dp->adapter));
576         intel_dp->adapter.owner = THIS_MODULE;
577         intel_dp->adapter.class = I2C_CLASS_DDC;
578         strncpy (intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
579         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
580         intel_dp->adapter.algo_data = &intel_dp->algo;
581         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
582
583         return i2c_dp_aux_add_bus(&intel_dp->adapter);
584 }
585
586 static bool
587 intel_dp_mode_fixup(struct drm_encoder *encoder, struct drm_display_mode *mode,
588                     struct drm_display_mode *adjusted_mode)
589 {
590         struct drm_device *dev = encoder->dev;
591         struct drm_i915_private *dev_priv = dev->dev_private;
592         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
593         int lane_count, clock;
594         int max_lane_count = intel_dp_max_lane_count(intel_dp);
595         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
596         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
597
598         if (is_edp(intel_dp) && dev_priv->panel_fixed_mode) {
599                 intel_fixed_panel_mode(dev_priv->panel_fixed_mode, adjusted_mode);
600                 intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN,
601                                         mode, adjusted_mode);
602                 /*
603                  * the mode->clock is used to calculate the Data&Link M/N
604                  * of the pipe. For the eDP the fixed clock should be used.
605                  */
606                 mode->clock = dev_priv->panel_fixed_mode->clock;
607         }
608
609         for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
610                 for (clock = 0; clock <= max_clock; clock++) {
611                         int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count);
612
613                         if (intel_dp_link_required(encoder->dev, intel_dp, mode->clock)
614                                         <= link_avail) {
615                                 intel_dp->link_bw = bws[clock];
616                                 intel_dp->lane_count = lane_count;
617                                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
618                                 DRM_DEBUG_KMS("Display port link bw %02x lane "
619                                                 "count %d clock %d\n",
620                                        intel_dp->link_bw, intel_dp->lane_count,
621                                        adjusted_mode->clock);
622                                 return true;
623                         }
624                 }
625         }
626
627         if (is_edp(intel_dp)) {
628                 /* okay we failed just pick the highest */
629                 intel_dp->lane_count = max_lane_count;
630                 intel_dp->link_bw = bws[max_clock];
631                 adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw);
632                 DRM_DEBUG_KMS("Force picking display port link bw %02x lane "
633                               "count %d clock %d\n",
634                               intel_dp->link_bw, intel_dp->lane_count,
635                               adjusted_mode->clock);
636
637                 return true;
638         }
639
640         return false;
641 }
642
643 struct intel_dp_m_n {
644         uint32_t        tu;
645         uint32_t        gmch_m;
646         uint32_t        gmch_n;
647         uint32_t        link_m;
648         uint32_t        link_n;
649 };
650
651 static void
652 intel_reduce_ratio(uint32_t *num, uint32_t *den)
653 {
654         while (*num > 0xffffff || *den > 0xffffff) {
655                 *num >>= 1;
656                 *den >>= 1;
657         }
658 }
659
660 static void
661 intel_dp_compute_m_n(int bpp,
662                      int nlanes,
663                      int pixel_clock,
664                      int link_clock,
665                      struct intel_dp_m_n *m_n)
666 {
667         m_n->tu = 64;
668         m_n->gmch_m = (pixel_clock * bpp) >> 3;
669         m_n->gmch_n = link_clock * nlanes;
670         intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
671         m_n->link_m = pixel_clock;
672         m_n->link_n = link_clock;
673         intel_reduce_ratio(&m_n->link_m, &m_n->link_n);
674 }
675
676 void
677 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
678                  struct drm_display_mode *adjusted_mode)
679 {
680         struct drm_device *dev = crtc->dev;
681         struct drm_mode_config *mode_config = &dev->mode_config;
682         struct drm_encoder *encoder;
683         struct drm_i915_private *dev_priv = dev->dev_private;
684         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
685         int lane_count = 4, bpp = 24;
686         struct intel_dp_m_n m_n;
687         int pipe = intel_crtc->pipe;
688
689         /*
690          * Find the lane count in the intel_encoder private
691          */
692         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
693                 struct intel_dp *intel_dp;
694
695                 if (encoder->crtc != crtc)
696                         continue;
697
698                 intel_dp = enc_to_intel_dp(encoder);
699                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT) {
700                         lane_count = intel_dp->lane_count;
701                         break;
702                 } else if (is_edp(intel_dp)) {
703                         lane_count = dev_priv->edp.lanes;
704                         bpp = dev_priv->edp.bpp;
705                         break;
706                 }
707         }
708
709         /*
710          * Compute the GMCH and Link ratios. The '3' here is
711          * the number of bytes_per_pixel post-LUT, which we always
712          * set up for 8-bits of R/G/B, or 3 bytes total.
713          */
714         intel_dp_compute_m_n(bpp, lane_count,
715                              mode->clock, adjusted_mode->clock, &m_n);
716
717         if (HAS_PCH_SPLIT(dev)) {
718                 I915_WRITE(TRANSDATA_M1(pipe),
719                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
720                            m_n.gmch_m);
721                 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
722                 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
723                 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
724         } else {
725                 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
726                            ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |
727                            m_n.gmch_m);
728                 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
729                 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
730                 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
731         }
732 }
733
734 static void
735 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
736                   struct drm_display_mode *adjusted_mode)
737 {
738         struct drm_device *dev = encoder->dev;
739         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
740         struct drm_crtc *crtc = intel_dp->base.base.crtc;
741         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
742
743         intel_dp->DP = DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
744         intel_dp->DP |= intel_dp->color_range;
745
746         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
747                 intel_dp->DP |= DP_SYNC_HS_HIGH;
748         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
749                 intel_dp->DP |= DP_SYNC_VS_HIGH;
750
751         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
752                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
753         else
754                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
755
756         switch (intel_dp->lane_count) {
757         case 1:
758                 intel_dp->DP |= DP_PORT_WIDTH_1;
759                 break;
760         case 2:
761                 intel_dp->DP |= DP_PORT_WIDTH_2;
762                 break;
763         case 4:
764                 intel_dp->DP |= DP_PORT_WIDTH_4;
765                 break;
766         }
767         if (intel_dp->has_audio)
768                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
769
770         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
771         intel_dp->link_configuration[0] = intel_dp->link_bw;
772         intel_dp->link_configuration[1] = intel_dp->lane_count;
773
774         /*
775          * Check for DPCD version > 1.1 and enhanced framing support
776          */
777         if (intel_dp->dpcd[0] >= 0x11 && (intel_dp->dpcd[2] & DP_ENHANCED_FRAME_CAP)) {
778                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
779                 intel_dp->DP |= DP_ENHANCED_FRAMING;
780         }
781
782         /* CPT DP's pipe select is decided in TRANS_DP_CTL */
783         if (intel_crtc->pipe == 1 && !HAS_PCH_CPT(dev))
784                 intel_dp->DP |= DP_PIPEB_SELECT;
785
786         if (is_edp(intel_dp) && !is_pch_edp(intel_dp)) {
787                 /* don't miss out required setting for eDP */
788                 intel_dp->DP |= DP_PLL_ENABLE;
789                 if (adjusted_mode->clock < 200000)
790                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
791                 else
792                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
793         }
794 }
795
796 static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
797 {
798         struct drm_device *dev = intel_dp->base.base.dev;
799         struct drm_i915_private *dev_priv = dev->dev_private;
800         u32 pp;
801
802         /*
803          * If the panel wasn't on, make sure there's not a currently
804          * active PP sequence before enabling AUX VDD.
805          */
806         if (!(I915_READ(PCH_PP_STATUS) & PP_ON))
807                 msleep(dev_priv->panel_t3);
808
809         pp = I915_READ(PCH_PP_CONTROL);
810         pp |= EDP_FORCE_VDD;
811         I915_WRITE(PCH_PP_CONTROL, pp);
812         POSTING_READ(PCH_PP_CONTROL);
813 }
814
815 static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp)
816 {
817         struct drm_device *dev = intel_dp->base.base.dev;
818         struct drm_i915_private *dev_priv = dev->dev_private;
819         u32 pp;
820
821         pp = I915_READ(PCH_PP_CONTROL);
822         pp &= ~EDP_FORCE_VDD;
823         I915_WRITE(PCH_PP_CONTROL, pp);
824         POSTING_READ(PCH_PP_CONTROL);
825
826         /* Make sure sequencer is idle before allowing subsequent activity */
827         msleep(dev_priv->panel_t12);
828 }
829
830 /* Returns true if the panel was already on when called */
831 static bool ironlake_edp_panel_on (struct intel_dp *intel_dp)
832 {
833         struct drm_device *dev = intel_dp->base.base.dev;
834         struct drm_i915_private *dev_priv = dev->dev_private;
835         u32 pp, idle_on_mask = PP_ON | PP_SEQUENCE_STATE_ON_IDLE;
836
837         if (I915_READ(PCH_PP_STATUS) & PP_ON)
838                 return true;
839
840         pp = I915_READ(PCH_PP_CONTROL);
841
842         /* ILK workaround: disable reset around power sequence */
843         pp &= ~PANEL_POWER_RESET;
844         I915_WRITE(PCH_PP_CONTROL, pp);
845         POSTING_READ(PCH_PP_CONTROL);
846
847         pp |= PANEL_UNLOCK_REGS | POWER_TARGET_ON;
848         I915_WRITE(PCH_PP_CONTROL, pp);
849         POSTING_READ(PCH_PP_CONTROL);
850
851         if (wait_for((I915_READ(PCH_PP_STATUS) & idle_on_mask) == idle_on_mask,
852                      5000))
853                 DRM_ERROR("panel on wait timed out: 0x%08x\n",
854                           I915_READ(PCH_PP_STATUS));
855
856         pp |= PANEL_POWER_RESET; /* restore panel reset bit */
857         I915_WRITE(PCH_PP_CONTROL, pp);
858         POSTING_READ(PCH_PP_CONTROL);
859
860         return false;
861 }
862
863 static void ironlake_edp_panel_off (struct drm_device *dev)
864 {
865         struct drm_i915_private *dev_priv = dev->dev_private;
866         u32 pp, idle_off_mask = PP_ON | PP_SEQUENCE_MASK |
867                 PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK;
868
869         pp = I915_READ(PCH_PP_CONTROL);
870
871         /* ILK workaround: disable reset around power sequence */
872         pp &= ~PANEL_POWER_RESET;
873         I915_WRITE(PCH_PP_CONTROL, pp);
874         POSTING_READ(PCH_PP_CONTROL);
875
876         pp &= ~POWER_TARGET_ON;
877         I915_WRITE(PCH_PP_CONTROL, pp);
878         POSTING_READ(PCH_PP_CONTROL);
879
880         if (wait_for((I915_READ(PCH_PP_STATUS) & idle_off_mask) == 0, 5000))
881                 DRM_ERROR("panel off wait timed out: 0x%08x\n",
882                           I915_READ(PCH_PP_STATUS));
883
884         pp |= PANEL_POWER_RESET; /* restore panel reset bit */
885         I915_WRITE(PCH_PP_CONTROL, pp);
886         POSTING_READ(PCH_PP_CONTROL);
887 }
888
889 static void ironlake_edp_backlight_on (struct drm_device *dev)
890 {
891         struct drm_i915_private *dev_priv = dev->dev_private;
892         u32 pp;
893
894         DRM_DEBUG_KMS("\n");
895         /*
896          * If we enable the backlight right away following a panel power
897          * on, we may see slight flicker as the panel syncs with the eDP
898          * link.  So delay a bit to make sure the image is solid before
899          * allowing it to appear.
900          */
901         msleep(300);
902         pp = I915_READ(PCH_PP_CONTROL);
903         pp |= EDP_BLC_ENABLE;
904         I915_WRITE(PCH_PP_CONTROL, pp);
905 }
906
907 static void ironlake_edp_backlight_off (struct drm_device *dev)
908 {
909         struct drm_i915_private *dev_priv = dev->dev_private;
910         u32 pp;
911
912         DRM_DEBUG_KMS("\n");
913         pp = I915_READ(PCH_PP_CONTROL);
914         pp &= ~EDP_BLC_ENABLE;
915         I915_WRITE(PCH_PP_CONTROL, pp);
916 }
917
918 static void ironlake_edp_pll_on(struct drm_encoder *encoder)
919 {
920         struct drm_device *dev = encoder->dev;
921         struct drm_i915_private *dev_priv = dev->dev_private;
922         u32 dpa_ctl;
923
924         DRM_DEBUG_KMS("\n");
925         dpa_ctl = I915_READ(DP_A);
926         dpa_ctl |= DP_PLL_ENABLE;
927         I915_WRITE(DP_A, dpa_ctl);
928         POSTING_READ(DP_A);
929         udelay(200);
930 }
931
932 static void ironlake_edp_pll_off(struct drm_encoder *encoder)
933 {
934         struct drm_device *dev = encoder->dev;
935         struct drm_i915_private *dev_priv = dev->dev_private;
936         u32 dpa_ctl;
937
938         dpa_ctl = I915_READ(DP_A);
939         dpa_ctl &= ~DP_PLL_ENABLE;
940         I915_WRITE(DP_A, dpa_ctl);
941         POSTING_READ(DP_A);
942         udelay(200);
943 }
944
945 static void intel_dp_prepare(struct drm_encoder *encoder)
946 {
947         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
948         struct drm_device *dev = encoder->dev;
949
950         if (is_edp(intel_dp)) {
951                 ironlake_edp_backlight_off(dev);
952                 ironlake_edp_panel_off(dev);
953                 if (!is_pch_edp(intel_dp))
954                         ironlake_edp_pll_on(encoder);
955                 else
956                         ironlake_edp_pll_off(encoder);
957         }
958         intel_dp_link_down(intel_dp);
959 }
960
961 static void intel_dp_commit(struct drm_encoder *encoder)
962 {
963         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
964         struct drm_device *dev = encoder->dev;
965
966         if (is_edp(intel_dp))
967                 ironlake_edp_panel_vdd_on(intel_dp);
968
969         intel_dp_start_link_train(intel_dp);
970
971         if (is_edp(intel_dp)) {
972                 ironlake_edp_panel_on(intel_dp);
973                 ironlake_edp_panel_vdd_off(intel_dp);
974         }
975
976         intel_dp_complete_link_train(intel_dp);
977
978         if (is_edp(intel_dp))
979                 ironlake_edp_backlight_on(dev);
980 }
981
982 static void
983 intel_dp_dpms(struct drm_encoder *encoder, int mode)
984 {
985         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
986         struct drm_device *dev = encoder->dev;
987         struct drm_i915_private *dev_priv = dev->dev_private;
988         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
989
990         if (mode != DRM_MODE_DPMS_ON) {
991                 if (is_edp(intel_dp))
992                         ironlake_edp_backlight_off(dev);
993                 intel_dp_link_down(intel_dp);
994                 if (is_edp(intel_dp))
995                         ironlake_edp_panel_off(dev);
996                 if (is_edp(intel_dp) && !is_pch_edp(intel_dp))
997                         ironlake_edp_pll_off(encoder);
998         } else {
999                 if (is_edp(intel_dp))
1000                         ironlake_edp_panel_vdd_on(intel_dp);
1001                 if (!(dp_reg & DP_PORT_EN)) {
1002                         intel_dp_start_link_train(intel_dp);
1003                         if (is_edp(intel_dp)) {
1004                                 ironlake_edp_panel_on(intel_dp);
1005                                 ironlake_edp_panel_vdd_off(intel_dp);
1006                         }
1007                         intel_dp_complete_link_train(intel_dp);
1008                 }
1009                 if (is_edp(intel_dp))
1010                         ironlake_edp_backlight_on(dev);
1011         }
1012         intel_dp->dpms_mode = mode;
1013 }
1014
1015 /*
1016  * Fetch AUX CH registers 0x202 - 0x207 which contain
1017  * link status information
1018  */
1019 static bool
1020 intel_dp_get_link_status(struct intel_dp *intel_dp)
1021 {
1022         int ret, i;
1023
1024         /* Must try AUX reads for this at least 3 times */
1025         for (i = 0; i < 3; i++) {
1026                 ret = intel_dp_aux_native_read(intel_dp,
1027                                                DP_LANE0_1_STATUS,
1028                                                intel_dp->link_status,
1029                                                DP_LINK_STATUS_SIZE);
1030                 if (ret == DP_LINK_STATUS_SIZE)
1031                         return true;
1032                 msleep(1);
1033         }
1034
1035         return false;
1036 }
1037
1038 static uint8_t
1039 intel_dp_link_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1040                      int r)
1041 {
1042         return link_status[r - DP_LANE0_1_STATUS];
1043 }
1044
1045 static uint8_t
1046 intel_get_adjust_request_voltage(uint8_t link_status[DP_LINK_STATUS_SIZE],
1047                                  int lane)
1048 {
1049         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1050         int         s = ((lane & 1) ?
1051                          DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
1052                          DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
1053         uint8_t l = intel_dp_link_status(link_status, i);
1054
1055         return ((l >> s) & 3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
1056 }
1057
1058 static uint8_t
1059 intel_get_adjust_request_pre_emphasis(uint8_t link_status[DP_LINK_STATUS_SIZE],
1060                                       int lane)
1061 {
1062         int         i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
1063         int         s = ((lane & 1) ?
1064                          DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
1065                          DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
1066         uint8_t l = intel_dp_link_status(link_status, i);
1067
1068         return ((l >> s) & 3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
1069 }
1070
1071
1072 #if 0
1073 static char     *voltage_names[] = {
1074         "0.4V", "0.6V", "0.8V", "1.2V"
1075 };
1076 static char     *pre_emph_names[] = {
1077         "0dB", "3.5dB", "6dB", "9.5dB"
1078 };
1079 static char     *link_train_names[] = {
1080         "pattern 1", "pattern 2", "idle", "off"
1081 };
1082 #endif
1083
1084 /*
1085  * These are source-specific values; current Intel hardware supports
1086  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1087  */
1088 #define I830_DP_VOLTAGE_MAX         DP_TRAIN_VOLTAGE_SWING_800
1089
1090 static uint8_t
1091 intel_dp_pre_emphasis_max(uint8_t voltage_swing)
1092 {
1093         switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1094         case DP_TRAIN_VOLTAGE_SWING_400:
1095                 return DP_TRAIN_PRE_EMPHASIS_6;
1096         case DP_TRAIN_VOLTAGE_SWING_600:
1097                 return DP_TRAIN_PRE_EMPHASIS_6;
1098         case DP_TRAIN_VOLTAGE_SWING_800:
1099                 return DP_TRAIN_PRE_EMPHASIS_3_5;
1100         case DP_TRAIN_VOLTAGE_SWING_1200:
1101         default:
1102                 return DP_TRAIN_PRE_EMPHASIS_0;
1103         }
1104 }
1105
1106 static void
1107 intel_get_adjust_train(struct intel_dp *intel_dp)
1108 {
1109         uint8_t v = 0;
1110         uint8_t p = 0;
1111         int lane;
1112
1113         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1114                 uint8_t this_v = intel_get_adjust_request_voltage(intel_dp->link_status, lane);
1115                 uint8_t this_p = intel_get_adjust_request_pre_emphasis(intel_dp->link_status, lane);
1116
1117                 if (this_v > v)
1118                         v = this_v;
1119                 if (this_p > p)
1120                         p = this_p;
1121         }
1122
1123         if (v >= I830_DP_VOLTAGE_MAX)
1124                 v = I830_DP_VOLTAGE_MAX | DP_TRAIN_MAX_SWING_REACHED;
1125
1126         if (p >= intel_dp_pre_emphasis_max(v))
1127                 p = intel_dp_pre_emphasis_max(v) | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1128
1129         for (lane = 0; lane < 4; lane++)
1130                 intel_dp->train_set[lane] = v | p;
1131 }
1132
1133 static uint32_t
1134 intel_dp_signal_levels(uint8_t train_set, int lane_count)
1135 {
1136         uint32_t        signal_levels = 0;
1137
1138         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1139         case DP_TRAIN_VOLTAGE_SWING_400:
1140         default:
1141                 signal_levels |= DP_VOLTAGE_0_4;
1142                 break;
1143         case DP_TRAIN_VOLTAGE_SWING_600:
1144                 signal_levels |= DP_VOLTAGE_0_6;
1145                 break;
1146         case DP_TRAIN_VOLTAGE_SWING_800:
1147                 signal_levels |= DP_VOLTAGE_0_8;
1148                 break;
1149         case DP_TRAIN_VOLTAGE_SWING_1200:
1150                 signal_levels |= DP_VOLTAGE_1_2;
1151                 break;
1152         }
1153         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1154         case DP_TRAIN_PRE_EMPHASIS_0:
1155         default:
1156                 signal_levels |= DP_PRE_EMPHASIS_0;
1157                 break;
1158         case DP_TRAIN_PRE_EMPHASIS_3_5:
1159                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1160                 break;
1161         case DP_TRAIN_PRE_EMPHASIS_6:
1162                 signal_levels |= DP_PRE_EMPHASIS_6;
1163                 break;
1164         case DP_TRAIN_PRE_EMPHASIS_9_5:
1165                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1166                 break;
1167         }
1168         return signal_levels;
1169 }
1170
1171 /* Gen6's DP voltage swing and pre-emphasis control */
1172 static uint32_t
1173 intel_gen6_edp_signal_levels(uint8_t train_set)
1174 {
1175         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1176                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1177         switch (signal_levels) {
1178         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1179         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1180                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1181         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1182                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1183         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1184         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1185                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1186         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1187         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1188                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1189         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1190         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1191                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1192         default:
1193                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1194                               "0x%x\n", signal_levels);
1195                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1196         }
1197 }
1198
1199 static uint8_t
1200 intel_get_lane_status(uint8_t link_status[DP_LINK_STATUS_SIZE],
1201                       int lane)
1202 {
1203         int i = DP_LANE0_1_STATUS + (lane >> 1);
1204         int s = (lane & 1) * 4;
1205         uint8_t l = intel_dp_link_status(link_status, i);
1206
1207         return (l >> s) & 0xf;
1208 }
1209
1210 /* Check for clock recovery is done on all channels */
1211 static bool
1212 intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count)
1213 {
1214         int lane;
1215         uint8_t lane_status;
1216
1217         for (lane = 0; lane < lane_count; lane++) {
1218                 lane_status = intel_get_lane_status(link_status, lane);
1219                 if ((lane_status & DP_LANE_CR_DONE) == 0)
1220                         return false;
1221         }
1222         return true;
1223 }
1224
1225 /* Check to see if channel eq is done on all channels */
1226 #define CHANNEL_EQ_BITS (DP_LANE_CR_DONE|\
1227                          DP_LANE_CHANNEL_EQ_DONE|\
1228                          DP_LANE_SYMBOL_LOCKED)
1229 static bool
1230 intel_channel_eq_ok(struct intel_dp *intel_dp)
1231 {
1232         uint8_t lane_align;
1233         uint8_t lane_status;
1234         int lane;
1235
1236         lane_align = intel_dp_link_status(intel_dp->link_status,
1237                                           DP_LANE_ALIGN_STATUS_UPDATED);
1238         if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
1239                 return false;
1240         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1241                 lane_status = intel_get_lane_status(intel_dp->link_status, lane);
1242                 if ((lane_status & CHANNEL_EQ_BITS) != CHANNEL_EQ_BITS)
1243                         return false;
1244         }
1245         return true;
1246 }
1247
1248 static bool
1249 intel_dp_set_link_train(struct intel_dp *intel_dp,
1250                         uint32_t dp_reg_value,
1251                         uint8_t dp_train_pat)
1252 {
1253         struct drm_device *dev = intel_dp->base.base.dev;
1254         struct drm_i915_private *dev_priv = dev->dev_private;
1255         int ret;
1256
1257         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1258         POSTING_READ(intel_dp->output_reg);
1259
1260         intel_dp_aux_native_write_1(intel_dp,
1261                                     DP_TRAINING_PATTERN_SET,
1262                                     dp_train_pat);
1263
1264         ret = intel_dp_aux_native_write(intel_dp,
1265                                         DP_TRAINING_LANE0_SET,
1266                                         intel_dp->train_set, 4);
1267         if (ret != 4)
1268                 return false;
1269
1270         return true;
1271 }
1272
1273 /* Enable corresponding port and start training pattern 1 */
1274 static void
1275 intel_dp_start_link_train(struct intel_dp *intel_dp)
1276 {
1277         struct drm_device *dev = intel_dp->base.base.dev;
1278         struct drm_i915_private *dev_priv = dev->dev_private;
1279         struct intel_crtc *intel_crtc = to_intel_crtc(intel_dp->base.base.crtc);
1280         int i;
1281         uint8_t voltage;
1282         bool clock_recovery = false;
1283         int tries;
1284         u32 reg;
1285         uint32_t DP = intel_dp->DP;
1286
1287         /* Enable output, wait for it to become active */
1288         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
1289         POSTING_READ(intel_dp->output_reg);
1290         intel_wait_for_vblank(dev, intel_crtc->pipe);
1291
1292         /* Write the link configuration data */
1293         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1294                                   intel_dp->link_configuration,
1295                                   DP_LINK_CONFIGURATION_SIZE);
1296
1297         DP |= DP_PORT_EN;
1298         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1299                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1300         else
1301                 DP &= ~DP_LINK_TRAIN_MASK;
1302         memset(intel_dp->train_set, 0, 4);
1303         voltage = 0xff;
1304         tries = 0;
1305         clock_recovery = false;
1306         for (;;) {
1307                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1308                 uint32_t    signal_levels;
1309                 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1310                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1311                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1312                 } else {
1313                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1314                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1315                 }
1316
1317                 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1318                         reg = DP | DP_LINK_TRAIN_PAT_1_CPT;
1319                 else
1320                         reg = DP | DP_LINK_TRAIN_PAT_1;
1321
1322                 if (!intel_dp_set_link_train(intel_dp, reg,
1323                                              DP_TRAINING_PATTERN_1))
1324                         break;
1325                 /* Set training pattern 1 */
1326
1327                 udelay(100);
1328                 if (!intel_dp_get_link_status(intel_dp))
1329                         break;
1330
1331                 if (intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1332                         clock_recovery = true;
1333                         break;
1334                 }
1335
1336                 /* Check to see if we've tried the max voltage */
1337                 for (i = 0; i < intel_dp->lane_count; i++)
1338                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1339                                 break;
1340                 if (i == intel_dp->lane_count)
1341                         break;
1342
1343                 /* Check to see if we've tried the same voltage 5 times */
1344                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1345                         ++tries;
1346                         if (tries == 5)
1347                                 break;
1348                 } else
1349                         tries = 0;
1350                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1351
1352                 /* Compute new intel_dp->train_set as requested by target */
1353                 intel_get_adjust_train(intel_dp);
1354         }
1355
1356         intel_dp->DP = DP;
1357 }
1358
1359 static void
1360 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1361 {
1362         struct drm_device *dev = intel_dp->base.base.dev;
1363         struct drm_i915_private *dev_priv = dev->dev_private;
1364         bool channel_eq = false;
1365         int tries, cr_tries;
1366         u32 reg;
1367         uint32_t DP = intel_dp->DP;
1368
1369         /* channel equalization */
1370         tries = 0;
1371         cr_tries = 0;
1372         channel_eq = false;
1373         for (;;) {
1374                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1375                 uint32_t    signal_levels;
1376
1377                 if (cr_tries > 5) {
1378                         DRM_ERROR("failed to train DP, aborting\n");
1379                         intel_dp_link_down(intel_dp);
1380                         break;
1381                 }
1382
1383                 if (IS_GEN6(dev) && is_edp(intel_dp)) {
1384                         signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]);
1385                         DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels;
1386                 } else {
1387                         signal_levels = intel_dp_signal_levels(intel_dp->train_set[0], intel_dp->lane_count);
1388                         DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels;
1389                 }
1390
1391                 if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1392                         reg = DP | DP_LINK_TRAIN_PAT_2_CPT;
1393                 else
1394                         reg = DP | DP_LINK_TRAIN_PAT_2;
1395
1396                 /* channel eq pattern */
1397                 if (!intel_dp_set_link_train(intel_dp, reg,
1398                                              DP_TRAINING_PATTERN_2))
1399                         break;
1400
1401                 udelay(400);
1402                 if (!intel_dp_get_link_status(intel_dp))
1403                         break;
1404
1405                 /* Make sure clock is still ok */
1406                 if (!intel_clock_recovery_ok(intel_dp->link_status, intel_dp->lane_count)) {
1407                         intel_dp_start_link_train(intel_dp);
1408                         cr_tries++;
1409                         continue;
1410                 }
1411
1412                 if (intel_channel_eq_ok(intel_dp)) {
1413                         channel_eq = true;
1414                         break;
1415                 }
1416
1417                 /* Try 5 times, then try clock recovery if that fails */
1418                 if (tries > 5) {
1419                         intel_dp_link_down(intel_dp);
1420                         intel_dp_start_link_train(intel_dp);
1421                         tries = 0;
1422                         cr_tries++;
1423                         continue;
1424                 }
1425
1426                 /* Compute new intel_dp->train_set as requested by target */
1427                 intel_get_adjust_train(intel_dp);
1428                 ++tries;
1429         }
1430
1431         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp))
1432                 reg = DP | DP_LINK_TRAIN_OFF_CPT;
1433         else
1434                 reg = DP | DP_LINK_TRAIN_OFF;
1435
1436         I915_WRITE(intel_dp->output_reg, reg);
1437         POSTING_READ(intel_dp->output_reg);
1438         intel_dp_aux_native_write_1(intel_dp,
1439                                     DP_TRAINING_PATTERN_SET, DP_TRAINING_PATTERN_DISABLE);
1440 }
1441
1442 static void
1443 intel_dp_link_down(struct intel_dp *intel_dp)
1444 {
1445         struct drm_device *dev = intel_dp->base.base.dev;
1446         struct drm_i915_private *dev_priv = dev->dev_private;
1447         uint32_t DP = intel_dp->DP;
1448
1449         if ((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)
1450                 return;
1451
1452         DRM_DEBUG_KMS("\n");
1453
1454         if (is_edp(intel_dp)) {
1455                 DP &= ~DP_PLL_ENABLE;
1456                 I915_WRITE(intel_dp->output_reg, DP);
1457                 POSTING_READ(intel_dp->output_reg);
1458                 udelay(100);
1459         }
1460
1461         if (HAS_PCH_CPT(dev) && !is_edp(intel_dp)) {
1462                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
1463                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
1464         } else {
1465                 DP &= ~DP_LINK_TRAIN_MASK;
1466                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
1467         }
1468         POSTING_READ(intel_dp->output_reg);
1469
1470         msleep(17);
1471
1472         if (is_edp(intel_dp))
1473                 DP |= DP_LINK_TRAIN_OFF;
1474
1475         if (!HAS_PCH_CPT(dev) &&
1476             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
1477                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1478
1479                 /* Hardware workaround: leaving our transcoder select
1480                  * set to transcoder B while it's off will prevent the
1481                  * corresponding HDMI output on transcoder A.
1482                  *
1483                  * Combine this with another hardware workaround:
1484                  * transcoder select bit can only be cleared while the
1485                  * port is enabled.
1486                  */
1487                 DP &= ~DP_PIPEB_SELECT;
1488                 I915_WRITE(intel_dp->output_reg, DP);
1489
1490                 /* Changes to enable or select take place the vblank
1491                  * after being written.
1492                  */
1493                 if (crtc == NULL) {
1494                         /* We can arrive here never having been attached
1495                          * to a CRTC, for instance, due to inheriting
1496                          * random state from the BIOS.
1497                          *
1498                          * If the pipe is not running, play safe and
1499                          * wait for the clocks to stabilise before
1500                          * continuing.
1501                          */
1502                         POSTING_READ(intel_dp->output_reg);
1503                         msleep(50);
1504                 } else
1505                         intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe);
1506         }
1507
1508         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
1509         POSTING_READ(intel_dp->output_reg);
1510 }
1511
1512 /*
1513  * According to DP spec
1514  * 5.1.2:
1515  *  1. Read DPCD
1516  *  2. Configure link according to Receiver Capabilities
1517  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
1518  *  4. Check link status on receipt of hot-plug interrupt
1519  */
1520
1521 static void
1522 intel_dp_check_link_status(struct intel_dp *intel_dp)
1523 {
1524         if (!intel_dp->base.base.crtc)
1525                 return;
1526
1527         if (!intel_dp_get_link_status(intel_dp)) {
1528                 intel_dp_link_down(intel_dp);
1529                 return;
1530         }
1531
1532         if (!intel_channel_eq_ok(intel_dp)) {
1533                 intel_dp_start_link_train(intel_dp);
1534                 intel_dp_complete_link_train(intel_dp);
1535         }
1536 }
1537
1538 static enum drm_connector_status
1539 ironlake_dp_detect(struct intel_dp *intel_dp)
1540 {
1541         enum drm_connector_status status;
1542
1543         /* Can't disconnect eDP, but you can close the lid... */
1544         if (is_edp(intel_dp)) {
1545                 status = intel_panel_detect(intel_dp->base.base.dev);
1546                 if (status == connector_status_unknown)
1547                         status = connector_status_connected;
1548                 return status;
1549         }
1550
1551         status = connector_status_disconnected;
1552         if (intel_dp_aux_native_read(intel_dp,
1553                                      0x000, intel_dp->dpcd,
1554                                      sizeof (intel_dp->dpcd))
1555             == sizeof(intel_dp->dpcd)) {
1556                 if (intel_dp->dpcd[0] != 0)
1557                         status = connector_status_connected;
1558         }
1559         DRM_DEBUG_KMS("DPCD: %hx%hx%hx%hx\n", intel_dp->dpcd[0],
1560                       intel_dp->dpcd[1], intel_dp->dpcd[2], intel_dp->dpcd[3]);
1561         return status;
1562 }
1563
1564 static enum drm_connector_status
1565 g4x_dp_detect(struct intel_dp *intel_dp)
1566 {
1567         struct drm_device *dev = intel_dp->base.base.dev;
1568         struct drm_i915_private *dev_priv = dev->dev_private;
1569         enum drm_connector_status status;
1570         uint32_t temp, bit;
1571
1572         switch (intel_dp->output_reg) {
1573         case DP_B:
1574                 bit = DPB_HOTPLUG_INT_STATUS;
1575                 break;
1576         case DP_C:
1577                 bit = DPC_HOTPLUG_INT_STATUS;
1578                 break;
1579         case DP_D:
1580                 bit = DPD_HOTPLUG_INT_STATUS;
1581                 break;
1582         default:
1583                 return connector_status_unknown;
1584         }
1585
1586         temp = I915_READ(PORT_HOTPLUG_STAT);
1587
1588         if ((temp & bit) == 0)
1589                 return connector_status_disconnected;
1590
1591         status = connector_status_disconnected;
1592         if (intel_dp_aux_native_read(intel_dp, 0x000, intel_dp->dpcd,
1593                                      sizeof (intel_dp->dpcd)) == sizeof (intel_dp->dpcd))
1594         {
1595                 if (intel_dp->dpcd[0] != 0)
1596                         status = connector_status_connected;
1597         }
1598
1599         return status;
1600 }
1601
1602 /**
1603  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection.
1604  *
1605  * \return true if DP port is connected.
1606  * \return false if DP port is disconnected.
1607  */
1608 static enum drm_connector_status
1609 intel_dp_detect(struct drm_connector *connector, bool force)
1610 {
1611         struct intel_dp *intel_dp = intel_attached_dp(connector);
1612         struct drm_device *dev = intel_dp->base.base.dev;
1613         enum drm_connector_status status;
1614         struct edid *edid = NULL;
1615
1616         intel_dp->has_audio = false;
1617
1618         if (HAS_PCH_SPLIT(dev))
1619                 status = ironlake_dp_detect(intel_dp);
1620         else
1621                 status = g4x_dp_detect(intel_dp);
1622         if (status != connector_status_connected)
1623                 return status;
1624
1625         if (intel_dp->force_audio) {
1626                 intel_dp->has_audio = intel_dp->force_audio > 0;
1627         } else {
1628                 edid = drm_get_edid(connector, &intel_dp->adapter);
1629                 if (edid) {
1630                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
1631                         connector->display_info.raw_edid = NULL;
1632                         kfree(edid);
1633                 }
1634         }
1635
1636         return connector_status_connected;
1637 }
1638
1639 static int intel_dp_get_modes(struct drm_connector *connector)
1640 {
1641         struct intel_dp *intel_dp = intel_attached_dp(connector);
1642         struct drm_device *dev = intel_dp->base.base.dev;
1643         struct drm_i915_private *dev_priv = dev->dev_private;
1644         int ret;
1645
1646         /* We should parse the EDID data and find out if it has an audio sink
1647          */
1648
1649         ret = intel_ddc_get_modes(connector, &intel_dp->adapter);
1650         if (ret) {
1651                 if (is_edp(intel_dp) && !dev_priv->panel_fixed_mode) {
1652                         struct drm_display_mode *newmode;
1653                         list_for_each_entry(newmode, &connector->probed_modes,
1654                                             head) {
1655                                 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
1656                                         dev_priv->panel_fixed_mode =
1657                                                 drm_mode_duplicate(dev, newmode);
1658                                         break;
1659                                 }
1660                         }
1661                 }
1662
1663                 return ret;
1664         }
1665
1666         /* if eDP has no EDID, try to use fixed panel mode from VBT */
1667         if (is_edp(intel_dp)) {
1668                 if (dev_priv->panel_fixed_mode != NULL) {
1669                         struct drm_display_mode *mode;
1670                         mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
1671                         drm_mode_probed_add(connector, mode);
1672                         return 1;
1673                 }
1674         }
1675         return 0;
1676 }
1677
1678 static bool
1679 intel_dp_detect_audio(struct drm_connector *connector)
1680 {
1681         struct intel_dp *intel_dp = intel_attached_dp(connector);
1682         struct edid *edid;
1683         bool has_audio = false;
1684
1685         edid = drm_get_edid(connector, &intel_dp->adapter);
1686         if (edid) {
1687                 has_audio = drm_detect_monitor_audio(edid);
1688
1689                 connector->display_info.raw_edid = NULL;
1690                 kfree(edid);
1691         }
1692
1693         return has_audio;
1694 }
1695
1696 static int
1697 intel_dp_set_property(struct drm_connector *connector,
1698                       struct drm_property *property,
1699                       uint64_t val)
1700 {
1701         struct drm_i915_private *dev_priv = connector->dev->dev_private;
1702         struct intel_dp *intel_dp = intel_attached_dp(connector);
1703         int ret;
1704
1705         ret = drm_connector_property_set_value(connector, property, val);
1706         if (ret)
1707                 return ret;
1708
1709         if (property == dev_priv->force_audio_property) {
1710                 int i = val;
1711                 bool has_audio;
1712
1713                 if (i == intel_dp->force_audio)
1714                         return 0;
1715
1716                 intel_dp->force_audio = i;
1717
1718                 if (i == 0)
1719                         has_audio = intel_dp_detect_audio(connector);
1720                 else
1721                         has_audio = i > 0;
1722
1723                 if (has_audio == intel_dp->has_audio)
1724                         return 0;
1725
1726                 intel_dp->has_audio = has_audio;
1727                 goto done;
1728         }
1729
1730         if (property == dev_priv->broadcast_rgb_property) {
1731                 if (val == !!intel_dp->color_range)
1732                         return 0;
1733
1734                 intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0;
1735                 goto done;
1736         }
1737
1738         return -EINVAL;
1739
1740 done:
1741         if (intel_dp->base.base.crtc) {
1742                 struct drm_crtc *crtc = intel_dp->base.base.crtc;
1743                 drm_crtc_helper_set_mode(crtc, &crtc->mode,
1744                                          crtc->x, crtc->y,
1745                                          crtc->fb);
1746         }
1747
1748         return 0;
1749 }
1750
1751 static void
1752 intel_dp_destroy (struct drm_connector *connector)
1753 {
1754         drm_sysfs_connector_remove(connector);
1755         drm_connector_cleanup(connector);
1756         kfree(connector);
1757 }
1758
1759 static void intel_dp_encoder_destroy(struct drm_encoder *encoder)
1760 {
1761         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1762
1763         i2c_del_adapter(&intel_dp->adapter);
1764         drm_encoder_cleanup(encoder);
1765         kfree(intel_dp);
1766 }
1767
1768 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
1769         .dpms = intel_dp_dpms,
1770         .mode_fixup = intel_dp_mode_fixup,
1771         .prepare = intel_dp_prepare,
1772         .mode_set = intel_dp_mode_set,
1773         .commit = intel_dp_commit,
1774 };
1775
1776 static const struct drm_connector_funcs intel_dp_connector_funcs = {
1777         .dpms = drm_helper_connector_dpms,
1778         .detect = intel_dp_detect,
1779         .fill_modes = drm_helper_probe_single_connector_modes,
1780         .set_property = intel_dp_set_property,
1781         .destroy = intel_dp_destroy,
1782 };
1783
1784 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
1785         .get_modes = intel_dp_get_modes,
1786         .mode_valid = intel_dp_mode_valid,
1787         .best_encoder = intel_best_encoder,
1788 };
1789
1790 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
1791         .destroy = intel_dp_encoder_destroy,
1792 };
1793
1794 static void
1795 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
1796 {
1797         struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base);
1798
1799         if (intel_dp->dpms_mode == DRM_MODE_DPMS_ON)
1800                 intel_dp_check_link_status(intel_dp);
1801 }
1802
1803 /* Return which DP Port should be selected for Transcoder DP control */
1804 int
1805 intel_trans_dp_port_sel (struct drm_crtc *crtc)
1806 {
1807         struct drm_device *dev = crtc->dev;
1808         struct drm_mode_config *mode_config = &dev->mode_config;
1809         struct drm_encoder *encoder;
1810
1811         list_for_each_entry(encoder, &mode_config->encoder_list, head) {
1812                 struct intel_dp *intel_dp;
1813
1814                 if (encoder->crtc != crtc)
1815                         continue;
1816
1817                 intel_dp = enc_to_intel_dp(encoder);
1818                 if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT)
1819                         return intel_dp->output_reg;
1820         }
1821
1822         return -1;
1823 }
1824
1825 /* check the VBT to see whether the eDP is on DP-D port */
1826 bool intel_dpd_is_edp(struct drm_device *dev)
1827 {
1828         struct drm_i915_private *dev_priv = dev->dev_private;
1829         struct child_device_config *p_child;
1830         int i;
1831
1832         if (!dev_priv->child_dev_num)
1833                 return false;
1834
1835         for (i = 0; i < dev_priv->child_dev_num; i++) {
1836                 p_child = dev_priv->child_dev + i;
1837
1838                 if (p_child->dvo_port == PORT_IDPD &&
1839                     p_child->device_type == DEVICE_TYPE_eDP)
1840                         return true;
1841         }
1842         return false;
1843 }
1844
1845 static void
1846 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
1847 {
1848         intel_attach_force_audio_property(connector);
1849         intel_attach_broadcast_rgb_property(connector);
1850 }
1851
1852 void
1853 intel_dp_init(struct drm_device *dev, int output_reg)
1854 {
1855         struct drm_i915_private *dev_priv = dev->dev_private;
1856         struct drm_connector *connector;
1857         struct intel_dp *intel_dp;
1858         struct intel_encoder *intel_encoder;
1859         struct intel_connector *intel_connector;
1860         const char *name = NULL;
1861         int type;
1862
1863         intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL);
1864         if (!intel_dp)
1865                 return;
1866
1867         intel_dp->output_reg = output_reg;
1868         intel_dp->dpms_mode = -1;
1869
1870         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
1871         if (!intel_connector) {
1872                 kfree(intel_dp);
1873                 return;
1874         }
1875         intel_encoder = &intel_dp->base;
1876
1877         if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D)
1878                 if (intel_dpd_is_edp(dev))
1879                         intel_dp->is_pch_edp = true;
1880
1881         if (output_reg == DP_A || is_pch_edp(intel_dp)) {
1882                 type = DRM_MODE_CONNECTOR_eDP;
1883                 intel_encoder->type = INTEL_OUTPUT_EDP;
1884         } else {
1885                 type = DRM_MODE_CONNECTOR_DisplayPort;
1886                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
1887         }
1888
1889         connector = &intel_connector->base;
1890         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
1891         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
1892
1893         connector->polled = DRM_CONNECTOR_POLL_HPD;
1894
1895         if (output_reg == DP_B || output_reg == PCH_DP_B)
1896                 intel_encoder->clone_mask = (1 << INTEL_DP_B_CLONE_BIT);
1897         else if (output_reg == DP_C || output_reg == PCH_DP_C)
1898                 intel_encoder->clone_mask = (1 << INTEL_DP_C_CLONE_BIT);
1899         else if (output_reg == DP_D || output_reg == PCH_DP_D)
1900                 intel_encoder->clone_mask = (1 << INTEL_DP_D_CLONE_BIT);
1901
1902         if (is_edp(intel_dp))
1903                 intel_encoder->clone_mask = (1 << INTEL_EDP_CLONE_BIT);
1904
1905         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1906         connector->interlace_allowed = true;
1907         connector->doublescan_allowed = 0;
1908
1909         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
1910                          DRM_MODE_ENCODER_TMDS);
1911         drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
1912
1913         intel_connector_attach_encoder(intel_connector, intel_encoder);
1914         drm_sysfs_connector_add(connector);
1915
1916         /* Set up the DDC bus. */
1917         switch (output_reg) {
1918                 case DP_A:
1919                         name = "DPDDC-A";
1920                         break;
1921                 case DP_B:
1922                 case PCH_DP_B:
1923                         dev_priv->hotplug_supported_mask |=
1924                                 HDMIB_HOTPLUG_INT_STATUS;
1925                         name = "DPDDC-B";
1926                         break;
1927                 case DP_C:
1928                 case PCH_DP_C:
1929                         dev_priv->hotplug_supported_mask |=
1930                                 HDMIC_HOTPLUG_INT_STATUS;
1931                         name = "DPDDC-C";
1932                         break;
1933                 case DP_D:
1934                 case PCH_DP_D:
1935                         dev_priv->hotplug_supported_mask |=
1936                                 HDMID_HOTPLUG_INT_STATUS;
1937                         name = "DPDDC-D";
1938                         break;
1939         }
1940
1941         intel_dp_i2c_init(intel_dp, intel_connector, name);
1942
1943         /* Cache some DPCD data in the eDP case */
1944         if (is_edp(intel_dp)) {
1945                 int ret;
1946                 u32 pp_on, pp_div;
1947
1948                 pp_on = I915_READ(PCH_PP_ON_DELAYS);
1949                 pp_div = I915_READ(PCH_PP_DIVISOR);
1950
1951                 /* Get T3 & T12 values (note: VESA not bspec terminology) */
1952                 dev_priv->panel_t3 = (pp_on & 0x1fff0000) >> 16;
1953                 dev_priv->panel_t3 /= 10; /* t3 in 100us units */
1954                 dev_priv->panel_t12 = pp_div & 0xf;
1955                 dev_priv->panel_t12 *= 100; /* t12 in 100ms units */
1956
1957                 ironlake_edp_panel_vdd_on(intel_dp);
1958                 ret = intel_dp_aux_native_read(intel_dp, DP_DPCD_REV,
1959                                                intel_dp->dpcd,
1960                                                sizeof(intel_dp->dpcd));
1961                 ironlake_edp_panel_vdd_off(intel_dp);
1962                 if (ret == sizeof(intel_dp->dpcd)) {
1963                         if (intel_dp->dpcd[0] >= 0x11)
1964                                 dev_priv->no_aux_handshake = intel_dp->dpcd[3] &
1965                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
1966                 } else {
1967                         /* if this fails, presume the device is a ghost */
1968                         DRM_INFO("failed to retrieve link info, disabling eDP\n");
1969                         intel_dp_encoder_destroy(&intel_dp->base.base);
1970                         intel_dp_destroy(&intel_connector->base);
1971                         return;
1972                 }
1973         }
1974
1975         intel_encoder->hot_plug = intel_dp_hot_plug;
1976
1977         if (is_edp(intel_dp)) {
1978                 /* initialize panel mode from VBT if available for eDP */
1979                 if (dev_priv->lfp_lvds_vbt_mode) {
1980                         dev_priv->panel_fixed_mode =
1981                                 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1982                         if (dev_priv->panel_fixed_mode) {
1983                                 dev_priv->panel_fixed_mode->type |=
1984                                         DRM_MODE_TYPE_PREFERRED;
1985                         }
1986                 }
1987         }
1988
1989         intel_dp_add_properties(intel_dp, connector);
1990
1991         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
1992          * 0xd.  Failure to do so will result in spurious interrupts being
1993          * generated on the port when a cable is not attached.
1994          */
1995         if (IS_G4X(dev) && !IS_GM45(dev)) {
1996                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
1997                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
1998         }
1999 }