drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include <linux/slab.h>
  32 #include <linux/vgaarb.h>
  33 #include "drmP.h"
  34 #include "intel_drv.h"
  35 #include "i915_drm.h"
  36 #include "i915_drv.h"
  37 #include "i915_trace.h"
  38 #include "drm_dp_helper.h"
  39
  40 #include "drm_crtc_helper.h"
  41
  42 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  43
  44 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  45 static void intel_update_watermarks(struct drm_device *dev);
  46 static void intel_increase_pllclock(struct drm_crtc *crtc);
  47 static void intel_crtc_update_cursor(struct drm_crtc *crtc);
  48
  49 typedef struct {
  50     /* given values */
  51     int n;
  52     int m1, m2;
  53     int p1, p2;
  54     /* derived values */
  55     int dot;
  56     int vco;
  57     int m;
  58     int p;
  59 } intel_clock_t;
  60
  61 typedef struct {
  62     int min, max;
  63 } intel_range_t;
  64
  65 typedef struct {
  66     int dot_limit;
  67     int p2_slow, p2_fast;
  68 } intel_p2_t;
  69
  70 #define INTEL_P2_NUM                  2
  71 typedef struct intel_limit intel_limit_t;
  72 struct intel_limit {
  73     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  74     intel_p2_t      p2;
  75     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  76                       int, int, intel_clock_t *);
  77 };
  78
  79 #define I8XX_DOT_MIN              25000
  80 #define I8XX_DOT_MAX             350000
  81 #define I8XX_VCO_MIN             930000
  82 #define I8XX_VCO_MAX            1400000
  83 #define I8XX_N_MIN                    3
  84 #define I8XX_N_MAX                   16
  85 #define I8XX_M_MIN                   96
  86 #define I8XX_M_MAX                  140
  87 #define I8XX_M1_MIN                  18
  88 #define I8XX_M1_MAX                  26
  89 #define I8XX_M2_MIN                   6
  90 #define I8XX_M2_MAX                  16
  91 #define I8XX_P_MIN                    4
  92 #define I8XX_P_MAX                  128
  93 #define I8XX_P1_MIN                   2
  94 #define I8XX_P1_MAX                  33
  95 #define I8XX_P1_LVDS_MIN              1
  96 #define I8XX_P1_LVDS_MAX              6
  97 #define I8XX_P2_SLOW                  4
  98 #define I8XX_P2_FAST                  2
  99 #define I8XX_P2_LVDS_SLOW             14
 100 #define I8XX_P2_LVDS_FAST             7
 101 #define I8XX_P2_SLOW_LIMIT       165000
 102
 103 #define I9XX_DOT_MIN              20000
 104 #define I9XX_DOT_MAX             400000
 105 #define I9XX_VCO_MIN            1400000
 106 #define I9XX_VCO_MAX            2800000
 107 #define PINEVIEW_VCO_MIN                1700000
 108 #define PINEVIEW_VCO_MAX                3500000
 109 #define I9XX_N_MIN                    1
 110 #define I9XX_N_MAX                    6
 111 /* Pineview's Ncounter is a ring counter */
 112 #define PINEVIEW_N_MIN                3
 113 #define PINEVIEW_N_MAX                6
 114 #define I9XX_M_MIN                   70
 115 #define I9XX_M_MAX                  120
 116 #define PINEVIEW_M_MIN                2
 117 #define PINEVIEW_M_MAX              256
 118 #define I9XX_M1_MIN                  10
 119 #define I9XX_M1_MAX                  22
 120 #define I9XX_M2_MIN                   5
 121 #define I9XX_M2_MAX                   9
 122 /* Pineview M1 is reserved, and must be 0 */
 123 #define PINEVIEW_M1_MIN               0
 124 #define PINEVIEW_M1_MAX               0
 125 #define PINEVIEW_M2_MIN               0
 126 #define PINEVIEW_M2_MAX               254
 127 #define I9XX_P_SDVO_DAC_MIN           5
 128 #define I9XX_P_SDVO_DAC_MAX          80
 129 #define I9XX_P_LVDS_MIN               7
 130 #define I9XX_P_LVDS_MAX              98
 131 #define PINEVIEW_P_LVDS_MIN                   7
 132 #define PINEVIEW_P_LVDS_MAX                  112
 133 #define I9XX_P1_MIN                   1
 134 #define I9XX_P1_MAX                   8
 135 #define I9XX_P2_SDVO_DAC_SLOW                10
 136 #define I9XX_P2_SDVO_DAC_FAST                 5
 137 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 138 #define I9XX_P2_LVDS_SLOW                    14
 139 #define I9XX_P2_LVDS_FAST                     7
 140 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 141
 142 /*The parameter is for SDVO on G4x platform*/
 143 #define G4X_DOT_SDVO_MIN           25000
 144 #define G4X_DOT_SDVO_MAX           270000
 145 #define G4X_VCO_MIN                1750000
 146 #define G4X_VCO_MAX                3500000
 147 #define G4X_N_SDVO_MIN             1
 148 #define G4X_N_SDVO_MAX             4
 149 #define G4X_M_SDVO_MIN             104
 150 #define G4X_M_SDVO_MAX             138
 151 #define G4X_M1_SDVO_MIN            17
 152 #define G4X_M1_SDVO_MAX            23
 153 #define G4X_M2_SDVO_MIN            5
 154 #define G4X_M2_SDVO_MAX            11
 155 #define G4X_P_SDVO_MIN             10
 156 #define G4X_P_SDVO_MAX             30
 157 #define G4X_P1_SDVO_MIN            1
 158 #define G4X_P1_SDVO_MAX            3
 159 #define G4X_P2_SDVO_SLOW           10
 160 #define G4X_P2_SDVO_FAST           10
 161 #define G4X_P2_SDVO_LIMIT          270000
 162
 163 /*The parameter is for HDMI_DAC on G4x platform*/
 164 #define G4X_DOT_HDMI_DAC_MIN           22000
 165 #define G4X_DOT_HDMI_DAC_MAX           400000
 166 #define G4X_N_HDMI_DAC_MIN             1
 167 #define G4X_N_HDMI_DAC_MAX             4
 168 #define G4X_M_HDMI_DAC_MIN             104
 169 #define G4X_M_HDMI_DAC_MAX             138
 170 #define G4X_M1_HDMI_DAC_MIN            16
 171 #define G4X_M1_HDMI_DAC_MAX            23
 172 #define G4X_M2_HDMI_DAC_MIN            5
 173 #define G4X_M2_HDMI_DAC_MAX            11
 174 #define G4X_P_HDMI_DAC_MIN             5
 175 #define G4X_P_HDMI_DAC_MAX             80
 176 #define G4X_P1_HDMI_DAC_MIN            1
 177 #define G4X_P1_HDMI_DAC_MAX            8
 178 #define G4X_P2_HDMI_DAC_SLOW           10
 179 #define G4X_P2_HDMI_DAC_FAST           5
 180 #define G4X_P2_HDMI_DAC_LIMIT          165000
 181
 182 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 183 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 184 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 185 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 186 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 187 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 188 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 189 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 190 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 191 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 192 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 193 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 194 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 195 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 196 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 197 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 198 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 199 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 200
 201 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 202 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 203 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 204 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 205 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 206 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 207 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 208 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 209 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 210 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 211 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 212 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 213 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 214 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 215 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 216 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 217 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 218 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 219
 220 /*The parameter is for DISPLAY PORT on G4x platform*/
 221 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 222 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 223 #define G4X_N_DISPLAY_PORT_MIN             1
 224 #define G4X_N_DISPLAY_PORT_MAX             2
 225 #define G4X_M_DISPLAY_PORT_MIN             97
 226 #define G4X_M_DISPLAY_PORT_MAX             108
 227 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 228 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 229 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 230 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 231 #define G4X_P_DISPLAY_PORT_MIN             10
 232 #define G4X_P_DISPLAY_PORT_MAX             20
 233 #define G4X_P1_DISPLAY_PORT_MIN            1
 234 #define G4X_P1_DISPLAY_PORT_MAX            2
 235 #define G4X_P2_DISPLAY_PORT_SLOW           10
 236 #define G4X_P2_DISPLAY_PORT_FAST           10
 237 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 238
 239 /* Ironlake / Sandybridge */
 240 /* as we calculate clock using (register_value + 2) for
 241    N/M1/M2, so here the range value for them is (actual_value-2).
 242  */
 243 #define IRONLAKE_DOT_MIN         25000
 244 #define IRONLAKE_DOT_MAX         350000
 245 #define IRONLAKE_VCO_MIN         1760000
 246 #define IRONLAKE_VCO_MAX         3510000
 247 #define IRONLAKE_M1_MIN          12
 248 #define IRONLAKE_M1_MAX          22
 249 #define IRONLAKE_M2_MIN          5
 250 #define IRONLAKE_M2_MAX          9
 251 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 252
 253 /* We have parameter ranges for different type of outputs. */
 254
 255 /* DAC & HDMI Refclk 120Mhz */
 256 #define IRONLAKE_DAC_N_MIN      1
 257 #define IRONLAKE_DAC_N_MAX      5
 258 #define IRONLAKE_DAC_M_MIN      79
 259 #define IRONLAKE_DAC_M_MAX      127
 260 #define IRONLAKE_DAC_P_MIN      5
 261 #define IRONLAKE_DAC_P_MAX      80
 262 #define IRONLAKE_DAC_P1_MIN     1
 263 #define IRONLAKE_DAC_P1_MAX     8
 264 #define IRONLAKE_DAC_P2_SLOW    10
 265 #define IRONLAKE_DAC_P2_FAST    5
 266
 267 /* LVDS single-channel 120Mhz refclk */
 268 #define IRONLAKE_LVDS_S_N_MIN   1
 269 #define IRONLAKE_LVDS_S_N_MAX   3
 270 #define IRONLAKE_LVDS_S_M_MIN   79
 271 #define IRONLAKE_LVDS_S_M_MAX   118
 272 #define IRONLAKE_LVDS_S_P_MIN   28
 273 #define IRONLAKE_LVDS_S_P_MAX   112
 274 #define IRONLAKE_LVDS_S_P1_MIN  2
 275 #define IRONLAKE_LVDS_S_P1_MAX  8
 276 #define IRONLAKE_LVDS_S_P2_SLOW 14
 277 #define IRONLAKE_LVDS_S_P2_FAST 14
 278
 279 /* LVDS dual-channel 120Mhz refclk */
 280 #define IRONLAKE_LVDS_D_N_MIN   1
 281 #define IRONLAKE_LVDS_D_N_MAX   3
 282 #define IRONLAKE_LVDS_D_M_MIN   79
 283 #define IRONLAKE_LVDS_D_M_MAX   127
 284 #define IRONLAKE_LVDS_D_P_MIN   14
 285 #define IRONLAKE_LVDS_D_P_MAX   56
 286 #define IRONLAKE_LVDS_D_P1_MIN  2
 287 #define IRONLAKE_LVDS_D_P1_MAX  8
 288 #define IRONLAKE_LVDS_D_P2_SLOW 7
 289 #define IRONLAKE_LVDS_D_P2_FAST 7
 290
 291 /* LVDS single-channel 100Mhz refclk */
 292 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 293 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 294 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 295 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 296 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 297 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 298 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 299 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 300 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 301 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 302
 303 /* LVDS dual-channel 100Mhz refclk */
 304 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 305 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 306 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 307 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 308 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 309 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 310 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 311 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 312 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 313 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 314
 315 /* DisplayPort */
 316 #define IRONLAKE_DP_N_MIN               1
 317 #define IRONLAKE_DP_N_MAX               2
 318 #define IRONLAKE_DP_M_MIN               81
 319 #define IRONLAKE_DP_M_MAX               90
 320 #define IRONLAKE_DP_P_MIN               10
 321 #define IRONLAKE_DP_P_MAX               20
 322 #define IRONLAKE_DP_P2_FAST             10
 323 #define IRONLAKE_DP_P2_SLOW             10
 324 #define IRONLAKE_DP_P2_LIMIT            0
 325 #define IRONLAKE_DP_P1_MIN              1
 326 #define IRONLAKE_DP_P1_MAX              2
 327
 328 /* FDI */
 329 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
 330
 331 static bool
 332 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 333                     int target, int refclk, intel_clock_t *best_clock);
 334 static bool
 335 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 336                         int target, int refclk, intel_clock_t *best_clock);
 337
 338 static bool
 339 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 340                       int target, int refclk, intel_clock_t *best_clock);
 341 static bool
 342 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 343                            int target, int refclk, intel_clock_t *best_clock);
 344
 345 static inline u32 /* units of 100MHz */
 346 intel_fdi_link_freq(struct drm_device *dev)
 347 {
 348         struct drm_i915_private *dev_priv = dev->dev_private;
 349         return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 350 }
 351
 352 static const intel_limit_t intel_limits_i8xx_dvo = {
 353         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 354         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 355         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 356         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 357         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 358         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 359         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 360         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 361         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 362                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 363         .find_pll = intel_find_best_PLL,
 364 };
 365
 366 static const intel_limit_t intel_limits_i8xx_lvds = {
 367         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 368         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 369         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 370         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 371         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 372         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 373         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 374         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 375         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 376                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 377         .find_pll = intel_find_best_PLL,
 378 };
 379
 380 static const intel_limit_t intel_limits_i9xx_sdvo = {
 381         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 382         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 383         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 384         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 385         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 386         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 387         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 388         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 389         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 390                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 391         .find_pll = intel_find_best_PLL,
 392 };
 393
 394 static const intel_limit_t intel_limits_i9xx_lvds = {
 395         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 396         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 397         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 398         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 399         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 400         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 401         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 402         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 403         /* The single-channel range is 25-112Mhz, and dual-channel
 404          * is 80-224Mhz.  Prefer single channel as much as possible.
 405          */
 406         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 407                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 408         .find_pll = intel_find_best_PLL,
 409 };
 410
 411     /* below parameter and function is for G4X Chipset Family*/
 412 static const intel_limit_t intel_limits_g4x_sdvo = {
 413         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 414         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 415         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 416         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 417         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 418         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 419         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 420         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 421         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 422                  .p2_slow = G4X_P2_SDVO_SLOW,
 423                  .p2_fast = G4X_P2_SDVO_FAST
 424         },
 425         .find_pll = intel_g4x_find_best_PLL,
 426 };
 427
 428 static const intel_limit_t intel_limits_g4x_hdmi = {
 429         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 430         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 431         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 432         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 433         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 434         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 435         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 436         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 437         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 438                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 439                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 440         },
 441         .find_pll = intel_g4x_find_best_PLL,
 442 };
 443
 444 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 445         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 446                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 447         .vco = { .min = G4X_VCO_MIN,
 448                  .max = G4X_VCO_MAX },
 449         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 450                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 451         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 452                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 453         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 454                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 455         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 456                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 457         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 458                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 459         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 460                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 461         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 462                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 463                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 464         },
 465         .find_pll = intel_g4x_find_best_PLL,
 466 };
 467
 468 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 469         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 470                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 471         .vco = { .min = G4X_VCO_MIN,
 472                  .max = G4X_VCO_MAX },
 473         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 474                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 475         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 476                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 477         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 478                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 479         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 480                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 481         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 482                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 483         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 484                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 485         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 486                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 487                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 488         },
 489         .find_pll = intel_g4x_find_best_PLL,
 490 };
 491
 492 static const intel_limit_t intel_limits_g4x_display_port = {
 493         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 494                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 495         .vco = { .min = G4X_VCO_MIN,
 496                  .max = G4X_VCO_MAX},
 497         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 498                  .max = G4X_N_DISPLAY_PORT_MAX },
 499         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 500                  .max = G4X_M_DISPLAY_PORT_MAX },
 501         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 502                  .max = G4X_M1_DISPLAY_PORT_MAX },
 503         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 504                  .max = G4X_M2_DISPLAY_PORT_MAX },
 505         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 506                  .max = G4X_P_DISPLAY_PORT_MAX },
 507         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 508                  .max = G4X_P1_DISPLAY_PORT_MAX},
 509         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 510                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 511                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 512         .find_pll = intel_find_pll_g4x_dp,
 513 };
 514
 515 static const intel_limit_t intel_limits_pineview_sdvo = {
 516         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 517         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 518         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 519         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 520         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 521         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 522         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 523         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 524         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 525                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 526         .find_pll = intel_find_best_PLL,
 527 };
 528
 529 static const intel_limit_t intel_limits_pineview_lvds = {
 530         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 531         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 532         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 533         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 534         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 535         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 536         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 537         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 538         /* Pineview only supports single-channel mode. */
 539         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 540                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 541         .find_pll = intel_find_best_PLL,
 542 };
 543
 544 static const intel_limit_t intel_limits_ironlake_dac = {
 545         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 546         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 547         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 548         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 549         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 550         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 551         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 552         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 553         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 554                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 555                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 556         .find_pll = intel_g4x_find_best_PLL,
 557 };
 558
 559 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 560         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 561         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 562         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 563         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 564         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 565         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 566         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 567         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 568         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 569                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 570                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 571         .find_pll = intel_g4x_find_best_PLL,
 572 };
 573
 574 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 575         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 576         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 577         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 578         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 579         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 580         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 581         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 582         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 583         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 584                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 585                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 586         .find_pll = intel_g4x_find_best_PLL,
 587 };
 588
 589 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 590         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 591         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 592         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 593         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 594         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 595         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 596         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 597         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 598         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 599                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 600                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 601         .find_pll = intel_g4x_find_best_PLL,
 602 };
 603
 604 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 605         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 606         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 607         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 608         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 609         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 610         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 611         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 612         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 613         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 614                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 615                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 616         .find_pll = intel_g4x_find_best_PLL,
 617 };
 618
 619 static const intel_limit_t intel_limits_ironlake_display_port = {
 620         .dot = { .min = IRONLAKE_DOT_MIN,
 621                  .max = IRONLAKE_DOT_MAX },
 622         .vco = { .min = IRONLAKE_VCO_MIN,
 623                  .max = IRONLAKE_VCO_MAX},
 624         .n   = { .min = IRONLAKE_DP_N_MIN,
 625                  .max = IRONLAKE_DP_N_MAX },
 626         .m   = { .min = IRONLAKE_DP_M_MIN,
 627                  .max = IRONLAKE_DP_M_MAX },
 628         .m1  = { .min = IRONLAKE_M1_MIN,
 629                  .max = IRONLAKE_M1_MAX },
 630         .m2  = { .min = IRONLAKE_M2_MIN,
 631                  .max = IRONLAKE_M2_MAX },
 632         .p   = { .min = IRONLAKE_DP_P_MIN,
 633                  .max = IRONLAKE_DP_P_MAX },
 634         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 635                  .max = IRONLAKE_DP_P1_MAX},
 636         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 637                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 638                  .p2_fast = IRONLAKE_DP_P2_FAST },
 639         .find_pll = intel_find_pll_ironlake_dp,
 640 };
 641
 642 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
 643 {
 644         struct drm_device *dev = crtc->dev;
 645         struct drm_i915_private *dev_priv = dev->dev_private;
 646         const intel_limit_t *limit;
 647         int refclk = 120;
 648
 649         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 650                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
 651                         refclk = 100;
 652
 653                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 654                     LVDS_CLKB_POWER_UP) {
 655                         /* LVDS dual channel */
 656                         if (refclk == 100)
 657                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 658                         else
 659                                 limit = &intel_limits_ironlake_dual_lvds;
 660                 } else {
 661                         if (refclk == 100)
 662                                 limit = &intel_limits_ironlake_single_lvds_100m;
 663                         else
 664                                 limit = &intel_limits_ironlake_single_lvds;
 665                 }
 666         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 667                         HAS_eDP)
 668                 limit = &intel_limits_ironlake_display_port;
 669         else
 670                 limit = &intel_limits_ironlake_dac;
 671
 672         return limit;
 673 }
 674
 675 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 676 {
 677         struct drm_device *dev = crtc->dev;
 678         struct drm_i915_private *dev_priv = dev->dev_private;
 679         const intel_limit_t *limit;
 680
 681         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 682                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 683                     LVDS_CLKB_POWER_UP)
 684                         /* LVDS with dual channel */
 685                         limit = &intel_limits_g4x_dual_channel_lvds;
 686                 else
 687                         /* LVDS with dual channel */
 688                         limit = &intel_limits_g4x_single_channel_lvds;
 689         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 690                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 691                 limit = &intel_limits_g4x_hdmi;
 692         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 693                 limit = &intel_limits_g4x_sdvo;
 694         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 695                 limit = &intel_limits_g4x_display_port;
 696         } else /* The option is for other outputs */
 697                 limit = &intel_limits_i9xx_sdvo;
 698
 699         return limit;
 700 }
 701
 702 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 703 {
 704         struct drm_device *dev = crtc->dev;
 705         const intel_limit_t *limit;
 706
 707         if (HAS_PCH_SPLIT(dev))
 708                 limit = intel_ironlake_limit(crtc);
 709         else if (IS_G4X(dev)) {
 710                 limit = intel_g4x_limit(crtc);
 711         } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
 712                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 713                         limit = &intel_limits_i9xx_lvds;
 714                 else
 715                         limit = &intel_limits_i9xx_sdvo;
 716         } else if (IS_PINEVIEW(dev)) {
 717                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 718                         limit = &intel_limits_pineview_lvds;
 719                 else
 720                         limit = &intel_limits_pineview_sdvo;
 721         } else {
 722                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 723                         limit = &intel_limits_i8xx_lvds;
 724                 else
 725                         limit = &intel_limits_i8xx_dvo;
 726         }
 727         return limit;
 728 }
 729
 730 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 731 static void pineview_clock(int refclk, intel_clock_t *clock)
 732 {
 733         clock->m = clock->m2 + 2;
 734         clock->p = clock->p1 * clock->p2;
 735         clock->vco = refclk * clock->m / clock->n;
 736         clock->dot = clock->vco / clock->p;
 737 }
 738
 739 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 740 {
 741         if (IS_PINEVIEW(dev)) {
 742                 pineview_clock(refclk, clock);
 743                 return;
 744         }
 745         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 746         clock->p = clock->p1 * clock->p2;
 747         clock->vco = refclk * clock->m / (clock->n + 2);
 748         clock->dot = clock->vco / clock->p;
 749 }
 750
 751 /**
 752  * Returns whether any output on the specified pipe is of the specified type
 753  */
 754 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 755 {
 756         struct drm_device *dev = crtc->dev;
 757         struct drm_mode_config *mode_config = &dev->mode_config;
 758         struct intel_encoder *encoder;
 759
 760         list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
 761                 if (encoder->base.crtc == crtc && encoder->type == type)
 762                         return true;
 763
 764         return false;
 765 }
 766
 767 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 768 /**
 769  * Returns whether the given set of divisors are valid for a given refclk with
 770  * the given connectors.
 771  */
 772
 773 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 774 {
 775         const intel_limit_t *limit = intel_limit (crtc);
 776         struct drm_device *dev = crtc->dev;
 777
 778         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 779                 INTELPllInvalid ("p1 out of range\n");
 780         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 781                 INTELPllInvalid ("p out of range\n");
 782         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 783                 INTELPllInvalid ("m2 out of range\n");
 784         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 785                 INTELPllInvalid ("m1 out of range\n");
 786         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 787                 INTELPllInvalid ("m1 <= m2\n");
 788         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 789                 INTELPllInvalid ("m out of range\n");
 790         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 791                 INTELPllInvalid ("n out of range\n");
 792         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 793                 INTELPllInvalid ("vco out of range\n");
 794         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 795          * connector, etc., rather than just a single range.
 796          */
 797         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 798                 INTELPllInvalid ("dot out of range\n");
 799
 800         return true;
 801 }
 802
 803 static bool
 804 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 805                     int target, int refclk, intel_clock_t *best_clock)
 806
 807 {
 808         struct drm_device *dev = crtc->dev;
 809         struct drm_i915_private *dev_priv = dev->dev_private;
 810         intel_clock_t clock;
 811         int err = target;
 812
 813         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 814             (I915_READ(LVDS)) != 0) {
 815                 /*
 816                  * For LVDS, if the panel is on, just rely on its current
 817                  * settings for dual-channel.  We haven't figured out how to
 818                  * reliably set up different single/dual channel state, if we
 819                  * even can.
 820                  */
 821                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 822                     LVDS_CLKB_POWER_UP)
 823                         clock.p2 = limit->p2.p2_fast;
 824                 else
 825                         clock.p2 = limit->p2.p2_slow;
 826         } else {
 827                 if (target < limit->p2.dot_limit)
 828                         clock.p2 = limit->p2.p2_slow;
 829                 else
 830                         clock.p2 = limit->p2.p2_fast;
 831         }
 832
 833         memset (best_clock, 0, sizeof (*best_clock));
 834
 835         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 836              clock.m1++) {
 837                 for (clock.m2 = limit->m2.min;
 838                      clock.m2 <= limit->m2.max; clock.m2++) {
 839                         /* m1 is always 0 in Pineview */
 840                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 841                                 break;
 842                         for (clock.n = limit->n.min;
 843                              clock.n <= limit->n.max; clock.n++) {
 844                                 for (clock.p1 = limit->p1.min;
 845                                         clock.p1 <= limit->p1.max; clock.p1++) {
 846                                         int this_err;
 847
 848                                         intel_clock(dev, refclk, &clock);
 849
 850                                         if (!intel_PLL_is_valid(crtc, &clock))
 851                                                 continue;
 852
 853                                         this_err = abs(clock.dot - target);
 854                                         if (this_err < err) {
 855                                                 *best_clock = clock;
 856                                                 err = this_err;
 857                                         }
 858                                 }
 859                         }
 860                 }
 861         }
 862
 863         return (err != target);
 864 }
 865
 866 static bool
 867 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 868                         int target, int refclk, intel_clock_t *best_clock)
 869 {
 870         struct drm_device *dev = crtc->dev;
 871         struct drm_i915_private *dev_priv = dev->dev_private;
 872         intel_clock_t clock;
 873         int max_n;
 874         bool found;
 875         /* approximately equals target * 0.00585 */
 876         int err_most = (target >> 8) + (target >> 9);
 877         found = false;
 878
 879         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 880                 int lvds_reg;
 881
 882                 if (HAS_PCH_SPLIT(dev))
 883                         lvds_reg = PCH_LVDS;
 884                 else
 885                         lvds_reg = LVDS;
 886                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 887                     LVDS_CLKB_POWER_UP)
 888                         clock.p2 = limit->p2.p2_fast;
 889                 else
 890                         clock.p2 = limit->p2.p2_slow;
 891         } else {
 892                 if (target < limit->p2.dot_limit)
 893                         clock.p2 = limit->p2.p2_slow;
 894                 else
 895                         clock.p2 = limit->p2.p2_fast;
 896         }
 897
 898         memset(best_clock, 0, sizeof(*best_clock));
 899         max_n = limit->n.max;
 900         /* based on hardware requirement, prefer smaller n to precision */
 901         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 902                 /* based on hardware requirement, prefere larger m1,m2 */
 903                 for (clock.m1 = limit->m1.max;
 904                      clock.m1 >= limit->m1.min; clock.m1--) {
 905                         for (clock.m2 = limit->m2.max;
 906                              clock.m2 >= limit->m2.min; clock.m2--) {
 907                                 for (clock.p1 = limit->p1.max;
 908                                      clock.p1 >= limit->p1.min; clock.p1--) {
 909                                         int this_err;
 910
 911                                         intel_clock(dev, refclk, &clock);
 912                                         if (!intel_PLL_is_valid(crtc, &clock))
 913                                                 continue;
 914                                         this_err = abs(clock.dot - target) ;
 915                                         if (this_err < err_most) {
 916                                                 *best_clock = clock;
 917                                                 err_most = this_err;
 918                                                 max_n = clock.n;
 919                                                 found = true;
 920                                         }
 921                                 }
 922                         }
 923                 }
 924         }
 925         return found;
 926 }
 927
 928 static bool
 929 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 930                            int target, int refclk, intel_clock_t *best_clock)
 931 {
 932         struct drm_device *dev = crtc->dev;
 933         intel_clock_t clock;
 934
 935         /* return directly when it is eDP */
 936         if (HAS_eDP)
 937                 return true;
 938
 939         if (target < 200000) {
 940                 clock.n = 1;
 941                 clock.p1 = 2;
 942                 clock.p2 = 10;
 943                 clock.m1 = 12;
 944                 clock.m2 = 9;
 945         } else {
 946                 clock.n = 2;
 947                 clock.p1 = 1;
 948                 clock.p2 = 10;
 949                 clock.m1 = 14;
 950                 clock.m2 = 8;
 951         }
 952         intel_clock(dev, refclk, &clock);
 953         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 954         return true;
 955 }
 956
 957 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 958 static bool
 959 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 960                       int target, int refclk, intel_clock_t *best_clock)
 961 {
 962         intel_clock_t clock;
 963         if (target < 200000) {
 964                 clock.p1 = 2;
 965                 clock.p2 = 10;
 966                 clock.n = 2;
 967                 clock.m1 = 23;
 968                 clock.m2 = 8;
 969         } else {
 970                 clock.p1 = 1;
 971                 clock.p2 = 10;
 972                 clock.n = 1;
 973                 clock.m1 = 14;
 974                 clock.m2 = 2;
 975         }
 976         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 977         clock.p = (clock.p1 * clock.p2);
 978         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 979         clock.vco = 0;
 980         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 981         return true;
 982 }
 983
 984 /**
 985  * intel_wait_for_vblank - wait for vblank on a given pipe
 986  * @dev: drm device
 987  * @pipe: pipe to wait for
 988  *
 989  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 990  * mode setting code.
 991  */
 992 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 993 {
 994         struct drm_i915_private *dev_priv = dev->dev_private;
 995         int pipestat_reg = (pipe == 0 ? PIPEASTAT : PIPEBSTAT);
 996
 997         /* Clear existing vblank status. Note this will clear any other
 998          * sticky status fields as well.
 999          *
1000          * This races with i915_driver_irq_handler() with the result
1001          * that either function could miss a vblank event.  Here it is not
1002          * fatal, as we will either wait upon the next vblank interrupt or
1003          * timeout.  Generally speaking intel_wait_for_vblank() is only
1004          * called during modeset at which time the GPU should be idle and
1005          * should *not* be performing page flips and thus not waiting on
1006          * vblanks...
1007          * Currently, the result of us stealing a vblank from the irq
1008          * handler is that a single frame will be skipped during swapbuffers.
1009          */
1010         I915_WRITE(pipestat_reg,
1011                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
1012
1013         /* Wait for vblank interrupt bit to set */
1014         if (wait_for(I915_READ(pipestat_reg) &
1015                      PIPE_VBLANK_INTERRUPT_STATUS,
1016                      50))
1017                 DRM_DEBUG_KMS("vblank wait timed out\n");
1018 }
1019
1020 /**
1021  * intel_wait_for_vblank_off - wait for vblank after disabling a pipe
1022  * @dev: drm device
1023  * @pipe: pipe to wait for
1024  *
1025  * After disabling a pipe, we can't wait for vblank in the usual way,
1026  * spinning on the vblank interrupt status bit, since we won't actually
1027  * see an interrupt when the pipe is disabled.
1028  *
1029  * So this function waits for the display line value to settle (it
1030  * usually ends up stopping at the start of the next frame).
1031  */
1032 void intel_wait_for_vblank_off(struct drm_device *dev, int pipe)
1033 {
1034         struct drm_i915_private *dev_priv = dev->dev_private;
1035         int pipedsl_reg = (pipe == 0 ? PIPEADSL : PIPEBDSL);
1036         unsigned long timeout = jiffies + msecs_to_jiffies(100);
1037         u32 last_line, line;
1038
1039         /* Wait for the display line to settle */
1040         line = I915_READ(pipedsl_reg) & DSL_LINEMASK;
1041         do {
1042                 last_line = line;
1043                 MSLEEP(5);
1044                 line = I915_READ(pipedsl_reg) & DSL_LINEMASK;
1045         } while (line != last_line && time_after(timeout, jiffies));
1046
1047         if (line != last_line)
1048                 DRM_DEBUG_KMS("vblank wait timed out\n");
1049 }
1050
1051 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1052 {
1053         struct drm_device *dev = crtc->dev;
1054         struct drm_i915_private *dev_priv = dev->dev_private;
1055         struct drm_framebuffer *fb = crtc->fb;
1056         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1057         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1058         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1059         int plane, i;
1060         u32 fbc_ctl, fbc_ctl2;
1061
1062         if (fb->pitch == dev_priv->cfb_pitch &&
1063             obj_priv->fence_reg == dev_priv->cfb_fence &&
1064             intel_crtc->plane == dev_priv->cfb_plane &&
1065             I915_READ(FBC_CONTROL) & FBC_CTL_EN)
1066                 return;
1067
1068         i8xx_disable_fbc(dev);
1069
1070         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1071
1072         if (fb->pitch < dev_priv->cfb_pitch)
1073                 dev_priv->cfb_pitch = fb->pitch;
1074
1075         /* FBC_CTL wants 64B units */
1076         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1077         dev_priv->cfb_fence = obj_priv->fence_reg;
1078         dev_priv->cfb_plane = intel_crtc->plane;
1079         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1080
1081         /* Clear old tags */
1082         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1083                 I915_WRITE(FBC_TAG + (i * 4), 0);
1084
1085         /* Set it up... */
1086         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1087         if (obj_priv->tiling_mode != I915_TILING_NONE)
1088                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1089         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1090         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1091
1092         /* enable it... */
1093         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1094         if (IS_I945GM(dev))
1095                 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
1096         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1097         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1098         if (obj_priv->tiling_mode != I915_TILING_NONE)
1099                 fbc_ctl |= dev_priv->cfb_fence;
1100         I915_WRITE(FBC_CONTROL, fbc_ctl);
1101
1102         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1103                       dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1104 }
1105
1106 void i8xx_disable_fbc(struct drm_device *dev)
1107 {
1108         struct drm_i915_private *dev_priv = dev->dev_private;
1109         u32 fbc_ctl;
1110
1111         /* Disable compression */
1112         fbc_ctl = I915_READ(FBC_CONTROL);
1113         fbc_ctl &= ~FBC_CTL_EN;
1114         I915_WRITE(FBC_CONTROL, fbc_ctl);
1115
1116         /* Wait for compressing bit to clear */
1117         if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
1118                 DRM_DEBUG_KMS("FBC idle timed out\n");
1119                 return;
1120         }
1121
1122         DRM_DEBUG_KMS("disabled FBC\n");
1123 }
1124
1125 static bool i8xx_fbc_enabled(struct drm_device *dev)
1126 {
1127         struct drm_i915_private *dev_priv = dev->dev_private;
1128
1129         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1130 }
1131
1132 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1133 {
1134         struct drm_device *dev = crtc->dev;
1135         struct drm_i915_private *dev_priv = dev->dev_private;
1136         struct drm_framebuffer *fb = crtc->fb;
1137         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1138         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1139         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1140         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1141         unsigned long stall_watermark = 200;
1142         u32 dpfc_ctl;
1143
1144         dpfc_ctl = I915_READ(DPFC_CONTROL);
1145         if (dpfc_ctl & DPFC_CTL_EN) {
1146                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1147                     dev_priv->cfb_fence == obj_priv->fence_reg &&
1148                     dev_priv->cfb_plane == intel_crtc->plane &&
1149                     dev_priv->cfb_y == crtc->y)
1150                         return;
1151
1152                 I915_WRITE(DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1153                 POSTING_READ(DPFC_CONTROL);
1154                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1155         }
1156
1157         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1158         dev_priv->cfb_fence = obj_priv->fence_reg;
1159         dev_priv->cfb_plane = intel_crtc->plane;
1160         dev_priv->cfb_y = crtc->y;
1161
1162         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1163         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1164                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1165                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1166         } else {
1167                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1168         }
1169
1170         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1171                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1172                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1173         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1174
1175         /* enable it... */
1176         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1177
1178         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1179 }
1180
1181 void g4x_disable_fbc(struct drm_device *dev)
1182 {
1183         struct drm_i915_private *dev_priv = dev->dev_private;
1184         u32 dpfc_ctl;
1185
1186         /* Disable compression */
1187         dpfc_ctl = I915_READ(DPFC_CONTROL);
1188         if (dpfc_ctl & DPFC_CTL_EN) {
1189                 dpfc_ctl &= ~DPFC_CTL_EN;
1190                 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1191
1192                 DRM_DEBUG_KMS("disabled FBC\n");
1193         }
1194 }
1195
1196 static bool g4x_fbc_enabled(struct drm_device *dev)
1197 {
1198         struct drm_i915_private *dev_priv = dev->dev_private;
1199
1200         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1201 }
1202
1203 static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1204 {
1205         struct drm_device *dev = crtc->dev;
1206         struct drm_i915_private *dev_priv = dev->dev_private;
1207         struct drm_framebuffer *fb = crtc->fb;
1208         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1209         struct drm_i915_gem_object *obj_priv = to_intel_bo(intel_fb->obj);
1210         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1211         int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
1212         unsigned long stall_watermark = 200;
1213         u32 dpfc_ctl;
1214
1215         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1216         if (dpfc_ctl & DPFC_CTL_EN) {
1217                 if (dev_priv->cfb_pitch == dev_priv->cfb_pitch / 64 - 1 &&
1218                     dev_priv->cfb_fence == obj_priv->fence_reg &&
1219                     dev_priv->cfb_plane == intel_crtc->plane &&
1220                     dev_priv->cfb_offset == obj_priv->gtt_offset &&
1221                     dev_priv->cfb_y == crtc->y)
1222                         return;
1223
1224                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl & ~DPFC_CTL_EN);
1225                 POSTING_READ(ILK_DPFC_CONTROL);
1226                 intel_wait_for_vblank(dev, intel_crtc->pipe);
1227         }
1228
1229         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1230         dev_priv->cfb_fence = obj_priv->fence_reg;
1231         dev_priv->cfb_plane = intel_crtc->plane;
1232         dev_priv->cfb_offset = obj_priv->gtt_offset;
1233         dev_priv->cfb_y = crtc->y;
1234
1235         dpfc_ctl &= DPFC_RESERVED;
1236         dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
1237         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1238                 dpfc_ctl |= (DPFC_CTL_FENCE_EN | dev_priv->cfb_fence);
1239                 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
1240         } else {
1241                 I915_WRITE(ILK_DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1242         }
1243
1244         I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1245                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1246                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1247         I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
1248         I915_WRITE(ILK_FBC_RT_BASE, obj_priv->gtt_offset | ILK_FBC_RT_VALID);
1249         /* enable it... */
1250         I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
1251
1252         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1253 }
1254
1255 void ironlake_disable_fbc(struct drm_device *dev)
1256 {
1257         struct drm_i915_private *dev_priv = dev->dev_private;
1258         u32 dpfc_ctl;
1259
1260         /* Disable compression */
1261         dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
1262         if (dpfc_ctl & DPFC_CTL_EN) {
1263                 dpfc_ctl &= ~DPFC_CTL_EN;
1264                 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
1265
1266                 DRM_DEBUG_KMS("disabled FBC\n");
1267         }
1268 }
1269
1270 static bool ironlake_fbc_enabled(struct drm_device *dev)
1271 {
1272         struct drm_i915_private *dev_priv = dev->dev_private;
1273
1274         return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
1275 }
1276
1277 bool intel_fbc_enabled(struct drm_device *dev)
1278 {
1279         struct drm_i915_private *dev_priv = dev->dev_private;
1280
1281         if (!dev_priv->display.fbc_enabled)
1282                 return false;
1283
1284         return dev_priv->display.fbc_enabled(dev);
1285 }
1286
1287 void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1288 {
1289         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
1290
1291         if (!dev_priv->display.enable_fbc)
1292                 return;
1293
1294         dev_priv->display.enable_fbc(crtc, interval);
1295 }
1296
1297 void intel_disable_fbc(struct drm_device *dev)
1298 {
1299         struct drm_i915_private *dev_priv = dev->dev_private;
1300
1301         if (!dev_priv->display.disable_fbc)
1302                 return;
1303
1304         dev_priv->display.disable_fbc(dev);
1305 }
1306
1307 /**
1308  * intel_update_fbc - enable/disable FBC as needed
1309  * @dev: the drm_device
1310  *
1311  * Set up the framebuffer compression hardware at mode set time.  We
1312  * enable it if possible:
1313  *   - plane A only (on pre-965)
1314  *   - no pixel mulitply/line duplication
1315  *   - no alpha buffer discard
1316  *   - no dual wide
1317  *   - framebuffer <= 2048 in width, 1536 in height
1318  *
1319  * We can't assume that any compression will take place (worst case),
1320  * so the compressed buffer has to be the same size as the uncompressed
1321  * one.  It also must reside (along with the line length buffer) in
1322  * stolen memory.
1323  *
1324  * We need to enable/disable FBC on a global basis.
1325  */
1326 static void intel_update_fbc(struct drm_device *dev)
1327 {
1328         struct drm_i915_private *dev_priv = dev->dev_private;
1329         struct drm_crtc *crtc = NULL, *tmp_crtc;
1330         struct intel_crtc *intel_crtc;
1331         struct drm_framebuffer *fb;
1332         struct intel_framebuffer *intel_fb;
1333         struct drm_i915_gem_object *obj_priv;
1334
1335         DRM_DEBUG_KMS("\n");
1336
1337         if (!i915_powersave)
1338                 return;
1339
1340         if (!I915_HAS_FBC(dev))
1341                 return;
1342
1343         /*
1344          * If FBC is already on, we just have to verify that we can
1345          * keep it that way...
1346          * Need to disable if:
1347          *   - more than one pipe is active
1348          *   - changing FBC params (stride, fence, mode)
1349          *   - new fb is too large to fit in compressed buffer
1350          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1351          */
1352         list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
1353                 if (tmp_crtc->enabled) {
1354                         if (crtc) {
1355                                 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
1356                                 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
1357                                 goto out_disable;
1358                         }
1359                         crtc = tmp_crtc;
1360                 }
1361         }
1362
1363         if (!crtc || crtc->fb == NULL) {
1364                 DRM_DEBUG_KMS("no output, disabling\n");
1365                 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
1366                 goto out_disable;
1367         }
1368
1369         intel_crtc = to_intel_crtc(crtc);
1370         fb = crtc->fb;
1371         intel_fb = to_intel_framebuffer(fb);
1372         obj_priv = to_intel_bo(intel_fb->obj);
1373
1374         if (intel_fb->obj->size > dev_priv->cfb_size) {
1375                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1376                               "compression\n");
1377                 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
1378                 goto out_disable;
1379         }
1380         if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
1381             (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
1382                 DRM_DEBUG_KMS("mode incompatible with compression, "
1383                               "disabling\n");
1384                 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
1385                 goto out_disable;
1386         }
1387         if ((crtc->mode.hdisplay > 2048) ||
1388             (crtc->mode.vdisplay > 1536)) {
1389                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1390                 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
1391                 goto out_disable;
1392         }
1393         if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
1394                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1395                 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
1396                 goto out_disable;
1397         }
1398         if (obj_priv->tiling_mode != I915_TILING_X) {
1399                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1400                 dev_priv->no_fbc_reason = FBC_NOT_TILED;
1401                 goto out_disable;
1402         }
1403
1404         /* If the kernel debugger is active, always disable compression */
1405         if (in_dbg_master())
1406                 goto out_disable;
1407
1408         intel_enable_fbc(crtc, 500);
1409         return;
1410
1411 out_disable:
1412         /* Multiple disables should be harmless */
1413         if (intel_fbc_enabled(dev)) {
1414                 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1415                 intel_disable_fbc(dev);
1416         }
1417 }
1418
1419 int
1420 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1421 {
1422         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
1423         u32 alignment;
1424         int ret;
1425
1426         switch (obj_priv->tiling_mode) {
1427         case I915_TILING_NONE:
1428                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1429                         alignment = 128 * 1024;
1430                 else if (IS_I965G(dev))
1431                         alignment = 4 * 1024;
1432                 else
1433                         alignment = 64 * 1024;
1434                 break;
1435         case I915_TILING_X:
1436                 /* pin() will align the object as required by fence */
1437                 alignment = 0;
1438                 break;
1439         case I915_TILING_Y:
1440                 /* FIXME: Is this true? */
1441                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1442                 return -EINVAL;
1443         default:
1444                 BUG();
1445         }
1446
1447         ret = i915_gem_object_pin(obj, alignment);
1448         if (ret != 0)
1449                 return ret;
1450
1451         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1452          * fence, whereas 965+ only requires a fence if using
1453          * framebuffer compression.  For simplicity, we always install
1454          * a fence as the cost is not that onerous.
1455          */
1456         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1457             obj_priv->tiling_mode != I915_TILING_NONE) {
1458                 ret = i915_gem_object_get_fence_reg(obj);
1459                 if (ret != 0) {
1460                         i915_gem_object_unpin(obj);
1461                         return ret;
1462                 }
1463         }
1464
1465         return 0;
1466 }
1467
1468 /* Assume fb object is pinned & idle & fenced and just update base pointers */
1469 static int
1470 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1471                            int x, int y)
1472 {
1473         struct drm_device *dev = crtc->dev;
1474         struct drm_i915_private *dev_priv = dev->dev_private;
1475         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1476         struct intel_framebuffer *intel_fb;
1477         struct drm_i915_gem_object *obj_priv;
1478         struct drm_gem_object *obj;
1479         int plane = intel_crtc->plane;
1480         unsigned long Start, Offset;
1481         u32 dspcntr;
1482         u32 reg;
1483
1484         switch (plane) {
1485         case 0:
1486         case 1:
1487                 break;
1488         default:
1489                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1490                 return -EINVAL;
1491         }
1492
1493         intel_fb = to_intel_framebuffer(fb);
1494         obj = intel_fb->obj;
1495         obj_priv = to_intel_bo(obj);
1496
1497         reg = DSPCNTR(plane);
1498         dspcntr = I915_READ(reg);
1499         /* Mask out pixel format bits in case we change it */
1500         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1501         switch (fb->bits_per_pixel) {
1502         case 8:
1503                 dspcntr |= DISPPLANE_8BPP;
1504                 break;
1505         case 16:
1506                 if (fb->depth == 15)
1507                         dspcntr |= DISPPLANE_15_16BPP;
1508                 else
1509                         dspcntr |= DISPPLANE_16BPP;
1510                 break;
1511         case 24:
1512         case 32:
1513                 dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1514                 break;
1515         default:
1516                 DRM_ERROR("Unknown color depth\n");
1517                 return -EINVAL;
1518         }
1519         if (IS_I965G(dev)) {
1520                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1521                         dspcntr |= DISPPLANE_TILED;
1522                 else
1523                         dspcntr &= ~DISPPLANE_TILED;
1524         }
1525
1526         if (HAS_PCH_SPLIT(dev))
1527                 /* must disable */
1528                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1529
1530         I915_WRITE(reg, dspcntr);
1531
1532         Start = obj_priv->gtt_offset;
1533         Offset = y * fb->pitch + x * (fb->bits_per_pixel / 8);
1534
1535         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d %d\n",
1536                       Start, Offset, x, y, fb->pitch);
1537         I915_WRITE(DSPSTRIDE(plane), fb->pitch);
1538         if (IS_I965G(dev)) {
1539                 I915_WRITE(DSPSURF(plane), Start);
1540                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
1541                 I915_WRITE(DSPADDR(plane), Offset);
1542         } else
1543                 I915_WRITE(DSPADDR(plane), Start + Offset);
1544         POSTING_READ(reg);
1545
1546         intel_update_fbc(dev);
1547         intel_increase_pllclock(crtc);
1548
1549         return 0;
1550 }
1551
1552 static int
1553 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1554                     struct drm_framebuffer *old_fb)
1555 {
1556         struct drm_device *dev = crtc->dev;
1557         struct drm_i915_master_private *master_priv;
1558         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1559         struct intel_framebuffer *intel_fb;
1560         struct drm_i915_gem_object *obj_priv;
1561         struct drm_gem_object *obj;
1562         int pipe = intel_crtc->pipe;
1563         int plane = intel_crtc->plane;
1564         int ret;
1565
1566         /* no fb bound */
1567         if (!crtc->fb) {
1568                 DRM_DEBUG_KMS("No FB bound\n");
1569                 return 0;
1570         }
1571
1572         switch (plane) {
1573         case 0:
1574         case 1:
1575                 break;
1576         default:
1577                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1578                 return -EINVAL;
1579         }
1580
1581         intel_fb = to_intel_framebuffer(crtc->fb);
1582         obj = intel_fb->obj;
1583         obj_priv = to_intel_bo(obj);
1584
1585         mutex_lock(&dev->struct_mutex);
1586         ret = intel_pin_and_fence_fb_obj(dev, obj);
1587         if (ret != 0) {
1588                 mutex_unlock(&dev->struct_mutex);
1589                 return ret;
1590         }
1591
1592         ret = i915_gem_object_set_to_display_plane(obj);
1593         if (ret != 0) {
1594                 i915_gem_object_unpin(obj);
1595                 mutex_unlock(&dev->struct_mutex);
1596                 return ret;
1597         }
1598
1599         ret = intel_pipe_set_base_atomic(crtc, crtc->fb, x, y);
1600         if (ret) {
1601                 i915_gem_object_unpin(obj);
1602                 mutex_unlock(&dev->struct_mutex);
1603                 return ret;
1604         }
1605
1606         if (old_fb) {
1607                 intel_fb = to_intel_framebuffer(old_fb);
1608                 obj_priv = to_intel_bo(intel_fb->obj);
1609                 i915_gem_object_unpin(intel_fb->obj);
1610         }
1611
1612         mutex_unlock(&dev->struct_mutex);
1613
1614         if (!dev->primary->master)
1615                 return 0;
1616
1617         master_priv = dev->primary->master->driver_priv;
1618         if (!master_priv->sarea_priv)
1619                 return 0;
1620
1621         if (pipe) {
1622                 master_priv->sarea_priv->pipeB_x = x;
1623                 master_priv->sarea_priv->pipeB_y = y;
1624         } else {
1625                 master_priv->sarea_priv->pipeA_x = x;
1626                 master_priv->sarea_priv->pipeA_y = y;
1627         }
1628
1629         return 0;
1630 }
1631
1632 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
1633 {
1634         struct drm_device *dev = crtc->dev;
1635         struct drm_i915_private *dev_priv = dev->dev_private;
1636         u32 dpa_ctl;
1637
1638         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1639         dpa_ctl = I915_READ(DP_A);
1640         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1641
1642         if (clock < 200000) {
1643                 u32 temp;
1644                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1645                 /* workaround for 160Mhz:
1646                    1) program 0x4600c bits 15:0 = 0x8124
1647                    2) program 0x46010 bit 0 = 1
1648                    3) program 0x46034 bit 24 = 1
1649                    4) program 0x64000 bit 14 = 1
1650                    */
1651                 temp = I915_READ(0x4600c);
1652                 temp &= 0xffff0000;
1653                 I915_WRITE(0x4600c, temp | 0x8124);
1654
1655                 temp = I915_READ(0x46010);
1656                 I915_WRITE(0x46010, temp | 1);
1657
1658                 temp = I915_READ(0x46034);
1659                 I915_WRITE(0x46034, temp | (1 << 24));
1660         } else {
1661                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1662         }
1663         I915_WRITE(DP_A, dpa_ctl);
1664
1665         POSTING_READ(DP_A);
1666         udelay(500);
1667 }
1668
1669 /* The FDI link training functions for ILK/Ibexpeak. */
1670 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
1671 {
1672         struct drm_device *dev = crtc->dev;
1673         struct drm_i915_private *dev_priv = dev->dev_private;
1674         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1675         int pipe = intel_crtc->pipe;
1676         u32 reg, temp, tries;
1677
1678         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1679            for train result */
1680         reg = FDI_RX_IMR(pipe);
1681         temp = I915_READ(reg);
1682         temp &= ~FDI_RX_SYMBOL_LOCK;
1683         temp &= ~FDI_RX_BIT_LOCK;
1684         I915_WRITE(reg, temp);
1685         I915_READ(reg);
1686         udelay(150);
1687
1688         /* enable CPU FDI TX and PCH FDI RX */
1689         reg = FDI_TX_CTL(pipe);
1690         temp = I915_READ(reg);
1691         temp &= ~(7 << 19);
1692         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1693         temp &= ~FDI_LINK_TRAIN_NONE;
1694         temp |= FDI_LINK_TRAIN_PATTERN_1;
1695         I915_WRITE(reg, temp | FDI_TX_ENABLE);
1696
1697         reg = FDI_RX_CTL(pipe);
1698         temp = I915_READ(reg);
1699         temp &= ~FDI_LINK_TRAIN_NONE;
1700         temp |= FDI_LINK_TRAIN_PATTERN_1;
1701         I915_WRITE(reg, temp | FDI_RX_ENABLE);
1702
1703         POSTING_READ(reg);
1704         udelay(150);
1705
1706         reg = FDI_RX_IIR(pipe);
1707         for (tries = 0; tries < 5; tries++) {
1708                 temp = I915_READ(reg);
1709                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1710
1711                 if ((temp & FDI_RX_BIT_LOCK)) {
1712                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1713                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1714                         break;
1715                 }
1716         }
1717         if (tries == 5)
1718                 DRM_ERROR("FDI train 1 fail!\n");
1719
1720         /* Train 2 */
1721         reg = FDI_TX_CTL(pipe);
1722         temp = I915_READ(reg);
1723         temp &= ~FDI_LINK_TRAIN_NONE;
1724         temp |= FDI_LINK_TRAIN_PATTERN_2;
1725         I915_WRITE(reg, temp);
1726
1727         reg = FDI_RX_CTL(pipe);
1728         temp = I915_READ(reg);
1729         temp &= ~FDI_LINK_TRAIN_NONE;
1730         temp |= FDI_LINK_TRAIN_PATTERN_2;
1731         I915_WRITE(reg, temp);
1732
1733         POSTING_READ(reg);
1734         udelay(150);
1735
1736         reg = FDI_RX_IIR(pipe);
1737         for (tries = 0; tries < 5; tries++) {
1738                 temp = I915_READ(reg);
1739                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1740
1741                 if (temp & FDI_RX_SYMBOL_LOCK) {
1742                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1743                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1744                         break;
1745                 }
1746         }
1747         if (tries == 5)
1748                 DRM_ERROR("FDI train 2 fail!\n");
1749
1750         DRM_DEBUG_KMS("FDI train done\n");
1751 }
1752
1753 static const int const snb_b_fdi_train_param [] = {
1754         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
1755         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
1756         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
1757         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
1758 };
1759
1760 /* The FDI link training functions for SNB/Cougarpoint. */
1761 static void gen6_fdi_link_train(struct drm_crtc *crtc)
1762 {
1763         struct drm_device *dev = crtc->dev;
1764         struct drm_i915_private *dev_priv = dev->dev_private;
1765         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1766         int pipe = intel_crtc->pipe;
1767         u32 reg, temp, i;
1768
1769         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
1770            for train result */
1771         reg = FDI_RX_IMR(pipe);
1772         temp = I915_READ(reg);
1773         temp &= ~FDI_RX_SYMBOL_LOCK;
1774         temp &= ~FDI_RX_BIT_LOCK;
1775         I915_WRITE(reg, temp);
1776
1777         POSTING_READ(reg);
1778         udelay(150);
1779
1780         /* enable CPU FDI TX and PCH FDI RX */
1781         reg = FDI_TX_CTL(pipe);
1782         temp = I915_READ(reg);
1783         temp &= ~(7 << 19);
1784         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1785         temp &= ~FDI_LINK_TRAIN_NONE;
1786         temp |= FDI_LINK_TRAIN_PATTERN_1;
1787         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1788         /* SNB-B */
1789         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1790         I915_WRITE(reg, temp | FDI_TX_ENABLE);
1791
1792         reg = FDI_RX_CTL(pipe);
1793         temp = I915_READ(reg);
1794         if (HAS_PCH_CPT(dev)) {
1795                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1796                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
1797         } else {
1798                 temp &= ~FDI_LINK_TRAIN_NONE;
1799                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1800         }
1801         I915_WRITE(reg, temp | FDI_RX_ENABLE);
1802
1803         POSTING_READ(reg);
1804         udelay(150);
1805
1806         for (i = 0; i < 4; i++ ) {
1807                 reg = FDI_TX_CTL(pipe);
1808                 temp = I915_READ(reg);
1809                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1810                 temp |= snb_b_fdi_train_param[i];
1811                 I915_WRITE(reg, temp);
1812
1813                 POSTING_READ(reg);
1814                 udelay(500);
1815
1816                 reg = FDI_RX_IIR(pipe);
1817                 temp = I915_READ(reg);
1818                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1819
1820                 if (temp & FDI_RX_BIT_LOCK) {
1821                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
1822                         DRM_DEBUG_KMS("FDI train 1 done.\n");
1823                         break;
1824                 }
1825         }
1826         if (i == 4)
1827                 DRM_ERROR("FDI train 1 fail!\n");
1828
1829         /* Train 2 */
1830         reg = FDI_TX_CTL(pipe);
1831         temp = I915_READ(reg);
1832         temp &= ~FDI_LINK_TRAIN_NONE;
1833         temp |= FDI_LINK_TRAIN_PATTERN_2;
1834         if (IS_GEN6(dev)) {
1835                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1836                 /* SNB-B */
1837                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
1838         }
1839         I915_WRITE(reg, temp);
1840
1841         reg = FDI_RX_CTL(pipe);
1842         temp = I915_READ(reg);
1843         if (HAS_PCH_CPT(dev)) {
1844                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
1845                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
1846         } else {
1847                 temp &= ~FDI_LINK_TRAIN_NONE;
1848                 temp |= FDI_LINK_TRAIN_PATTERN_2;
1849         }
1850         I915_WRITE(reg, temp);
1851
1852         POSTING_READ(reg);
1853         udelay(150);
1854
1855         for (i = 0; i < 4; i++ ) {
1856                 reg = FDI_TX_CTL(pipe);
1857                 temp = I915_READ(reg);
1858                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
1859                 temp |= snb_b_fdi_train_param[i];
1860                 I915_WRITE(reg, temp);
1861
1862                 POSTING_READ(reg);
1863                 udelay(500);
1864
1865                 reg = FDI_RX_IIR(pipe);
1866                 temp = I915_READ(reg);
1867                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1868
1869                 if (temp & FDI_RX_SYMBOL_LOCK) {
1870                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
1871                         DRM_DEBUG_KMS("FDI train 2 done.\n");
1872                         break;
1873                 }
1874         }
1875         if (i == 4)
1876                 DRM_ERROR("FDI train 2 fail!\n");
1877
1878         DRM_DEBUG_KMS("FDI train done.\n");
1879 }
1880
1881 static void ironlake_fdi_enable(struct drm_crtc *crtc)
1882 {
1883         struct drm_device *dev = crtc->dev;
1884         struct drm_i915_private *dev_priv = dev->dev_private;
1885         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1886         int pipe = intel_crtc->pipe;
1887         u32 reg, temp;
1888
1889         /* Write the TU size bits so error detection works */
1890         I915_WRITE(FDI_RX_TUSIZE1(pipe),
1891                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
1892
1893         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1894         reg = FDI_RX_CTL(pipe);
1895         temp = I915_READ(reg);
1896         temp &= ~((0x7 << 19) | (0x7 << 16));
1897         temp |= (intel_crtc->fdi_lanes - 1) << 19;
1898         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
1899         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
1900
1901         POSTING_READ(reg);
1902         udelay(200);
1903
1904         /* Switch from Rawclk to PCDclk */
1905         temp = I915_READ(reg);
1906         I915_WRITE(reg, temp | FDI_PCDCLK);
1907
1908         POSTING_READ(reg);
1909         udelay(200);
1910
1911         /* Enable CPU FDI TX PLL, always on for Ironlake */
1912         reg = FDI_TX_CTL(pipe);
1913         temp = I915_READ(reg);
1914         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1915                 I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
1916
1917                 POSTING_READ(reg);
1918                 udelay(100);
1919         }
1920 }
1921
1922 static void intel_flush_display_plane(struct drm_device *dev,
1923                                       int plane)
1924 {
1925         struct drm_i915_private *dev_priv = dev->dev_private;
1926         u32 reg = DSPADDR(plane);
1927         I915_WRITE(reg, I915_READ(reg));
1928 }
1929
1930 static void ironlake_crtc_enable(struct drm_crtc *crtc)
1931 {
1932         struct drm_device *dev = crtc->dev;
1933         struct drm_i915_private *dev_priv = dev->dev_private;
1934         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1935         int pipe = intel_crtc->pipe;
1936         int plane = intel_crtc->plane;
1937         u32 reg, temp;
1938
1939         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1940                 temp = I915_READ(PCH_LVDS);
1941                 if ((temp & LVDS_PORT_EN) == 0)
1942                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1943         }
1944
1945         ironlake_fdi_enable(crtc);
1946
1947         /* Enable panel fitting for LVDS */
1948         if (dev_priv->pch_pf_size &&
1949             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)
1950              || HAS_eDP || intel_pch_has_edp(crtc))) {
1951                 /* Force use of hard-coded filter coefficients
1952                  * as some pre-programmed values are broken,
1953                  * e.g. x201.
1954                  */
1955                 I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1,
1956                            PF_ENABLE | PF_FILTER_MED_3x3);
1957                 I915_WRITE(pipe ? PFB_WIN_POS : PFA_WIN_POS,
1958                            dev_priv->pch_pf_pos);
1959                 I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ,
1960                            dev_priv->pch_pf_size);
1961         }
1962
1963         /* Enable CPU pipe */
1964         reg = PIPECONF(pipe);
1965         temp = I915_READ(reg);
1966         if ((temp & PIPECONF_ENABLE) == 0) {
1967                 I915_WRITE(reg, temp | PIPECONF_ENABLE);
1968                 POSTING_READ(reg);
1969                 udelay(100);
1970         }
1971
1972         /* configure and enable CPU plane */
1973         reg = DSPCNTR(plane);
1974         temp = I915_READ(reg);
1975         if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1976                 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
1977                 intel_flush_display_plane(dev, plane);
1978         }
1979
1980         /* For PCH output, training FDI link */
1981         if (IS_GEN6(dev))
1982                 gen6_fdi_link_train(crtc);
1983         else
1984                 ironlake_fdi_link_train(crtc);
1985
1986         /* enable PCH DPLL */
1987         reg = PCH_DPLL(pipe);
1988         temp = I915_READ(reg);
1989         if ((temp & DPLL_VCO_ENABLE) == 0) {
1990                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
1991                 POSTING_READ(reg);
1992                 udelay(200);
1993         }
1994
1995         if (HAS_PCH_CPT(dev)) {
1996                 /* Be sure PCH DPLL SEL is set */
1997                 temp = I915_READ(PCH_DPLL_SEL);
1998                 if (pipe == 0 && (temp & TRANSA_DPLL_ENABLE) == 0)
1999                         temp |= (TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL);
2000                 else if (pipe == 1 && (temp & TRANSB_DPLL_ENABLE) == 0)
2001                         temp |= (TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2002                 I915_WRITE(PCH_DPLL_SEL, temp);
2003         }
2004
2005         /* set transcoder timing */
2006         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
2007         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
2008         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
2009
2010         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
2011         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
2012         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
2013
2014         /* enable normal train */
2015         reg = FDI_TX_CTL(pipe);
2016         temp = I915_READ(reg);
2017         temp &= ~FDI_LINK_TRAIN_NONE;
2018         temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2019         I915_WRITE(reg, temp);
2020
2021         reg = FDI_RX_CTL(pipe);
2022         temp = I915_READ(reg);
2023         if (HAS_PCH_CPT(dev)) {
2024                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2025                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2026         } else {
2027                 temp &= ~FDI_LINK_TRAIN_NONE;
2028                 temp |= FDI_LINK_TRAIN_NONE;
2029         }
2030         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2031
2032         /* wait one idle pattern time */
2033         POSTING_READ(reg);
2034         udelay(100);
2035
2036         /* For PCH DP, enable TRANS_DP_CTL */
2037         if (HAS_PCH_CPT(dev) &&
2038             intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
2039                 reg = TRANS_DP_CTL(pipe);
2040                 temp = I915_READ(reg);
2041                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
2042                           TRANS_DP_SYNC_MASK);
2043                 temp |= (TRANS_DP_OUTPUT_ENABLE |
2044                          TRANS_DP_ENH_FRAMING);
2045
2046                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
2047                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
2048                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
2049                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
2050
2051                 switch (intel_trans_dp_port_sel(crtc)) {
2052                 case PCH_DP_B:
2053                         temp |= TRANS_DP_PORT_SEL_B;
2054                         break;
2055                 case PCH_DP_C:
2056                         temp |= TRANS_DP_PORT_SEL_C;
2057                         break;
2058                 case PCH_DP_D:
2059                         temp |= TRANS_DP_PORT_SEL_D;
2060                         break;
2061                 default:
2062                         DRM_DEBUG_KMS("Wrong PCH DP port return. Guess port B\n");
2063                         temp |= TRANS_DP_PORT_SEL_B;
2064                         break;
2065                 }
2066
2067                 I915_WRITE(reg, temp);
2068         }
2069
2070         /* enable PCH transcoder */
2071         reg = TRANSCONF(pipe);
2072         temp = I915_READ(reg);
2073         /*
2074          * make the BPC in transcoder be consistent with
2075          * that in pipeconf reg.
2076          */
2077         temp &= ~PIPE_BPC_MASK;
2078         temp |= I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK;
2079         I915_WRITE(reg, temp | TRANS_ENABLE);
2080         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
2081                 DRM_ERROR("failed to enable transcoder\n");
2082
2083         intel_crtc_load_lut(crtc);
2084         intel_update_fbc(dev);
2085 }
2086
2087 static void ironlake_crtc_disable(struct drm_crtc *crtc)
2088 {
2089         struct drm_device *dev = crtc->dev;
2090         struct drm_i915_private *dev_priv = dev->dev_private;
2091         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2092         int pipe = intel_crtc->pipe;
2093         int plane = intel_crtc->plane;
2094         u32 reg, temp;
2095
2096         drm_vblank_off(dev, pipe);
2097
2098         /* Disable display plane */
2099         reg = DSPCNTR(plane);
2100         temp = I915_READ(reg);
2101         if (temp & DISPLAY_PLANE_ENABLE) {
2102                 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2103                 intel_flush_display_plane(dev, plane);
2104         }
2105
2106         if (dev_priv->cfb_plane == plane &&
2107             dev_priv->display.disable_fbc)
2108                 dev_priv->display.disable_fbc(dev);
2109
2110         /* disable cpu pipe, disable after all planes disabled */
2111         reg = PIPECONF(pipe);
2112         temp = I915_READ(reg);
2113         if (temp & PIPECONF_ENABLE) {
2114                 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2115                 /* wait for cpu pipe off, pipe state */
2116                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, 50))
2117                         DRM_ERROR("failed to turn off cpu pipe\n");
2118         }
2119
2120         /* Disable PF */
2121         I915_WRITE(pipe ? PFB_CTL_1 : PFA_CTL_1, 0);
2122         I915_WRITE(pipe ? PFB_WIN_SZ : PFA_WIN_SZ, 0);
2123
2124         /* disable CPU FDI tx and PCH FDI rx */
2125         reg = FDI_TX_CTL(pipe);
2126         temp = I915_READ(reg);
2127         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2128         POSTING_READ(reg);
2129
2130         reg = FDI_RX_CTL(pipe);
2131         temp = I915_READ(reg);
2132         temp &= ~(0x7 << 16);
2133         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2134         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2135
2136         POSTING_READ(reg);
2137         udelay(100);
2138
2139         /* still set train pattern 1 */
2140         reg = FDI_TX_CTL(pipe);
2141         temp = I915_READ(reg);
2142         temp &= ~FDI_LINK_TRAIN_NONE;
2143         temp |= FDI_LINK_TRAIN_PATTERN_1;
2144         I915_WRITE(reg, temp);
2145
2146         reg = FDI_RX_CTL(pipe);
2147         temp = I915_READ(reg);
2148         if (HAS_PCH_CPT(dev)) {
2149                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2150                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2151         } else {
2152                 temp &= ~FDI_LINK_TRAIN_NONE;
2153                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2154         }
2155         /* BPC in FDI rx is consistent with that in PIPECONF */
2156         temp &= ~(0x07 << 16);
2157         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2158         I915_WRITE(reg, temp);
2159
2160         POSTING_READ(reg);
2161         udelay(100);
2162
2163         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
2164                 temp = I915_READ(PCH_LVDS);
2165                 if (temp & LVDS_PORT_EN) {
2166                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
2167                         POSTING_READ(PCH_LVDS);
2168                         udelay(100);
2169                 }
2170         }
2171
2172         /* disable PCH transcoder */
2173         reg = TRANSCONF(plane);
2174         temp = I915_READ(reg);
2175         if (temp & TRANS_ENABLE) {
2176                 I915_WRITE(reg, temp & ~TRANS_ENABLE);
2177                 /* wait for PCH transcoder off, transcoder state */
2178                 if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
2179                         DRM_ERROR("failed to disable transcoder\n");
2180         }
2181
2182         if (HAS_PCH_CPT(dev)) {
2183                 /* disable TRANS_DP_CTL */
2184                 reg = TRANS_DP_CTL(pipe);
2185                 temp = I915_READ(reg);
2186                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
2187                 I915_WRITE(reg, temp);
2188
2189                 /* disable DPLL_SEL */
2190                 temp = I915_READ(PCH_DPLL_SEL);
2191                 if (pipe == 0)
2192                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
2193                 else
2194                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
2195                 I915_WRITE(PCH_DPLL_SEL, temp);
2196         }
2197
2198         /* disable PCH DPLL */
2199         reg = PCH_DPLL(pipe);
2200         temp = I915_READ(reg);
2201         I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2202
2203         /* Switch from PCDclk to Rawclk */
2204         reg = FDI_RX_CTL(pipe);
2205         temp = I915_READ(reg);
2206         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2207
2208         /* Disable CPU FDI TX PLL */
2209         reg = FDI_TX_CTL(pipe);
2210         temp = I915_READ(reg);
2211         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2212
2213         POSTING_READ(reg);
2214         udelay(100);
2215
2216         reg = FDI_RX_CTL(pipe);
2217         temp = I915_READ(reg);
2218         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2219
2220         /* Wait for the clocks to turn off. */
2221         POSTING_READ(reg);
2222         udelay(100);
2223 }
2224
2225 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
2226 {
2227         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2228         int pipe = intel_crtc->pipe;
2229         int plane = intel_crtc->plane;
2230
2231         /* XXX: When our outputs are all unaware of DPMS modes other than off
2232          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2233          */
2234         switch (mode) {
2235         case DRM_MODE_DPMS_ON:
2236         case DRM_MODE_DPMS_STANDBY:
2237         case DRM_MODE_DPMS_SUSPEND:
2238                 DRM_DEBUG_KMS("crtc %d/%d dpms on\n", pipe, plane);
2239                 ironlake_crtc_enable(crtc);
2240                 break;
2241
2242         case DRM_MODE_DPMS_OFF:
2243                 DRM_DEBUG_KMS("crtc %d/%d dpms off\n", pipe, plane);
2244                 ironlake_crtc_disable(crtc);
2245                 break;
2246         }
2247 }
2248
2249 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
2250 {
2251         if (!enable && intel_crtc->overlay) {
2252                 struct drm_device *dev = intel_crtc->base.dev;
2253
2254                 mutex_lock(&dev->struct_mutex);
2255                 (void) intel_overlay_switch_off(intel_crtc->overlay, false);
2256                 mutex_unlock(&dev->struct_mutex);
2257         }
2258
2259         /* Let userspace switch the overlay on again. In most cases userspace
2260          * has to recompute where to put it anyway.
2261          */
2262 }
2263
2264 static void i9xx_crtc_enable(struct drm_crtc *crtc)
2265 {
2266         struct drm_device *dev = crtc->dev;
2267         struct drm_i915_private *dev_priv = dev->dev_private;
2268         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2269         int pipe = intel_crtc->pipe;
2270         int plane = intel_crtc->plane;
2271         u32 reg, temp;
2272
2273         /* Enable the DPLL */
2274         reg = DPLL(pipe);
2275         temp = I915_READ(reg);
2276         if ((temp & DPLL_VCO_ENABLE) == 0) {
2277                 I915_WRITE(reg, temp);
2278
2279                 /* Wait for the clocks to stabilize. */
2280                 POSTING_READ(reg);
2281                 udelay(150);
2282
2283                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2284
2285                 /* Wait for the clocks to stabilize. */
2286                 POSTING_READ(reg);
2287                 udelay(150);
2288
2289                 I915_WRITE(reg, temp | DPLL_VCO_ENABLE);
2290
2291                 /* Wait for the clocks to stabilize. */
2292                 POSTING_READ(reg);
2293                 udelay(150);
2294         }
2295
2296         /* Enable the pipe */
2297         reg = PIPECONF(pipe);
2298         temp = I915_READ(reg);
2299         if ((temp & PIPECONF_ENABLE) == 0)
2300                 I915_WRITE(reg, temp | PIPECONF_ENABLE);
2301
2302         /* Enable the plane */
2303         reg = DSPCNTR(plane);
2304         temp = I915_READ(reg);
2305         if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
2306                 I915_WRITE(reg, temp | DISPLAY_PLANE_ENABLE);
2307                 intel_flush_display_plane(dev, plane);
2308         }
2309
2310         intel_crtc_load_lut(crtc);
2311         intel_update_fbc(dev);
2312
2313         /* Give the overlay scaler a chance to enable if it's on this pipe */
2314         intel_crtc_dpms_overlay(intel_crtc, true);
2315 }
2316
2317 static void i9xx_crtc_disable(struct drm_crtc *crtc)
2318 {
2319         struct drm_device *dev = crtc->dev;
2320         struct drm_i915_private *dev_priv = dev->dev_private;
2321         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2322         int pipe = intel_crtc->pipe;
2323         int plane = intel_crtc->plane;
2324         u32 reg, temp;
2325
2326         /* Give the overlay scaler a chance to disable if it's on this pipe */
2327         intel_crtc_dpms_overlay(intel_crtc, false);
2328         drm_vblank_off(dev, pipe);
2329
2330         if (dev_priv->cfb_plane == plane &&
2331             dev_priv->display.disable_fbc)
2332                 dev_priv->display.disable_fbc(dev);
2333
2334         /* Disable display plane */
2335         reg = DSPCNTR(plane);
2336         temp = I915_READ(reg);
2337         if (temp & DISPLAY_PLANE_ENABLE) {
2338                 I915_WRITE(reg, temp & ~DISPLAY_PLANE_ENABLE);
2339                 /* Flush the plane changes */
2340                 intel_flush_display_plane(dev, plane);
2341
2342                 /* Wait for vblank for the disable to take effect */
2343                 if (!IS_I9XX(dev))
2344                         intel_wait_for_vblank_off(dev, pipe);
2345         }
2346
2347         /* Don't disable pipe A or pipe A PLLs if needed */
2348         if (pipe == 0 && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
2349                 return;
2350
2351         /* Next, disable display pipes */
2352         reg = PIPECONF(pipe);
2353         temp = I915_READ(reg);
2354         if (temp & PIPECONF_ENABLE) {
2355                 I915_WRITE(reg, temp & ~PIPECONF_ENABLE);
2356
2357                 /* Wait for vblank for the disable to take effect. */
2358                 POSTING_READ(reg);
2359                 intel_wait_for_vblank_off(dev, pipe);
2360         }
2361
2362         reg = DPLL(pipe);
2363         temp = I915_READ(reg);
2364         if (temp & DPLL_VCO_ENABLE) {
2365                 I915_WRITE(reg, temp & ~DPLL_VCO_ENABLE);
2366
2367                 /* Wait for the clocks to turn off. */
2368                 POSTING_READ(reg);
2369                 udelay(150);
2370         }
2371 }
2372
2373 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
2374 {
2375         /* XXX: When our outputs are all unaware of DPMS modes other than off
2376          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
2377          */
2378         switch (mode) {
2379         case DRM_MODE_DPMS_ON:
2380         case DRM_MODE_DPMS_STANDBY:
2381         case DRM_MODE_DPMS_SUSPEND:
2382                 i9xx_crtc_enable(crtc);
2383                 break;
2384         case DRM_MODE_DPMS_OFF:
2385                 i9xx_crtc_disable(crtc);
2386                 break;
2387         }
2388 }
2389
2390 /*
2391  * When we disable a pipe, we need to clear any pending scanline wait events
2392  * to avoid hanging the ring, which we assume we are waiting on.
2393  */
2394 static void intel_clear_scanline_wait(struct drm_device *dev)
2395 {
2396         struct drm_i915_private *dev_priv = dev->dev_private;
2397         u32 tmp;
2398
2399         if (IS_GEN2(dev))
2400                 /* Can't break the hang on i8xx */
2401                 return;
2402
2403         tmp = I915_READ(PRB0_CTL);
2404         if (tmp & RING_WAIT) {
2405                 I915_WRITE(PRB0_CTL, tmp);
2406                 POSTING_READ(PRB0_CTL);
2407         }
2408 }
2409
2410 /**
2411  * Sets the power management mode of the pipe and plane.
2412  */
2413 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2414 {
2415         struct drm_device *dev = crtc->dev;
2416         struct drm_i915_private *dev_priv = dev->dev_private;
2417         struct drm_i915_master_private *master_priv;
2418         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2419         int pipe = intel_crtc->pipe;
2420         bool enabled;
2421
2422         if (intel_crtc->dpms_mode == mode)
2423                 return;
2424
2425         intel_crtc->dpms_mode = mode;
2426         intel_crtc->cursor_on = mode == DRM_MODE_DPMS_ON;
2427
2428         /* When switching on the display, ensure that SR is disabled
2429          * with multiple pipes prior to enabling to new pipe.
2430          *
2431          * When switching off the display, make sure the cursor is
2432          * properly hidden and there are no pending waits prior to
2433          * disabling the pipe.
2434          */
2435         if (mode == DRM_MODE_DPMS_ON)
2436                 intel_update_watermarks(dev);
2437         else
2438                 intel_crtc_update_cursor(crtc);
2439
2440         dev_priv->display.dpms(crtc, mode);
2441
2442         if (mode == DRM_MODE_DPMS_ON) {
2443                 intel_crtc_update_cursor(crtc);
2444         } else {
2445                 /* XXX Note that this is not a complete solution, but a hack
2446                  * to avoid the most frequently hit hang.
2447                  */
2448                 intel_clear_scanline_wait(dev);
2449
2450                 intel_update_watermarks(dev);
2451         }
2452         intel_update_fbc(dev);
2453
2454         if (!dev->primary->master)
2455                 return;
2456
2457         master_priv = dev->primary->master->driver_priv;
2458         if (!master_priv->sarea_priv)
2459                 return;
2460
2461         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2462
2463         switch (pipe) {
2464         case 0:
2465                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2466                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2467                 break;
2468         case 1:
2469                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2470                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2471                 break;
2472         default:
2473                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2474                 break;
2475         }
2476 }
2477
2478 /* Prepare for a mode set.
2479  *
2480  * Note we could be a lot smarter here.  We need to figure out which outputs
2481  * will be enabled, which disabled (in short, how the config will changes)
2482  * and perform the minimum necessary steps to accomplish that, e.g. updating
2483  * watermarks, FBC configuration, making sure PLLs are programmed correctly,
2484  * panel fitting is in the proper state, etc.
2485  */
2486 static void i9xx_crtc_prepare(struct drm_crtc *crtc)
2487 {
2488         struct drm_device *dev = crtc->dev;
2489         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2490
2491         intel_crtc->cursor_on = false;
2492         intel_crtc_update_cursor(crtc);
2493
2494         i9xx_crtc_disable(crtc);
2495         intel_clear_scanline_wait(dev);
2496 }
2497
2498 static void i9xx_crtc_commit(struct drm_crtc *crtc)
2499 {
2500         struct drm_device *dev = crtc->dev;
2501         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2502
2503         intel_update_watermarks(dev);
2504         i9xx_crtc_enable(crtc);
2505
2506         intel_crtc->cursor_on = true;
2507         intel_crtc_update_cursor(crtc);
2508 }
2509
2510 static void ironlake_crtc_prepare(struct drm_crtc *crtc)
2511 {
2512         struct drm_device *dev = crtc->dev;
2513         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2514
2515         intel_crtc->cursor_on = false;
2516         intel_crtc_update_cursor(crtc);
2517
2518         ironlake_crtc_disable(crtc);
2519         intel_clear_scanline_wait(dev);
2520 }
2521
2522 static void ironlake_crtc_commit(struct drm_crtc *crtc)
2523 {
2524         struct drm_device *dev = crtc->dev;
2525         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2526
2527         intel_update_watermarks(dev);
2528         ironlake_crtc_enable(crtc);
2529
2530         intel_crtc->cursor_on = true;
2531         intel_crtc_update_cursor(crtc);
2532 }
2533
2534 void intel_encoder_prepare (struct drm_encoder *encoder)
2535 {
2536         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2537         /* lvds has its own version of prepare see intel_lvds_prepare */
2538         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2539 }
2540
2541 void intel_encoder_commit (struct drm_encoder *encoder)
2542 {
2543         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2544         /* lvds has its own version of commit see intel_lvds_commit */
2545         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2546 }
2547
2548 void intel_encoder_destroy(struct drm_encoder *encoder)
2549 {
2550         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2551
2552         if (intel_encoder->ddc_bus)
2553                 intel_i2c_destroy(intel_encoder->ddc_bus);
2554
2555         if (intel_encoder->i2c_bus)
2556                 intel_i2c_destroy(intel_encoder->i2c_bus);
2557
2558         drm_encoder_cleanup(encoder);
2559         kfree(intel_encoder);
2560 }
2561
2562 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2563                                   struct drm_display_mode *mode,
2564                                   struct drm_display_mode *adjusted_mode)
2565 {
2566         struct drm_device *dev = crtc->dev;
2567         if (HAS_PCH_SPLIT(dev)) {
2568                 /* FDI link clock is fixed at 2.7G */
2569                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
2570                         return false;
2571         }
2572         return true;
2573 }
2574
2575 static int i945_get_display_clock_speed(struct drm_device *dev)
2576 {
2577         return 400000;
2578 }
2579
2580 static int i915_get_display_clock_speed(struct drm_device *dev)
2581 {
2582         return 333000;
2583 }
2584
2585 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2586 {
2587         return 200000;
2588 }
2589
2590 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2591 {
2592         u16 gcfgc = 0;
2593
2594         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2595
2596         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2597                 return 133000;
2598         else {
2599                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2600                 case GC_DISPLAY_CLOCK_333_MHZ:
2601                         return 333000;
2602                 default:
2603                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2604                         return 190000;
2605                 }
2606         }
2607 }
2608
2609 static int i865_get_display_clock_speed(struct drm_device *dev)
2610 {
2611         return 266000;
2612 }
2613
2614 static int i855_get_display_clock_speed(struct drm_device *dev)
2615 {
2616         u16 hpllcc = 0;
2617         /* Assume that the hardware is in the high speed state.  This
2618          * should be the default.
2619          */
2620         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2621         case GC_CLOCK_133_200:
2622         case GC_CLOCK_100_200:
2623                 return 200000;
2624         case GC_CLOCK_166_250:
2625                 return 250000;
2626         case GC_CLOCK_100_133:
2627                 return 133000;
2628         }
2629
2630         /* Shouldn't happen */
2631         return 0;
2632 }
2633
2634 static int i830_get_display_clock_speed(struct drm_device *dev)
2635 {
2636         return 133000;
2637 }
2638
2639 struct fdi_m_n {
2640         u32        tu;
2641         u32        gmch_m;
2642         u32        gmch_n;
2643         u32        link_m;
2644         u32        link_n;
2645 };
2646
2647 static void
2648 fdi_reduce_ratio(u32 *num, u32 *den)
2649 {
2650         while (*num > 0xffffff || *den > 0xffffff) {
2651                 *num >>= 1;
2652                 *den >>= 1;
2653         }
2654 }
2655
2656 #define DATA_N 0x800000
2657 #define LINK_N 0x80000
2658
2659 static void
2660 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2661                      int link_clock, struct fdi_m_n *m_n)
2662 {
2663         u64 temp;
2664
2665         m_n->tu = 64; /* default size */
2666
2667         temp = (u64) DATA_N * pixel_clock;
2668         temp = div_u64(temp, link_clock);
2669         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2670         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2671         m_n->gmch_n = DATA_N;
2672         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2673
2674         temp = (u64) LINK_N * pixel_clock;
2675         m_n->link_m = div_u64(temp, link_clock);
2676         m_n->link_n = LINK_N;
2677         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2678 }
2679
2680
2681 struct intel_watermark_params {
2682         unsigned long fifo_size;
2683         unsigned long max_wm;
2684         unsigned long default_wm;
2685         unsigned long guard_size;
2686         unsigned long cacheline_size;
2687 };
2688
2689 /* Pineview has different values for various configs */
2690 static struct intel_watermark_params pineview_display_wm = {
2691         PINEVIEW_DISPLAY_FIFO,
2692         PINEVIEW_MAX_WM,
2693         PINEVIEW_DFT_WM,
2694         PINEVIEW_GUARD_WM,
2695         PINEVIEW_FIFO_LINE_SIZE
2696 };
2697 static struct intel_watermark_params pineview_display_hplloff_wm = {
2698         PINEVIEW_DISPLAY_FIFO,
2699         PINEVIEW_MAX_WM,
2700         PINEVIEW_DFT_HPLLOFF_WM,
2701         PINEVIEW_GUARD_WM,
2702         PINEVIEW_FIFO_LINE_SIZE
2703 };
2704 static struct intel_watermark_params pineview_cursor_wm = {
2705         PINEVIEW_CURSOR_FIFO,
2706         PINEVIEW_CURSOR_MAX_WM,
2707         PINEVIEW_CURSOR_DFT_WM,
2708         PINEVIEW_CURSOR_GUARD_WM,
2709         PINEVIEW_FIFO_LINE_SIZE,
2710 };
2711 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2712         PINEVIEW_CURSOR_FIFO,
2713         PINEVIEW_CURSOR_MAX_WM,
2714         PINEVIEW_CURSOR_DFT_WM,
2715         PINEVIEW_CURSOR_GUARD_WM,
2716         PINEVIEW_FIFO_LINE_SIZE
2717 };
2718 static struct intel_watermark_params g4x_wm_info = {
2719         G4X_FIFO_SIZE,
2720         G4X_MAX_WM,
2721         G4X_MAX_WM,
2722         2,
2723         G4X_FIFO_LINE_SIZE,
2724 };
2725 static struct intel_watermark_params g4x_cursor_wm_info = {
2726         I965_CURSOR_FIFO,
2727         I965_CURSOR_MAX_WM,
2728         I965_CURSOR_DFT_WM,
2729         2,
2730         G4X_FIFO_LINE_SIZE,
2731 };
2732 static struct intel_watermark_params i965_cursor_wm_info = {
2733         I965_CURSOR_FIFO,
2734         I965_CURSOR_MAX_WM,
2735         I965_CURSOR_DFT_WM,
2736         2,
2737         I915_FIFO_LINE_SIZE,
2738 };
2739 static struct intel_watermark_params i945_wm_info = {
2740         I945_FIFO_SIZE,
2741         I915_MAX_WM,
2742         1,
2743         2,
2744         I915_FIFO_LINE_SIZE
2745 };
2746 static struct intel_watermark_params i915_wm_info = {
2747         I915_FIFO_SIZE,
2748         I915_MAX_WM,
2749         1,
2750         2,
2751         I915_FIFO_LINE_SIZE
2752 };
2753 static struct intel_watermark_params i855_wm_info = {
2754         I855GM_FIFO_SIZE,
2755         I915_MAX_WM,
2756         1,
2757         2,
2758         I830_FIFO_LINE_SIZE
2759 };
2760 static struct intel_watermark_params i830_wm_info = {
2761         I830_FIFO_SIZE,
2762         I915_MAX_WM,
2763         1,
2764         2,
2765         I830_FIFO_LINE_SIZE
2766 };
2767
2768 static struct intel_watermark_params ironlake_display_wm_info = {
2769         ILK_DISPLAY_FIFO,
2770         ILK_DISPLAY_MAXWM,
2771         ILK_DISPLAY_DFTWM,
2772         2,
2773         ILK_FIFO_LINE_SIZE
2774 };
2775
2776 static struct intel_watermark_params ironlake_cursor_wm_info = {
2777         ILK_CURSOR_FIFO,
2778         ILK_CURSOR_MAXWM,
2779         ILK_CURSOR_DFTWM,
2780         2,
2781         ILK_FIFO_LINE_SIZE
2782 };
2783
2784 static struct intel_watermark_params ironlake_display_srwm_info = {
2785         ILK_DISPLAY_SR_FIFO,
2786         ILK_DISPLAY_MAX_SRWM,
2787         ILK_DISPLAY_DFT_SRWM,
2788         2,
2789         ILK_FIFO_LINE_SIZE
2790 };
2791
2792 static struct intel_watermark_params ironlake_cursor_srwm_info = {
2793         ILK_CURSOR_SR_FIFO,
2794         ILK_CURSOR_MAX_SRWM,
2795         ILK_CURSOR_DFT_SRWM,
2796         2,
2797         ILK_FIFO_LINE_SIZE
2798 };
2799
2800 /**
2801  * intel_calculate_wm - calculate watermark level
2802  * @clock_in_khz: pixel clock
2803  * @wm: chip FIFO params
2804  * @pixel_size: display pixel size
2805  * @latency_ns: memory latency for the platform
2806  *
2807  * Calculate the watermark level (the level at which the display plane will
2808  * start fetching from memory again).  Each chip has a different display
2809  * FIFO size and allocation, so the caller needs to figure that out and pass
2810  * in the correct intel_watermark_params structure.
2811  *
2812  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2813  * on the pixel size.  When it reaches the watermark level, it'll start
2814  * fetching FIFO line sized based chunks from memory until the FIFO fills
2815  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2816  * will occur, and a display engine hang could result.
2817  */
2818 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2819                                         struct intel_watermark_params *wm,
2820                                         int pixel_size,
2821                                         unsigned long latency_ns)
2822 {
2823         long entries_required, wm_size;
2824
2825         /*
2826          * Note: we need to make sure we don't overflow for various clock &
2827          * latency values.
2828          * clocks go from a few thousand to several hundred thousand.
2829          * latency is usually a few thousand
2830          */
2831         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2832                 1000;
2833         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
2834
2835         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2836
2837         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2838
2839         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2840
2841         /* Don't promote wm_size to unsigned... */
2842         if (wm_size > (long)wm->max_wm)
2843                 wm_size = wm->max_wm;
2844         if (wm_size <= 0)
2845                 wm_size = wm->default_wm;
2846         return wm_size;
2847 }
2848
2849 struct cxsr_latency {
2850         int is_desktop;
2851         int is_ddr3;
2852         unsigned long fsb_freq;
2853         unsigned long mem_freq;
2854         unsigned long display_sr;
2855         unsigned long display_hpll_disable;
2856         unsigned long cursor_sr;
2857         unsigned long cursor_hpll_disable;
2858 };
2859
2860 static const struct cxsr_latency cxsr_latency_table[] = {
2861         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2862         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2863         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2864         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
2865         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
2866
2867         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2868         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2869         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2870         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
2871         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
2872
2873         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2874         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2875         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2876         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
2877         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
2878
2879         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2880         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2881         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2882         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
2883         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
2884
2885         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2886         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2887         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2888         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
2889         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
2890
2891         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2892         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2893         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2894         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
2895         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
2896 };
2897
2898 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
2899                                                          int is_ddr3,
2900                                                          int fsb,
2901                                                          int mem)
2902 {
2903         const struct cxsr_latency *latency;
2904         int i;
2905
2906         if (fsb == 0 || mem == 0)
2907                 return NULL;
2908
2909         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2910                 latency = &cxsr_latency_table[i];
2911                 if (is_desktop == latency->is_desktop &&
2912                     is_ddr3 == latency->is_ddr3 &&
2913                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2914                         return latency;
2915         }
2916
2917         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2918
2919         return NULL;
2920 }
2921
2922 static void pineview_disable_cxsr(struct drm_device *dev)
2923 {
2924         struct drm_i915_private *dev_priv = dev->dev_private;
2925
2926         /* deactivate cxsr */
2927         I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
2928 }
2929
2930 /*
2931  * Latency for FIFO fetches is dependent on several factors:
2932  *   - memory configuration (speed, channels)
2933  *   - chipset
2934  *   - current MCH state
2935  * It can be fairly high in some situations, so here we assume a fairly
2936  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2937  * set this value too high, the FIFO will fetch frequently to stay full)
2938  * and power consumption (set it too low to save power and we might see
2939  * FIFO underruns and display "flicker").
2940  *
2941  * A value of 5us seems to be a good balance; safe for very low end
2942  * platforms but not overly aggressive on lower latency configs.
2943  */
2944 static const int latency_ns = 5000;
2945
2946 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2947 {
2948         struct drm_i915_private *dev_priv = dev->dev_private;
2949         uint32_t dsparb = I915_READ(DSPARB);
2950         int size;
2951
2952         size = dsparb & 0x7f;
2953         if (plane)
2954                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
2955
2956         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2957                       plane ? "B" : "A", size);
2958
2959         return size;
2960 }
2961
2962 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2963 {
2964         struct drm_i915_private *dev_priv = dev->dev_private;
2965         uint32_t dsparb = I915_READ(DSPARB);
2966         int size;
2967
2968         size = dsparb & 0x1ff;
2969         if (plane)
2970                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
2971         size >>= 1; /* Convert to cachelines */
2972
2973         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2974                       plane ? "B" : "A", size);
2975
2976         return size;
2977 }
2978
2979 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2980 {
2981         struct drm_i915_private *dev_priv = dev->dev_private;
2982         uint32_t dsparb = I915_READ(DSPARB);
2983         int size;
2984
2985         size = dsparb & 0x7f;
2986         size >>= 2; /* Convert to cachelines */
2987
2988         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2989                       plane ? "B" : "A",
2990                       size);
2991
2992         return size;
2993 }
2994
2995 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2996 {
2997         struct drm_i915_private *dev_priv = dev->dev_private;
2998         uint32_t dsparb = I915_READ(DSPARB);
2999         int size;
3000
3001         size = dsparb & 0x7f;
3002         size >>= 1; /* Convert to cachelines */
3003
3004         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
3005                       plane ? "B" : "A", size);
3006
3007         return size;
3008 }
3009
3010 static void pineview_update_wm(struct drm_device *dev,  int planea_clock,
3011                                int planeb_clock, int sr_hdisplay, int unused,
3012                                int pixel_size)
3013 {
3014         struct drm_i915_private *dev_priv = dev->dev_private;
3015         const struct cxsr_latency *latency;
3016         u32 reg;
3017         unsigned long wm;
3018         int sr_clock;
3019
3020         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
3021                                          dev_priv->fsb_freq, dev_priv->mem_freq);
3022         if (!latency) {
3023                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
3024                 pineview_disable_cxsr(dev);
3025                 return;
3026         }
3027
3028         if (!planea_clock || !planeb_clock) {
3029                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3030
3031                 /* Display SR */
3032                 wm = intel_calculate_wm(sr_clock, &pineview_display_wm,
3033                                         pixel_size, latency->display_sr);
3034                 reg = I915_READ(DSPFW1);
3035                 reg &= ~DSPFW_SR_MASK;
3036                 reg |= wm << DSPFW_SR_SHIFT;
3037                 I915_WRITE(DSPFW1, reg);
3038                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
3039
3040                 /* cursor SR */
3041                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_wm,
3042                                         pixel_size, latency->cursor_sr);
3043                 reg = I915_READ(DSPFW3);
3044                 reg &= ~DSPFW_CURSOR_SR_MASK;
3045                 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
3046                 I915_WRITE(DSPFW3, reg);
3047
3048                 /* Display HPLL off SR */
3049                 wm = intel_calculate_wm(sr_clock, &pineview_display_hplloff_wm,
3050                                         pixel_size, latency->display_hpll_disable);
3051                 reg = I915_READ(DSPFW3);
3052                 reg &= ~DSPFW_HPLL_SR_MASK;
3053                 reg |= wm & DSPFW_HPLL_SR_MASK;
3054                 I915_WRITE(DSPFW3, reg);
3055
3056                 /* cursor HPLL off SR */
3057                 wm = intel_calculate_wm(sr_clock, &pineview_cursor_hplloff_wm,
3058                                         pixel_size, latency->cursor_hpll_disable);
3059                 reg = I915_READ(DSPFW3);
3060                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
3061                 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
3062                 I915_WRITE(DSPFW3, reg);
3063                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
3064
3065                 /* activate cxsr */
3066                 I915_WRITE(DSPFW3,
3067                            I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
3068                 DRM_DEBUG_KMS("Self-refresh is enabled\n");
3069         } else {
3070                 pineview_disable_cxsr(dev);
3071                 DRM_DEBUG_KMS("Self-refresh is disabled\n");
3072         }
3073 }
3074
3075 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
3076                           int planeb_clock, int sr_hdisplay, int sr_htotal,
3077                           int pixel_size)
3078 {
3079         struct drm_i915_private *dev_priv = dev->dev_private;
3080         int total_size, cacheline_size;
3081         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
3082         struct intel_watermark_params planea_params, planeb_params;
3083         unsigned long line_time_us;
3084         int sr_clock, sr_entries = 0, entries_required;
3085
3086         /* Create copies of the base settings for each pipe */
3087         planea_params = planeb_params = g4x_wm_info;
3088
3089         /* Grab a couple of global values before we overwrite them */
3090         total_size = planea_params.fifo_size;
3091         cacheline_size = planea_params.cacheline_size;
3092
3093         /*
3094          * Note: we need to make sure we don't overflow for various clock &
3095          * latency values.
3096          * clocks go from a few thousand to several hundred thousand.
3097          * latency is usually a few thousand
3098          */
3099         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
3100                 1000;
3101         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3102         planea_wm = entries_required + planea_params.guard_size;
3103
3104         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
3105                 1000;
3106         entries_required = DIV_ROUND_UP(entries_required, G4X_FIFO_LINE_SIZE);
3107         planeb_wm = entries_required + planeb_params.guard_size;
3108
3109         cursora_wm = cursorb_wm = 16;
3110         cursor_sr = 32;
3111
3112         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3113
3114         /* Calc sr entries for one plane configs */
3115         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3116                 /* self-refresh has much higher latency */
3117                 static const int sr_latency_ns = 12000;
3118
3119                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3120                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3121
3122                 /* Use ns/us then divide to preserve precision */
3123                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3124                         pixel_size * sr_hdisplay;
3125                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3126
3127                 entries_required = (((sr_latency_ns / line_time_us) +
3128                                      1000) / 1000) * pixel_size * 64;
3129                 entries_required = DIV_ROUND_UP(entries_required,
3130                                                 g4x_cursor_wm_info.cacheline_size);
3131                 cursor_sr = entries_required + g4x_cursor_wm_info.guard_size;
3132
3133                 if (cursor_sr > g4x_cursor_wm_info.max_wm)
3134                         cursor_sr = g4x_cursor_wm_info.max_wm;
3135                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3136                               "cursor %d\n", sr_entries, cursor_sr);
3137
3138                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3139         } else {
3140                 /* Turn off self refresh if both pipes are enabled */
3141                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3142                            & ~FW_BLC_SELF_EN);
3143         }
3144
3145         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
3146                   planea_wm, planeb_wm, sr_entries);
3147
3148         planea_wm &= 0x3f;
3149         planeb_wm &= 0x3f;
3150
3151         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
3152                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
3153                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
3154         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
3155                    (cursora_wm << DSPFW_CURSORA_SHIFT));
3156         /* HPLL off in SR has some issues on G4x... disable it */
3157         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
3158                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3159 }
3160
3161 static void i965_update_wm(struct drm_device *dev, int planea_clock,
3162                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3163                            int pixel_size)
3164 {
3165         struct drm_i915_private *dev_priv = dev->dev_private;
3166         unsigned long line_time_us;
3167         int sr_clock, sr_entries, srwm = 1;
3168         int cursor_sr = 16;
3169
3170         /* Calc sr entries for one plane configs */
3171         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
3172                 /* self-refresh has much higher latency */
3173                 static const int sr_latency_ns = 12000;
3174
3175                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3176                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3177
3178                 /* Use ns/us then divide to preserve precision */
3179                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3180                         pixel_size * sr_hdisplay;
3181                 sr_entries = DIV_ROUND_UP(sr_entries, I915_FIFO_LINE_SIZE);
3182                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
3183                 srwm = I965_FIFO_SIZE - sr_entries;
3184                 if (srwm < 0)
3185                         srwm = 1;
3186                 srwm &= 0x1ff;
3187
3188                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3189                         pixel_size * 64;
3190                 sr_entries = DIV_ROUND_UP(sr_entries,
3191                                           i965_cursor_wm_info.cacheline_size);
3192                 cursor_sr = i965_cursor_wm_info.fifo_size -
3193                         (sr_entries + i965_cursor_wm_info.guard_size);
3194
3195                 if (cursor_sr > i965_cursor_wm_info.max_wm)
3196                         cursor_sr = i965_cursor_wm_info.max_wm;
3197
3198                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
3199                               "cursor %d\n", srwm, cursor_sr);
3200
3201                 if (IS_I965GM(dev))
3202                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
3203         } else {
3204                 /* Turn off self refresh if both pipes are enabled */
3205                 if (IS_I965GM(dev))
3206                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3207                                    & ~FW_BLC_SELF_EN);
3208         }
3209
3210         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
3211                       srwm);
3212
3213         /* 965 has limitations... */
3214         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
3215                    (8 << 0));
3216         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
3217         /* update cursor SR watermark */
3218         I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
3219 }
3220
3221 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
3222                            int planeb_clock, int sr_hdisplay, int sr_htotal,
3223                            int pixel_size)
3224 {
3225         struct drm_i915_private *dev_priv = dev->dev_private;
3226         uint32_t fwater_lo;
3227         uint32_t fwater_hi;
3228         int total_size, cacheline_size, cwm, srwm = 1;
3229         int planea_wm, planeb_wm;
3230         struct intel_watermark_params planea_params, planeb_params;
3231         unsigned long line_time_us;
3232         int sr_clock, sr_entries = 0;
3233
3234         /* Create copies of the base settings for each pipe */
3235         if (IS_I965GM(dev) || IS_I945GM(dev))
3236                 planea_params = planeb_params = i945_wm_info;
3237         else if (IS_I9XX(dev))
3238                 planea_params = planeb_params = i915_wm_info;
3239         else
3240                 planea_params = planeb_params = i855_wm_info;
3241
3242         /* Grab a couple of global values before we overwrite them */
3243         total_size = planea_params.fifo_size;
3244         cacheline_size = planea_params.cacheline_size;
3245
3246         /* Update per-plane FIFO sizes */
3247         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3248         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
3249
3250         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
3251                                        pixel_size, latency_ns);
3252         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
3253                                        pixel_size, latency_ns);
3254         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
3255
3256         /*
3257          * Overlay gets an aggressive default since video jitter is bad.
3258          */
3259         cwm = 2;
3260
3261         /* Calc sr entries for one plane configs */
3262         if (HAS_FW_BLC(dev) && sr_hdisplay &&
3263             (!planea_clock || !planeb_clock)) {
3264                 /* self-refresh has much higher latency */
3265                 static const int sr_latency_ns = 6000;
3266
3267                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3268                 line_time_us = ((sr_htotal * 1000) / sr_clock);
3269
3270                 /* Use ns/us then divide to preserve precision */
3271                 sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3272                         pixel_size * sr_hdisplay;
3273                 sr_entries = DIV_ROUND_UP(sr_entries, cacheline_size);
3274                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
3275                 srwm = total_size - sr_entries;
3276                 if (srwm < 0)
3277                         srwm = 1;
3278
3279                 if (IS_I945G(dev) || IS_I945GM(dev))
3280                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
3281                 else if (IS_I915GM(dev)) {
3282                         /* 915M has a smaller SRWM field */
3283                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
3284                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
3285                 }
3286         } else {
3287                 /* Turn off self refresh if both pipes are enabled */
3288                 if (IS_I945G(dev) || IS_I945GM(dev)) {
3289                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
3290                                    & ~FW_BLC_SELF_EN);
3291                 } else if (IS_I915GM(dev)) {
3292                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
3293                 }
3294         }
3295
3296         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
3297                       planea_wm, planeb_wm, cwm, srwm);
3298
3299         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
3300         fwater_hi = (cwm & 0x1f);
3301
3302         /* Set request length to 8 cachelines per fetch */
3303         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
3304         fwater_hi = fwater_hi | (1 << 8);
3305
3306         I915_WRITE(FW_BLC, fwater_lo);
3307         I915_WRITE(FW_BLC2, fwater_hi);
3308 }
3309
3310 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
3311                            int unused2, int unused3, int pixel_size)
3312 {
3313         struct drm_i915_private *dev_priv = dev->dev_private;
3314         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
3315         int planea_wm;
3316
3317         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
3318
3319         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
3320                                        pixel_size, latency_ns);
3321         fwater_lo |= (3<<8) | planea_wm;
3322
3323         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
3324
3325         I915_WRITE(FW_BLC, fwater_lo);
3326 }
3327
3328 #define ILK_LP0_PLANE_LATENCY           700
3329 #define ILK_LP0_CURSOR_LATENCY          1300
3330
3331 static bool ironlake_compute_wm0(struct drm_device *dev,
3332                                  int pipe,
3333                                  int *plane_wm,
3334                                  int *cursor_wm)
3335 {
3336         struct drm_crtc *crtc;
3337         int htotal, hdisplay, clock, pixel_size = 0;
3338         int line_time_us, line_count, entries;
3339
3340         crtc = intel_get_crtc_for_pipe(dev, pipe);
3341         if (crtc->fb == NULL || !crtc->enabled)
3342                 return false;
3343
3344         htotal = crtc->mode.htotal;
3345         hdisplay = crtc->mode.hdisplay;
3346         clock = crtc->mode.clock;
3347         pixel_size = crtc->fb->bits_per_pixel / 8;
3348
3349         /* Use the small buffer method to calculate plane watermark */
3350         entries = ((clock * pixel_size / 1000) * ILK_LP0_PLANE_LATENCY) / 1000;
3351         entries = DIV_ROUND_UP(entries,
3352                                ironlake_display_wm_info.cacheline_size);
3353         *plane_wm = entries + ironlake_display_wm_info.guard_size;
3354         if (*plane_wm > (int)ironlake_display_wm_info.max_wm)
3355                 *plane_wm = ironlake_display_wm_info.max_wm;
3356
3357         /* Use the large buffer method to calculate cursor watermark */
3358         line_time_us = ((htotal * 1000) / clock);
3359         line_count = (ILK_LP0_CURSOR_LATENCY / line_time_us + 1000) / 1000;
3360         entries = line_count * 64 * pixel_size;
3361         entries = DIV_ROUND_UP(entries,
3362                                ironlake_cursor_wm_info.cacheline_size);
3363         *cursor_wm = entries + ironlake_cursor_wm_info.guard_size;
3364         if (*cursor_wm > ironlake_cursor_wm_info.max_wm)
3365                 *cursor_wm = ironlake_cursor_wm_info.max_wm;
3366
3367         return true;
3368 }
3369
3370 static void ironlake_update_wm(struct drm_device *dev,
3371                                int planea_clock, int planeb_clock,
3372                                int sr_hdisplay, int sr_htotal,
3373                                int pixel_size)
3374 {
3375         struct drm_i915_private *dev_priv = dev->dev_private;
3376         int plane_wm, cursor_wm, enabled;
3377         int tmp;
3378
3379         enabled = 0;
3380         if (ironlake_compute_wm0(dev, 0, &plane_wm, &cursor_wm)) {
3381                 I915_WRITE(WM0_PIPEA_ILK,
3382                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3383                 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
3384                               " plane %d, " "cursor: %d\n",
3385                               plane_wm, cursor_wm);
3386                 enabled++;
3387         }
3388
3389         if (ironlake_compute_wm0(dev, 1, &plane_wm, &cursor_wm)) {
3390                 I915_WRITE(WM0_PIPEB_ILK,
3391                            (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
3392                 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
3393                               " plane %d, cursor: %d\n",
3394                               plane_wm, cursor_wm);
3395                 enabled++;
3396         }
3397
3398         /*
3399          * Calculate and update the self-refresh watermark only when one
3400          * display plane is used.
3401          */
3402         tmp = 0;
3403         if (enabled == 1 && /* XXX disabled due to buggy implmentation? */ 0) {
3404                 unsigned long line_time_us;
3405                 int small, large, plane_fbc;
3406                 int sr_clock, entries;
3407                 int line_count, line_size;
3408                 /* Read the self-refresh latency. The unit is 0.5us */
3409                 int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
3410
3411                 sr_clock = planea_clock ? planea_clock : planeb_clock;
3412                 line_time_us = (sr_htotal * 1000) / sr_clock;
3413
3414                 /* Use ns/us then divide to preserve precision */
3415                 line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
3416                         / 1000;
3417                 line_size = sr_hdisplay * pixel_size;
3418
3419                 /* Use the minimum of the small and large buffer method for primary */
3420                 small = ((sr_clock * pixel_size / 1000) * (ilk_sr_latency * 500)) / 1000;
3421                 large = line_count * line_size;
3422
3423                 entries = DIV_ROUND_UP(min(small, large),
3424                                        ironlake_display_srwm_info.cacheline_size);
3425
3426                 plane_fbc = entries * 64;
3427                 plane_fbc = DIV_ROUND_UP(plane_fbc, line_size);
3428
3429                 plane_wm = entries + ironlake_display_srwm_info.guard_size;
3430                 if (plane_wm > (int)ironlake_display_srwm_info.max_wm)
3431                         plane_wm = ironlake_display_srwm_info.max_wm;
3432
3433                 /* calculate the self-refresh watermark for display cursor */
3434                 entries = line_count * pixel_size * 64;
3435                 entries = DIV_ROUND_UP(entries,
3436                                        ironlake_cursor_srwm_info.cacheline_size);
3437
3438                 cursor_wm = entries + ironlake_cursor_srwm_info.guard_size;
3439                 if (cursor_wm > (int)ironlake_cursor_srwm_info.max_wm)
3440                         cursor_wm = ironlake_cursor_srwm_info.max_wm;
3441
3442                 /* configure watermark and enable self-refresh */
3443                 tmp = (WM1_LP_SR_EN |
3444                        (ilk_sr_latency << WM1_LP_LATENCY_SHIFT) |
3445                        (plane_fbc << WM1_LP_FBC_SHIFT) |
3446                        (plane_wm << WM1_LP_SR_SHIFT) |
3447                        cursor_wm);
3448                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d, fbc lines %d,"
3449                               " cursor %d\n", plane_wm, plane_fbc, cursor_wm);
3450         }
3451         I915_WRITE(WM1_LP_ILK, tmp);
3452         /* XXX setup WM2 and WM3 */
3453 }
3454
3455 /**
3456  * intel_update_watermarks - update FIFO watermark values based on current modes
3457  *
3458  * Calculate watermark values for the various WM regs based on current mode
3459  * and plane configuration.
3460  *
3461  * There are several cases to deal with here:
3462  *   - normal (i.e. non-self-refresh)
3463  *   - self-refresh (SR) mode
3464  *   - lines are large relative to FIFO size (buffer can hold up to 2)
3465  *   - lines are small relative to FIFO size (buffer can hold more than 2
3466  *     lines), so need to account for TLB latency
3467  *
3468  *   The normal calculation is:
3469  *     watermark = dotclock * bytes per pixel * latency
3470  *   where latency is platform & configuration dependent (we assume pessimal
3471  *   values here).
3472  *
3473  *   The SR calculation is:
3474  *     watermark = (trunc(latency/line time)+1) * surface width *
3475  *       bytes per pixel
3476  *   where
3477  *     line time = htotal / dotclock
3478  *     surface width = hdisplay for normal plane and 64 for cursor
3479  *   and latency is assumed to be high, as above.
3480  *
3481  * The final value programmed to the register should always be rounded up,
3482  * and include an extra 2 entries to account for clock crossings.
3483  *
3484  * We don't use the sprite, so we can ignore that.  And on Crestline we have
3485  * to set the non-SR watermarks to 8.
3486  */
3487 static void intel_update_watermarks(struct drm_device *dev)
3488 {
3489         struct drm_i915_private *dev_priv = dev->dev_private;
3490         struct drm_crtc *crtc;
3491         int sr_hdisplay = 0;
3492         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
3493         int enabled = 0, pixel_size = 0;
3494         int sr_htotal = 0;
3495
3496         if (!dev_priv->display.update_wm)
3497                 return;
3498
3499         /* Get the clock config from both planes */
3500         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3501                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3502                 if (intel_crtc->dpms_mode == DRM_MODE_DPMS_ON) {
3503                         enabled++;
3504                         if (intel_crtc->plane == 0) {
3505                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
3506                                               intel_crtc->pipe, crtc->mode.clock);
3507                                 planea_clock = crtc->mode.clock;
3508                         } else {
3509                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
3510                                               intel_crtc->pipe, crtc->mode.clock);
3511                                 planeb_clock = crtc->mode.clock;
3512                         }
3513                         sr_hdisplay = crtc->mode.hdisplay;
3514                         sr_clock = crtc->mode.clock;
3515                         sr_htotal = crtc->mode.htotal;
3516                         if (crtc->fb)
3517                                 pixel_size = crtc->fb->bits_per_pixel / 8;
3518                         else
3519                                 pixel_size = 4; /* by default */
3520                 }
3521         }
3522
3523         if (enabled <= 0)
3524                 return;
3525
3526         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
3527                                     sr_hdisplay, sr_htotal, pixel_size);
3528 }
3529
3530 static int intel_crtc_mode_set(struct drm_crtc *crtc,
3531                                struct drm_display_mode *mode,
3532                                struct drm_display_mode *adjusted_mode,
3533                                int x, int y,
3534                                struct drm_framebuffer *old_fb)
3535 {
3536         struct drm_device *dev = crtc->dev;
3537         struct drm_i915_private *dev_priv = dev->dev_private;
3538         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3539         int pipe = intel_crtc->pipe;
3540         int plane = intel_crtc->plane;
3541         u32 fp_reg, dpll_reg;
3542         int refclk, num_connectors = 0;
3543         intel_clock_t clock, reduced_clock;
3544         u32 dpll, fp = 0, fp2 = 0, dspcntr, pipeconf;
3545         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
3546         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
3547         struct intel_encoder *has_edp_encoder = NULL;
3548         struct drm_mode_config *mode_config = &dev->mode_config;
3549         struct intel_encoder *encoder;
3550         const intel_limit_t *limit;
3551         int ret;
3552         struct fdi_m_n m_n = {0};
3553         u32 reg, temp;
3554         int target_clock;
3555
3556         drm_vblank_pre_modeset(dev, pipe);
3557
3558         list_for_each_entry(encoder, &mode_config->encoder_list, base.head) {
3559                 if (encoder->base.crtc != crtc)
3560                         continue;
3561
3562                 switch (encoder->type) {
3563                 case INTEL_OUTPUT_LVDS:
3564                         is_lvds = true;
3565                         break;
3566                 case INTEL_OUTPUT_SDVO:
3567                 case INTEL_OUTPUT_HDMI:
3568                         is_sdvo = true;
3569                         if (encoder->needs_tv_clock)
3570                                 is_tv = true;
3571                         break;
3572                 case INTEL_OUTPUT_DVO:
3573                         is_dvo = true;
3574                         break;
3575                 case INTEL_OUTPUT_TVOUT:
3576                         is_tv = true;
3577                         break;
3578                 case INTEL_OUTPUT_ANALOG:
3579                         is_crt = true;
3580                         break;
3581                 case INTEL_OUTPUT_DISPLAYPORT:
3582                         is_dp = true;
3583                         break;
3584                 case INTEL_OUTPUT_EDP:
3585                         has_edp_encoder = encoder;
3586                         break;
3587                 }
3588
3589                 num_connectors++;
3590         }
3591
3592         if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2) {
3593                 refclk = dev_priv->lvds_ssc_freq * 1000;
3594                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
3595                               refclk / 1000);
3596         } else if (IS_I9XX(dev)) {
3597                 refclk = 96000;
3598                 if (HAS_PCH_SPLIT(dev))
3599                         refclk = 120000; /* 120Mhz refclk */
3600         } else {
3601                 refclk = 48000;
3602         }
3603
3604         /*
3605          * Returns a set of divisors for the desired target clock with the given
3606          * refclk, or FALSE.  The returned values represent the clock equation:
3607          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
3608          */
3609         limit = intel_limit(crtc);
3610         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
3611         if (!ok) {
3612                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
3613                 drm_vblank_post_modeset(dev, pipe);
3614                 return -EINVAL;
3615         }
3616
3617         /* Ensure that the cursor is valid for the new mode before changing... */
3618         intel_crtc_update_cursor(crtc);
3619
3620         if (is_lvds && dev_priv->lvds_downclock_avail) {
3621                 has_reduced_clock = limit->find_pll(limit, crtc,
3622                                                     dev_priv->lvds_downclock,
3623                                                     refclk,
3624                                                     &reduced_clock);
3625                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3626                         /*
3627                          * If the different P is found, it means that we can't
3628                          * switch the display clock by using the FP0/FP1.
3629                          * In such case we will disable the LVDS downclock
3630                          * feature.
3631                          */
3632                         DRM_DEBUG_KMS("Different P is found for "
3633                                       "LVDS clock/downclock\n");
3634                         has_reduced_clock = 0;
3635                 }
3636         }
3637         /* SDVO TV has fixed PLL values depend on its clock range,
3638            this mirrors vbios setting. */
3639         if (is_sdvo && is_tv) {
3640                 if (adjusted_mode->clock >= 100000
3641                     && adjusted_mode->clock < 140500) {
3642                         clock.p1 = 2;
3643                         clock.p2 = 10;
3644                         clock.n = 3;
3645                         clock.m1 = 16;
3646                         clock.m2 = 8;
3647                 } else if (adjusted_mode->clock >= 140500
3648                            && adjusted_mode->clock <= 200000) {
3649                         clock.p1 = 1;
3650                         clock.p2 = 10;
3651                         clock.n = 6;
3652                         clock.m1 = 12;
3653                         clock.m2 = 8;
3654                 }
3655         }
3656
3657         /* FDI link */
3658         if (HAS_PCH_SPLIT(dev)) {
3659                 int lane = 0, link_bw, bpp;
3660                 /* eDP doesn't require FDI link, so just set DP M/N
3661                    according to current link config */
3662                 if (has_edp_encoder) {
3663                         target_clock = mode->clock;
3664                         intel_edp_link_config(has_edp_encoder,
3665                                               &lane, &link_bw);
3666                 } else {
3667                         /* DP over FDI requires target mode clock
3668                            instead of link clock */
3669                         if (is_dp)
3670                                 target_clock = mode->clock;
3671                         else
3672                                 target_clock = adjusted_mode->clock;
3673
3674                         /* FDI is a binary signal running at ~2.7GHz, encoding
3675                          * each output octet as 10 bits. The actual frequency
3676                          * is stored as a divider into a 100MHz clock, and the
3677                          * mode pixel clock is stored in units of 1KHz.
3678                          * Hence the bw of each lane in terms of the mode signal
3679                          * is:
3680                          */
3681                         link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
3682                 }
3683
3684                 /* determine panel color depth */
3685                 temp = I915_READ(PIPECONF(pipe));
3686                 temp &= ~PIPE_BPC_MASK;
3687                 if (is_lvds) {
3688                         /* the BPC will be 6 if it is 18-bit LVDS panel */
3689                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3690                                 temp |= PIPE_8BPC;
3691                         else
3692                                 temp |= PIPE_6BPC;
3693                 } else if (has_edp_encoder || (is_dp && intel_pch_has_edp(crtc))) {
3694                         switch (dev_priv->edp_bpp/3) {
3695                         case 8:
3696                                 temp |= PIPE_8BPC;
3697                                 break;
3698                         case 10:
3699                                 temp |= PIPE_10BPC;
3700                                 break;
3701                         case 6:
3702                                 temp |= PIPE_6BPC;
3703                                 break;
3704                         case 12:
3705                                 temp |= PIPE_12BPC;
3706                                 break;
3707                         }
3708                 } else
3709                         temp |= PIPE_8BPC;
3710                 I915_WRITE(PIPECONF(pipe), temp);
3711
3712                 switch (temp & PIPE_BPC_MASK) {
3713                 case PIPE_8BPC:
3714                         bpp = 24;
3715                         break;
3716                 case PIPE_10BPC:
3717                         bpp = 30;
3718                         break;
3719                 case PIPE_6BPC:
3720                         bpp = 18;
3721                         break;
3722                 case PIPE_12BPC:
3723                         bpp = 36;
3724                         break;
3725                 default:
3726                         DRM_ERROR("unknown pipe bpc value\n");
3727                         bpp = 24;
3728                 }
3729
3730                 if (!lane) {
3731                         /*
3732                          * Account for spread spectrum to avoid
3733                          * oversubscribing the link. Max center spread
3734                          * is 2.5%; use 5% for safety's sake.
3735                          */
3736                         u32 bps = target_clock * bpp * 21 / 20;
3737                         lane = bps / (link_bw * 8) + 1;
3738                 }
3739
3740                 intel_crtc->fdi_lanes = lane;
3741
3742                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3743         }
3744
3745         /* Ironlake: try to setup display ref clock before DPLL
3746          * enabling. This is only under driver's control after
3747          * PCH B stepping, previous chipset stepping should be
3748          * ignoring this setting.
3749          */
3750         if (HAS_PCH_SPLIT(dev)) {
3751                 temp = I915_READ(PCH_DREF_CONTROL);
3752                 /* Always enable nonspread source */
3753                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3754                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3755                 temp &= ~DREF_SSC_SOURCE_MASK;
3756                 temp |= DREF_SSC_SOURCE_ENABLE;
3757                 I915_WRITE(PCH_DREF_CONTROL, temp);
3758
3759                 POSTING_READ(PCH_DREF_CONTROL);
3760                 udelay(200);
3761
3762                 if (has_edp_encoder) {
3763                         if (dev_priv->lvds_use_ssc) {
3764                                 temp |= DREF_SSC1_ENABLE;
3765                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3766
3767                                 POSTING_READ(PCH_DREF_CONTROL);
3768                                 udelay(200);
3769
3770                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3771                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3772                         } else {
3773                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3774                         }
3775                         I915_WRITE(PCH_DREF_CONTROL, temp);
3776                 }
3777         }
3778
3779         if (IS_PINEVIEW(dev)) {
3780                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3781                 if (has_reduced_clock)
3782                         fp2 = (1 << reduced_clock.n) << 16 |
3783                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3784         } else {
3785                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3786                 if (has_reduced_clock)
3787                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3788                                 reduced_clock.m2;
3789         }
3790
3791         dpll = 0;
3792         if (!HAS_PCH_SPLIT(dev))
3793                 dpll = DPLL_VGA_MODE_DIS;
3794
3795         if (IS_I9XX(dev)) {
3796                 if (is_lvds)
3797                         dpll |= DPLLB_MODE_LVDS;
3798                 else
3799                         dpll |= DPLLB_MODE_DAC_SERIAL;
3800                 if (is_sdvo) {
3801                         int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
3802                         if (pixel_multiplier > 1) {
3803                                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3804                                         dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3805                                 else if (HAS_PCH_SPLIT(dev))
3806                                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3807                         }
3808                         dpll |= DPLL_DVO_HIGH_SPEED;
3809                 }
3810                 if (is_dp)
3811                         dpll |= DPLL_DVO_HIGH_SPEED;
3812
3813                 /* compute bitmask from p1 value */
3814                 if (IS_PINEVIEW(dev))
3815                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3816                 else {
3817                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3818                         /* also FPA1 */
3819                         if (HAS_PCH_SPLIT(dev))
3820                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3821                         if (IS_G4X(dev) && has_reduced_clock)
3822                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3823                 }
3824                 switch (clock.p2) {
3825                 case 5:
3826                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3827                         break;
3828                 case 7:
3829                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3830                         break;
3831                 case 10:
3832                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3833                         break;
3834                 case 14:
3835                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3836                         break;
3837                 }
3838                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev))
3839                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3840         } else {
3841                 if (is_lvds) {
3842                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3843                 } else {
3844                         if (clock.p1 == 2)
3845                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3846                         else
3847                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3848                         if (clock.p2 == 4)
3849                                 dpll |= PLL_P2_DIVIDE_BY_4;
3850                 }
3851         }
3852
3853         if (is_sdvo && is_tv)
3854                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3855         else if (is_tv)
3856                 /* XXX: just matching BIOS for now */
3857                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3858                 dpll |= 3;
3859         else if (is_lvds && dev_priv->lvds_use_ssc && num_connectors < 2)
3860                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3861         else
3862                 dpll |= PLL_REF_INPUT_DREFCLK;
3863
3864         /* setup pipeconf */
3865         pipeconf = I915_READ(PIPECONF(pipe));
3866
3867         /* Set up the display plane register */
3868         dspcntr = DISPPLANE_GAMMA_ENABLE;
3869
3870         /* Ironlake's plane is forced to pipe, bit 24 is to
3871            enable color space conversion */
3872         if (!HAS_PCH_SPLIT(dev)) {
3873                 if (pipe == 0)
3874                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3875                 else
3876                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3877         }
3878
3879         if (pipe == 0 && !IS_I965G(dev)) {
3880                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3881                  * core speed.
3882                  *
3883                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3884                  * pipe == 0 check?
3885                  */
3886                 if (mode->clock >
3887                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3888                         pipeconf |= PIPECONF_DOUBLE_WIDE;
3889                 else
3890                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
3891         }
3892
3893         dspcntr |= DISPLAY_PLANE_ENABLE;
3894         pipeconf |= PIPECONF_ENABLE;
3895         dpll |= DPLL_VCO_ENABLE;
3896
3897         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3898         drm_mode_debug_printmodeline(mode);
3899
3900         /* assign to Ironlake registers */
3901         if (HAS_PCH_SPLIT(dev)) {
3902                 fp_reg = PCH_FP0(pipe);
3903                 dpll_reg = PCH_DPLL(pipe);
3904         } else {
3905                 fp_reg = FP0(pipe);
3906                 dpll_reg = DPLL(pipe);
3907         }
3908
3909         if (!has_edp_encoder) {
3910                 I915_WRITE(fp_reg, fp);
3911                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3912
3913                 POSTING_READ(dpll_reg);
3914                 udelay(150);
3915         }
3916
3917         /* enable transcoder DPLL */
3918         if (HAS_PCH_CPT(dev)) {
3919                 temp = I915_READ(PCH_DPLL_SEL);
3920                 if (pipe == 0)
3921                         temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL;
3922                 else
3923                         temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL;
3924                 I915_WRITE(PCH_DPLL_SEL, temp);
3925
3926                 POSTING_READ(PCH_DPLL_SEL);
3927                 udelay(150);
3928         }
3929
3930         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3931          * This is an exception to the general rule that mode_set doesn't turn
3932          * things on.
3933          */
3934         if (is_lvds) {
3935                 reg = LVDS;
3936                 if (HAS_PCH_SPLIT(dev))
3937                         reg = PCH_LVDS;
3938
3939                 temp = I915_READ(reg);
3940                 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
3941                 if (pipe == 1) {
3942                         if (HAS_PCH_CPT(dev))
3943                                 temp |= PORT_TRANS_B_SEL_CPT;
3944                         else
3945                                 temp |= LVDS_PIPEB_SELECT;
3946                 } else {
3947                         if (HAS_PCH_CPT(dev))
3948                                 temp &= ~PORT_TRANS_SEL_MASK;
3949                         else
3950                                 temp &= ~LVDS_PIPEB_SELECT;
3951                 }
3952                 /* set the corresponsding LVDS_BORDER bit */
3953                 temp |= dev_priv->lvds_border_bits;
3954                 /* Set the B0-B3 data pairs corresponding to whether we're going to
3955                  * set the DPLLs for dual-channel mode or not.
3956                  */
3957                 if (clock.p2 == 7)
3958                         temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3959                 else
3960                         temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3961
3962                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3963                  * appropriately here, but we need to look more thoroughly into how
3964                  * panels behave in the two modes.
3965                  */
3966                 /* set the dithering flag on non-PCH LVDS as needed */
3967                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
3968                         if (dev_priv->lvds_dither)
3969                                 temp |= LVDS_ENABLE_DITHER;
3970                         else
3971                                 temp &= ~LVDS_ENABLE_DITHER;
3972                 }
3973                 I915_WRITE(reg, temp);
3974         }
3975
3976         /* set the dithering flag and clear for anything other than a panel. */
3977         if (HAS_PCH_SPLIT(dev)) {
3978                 pipeconf &= ~PIPECONF_DITHER_EN;
3979                 pipeconf &= ~PIPECONF_DITHER_TYPE_MASK;
3980                 if (dev_priv->lvds_dither && (is_lvds || has_edp_encoder)) {
3981                         pipeconf |= PIPECONF_DITHER_EN;
3982                         pipeconf |= PIPECONF_DITHER_TYPE_ST1;
3983                 }
3984         }
3985
3986         if (is_dp)
3987                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3988         else if (HAS_PCH_SPLIT(dev)) {
3989                 /* For non-DP output, clear any trans DP clock recovery setting.*/
3990                 if (pipe == 0) {
3991                         I915_WRITE(TRANSA_DATA_M1, 0);
3992                         I915_WRITE(TRANSA_DATA_N1, 0);
3993                         I915_WRITE(TRANSA_DP_LINK_M1, 0);
3994                         I915_WRITE(TRANSA_DP_LINK_N1, 0);
3995                 } else {
3996                         I915_WRITE(TRANSB_DATA_M1, 0);
3997                         I915_WRITE(TRANSB_DATA_N1, 0);
3998                         I915_WRITE(TRANSB_DP_LINK_M1, 0);
3999                         I915_WRITE(TRANSB_DP_LINK_N1, 0);
4000                 }
4001         }
4002
4003         if (!has_edp_encoder) {
4004                 I915_WRITE(fp_reg, fp);
4005                 I915_WRITE(dpll_reg, dpll);
4006
4007                 /* Wait for the clocks to stabilize. */
4008                 POSTING_READ(dpll_reg);
4009                 udelay(150);
4010
4011                 if (IS_I965G(dev) && !HAS_PCH_SPLIT(dev)) {
4012                         temp = 0;
4013                         if (is_sdvo) {
4014                                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4015                                 if (temp > 1)
4016                                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4017                                 else
4018                                         temp = 0;
4019                         }
4020                         I915_WRITE(DPLL_MD(pipe), temp);
4021                 } else {
4022                         /* write it again -- the BIOS does, after all */
4023                         I915_WRITE(dpll_reg, dpll);
4024                 }
4025
4026                 /* Wait for the clocks to stabilize. */
4027                 POSTING_READ(dpll_reg);
4028                 udelay(150);
4029         }
4030
4031         intel_crtc->lowfreq_avail = false;
4032         if (is_lvds && has_reduced_clock && i915_powersave) {
4033                 I915_WRITE(fp_reg + 4, fp2);
4034                 intel_crtc->lowfreq_avail = true;
4035                 if (HAS_PIPE_CXSR(dev)) {
4036                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4037                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4038                 }
4039         } else {
4040                 I915_WRITE(fp_reg + 4, fp);
4041                 if (HAS_PIPE_CXSR(dev)) {
4042                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4043                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4044                 }
4045         }
4046
4047         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4048                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4049                 /* the chip adds 2 halflines automatically */
4050                 adjusted_mode->crtc_vdisplay -= 1;
4051                 adjusted_mode->crtc_vtotal -= 1;
4052                 adjusted_mode->crtc_vblank_start -= 1;
4053                 adjusted_mode->crtc_vblank_end -= 1;
4054                 adjusted_mode->crtc_vsync_end -= 1;
4055                 adjusted_mode->crtc_vsync_start -= 1;
4056         } else
4057                 pipeconf &= ~PIPECONF_INTERLACE_W_FIELD_INDICATION; /* progressive */
4058
4059         I915_WRITE(HTOTAL(pipe),
4060                    (adjusted_mode->crtc_hdisplay - 1) |
4061                    ((adjusted_mode->crtc_htotal - 1) << 16));
4062         I915_WRITE(HBLANK(pipe),
4063                    (adjusted_mode->crtc_hblank_start - 1) |
4064                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4065         I915_WRITE(HSYNC(pipe),
4066                    (adjusted_mode->crtc_hsync_start - 1) |
4067                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4068
4069         I915_WRITE(VTOTAL(pipe),
4070                    (adjusted_mode->crtc_vdisplay - 1) |
4071                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4072         I915_WRITE(VBLANK(pipe),
4073                    (adjusted_mode->crtc_vblank_start - 1) |
4074                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4075         I915_WRITE(VSYNC(pipe),
4076                    (adjusted_mode->crtc_vsync_start - 1) |
4077                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4078
4079         /* pipesrc and dspsize control the size that is scaled from,
4080          * which should always be the user's requested size.
4081          */
4082         if (!HAS_PCH_SPLIT(dev)) {
4083                 I915_WRITE(DSPSIZE(plane),
4084                            ((mode->vdisplay - 1) << 16) |
4085                            (mode->hdisplay - 1));
4086                 I915_WRITE(DSPPOS(plane), 0);
4087         }
4088         I915_WRITE(PIPESRC(pipe),
4089                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4090
4091         if (HAS_PCH_SPLIT(dev)) {
4092                 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
4093                 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
4094                 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
4095                 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
4096
4097                 if (has_edp_encoder) {
4098                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
4099                 } else {
4100                         /* enable FDI RX PLL too */
4101                         reg = FDI_RX_CTL(pipe);
4102                         temp = I915_READ(reg);
4103                         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
4104
4105                         POSTING_READ(reg);
4106                         udelay(200);
4107
4108                         /* enable FDI TX PLL too */
4109                         reg = FDI_TX_CTL(pipe);
4110                         temp = I915_READ(reg);
4111                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
4112
4113                         /* enable FDI RX PCDCLK */
4114                         reg = FDI_RX_CTL(pipe);
4115                         temp = I915_READ(reg);
4116                         I915_WRITE(reg, temp | FDI_PCDCLK);
4117
4118                         POSTING_READ(reg);
4119                         udelay(200);
4120                 }
4121         }
4122
4123         I915_WRITE(PIPECONF(pipe), pipeconf);
4124         POSTING_READ(PIPECONF(pipe));
4125
4126         intel_wait_for_vblank(dev, pipe);
4127
4128         if (IS_IRONLAKE(dev)) {
4129                 /* enable address swizzle for tiling buffer */
4130                 temp = I915_READ(DISP_ARB_CTL);
4131                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
4132         }
4133
4134         I915_WRITE(DSPCNTR(plane), dspcntr);
4135
4136         ret = intel_pipe_set_base(crtc, x, y, old_fb);
4137
4138         intel_update_watermarks(dev);
4139
4140         drm_vblank_post_modeset(dev, pipe);
4141
4142         return ret;
4143 }
4144
4145 /** Loads the palette/gamma unit for the CRTC with the prepared values */
4146 void intel_crtc_load_lut(struct drm_crtc *crtc)
4147 {
4148         struct drm_device *dev = crtc->dev;
4149         struct drm_i915_private *dev_priv = dev->dev_private;
4150         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4151         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
4152         int i;
4153
4154         /* The clocks have to be on to load the palette. */
4155         if (!crtc->enabled)
4156                 return;
4157
4158         /* use legacy palette for Ironlake */
4159         if (HAS_PCH_SPLIT(dev))
4160                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
4161                                                    LGC_PALETTE_B;
4162
4163         for (i = 0; i < 256; i++) {
4164                 I915_WRITE(palreg + 4 * i,
4165                            (intel_crtc->lut_r[i] << 16) |
4166                            (intel_crtc->lut_g[i] << 8) |
4167                            intel_crtc->lut_b[i]);
4168         }
4169 }
4170
4171 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
4172 {
4173         struct drm_device *dev = crtc->dev;
4174         struct drm_i915_private *dev_priv = dev->dev_private;
4175         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4176         bool visible = base != 0;
4177         u32 cntl;
4178
4179         if (intel_crtc->cursor_visible == visible)
4180                 return;
4181
4182         cntl = I915_READ(CURACNTR);
4183         if (visible) {
4184                 /* On these chipsets we can only modify the base whilst
4185                  * the cursor is disabled.
4186                  */
4187                 I915_WRITE(CURABASE, base);
4188
4189                 cntl &= ~(CURSOR_FORMAT_MASK);
4190                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
4191                 cntl |= CURSOR_ENABLE |
4192                         CURSOR_GAMMA_ENABLE |
4193                         CURSOR_FORMAT_ARGB;
4194         } else
4195                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
4196         I915_WRITE(CURACNTR, cntl);
4197
4198         intel_crtc->cursor_visible = visible;
4199 }
4200
4201 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
4202 {
4203         struct drm_device *dev = crtc->dev;
4204         struct drm_i915_private *dev_priv = dev->dev_private;
4205         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4206         int pipe = intel_crtc->pipe;
4207         bool visible = base != 0;
4208
4209         if (intel_crtc->cursor_visible != visible) {
4210                 uint32_t cntl = I915_READ(pipe == 0 ? CURACNTR : CURBCNTR);
4211                 if (base) {
4212                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
4213                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
4214                         cntl |= pipe << 28; /* Connect to correct pipe */
4215                 } else {
4216                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
4217                         cntl |= CURSOR_MODE_DISABLE;
4218                 }
4219                 I915_WRITE(pipe == 0 ? CURACNTR : CURBCNTR, cntl);
4220
4221                 intel_crtc->cursor_visible = visible;
4222         }
4223         /* and commit changes on next vblank */
4224         I915_WRITE(pipe == 0 ? CURABASE : CURBBASE, base);
4225 }
4226
4227 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
4228 static void intel_crtc_update_cursor(struct drm_crtc *crtc)
4229 {
4230         struct drm_device *dev = crtc->dev;
4231         struct drm_i915_private *dev_priv = dev->dev_private;
4232         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4233         int pipe = intel_crtc->pipe;
4234         int x = intel_crtc->cursor_x;
4235         int y = intel_crtc->cursor_y;
4236         u32 base, pos;
4237         bool visible;
4238
4239         pos = 0;
4240
4241         if (intel_crtc->cursor_on && crtc->fb) {
4242                 base = intel_crtc->cursor_addr;
4243                 if (x > (int) crtc->fb->width)
4244                         base = 0;
4245
4246                 if (y > (int) crtc->fb->height)
4247                         base = 0;
4248         } else
4249                 base = 0;
4250
4251         if (x < 0) {
4252                 if (x + intel_crtc->cursor_width < 0)
4253                         base = 0;
4254
4255                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
4256                 x = -x;
4257         }
4258         pos |= x << CURSOR_X_SHIFT;
4259
4260         if (y < 0) {
4261                 if (y + intel_crtc->cursor_height < 0)
4262                         base = 0;
4263
4264                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
4265                 y = -y;
4266         }
4267         pos |= y << CURSOR_Y_SHIFT;
4268
4269         visible = base != 0;
4270         if (!visible && !intel_crtc->cursor_visible)
4271                 return;
4272
4273         I915_WRITE(pipe == 0 ? CURAPOS : CURBPOS, pos);
4274         if (IS_845G(dev) || IS_I865G(dev))
4275                 i845_update_cursor(crtc, base);
4276         else
4277                 i9xx_update_cursor(crtc, base);
4278
4279         if (visible)
4280                 intel_mark_busy(dev, to_intel_framebuffer(crtc->fb)->obj);
4281 }
4282
4283 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
4284                                  struct drm_file *file_priv,
4285                                  uint32_t handle,
4286                                  uint32_t width, uint32_t height)
4287 {
4288         struct drm_device *dev = crtc->dev;
4289         struct drm_i915_private *dev_priv = dev->dev_private;
4290         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4291         struct drm_gem_object *bo;
4292         struct drm_i915_gem_object *obj_priv;
4293         uint32_t addr;
4294         int ret;
4295
4296         DRM_DEBUG_KMS("\n");
4297
4298         /* if we want to turn off the cursor ignore width and height */
4299         if (!handle) {
4300                 DRM_DEBUG_KMS("cursor off\n");
4301                 addr = 0;
4302                 bo = NULL;
4303                 mutex_lock(&dev->struct_mutex);
4304                 goto finish;
4305         }
4306
4307         /* Currently we only support 64x64 cursors */
4308         if (width != 64 || height != 64) {
4309                 DRM_ERROR("we currently only support 64x64 cursors\n");
4310                 return -EINVAL;
4311         }
4312
4313         bo = drm_gem_object_lookup(dev, file_priv, handle);
4314         if (!bo)
4315                 return -ENOENT;
4316
4317         obj_priv = to_intel_bo(bo);
4318
4319         if (bo->size < width * height * 4) {
4320                 DRM_ERROR("buffer is to small\n");
4321                 ret = -ENOMEM;
4322                 goto fail;
4323         }
4324
4325         /* we only need to pin inside GTT if cursor is non-phy */
4326         mutex_lock(&dev->struct_mutex);
4327         if (!dev_priv->info->cursor_needs_physical) {
4328                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
4329                 if (ret) {
4330                         DRM_ERROR("failed to pin cursor bo\n");
4331                         goto fail_locked;
4332                 }
4333
4334                 ret = i915_gem_object_set_to_gtt_domain(bo, 0);
4335                 if (ret) {
4336                         DRM_ERROR("failed to move cursor bo into the GTT\n");
4337                         goto fail_unpin;
4338                 }
4339
4340                 addr = obj_priv->gtt_offset;
4341         } else {
4342                 int align = IS_I830(dev) ? 16 * 1024 : 256;
4343                 ret = i915_gem_attach_phys_object(dev, bo,
4344                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
4345                                                   align);
4346                 if (ret) {
4347                         DRM_ERROR("failed to attach phys object\n");
4348                         goto fail_locked;
4349                 }
4350                 addr = obj_priv->phys_obj->handle->busaddr;
4351         }
4352
4353         if (!IS_I9XX(dev))
4354                 I915_WRITE(CURSIZE, (height << 12) | width);
4355
4356  finish:
4357         if (intel_crtc->cursor_bo) {
4358                 if (dev_priv->info->cursor_needs_physical) {
4359                         if (intel_crtc->cursor_bo != bo)
4360                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
4361                 } else
4362                         i915_gem_object_unpin(intel_crtc->cursor_bo);
4363                 drm_gem_object_unreference(intel_crtc->cursor_bo);
4364         }
4365
4366         mutex_unlock(&dev->struct_mutex);
4367
4368         intel_crtc->cursor_addr = addr;
4369         intel_crtc->cursor_bo = bo;
4370         intel_crtc->cursor_width = width;
4371         intel_crtc->cursor_height = height;
4372
4373         intel_crtc_update_cursor(crtc);
4374
4375         return 0;
4376 fail_unpin:
4377         i915_gem_object_unpin(bo);
4378 fail_locked:
4379         mutex_unlock(&dev->struct_mutex);
4380 fail:
4381         drm_gem_object_unreference_unlocked(bo);
4382         return ret;
4383 }
4384
4385 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
4386 {
4387         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4388
4389         intel_crtc->cursor_x = x;
4390         intel_crtc->cursor_y = y;
4391
4392         intel_crtc_update_cursor(crtc);
4393
4394         return 0;
4395 }
4396
4397 /** Sets the color ramps on behalf of RandR */
4398 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
4399                                  u16 blue, int regno)
4400 {
4401         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4402
4403         intel_crtc->lut_r[regno] = red >> 8;
4404         intel_crtc->lut_g[regno] = green >> 8;
4405         intel_crtc->lut_b[regno] = blue >> 8;
4406 }
4407
4408 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
4409                              u16 *blue, int regno)
4410 {
4411         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4412
4413         *red = intel_crtc->lut_r[regno] << 8;
4414         *green = intel_crtc->lut_g[regno] << 8;
4415         *blue = intel_crtc->lut_b[regno] << 8;
4416 }
4417
4418 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
4419                                  u16 *blue, uint32_t start, uint32_t size)
4420 {
4421         int end = (start + size > 256) ? 256 : start + size, i;
4422         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4423
4424         for (i = start; i < end; i++) {
4425                 intel_crtc->lut_r[i] = red[i] >> 8;
4426                 intel_crtc->lut_g[i] = green[i] >> 8;
4427                 intel_crtc->lut_b[i] = blue[i] >> 8;
4428         }
4429
4430         intel_crtc_load_lut(crtc);
4431 }
4432
4433 /**
4434  * Get a pipe with a simple mode set on it for doing load-based monitor
4435  * detection.
4436  *
4437  * It will be up to the load-detect code to adjust the pipe as appropriate for
4438  * its requirements.  The pipe will be connected to no other encoders.
4439  *
4440  * Currently this code will only succeed if there is a pipe with no encoders
4441  * configured for it.  In the future, it could choose to temporarily disable
4442  * some outputs to free up a pipe for its use.
4443  *
4444  * \return crtc, or NULL if no pipes are available.
4445  */
4446
4447 /* VESA 640x480x72Hz mode to set on the pipe */
4448 static struct drm_display_mode load_detect_mode = {
4449         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
4450                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
4451 };
4452
4453 struct drm_crtc *intel_get_load_detect_pipe(struct intel_encoder *intel_encoder,
4454                                             struct drm_connector *connector,
4455                                             struct drm_display_mode *mode,
4456                                             int *dpms_mode)
4457 {
4458         struct intel_crtc *intel_crtc;
4459         struct drm_crtc *possible_crtc;
4460         struct drm_crtc *supported_crtc =NULL;
4461         struct drm_encoder *encoder = &intel_encoder->base;
4462         struct drm_crtc *crtc = NULL;
4463         struct drm_device *dev = encoder->dev;
4464         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4465         struct drm_crtc_helper_funcs *crtc_funcs;
4466         int i = -1;
4467
4468         /*
4469          * Algorithm gets a little messy:
4470          *   - if the connector already has an assigned crtc, use it (but make
4471          *     sure it's on first)
4472          *   - try to find the first unused crtc that can drive this connector,
4473          *     and use that if we find one
4474          *   - if there are no unused crtcs available, try to use the first
4475          *     one we found that supports the connector
4476          */
4477
4478         /* See if we already have a CRTC for this connector */
4479         if (encoder->crtc) {
4480                 crtc = encoder->crtc;
4481                 /* Make sure the crtc and connector are running */
4482                 intel_crtc = to_intel_crtc(crtc);
4483                 *dpms_mode = intel_crtc->dpms_mode;
4484                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4485                         crtc_funcs = crtc->helper_private;
4486                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4487                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
4488                 }
4489                 return crtc;
4490         }
4491
4492         /* Find an unused one (if possible) */
4493         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
4494                 i++;
4495                 if (!(encoder->possible_crtcs & (1 << i)))
4496                         continue;
4497                 if (!possible_crtc->enabled) {
4498                         crtc = possible_crtc;
4499                         break;
4500                 }
4501                 if (!supported_crtc)
4502                         supported_crtc = possible_crtc;
4503         }
4504
4505         /*
4506          * If we didn't find an unused CRTC, don't use any.
4507          */
4508         if (!crtc) {
4509                 return NULL;
4510         }
4511
4512         encoder->crtc = crtc;
4513         connector->encoder = encoder;
4514         intel_encoder->load_detect_temp = true;
4515
4516         intel_crtc = to_intel_crtc(crtc);
4517         *dpms_mode = intel_crtc->dpms_mode;
4518
4519         if (!crtc->enabled) {
4520                 if (!mode)
4521                         mode = &load_detect_mode;
4522                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
4523         } else {
4524                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
4525                         crtc_funcs = crtc->helper_private;
4526                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
4527                 }
4528
4529                 /* Add this connector to the crtc */
4530                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
4531                 encoder_funcs->commit(encoder);
4532         }
4533         /* let the connector get through one full cycle before testing */
4534         intel_wait_for_vblank(dev, intel_crtc->pipe);
4535
4536         return crtc;
4537 }
4538
4539 void intel_release_load_detect_pipe(struct intel_encoder *intel_encoder,
4540                                     struct drm_connector *connector, int dpms_mode)
4541 {
4542         struct drm_encoder *encoder = &intel_encoder->base;
4543         struct drm_device *dev = encoder->dev;
4544         struct drm_crtc *crtc = encoder->crtc;
4545         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
4546         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
4547
4548         if (intel_encoder->load_detect_temp) {
4549                 encoder->crtc = NULL;
4550                 connector->encoder = NULL;
4551                 intel_encoder->load_detect_temp = false;
4552                 crtc->enabled = drm_helper_crtc_in_use(crtc);
4553                 drm_helper_disable_unused_functions(dev);
4554         }
4555
4556         /* Switch crtc and encoder back off if necessary */
4557         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
4558                 if (encoder->crtc == crtc)
4559                         encoder_funcs->dpms(encoder, dpms_mode);
4560                 crtc_funcs->dpms(crtc, dpms_mode);
4561         }
4562 }
4563
4564 /* Returns the clock of the currently programmed mode of the given pipe. */
4565 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
4566 {
4567         struct drm_i915_private *dev_priv = dev->dev_private;
4568         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4569         int pipe = intel_crtc->pipe;
4570         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
4571         u32 fp;
4572         intel_clock_t clock;
4573
4574         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
4575                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
4576         else
4577                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
4578
4579         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
4580         if (IS_PINEVIEW(dev)) {
4581                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
4582                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
4583         } else {
4584                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
4585                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
4586         }
4587
4588         if (IS_I9XX(dev)) {
4589                 if (IS_PINEVIEW(dev))
4590                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
4591                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
4592                 else
4593                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
4594                                DPLL_FPA01_P1_POST_DIV_SHIFT);
4595
4596                 switch (dpll & DPLL_MODE_MASK) {
4597                 case DPLLB_MODE_DAC_SERIAL:
4598                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
4599                                 5 : 10;
4600                         break;
4601                 case DPLLB_MODE_LVDS:
4602                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
4603                                 7 : 14;
4604                         break;
4605                 default:
4606                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
4607                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
4608                         return 0;
4609                 }
4610
4611                 /* XXX: Handle the 100Mhz refclk */
4612                 intel_clock(dev, 96000, &clock);
4613         } else {
4614                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
4615
4616                 if (is_lvds) {
4617                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
4618                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
4619                         clock.p2 = 14;
4620
4621                         if ((dpll & PLL_REF_INPUT_MASK) ==
4622                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
4623                                 /* XXX: might not be 66MHz */
4624                                 intel_clock(dev, 66000, &clock);
4625                         } else
4626                                 intel_clock(dev, 48000, &clock);
4627                 } else {
4628                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
4629                                 clock.p1 = 2;
4630                         else {
4631                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
4632                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
4633                         }
4634                         if (dpll & PLL_P2_DIVIDE_BY_4)
4635                                 clock.p2 = 4;
4636                         else
4637                                 clock.p2 = 2;
4638
4639                         intel_clock(dev, 48000, &clock);
4640                 }
4641         }
4642
4643         /* XXX: It would be nice to validate the clocks, but we can't reuse
4644          * i830PllIsValid() because it relies on the xf86_config connector
4645          * configuration being accurate, which it isn't necessarily.
4646          */
4647
4648         return clock.dot;
4649 }
4650
4651 /** Returns the currently programmed mode of the given pipe. */
4652 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
4653                                              struct drm_crtc *crtc)
4654 {
4655         struct drm_i915_private *dev_priv = dev->dev_private;
4656         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4657         int pipe = intel_crtc->pipe;
4658         struct drm_display_mode *mode;
4659         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
4660         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
4661         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
4662         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
4663
4664         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
4665         if (!mode)
4666                 return NULL;
4667
4668         mode->clock = intel_crtc_clock_get(dev, crtc);
4669         mode->hdisplay = (htot & 0xffff) + 1;
4670         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
4671         mode->hsync_start = (hsync & 0xffff) + 1;
4672         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
4673         mode->vdisplay = (vtot & 0xffff) + 1;
4674         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
4675         mode->vsync_start = (vsync & 0xffff) + 1;
4676         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
4677
4678         drm_mode_set_name(mode);
4679         drm_mode_set_crtcinfo(mode, 0);
4680
4681         return mode;
4682 }
4683
4684 #define GPU_IDLE_TIMEOUT 500 /* ms */
4685
4686 /* When this timer fires, we've been idle for awhile */
4687 static void intel_gpu_idle_timer(unsigned long arg)
4688 {
4689         struct drm_device *dev = (struct drm_device *)arg;
4690         drm_i915_private_t *dev_priv = dev->dev_private;
4691
4692         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4693
4694         dev_priv->busy = false;
4695
4696         queue_work(dev_priv->wq, &dev_priv->idle_work);
4697 }
4698
4699 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
4700
4701 static void intel_crtc_idle_timer(unsigned long arg)
4702 {
4703         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
4704         struct drm_crtc *crtc = &intel_crtc->base;
4705         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
4706
4707         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
4708
4709         intel_crtc->busy = false;
4710
4711         queue_work(dev_priv->wq, &dev_priv->idle_work);
4712 }
4713
4714 static void intel_increase_pllclock(struct drm_crtc *crtc)
4715 {
4716         struct drm_device *dev = crtc->dev;
4717         drm_i915_private_t *dev_priv = dev->dev_private;
4718         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4719         int pipe = intel_crtc->pipe;
4720         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4721         int dpll = I915_READ(dpll_reg);
4722
4723         if (HAS_PCH_SPLIT(dev))
4724                 return;
4725
4726         if (!dev_priv->lvds_downclock_avail)
4727                 return;
4728
4729         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
4730                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
4731
4732                 /* Unlock panel regs */
4733                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4734                            PANEL_UNLOCK_REGS);
4735
4736                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
4737                 I915_WRITE(dpll_reg, dpll);
4738                 dpll = I915_READ(dpll_reg);
4739                 intel_wait_for_vblank(dev, pipe);
4740                 dpll = I915_READ(dpll_reg);
4741                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
4742                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
4743
4744                 /* ...and lock them again */
4745                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4746         }
4747
4748         /* Schedule downclock */
4749         mod_timer(&intel_crtc->idle_timer, jiffies +
4750                   msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4751 }
4752
4753 static void intel_decrease_pllclock(struct drm_crtc *crtc)
4754 {
4755         struct drm_device *dev = crtc->dev;
4756         drm_i915_private_t *dev_priv = dev->dev_private;
4757         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4758         int pipe = intel_crtc->pipe;
4759         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
4760         int dpll = I915_READ(dpll_reg);
4761
4762         if (HAS_PCH_SPLIT(dev))
4763                 return;
4764
4765         if (!dev_priv->lvds_downclock_avail)
4766                 return;
4767
4768         /*
4769          * Since this is called by a timer, we should never get here in
4770          * the manual case.
4771          */
4772         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
4773                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
4774
4775                 /* Unlock panel regs */
4776                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) |
4777                            PANEL_UNLOCK_REGS);
4778
4779                 dpll |= DISPLAY_RATE_SELECT_FPA1;
4780                 I915_WRITE(dpll_reg, dpll);
4781                 dpll = I915_READ(dpll_reg);
4782                 intel_wait_for_vblank(dev, pipe);
4783                 dpll = I915_READ(dpll_reg);
4784                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
4785                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
4786
4787                 /* ...and lock them again */
4788                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4789         }
4790
4791 }
4792
4793 /**
4794  * intel_idle_update - adjust clocks for idleness
4795  * @work: work struct
4796  *
4797  * Either the GPU or display (or both) went idle.  Check the busy status
4798  * here and adjust the CRTC and GPU clocks as necessary.
4799  */
4800 static void intel_idle_update(struct work_struct *work)
4801 {
4802         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4803                                                     idle_work);
4804         struct drm_device *dev = dev_priv->dev;
4805         struct drm_crtc *crtc;
4806         struct intel_crtc *intel_crtc;
4807         int enabled = 0;
4808
4809         if (!i915_powersave)
4810                 return;
4811
4812         mutex_lock(&dev->struct_mutex);
4813
4814         i915_update_gfx_val(dev_priv);
4815
4816         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4817                 /* Skip inactive CRTCs */
4818                 if (!crtc->fb)
4819                         continue;
4820
4821                 enabled++;
4822                 intel_crtc = to_intel_crtc(crtc);
4823                 if (!intel_crtc->busy)
4824                         intel_decrease_pllclock(crtc);
4825         }
4826
4827         if ((enabled == 1) && (IS_I945G(dev) || IS_I945GM(dev))) {
4828                 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4829                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4830         }
4831
4832         mutex_unlock(&dev->struct_mutex);
4833 }
4834
4835 /**
4836  * intel_mark_busy - mark the GPU and possibly the display busy
4837  * @dev: drm device
4838  * @obj: object we're operating on
4839  *
4840  * Callers can use this function to indicate that the GPU is busy processing
4841  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
4842  * buffer), we'll also mark the display as busy, so we know to increase its
4843  * clock frequency.
4844  */
4845 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4846 {
4847         drm_i915_private_t *dev_priv = dev->dev_private;
4848         struct drm_crtc *crtc = NULL;
4849         struct intel_framebuffer *intel_fb;
4850         struct intel_crtc *intel_crtc;
4851
4852         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4853                 return;
4854
4855         if (!dev_priv->busy) {
4856                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4857                         u32 fw_blc_self;
4858
4859                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4860                         fw_blc_self = I915_READ(FW_BLC_SELF);
4861                         fw_blc_self &= ~FW_BLC_SELF_EN;
4862                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4863                 }
4864                 dev_priv->busy = true;
4865         } else
4866                 mod_timer(&dev_priv->idle_timer, jiffies +
4867                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4868
4869         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4870                 if (!crtc->fb)
4871                         continue;
4872
4873                 intel_crtc = to_intel_crtc(crtc);
4874                 intel_fb = to_intel_framebuffer(crtc->fb);
4875                 if (intel_fb->obj == obj) {
4876                         if (!intel_crtc->busy) {
4877                                 if (IS_I945G(dev) || IS_I945GM(dev)) {
4878                                         u32 fw_blc_self;
4879
4880                                         DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4881                                         fw_blc_self = I915_READ(FW_BLC_SELF);
4882                                         fw_blc_self &= ~FW_BLC_SELF_EN;
4883                                         I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4884                                 }
4885                                 /* Non-busy -> busy, upclock */
4886                                 intel_increase_pllclock(crtc);
4887                                 intel_crtc->busy = true;
4888                         } else {
4889                                 /* Busy -> busy, put off timer */
4890                                 mod_timer(&intel_crtc->idle_timer, jiffies +
4891                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4892                         }
4893                 }
4894         }
4895 }
4896
4897 static void intel_crtc_destroy(struct drm_crtc *crtc)
4898 {
4899         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4900         struct drm_device *dev = crtc->dev;
4901         struct intel_unpin_work *work;
4902         unsigned long flags;
4903
4904         spin_lock_irqsave(&dev->event_lock, flags);
4905         work = intel_crtc->unpin_work;
4906         intel_crtc->unpin_work = NULL;
4907         spin_unlock_irqrestore(&dev->event_lock, flags);
4908
4909         if (work) {
4910                 cancel_work_sync(&work->work);
4911                 kfree(work);
4912         }
4913
4914         drm_crtc_cleanup(crtc);
4915
4916         kfree(intel_crtc);
4917 }
4918
4919 static void intel_unpin_work_fn(struct work_struct *__work)
4920 {
4921         struct intel_unpin_work *work =
4922                 container_of(__work, struct intel_unpin_work, work);
4923
4924         mutex_lock(&work->dev->struct_mutex);
4925         i915_gem_object_unpin(work->old_fb_obj);
4926         drm_gem_object_unreference(work->pending_flip_obj);
4927         drm_gem_object_unreference(work->old_fb_obj);
4928         mutex_unlock(&work->dev->struct_mutex);
4929         kfree(work);
4930 }
4931
4932 static void do_intel_finish_page_flip(struct drm_device *dev,
4933                                       struct drm_crtc *crtc)
4934 {
4935         drm_i915_private_t *dev_priv = dev->dev_private;
4936         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4937         struct intel_unpin_work *work;
4938         struct drm_i915_gem_object *obj_priv;
4939         struct drm_pending_vblank_event *e;
4940         struct timeval now;
4941         unsigned long flags;
4942
4943         /* Ignore early vblank irqs */
4944         if (intel_crtc == NULL)
4945                 return;
4946
4947         spin_lock_irqsave(&dev->event_lock, flags);
4948         work = intel_crtc->unpin_work;
4949         if (work == NULL || !work->pending) {
4950                 spin_unlock_irqrestore(&dev->event_lock, flags);
4951                 return;
4952         }
4953
4954         intel_crtc->unpin_work = NULL;
4955         drm_vblank_put(dev, intel_crtc->pipe);
4956
4957         if (work->event) {
4958                 e = work->event;
4959                 do_gettimeofday(&now);
4960                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4961                 e->event.tv_sec = now.tv_sec;
4962                 e->event.tv_usec = now.tv_usec;
4963                 list_add_tail(&e->base.link,
4964                               &e->base.file_priv->event_list);
4965                 wake_up_interruptible(&e->base.file_priv->event_wait);
4966         }
4967
4968         spin_unlock_irqrestore(&dev->event_lock, flags);
4969
4970         obj_priv = to_intel_bo(work->pending_flip_obj);
4971
4972         /* Initial scanout buffer will have a 0 pending flip count */
4973         if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4974             atomic_dec_and_test(&obj_priv->pending_flip))
4975                 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4976         schedule_work(&work->work);
4977
4978         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
4979 }
4980
4981 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4982 {
4983         drm_i915_private_t *dev_priv = dev->dev_private;
4984         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4985
4986         do_intel_finish_page_flip(dev, crtc);
4987 }
4988
4989 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
4990 {
4991         drm_i915_private_t *dev_priv = dev->dev_private;
4992         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
4993
4994         do_intel_finish_page_flip(dev, crtc);
4995 }
4996
4997 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4998 {
4999         drm_i915_private_t *dev_priv = dev->dev_private;
5000         struct intel_crtc *intel_crtc =
5001                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
5002         unsigned long flags;
5003
5004         spin_lock_irqsave(&dev->event_lock, flags);
5005         if (intel_crtc->unpin_work) {
5006                 if ((++intel_crtc->unpin_work->pending) > 1)
5007                         DRM_ERROR("Prepared flip multiple times\n");
5008         } else {
5009                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
5010         }
5011         spin_unlock_irqrestore(&dev->event_lock, flags);
5012 }
5013
5014 static int intel_crtc_page_flip(struct drm_crtc *crtc,
5015                                 struct drm_framebuffer *fb,
5016                                 struct drm_pending_vblank_event *event)
5017 {
5018         struct drm_device *dev = crtc->dev;
5019         struct drm_i915_private *dev_priv = dev->dev_private;
5020         struct intel_framebuffer *intel_fb;
5021         struct drm_i915_gem_object *obj_priv;
5022         struct drm_gem_object *obj;
5023         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5024         struct intel_unpin_work *work;
5025         unsigned long flags, offset;
5026         int pipe = intel_crtc->pipe;
5027         u32 pf, pipesrc;
5028         int ret;
5029
5030         work = kzalloc(sizeof *work, GFP_KERNEL);
5031         if (work == NULL)
5032                 return -ENOMEM;
5033
5034         work->event = event;
5035         work->dev = crtc->dev;
5036         intel_fb = to_intel_framebuffer(crtc->fb);
5037         work->old_fb_obj = intel_fb->obj;
5038         INIT_WORK(&work->work, intel_unpin_work_fn);
5039
5040         /* We borrow the event spin lock for protecting unpin_work */
5041         spin_lock_irqsave(&dev->event_lock, flags);
5042         if (intel_crtc->unpin_work) {
5043                 spin_unlock_irqrestore(&dev->event_lock, flags);
5044                 kfree(work);
5045
5046                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
5047                 return -EBUSY;
5048         }
5049         intel_crtc->unpin_work = work;
5050         spin_unlock_irqrestore(&dev->event_lock, flags);
5051
5052         intel_fb = to_intel_framebuffer(fb);
5053         obj = intel_fb->obj;
5054
5055         mutex_lock(&dev->struct_mutex);
5056         ret = intel_pin_and_fence_fb_obj(dev, obj);
5057         if (ret)
5058                 goto cleanup_work;
5059
5060         /* Reference the objects for the scheduled work. */
5061         drm_gem_object_reference(work->old_fb_obj);
5062         drm_gem_object_reference(obj);
5063
5064         crtc->fb = fb;
5065         ret = i915_gem_object_flush_write_domain(obj);
5066         if (ret)
5067                 goto cleanup_objs;
5068
5069         ret = drm_vblank_get(dev, intel_crtc->pipe);
5070         if (ret)
5071                 goto cleanup_objs;
5072
5073         obj_priv = to_intel_bo(obj);
5074         atomic_inc(&obj_priv->pending_flip);
5075         work->pending_flip_obj = obj;
5076
5077         if (IS_GEN3(dev) || IS_GEN2(dev)) {
5078                 u32 flip_mask;
5079
5080                 if (intel_crtc->plane)
5081                         flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
5082                 else
5083                         flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
5084
5085                 BEGIN_LP_RING(2);
5086                 OUT_RING(MI_WAIT_FOR_EVENT | flip_mask);
5087                 OUT_RING(0);
5088                 ADVANCE_LP_RING();
5089         }
5090
5091         work->enable_stall_check = true;
5092
5093         /* Offset into the new buffer for cases of shared fbs between CRTCs */
5094         offset = crtc->y * fb->pitch + crtc->x * fb->bits_per_pixel/8;
5095
5096         BEGIN_LP_RING(4);
5097         switch(INTEL_INFO(dev)->gen) {
5098         case 2:
5099                 OUT_RING(MI_DISPLAY_FLIP |
5100                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5101                 OUT_RING(fb->pitch);
5102                 OUT_RING(obj_priv->gtt_offset + offset);
5103                 OUT_RING(MI_NOOP);
5104                 break;
5105
5106         case 3:
5107                 OUT_RING(MI_DISPLAY_FLIP_I915 |
5108                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5109                 OUT_RING(fb->pitch);
5110                 OUT_RING(obj_priv->gtt_offset + offset);
5111                 OUT_RING(MI_NOOP);
5112                 break;
5113
5114         case 4:
5115         case 5:
5116                 /* i965+ uses the linear or tiled offsets from the
5117                  * Display Registers (which do not change across a page-flip)
5118                  * so we need only reprogram the base address.
5119                  */
5120                 OUT_RING(MI_DISPLAY_FLIP |
5121                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5122                 OUT_RING(fb->pitch);
5123                 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
5124
5125                 /* XXX Enabling the panel-fitter across page-flip is so far
5126                  * untested on non-native modes, so ignore it for now.
5127                  * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5128                  */
5129                 pf = 0;
5130                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5131                 OUT_RING(pf | pipesrc);
5132                 break;
5133
5134         case 6:
5135                 OUT_RING(MI_DISPLAY_FLIP |
5136                          MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
5137                 OUT_RING(fb->pitch | obj_priv->tiling_mode);
5138                 OUT_RING(obj_priv->gtt_offset);
5139
5140                 pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
5141                 pipesrc = I915_READ(pipe == 0 ? PIPEASRC : PIPEBSRC) & 0x0fff0fff;
5142                 OUT_RING(pf | pipesrc);
5143                 break;
5144         }
5145         ADVANCE_LP_RING();
5146
5147         mutex_unlock(&dev->struct_mutex);
5148
5149         trace_i915_flip_request(intel_crtc->plane, obj);
5150
5151         return 0;
5152
5153 cleanup_objs:
5154         drm_gem_object_unreference(work->old_fb_obj);
5155         drm_gem_object_unreference(obj);
5156 cleanup_work:
5157         mutex_unlock(&dev->struct_mutex);
5158
5159         spin_lock_irqsave(&dev->event_lock, flags);
5160         intel_crtc->unpin_work = NULL;
5161         spin_unlock_irqrestore(&dev->event_lock, flags);
5162
5163         kfree(work);
5164
5165         return ret;
5166 }
5167
5168 static struct drm_crtc_helper_funcs intel_helper_funcs = {
5169         .dpms = intel_crtc_dpms,
5170         .mode_fixup = intel_crtc_mode_fixup,
5171         .mode_set = intel_crtc_mode_set,
5172         .mode_set_base = intel_pipe_set_base,
5173         .mode_set_base_atomic = intel_pipe_set_base_atomic,
5174         .load_lut = intel_crtc_load_lut,
5175 };
5176
5177 static const struct drm_crtc_funcs intel_crtc_funcs = {
5178         .cursor_set = intel_crtc_cursor_set,
5179         .cursor_move = intel_crtc_cursor_move,
5180         .gamma_set = intel_crtc_gamma_set,
5181         .set_config = drm_crtc_helper_set_config,
5182         .destroy = intel_crtc_destroy,
5183         .page_flip = intel_crtc_page_flip,
5184 };
5185
5186
5187 static void intel_crtc_init(struct drm_device *dev, int pipe)
5188 {
5189         drm_i915_private_t *dev_priv = dev->dev_private;
5190         struct intel_crtc *intel_crtc;
5191         int i;
5192
5193         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
5194         if (intel_crtc == NULL)
5195                 return;
5196
5197         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
5198
5199         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
5200         intel_crtc->pipe = pipe;
5201         intel_crtc->plane = pipe;
5202         for (i = 0; i < 256; i++) {
5203                 intel_crtc->lut_r[i] = i;
5204                 intel_crtc->lut_g[i] = i;
5205                 intel_crtc->lut_b[i] = i;
5206         }
5207
5208         /* Swap pipes & planes for FBC on pre-965 */
5209         intel_crtc->pipe = pipe;
5210         intel_crtc->plane = pipe;
5211         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
5212                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
5213                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
5214         }
5215
5216         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
5217                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
5218         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
5219         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
5220
5221         intel_crtc->cursor_addr = 0;
5222         intel_crtc->dpms_mode = -1;
5223
5224         if (HAS_PCH_SPLIT(dev)) {
5225                 intel_helper_funcs.prepare = ironlake_crtc_prepare;
5226                 intel_helper_funcs.commit = ironlake_crtc_commit;
5227         } else {
5228                 intel_helper_funcs.prepare = i9xx_crtc_prepare;
5229                 intel_helper_funcs.commit = i9xx_crtc_commit;
5230         }
5231
5232         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
5233
5234         intel_crtc->busy = false;
5235
5236         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
5237                     (unsigned long)intel_crtc);
5238 }
5239
5240 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
5241                                 struct drm_file *file_priv)
5242 {
5243         drm_i915_private_t *dev_priv = dev->dev_private;
5244         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
5245         struct drm_mode_object *drmmode_obj;
5246         struct intel_crtc *crtc;
5247
5248         if (!dev_priv) {
5249                 DRM_ERROR("called with no initialization\n");
5250                 return -EINVAL;
5251         }
5252
5253         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
5254                         DRM_MODE_OBJECT_CRTC);
5255
5256         if (!drmmode_obj) {
5257                 DRM_ERROR("no such CRTC id\n");
5258                 return -EINVAL;
5259         }
5260
5261         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
5262         pipe_from_crtc_id->pipe = crtc->pipe;
5263
5264         return 0;
5265 }
5266
5267 static int intel_encoder_clones(struct drm_device *dev, int type_mask)
5268 {
5269         struct intel_encoder *encoder;
5270         int index_mask = 0;
5271         int entry = 0;
5272
5273         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5274                 if (type_mask & encoder->clone_mask)
5275                         index_mask |= (1 << entry);
5276                 entry++;
5277         }
5278
5279         return index_mask;
5280 }
5281
5282 static void intel_setup_outputs(struct drm_device *dev)
5283 {
5284         struct drm_i915_private *dev_priv = dev->dev_private;
5285         struct intel_encoder *encoder;
5286         bool dpd_is_edp = false;
5287
5288         if (IS_MOBILE(dev) && !IS_I830(dev))
5289                 intel_lvds_init(dev);
5290
5291         if (HAS_PCH_SPLIT(dev)) {
5292                 dpd_is_edp = intel_dpd_is_edp(dev);
5293
5294                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
5295                         intel_dp_init(dev, DP_A);
5296
5297                 if (dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5298                         intel_dp_init(dev, PCH_DP_D);
5299         }
5300
5301         intel_crt_init(dev);
5302
5303         if (HAS_PCH_SPLIT(dev)) {
5304                 int found;
5305
5306                 if (I915_READ(HDMIB) & PORT_DETECTED) {
5307                         /* PCH SDVOB multiplex with HDMIB */
5308                         found = intel_sdvo_init(dev, PCH_SDVOB);
5309                         if (!found)
5310                                 intel_hdmi_init(dev, HDMIB);
5311                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
5312                                 intel_dp_init(dev, PCH_DP_B);
5313                 }
5314
5315                 if (I915_READ(HDMIC) & PORT_DETECTED)
5316                         intel_hdmi_init(dev, HDMIC);
5317
5318                 if (I915_READ(HDMID) & PORT_DETECTED)
5319                         intel_hdmi_init(dev, HDMID);
5320
5321                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
5322                         intel_dp_init(dev, PCH_DP_C);
5323
5324                 if (!dpd_is_edp && (I915_READ(PCH_DP_D) & DP_DETECTED))
5325                         intel_dp_init(dev, PCH_DP_D);
5326
5327         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
5328                 bool found = false;
5329
5330                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5331                         DRM_DEBUG_KMS("probing SDVOB\n");
5332                         found = intel_sdvo_init(dev, SDVOB);
5333                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
5334                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
5335                                 intel_hdmi_init(dev, SDVOB);
5336                         }
5337
5338                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
5339                                 DRM_DEBUG_KMS("probing DP_B\n");
5340                                 intel_dp_init(dev, DP_B);
5341                         }
5342                 }
5343
5344                 /* Before G4X SDVOC doesn't have its own detect register */
5345
5346                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
5347                         DRM_DEBUG_KMS("probing SDVOC\n");
5348                         found = intel_sdvo_init(dev, SDVOC);
5349                 }
5350
5351                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
5352
5353                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
5354                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
5355                                 intel_hdmi_init(dev, SDVOC);
5356                         }
5357                         if (SUPPORTS_INTEGRATED_DP(dev)) {
5358                                 DRM_DEBUG_KMS("probing DP_C\n");
5359                                 intel_dp_init(dev, DP_C);
5360                         }
5361                 }
5362
5363                 if (SUPPORTS_INTEGRATED_DP(dev) &&
5364                     (I915_READ(DP_D) & DP_DETECTED)) {
5365                         DRM_DEBUG_KMS("probing DP_D\n");
5366                         intel_dp_init(dev, DP_D);
5367                 }
5368         } else if (IS_GEN2(dev))
5369                 intel_dvo_init(dev);
5370
5371         if (SUPPORTS_TV(dev))
5372                 intel_tv_init(dev);
5373
5374         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
5375                 encoder->base.possible_crtcs = encoder->crtc_mask;
5376                 encoder->base.possible_clones =
5377                         intel_encoder_clones(dev, encoder->clone_mask);
5378         }
5379 }
5380
5381 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
5382 {
5383         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5384
5385         drm_framebuffer_cleanup(fb);
5386         drm_gem_object_unreference_unlocked(intel_fb->obj);
5387
5388         kfree(intel_fb);
5389 }
5390
5391 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
5392                                                 struct drm_file *file_priv,
5393                                                 unsigned int *handle)
5394 {
5395         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
5396         struct drm_gem_object *object = intel_fb->obj;
5397
5398         return drm_gem_handle_create(file_priv, object, handle);
5399 }
5400
5401 static const struct drm_framebuffer_funcs intel_fb_funcs = {
5402         .destroy = intel_user_framebuffer_destroy,
5403         .create_handle = intel_user_framebuffer_create_handle,
5404 };
5405
5406 int intel_framebuffer_init(struct drm_device *dev,
5407                            struct intel_framebuffer *intel_fb,
5408                            struct drm_mode_fb_cmd *mode_cmd,
5409                            struct drm_gem_object *obj)
5410 {
5411         struct drm_i915_gem_object *obj_priv = to_intel_bo(obj);
5412         int ret;
5413
5414         if (obj_priv->tiling_mode == I915_TILING_Y)
5415                 return -EINVAL;
5416
5417         if (mode_cmd->pitch & 63)
5418                 return -EINVAL;
5419
5420         switch (mode_cmd->bpp) {
5421         case 8:
5422         case 16:
5423         case 24:
5424         case 32:
5425                 break;
5426         default:
5427                 return -EINVAL;
5428         }
5429
5430         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
5431         if (ret) {
5432                 DRM_ERROR("framebuffer init failed %d\n", ret);
5433                 return ret;
5434         }
5435
5436         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
5437         intel_fb->obj = obj;
5438         return 0;
5439 }
5440
5441 static struct drm_framebuffer *
5442 intel_user_framebuffer_create(struct drm_device *dev,
5443                               struct drm_file *filp,
5444                               struct drm_mode_fb_cmd *mode_cmd)
5445 {
5446         struct drm_gem_object *obj;
5447         struct intel_framebuffer *intel_fb;
5448         int ret;
5449
5450         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
5451         if (!obj)
5452                 return ERR_PTR(-ENOENT);
5453
5454         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
5455         if (!intel_fb)
5456                 return ERR_PTR(-ENOMEM);
5457
5458         ret = intel_framebuffer_init(dev, intel_fb,
5459                                      mode_cmd, obj);
5460         if (ret) {
5461                 drm_gem_object_unreference_unlocked(obj);
5462                 kfree(intel_fb);
5463                 return ERR_PTR(ret);
5464         }
5465
5466         return &intel_fb->base;
5467 }
5468
5469 static const struct drm_mode_config_funcs intel_mode_funcs = {
5470         .fb_create = intel_user_framebuffer_create,
5471         .output_poll_changed = intel_fb_output_poll_changed,
5472 };
5473
5474 static struct drm_gem_object *
5475 intel_alloc_context_page(struct drm_device *dev)
5476 {
5477         struct drm_gem_object *ctx;
5478         int ret;
5479
5480         ctx = i915_gem_alloc_object(dev, 4096);
5481         if (!ctx) {
5482                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
5483                 return NULL;
5484         }
5485
5486         mutex_lock(&dev->struct_mutex);
5487         ret = i915_gem_object_pin(ctx, 4096);
5488         if (ret) {
5489                 DRM_ERROR("failed to pin power context: %d\n", ret);
5490                 goto err_unref;
5491         }
5492
5493         ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
5494         if (ret) {
5495                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
5496                 goto err_unpin;
5497         }
5498         mutex_unlock(&dev->struct_mutex);
5499
5500         return ctx;
5501
5502 err_unpin:
5503         i915_gem_object_unpin(ctx);
5504 err_unref:
5505         drm_gem_object_unreference(ctx);
5506         mutex_unlock(&dev->struct_mutex);
5507         return NULL;
5508 }
5509
5510 bool ironlake_set_drps(struct drm_device *dev, u8 val)
5511 {
5512         struct drm_i915_private *dev_priv = dev->dev_private;
5513         u16 rgvswctl;
5514
5515         rgvswctl = I915_READ16(MEMSWCTL);
5516         if (rgvswctl & MEMCTL_CMD_STS) {
5517                 DRM_DEBUG("gpu busy, RCS change rejected\n");
5518                 return false; /* still busy with another command */
5519         }
5520
5521         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
5522                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
5523         I915_WRITE16(MEMSWCTL, rgvswctl);
5524         POSTING_READ16(MEMSWCTL);
5525
5526         rgvswctl |= MEMCTL_CMD_STS;
5527         I915_WRITE16(MEMSWCTL, rgvswctl);
5528
5529         return true;
5530 }
5531
5532 void ironlake_enable_drps(struct drm_device *dev)
5533 {
5534         struct drm_i915_private *dev_priv = dev->dev_private;
5535         u32 rgvmodectl = I915_READ(MEMMODECTL);
5536         u8 fmax, fmin, fstart, vstart;
5537
5538         /* Enable temp reporting */
5539         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
5540         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
5541
5542         /* 100ms RC evaluation intervals */
5543         I915_WRITE(RCUPEI, 100000);
5544         I915_WRITE(RCDNEI, 100000);
5545
5546         /* Set max/min thresholds to 90ms and 80ms respectively */
5547         I915_WRITE(RCBMAXAVG, 90000);
5548         I915_WRITE(RCBMINAVG, 80000);
5549
5550         I915_WRITE(MEMIHYST, 1);
5551
5552         /* Set up min, max, and cur for interrupt handling */
5553         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
5554         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
5555         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
5556                 MEMMODE_FSTART_SHIFT;
5557         fstart = fmax;
5558
5559         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
5560                 PXVFREQ_PX_SHIFT;
5561
5562         dev_priv->fmax = fstart; /* IPS callback will increase this */
5563         dev_priv->fstart = fstart;
5564
5565         dev_priv->max_delay = fmax;
5566         dev_priv->min_delay = fmin;
5567         dev_priv->cur_delay = fstart;
5568
5569         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", fmax, fmin,
5570                          fstart);
5571
5572         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
5573
5574         /*
5575          * Interrupts will be enabled in ironlake_irq_postinstall
5576          */
5577
5578         I915_WRITE(VIDSTART, vstart);
5579         POSTING_READ(VIDSTART);
5580
5581         rgvmodectl |= MEMMODE_SWMODE_EN;
5582         I915_WRITE(MEMMODECTL, rgvmodectl);
5583
5584         if (wait_for((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
5585                 DRM_ERROR("stuck trying to change perf mode\n");
5586         msleep(1);
5587
5588         ironlake_set_drps(dev, fstart);
5589
5590         dev_priv->last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
5591                 I915_READ(0x112e0);
5592         dev_priv->last_time1 = jiffies_to_msecs(jiffies);
5593         dev_priv->last_count2 = I915_READ(0x112f4);
5594         getrawmonotonic(&dev_priv->last_time2);
5595 }
5596
5597 void ironlake_disable_drps(struct drm_device *dev)
5598 {
5599         struct drm_i915_private *dev_priv = dev->dev_private;
5600         u16 rgvswctl = I915_READ16(MEMSWCTL);
5601
5602         /* Ack interrupts, disable EFC interrupt */
5603         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
5604         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
5605         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
5606         I915_WRITE(DEIIR, DE_PCU_EVENT);
5607         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
5608
5609         /* Go back to the starting frequency */
5610         ironlake_set_drps(dev, dev_priv->fstart);
5611         msleep(1);
5612         rgvswctl |= MEMCTL_CMD_STS;
5613         I915_WRITE(MEMSWCTL, rgvswctl);
5614         msleep(1);
5615
5616 }
5617
5618 static unsigned long intel_pxfreq(u32 vidfreq)
5619 {
5620         unsigned long freq;
5621         int div = (vidfreq & 0x3f0000) >> 16;
5622         int post = (vidfreq & 0x3000) >> 12;
5623         int pre = (vidfreq & 0x7);
5624
5625         if (!pre)
5626                 return 0;
5627
5628         freq = ((div * 133333) / ((1<<post) * pre));
5629
5630         return freq;
5631 }
5632
5633 void intel_init_emon(struct drm_device *dev)
5634 {
5635         struct drm_i915_private *dev_priv = dev->dev_private;
5636         u32 lcfuse;
5637         u8 pxw[16];
5638         int i;
5639
5640         /* Disable to program */
5641         I915_WRITE(ECR, 0);
5642         POSTING_READ(ECR);
5643
5644         /* Program energy weights for various events */
5645         I915_WRITE(SDEW, 0x15040d00);
5646         I915_WRITE(CSIEW0, 0x007f0000);
5647         I915_WRITE(CSIEW1, 0x1e220004);
5648         I915_WRITE(CSIEW2, 0x04000004);
5649
5650         for (i = 0; i < 5; i++)
5651                 I915_WRITE(PEW + (i * 4), 0);
5652         for (i = 0; i < 3; i++)
5653                 I915_WRITE(DEW + (i * 4), 0);
5654
5655         /* Program P-state weights to account for frequency power adjustment */
5656         for (i = 0; i < 16; i++) {
5657                 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5658                 unsigned long freq = intel_pxfreq(pxvidfreq);
5659                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5660                         PXVFREQ_PX_SHIFT;
5661                 unsigned long val;
5662
5663                 val = vid * vid;
5664                 val *= (freq / 1000);
5665                 val *= 255;
5666                 val /= (127*127*900);
5667                 if (val > 0xff)
5668                         DRM_ERROR("bad pxval: %ld\n", val);
5669                 pxw[i] = val;
5670         }
5671         /* Render standby states get 0 weight */
5672         pxw[14] = 0;
5673         pxw[15] = 0;
5674
5675         for (i = 0; i < 4; i++) {
5676                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5677                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5678                 I915_WRITE(PXW + (i * 4), val);
5679         }
5680
5681         /* Adjust magic regs to magic values (more experimental results) */
5682         I915_WRITE(OGW0, 0);
5683         I915_WRITE(OGW1, 0);
5684         I915_WRITE(EG0, 0x00007f00);
5685         I915_WRITE(EG1, 0x0000000e);
5686         I915_WRITE(EG2, 0x000e0000);
5687         I915_WRITE(EG3, 0x68000300);
5688         I915_WRITE(EG4, 0x42000000);
5689         I915_WRITE(EG5, 0x00140031);
5690         I915_WRITE(EG6, 0);
5691         I915_WRITE(EG7, 0);
5692
5693         for (i = 0; i < 8; i++)
5694                 I915_WRITE(PXWL + (i * 4), 0);
5695
5696         /* Enable PMON + select events */
5697         I915_WRITE(ECR, 0x80000019);
5698
5699         lcfuse = I915_READ(LCFUSE02);
5700
5701         dev_priv->corr = (lcfuse & LCFUSE_HIV_MASK);
5702 }
5703
5704 void intel_init_clock_gating(struct drm_device *dev)
5705 {
5706         struct drm_i915_private *dev_priv = dev->dev_private;
5707
5708         /*
5709          * Disable clock gating reported to work incorrectly according to the
5710          * specs, but enable as much else as we can.
5711          */
5712         if (HAS_PCH_SPLIT(dev)) {
5713                 uint32_t dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE;
5714
5715                 if (IS_IRONLAKE(dev)) {
5716                         /* Required for FBC */
5717                         dspclk_gate |= DPFDUNIT_CLOCK_GATE_DISABLE;
5718                         /* Required for CxSR */
5719                         dspclk_gate |= DPARBUNIT_CLOCK_GATE_DISABLE;
5720
5721                         I915_WRITE(PCH_3DCGDIS0,
5722                                    MARIUNIT_CLOCK_GATE_DISABLE |
5723                                    SVSMUNIT_CLOCK_GATE_DISABLE);
5724                 }
5725
5726                 I915_WRITE(PCH_DSPCLK_GATE_D, dspclk_gate);
5727
5728                 /*
5729                  * According to the spec the following bits should be set in
5730                  * order to enable memory self-refresh
5731                  * The bit 22/21 of 0x42004
5732                  * The bit 5 of 0x42020
5733                  * The bit 15 of 0x45000
5734                  */
5735                 if (IS_IRONLAKE(dev)) {
5736                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5737                                         (I915_READ(ILK_DISPLAY_CHICKEN2) |
5738                                         ILK_DPARB_GATE | ILK_VSDPFD_FULL));
5739                         I915_WRITE(ILK_DSPCLK_GATE,
5740                                         (I915_READ(ILK_DSPCLK_GATE) |
5741                                                 ILK_DPARB_CLK_GATE));
5742                         I915_WRITE(DISP_ARB_CTL,
5743                                         (I915_READ(DISP_ARB_CTL) |
5744                                                 DISP_FBC_WM_DIS));
5745                 I915_WRITE(WM3_LP_ILK, 0);
5746                 I915_WRITE(WM2_LP_ILK, 0);
5747                 I915_WRITE(WM1_LP_ILK, 0);
5748                 }
5749                 /*
5750                  * Based on the document from hardware guys the following bits
5751                  * should be set unconditionally in order to enable FBC.
5752                  * The bit 22 of 0x42000
5753                  * The bit 22 of 0x42004
5754                  * The bit 7,8,9 of 0x42020.
5755                  */
5756                 if (IS_IRONLAKE_M(dev)) {
5757                         I915_WRITE(ILK_DISPLAY_CHICKEN1,
5758                                    I915_READ(ILK_DISPLAY_CHICKEN1) |
5759                                    ILK_FBCQ_DIS);
5760                         I915_WRITE(ILK_DISPLAY_CHICKEN2,
5761                                    I915_READ(ILK_DISPLAY_CHICKEN2) |
5762                                    ILK_DPARB_GATE);
5763                         I915_WRITE(ILK_DSPCLK_GATE,
5764                                    I915_READ(ILK_DSPCLK_GATE) |
5765                                    ILK_DPFC_DIS1 |
5766                                    ILK_DPFC_DIS2 |
5767                                    ILK_CLK_FBC);
5768                 }
5769                 return;
5770         } else if (IS_G4X(dev)) {
5771                 uint32_t dspclk_gate;
5772                 I915_WRITE(RENCLK_GATE_D1, 0);
5773                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5774                        GS_UNIT_CLOCK_GATE_DISABLE |
5775                        CL_UNIT_CLOCK_GATE_DISABLE);
5776                 I915_WRITE(RAMCLK_GATE_D, 0);
5777                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5778                         OVRUNIT_CLOCK_GATE_DISABLE |
5779                         OVCUNIT_CLOCK_GATE_DISABLE;
5780                 if (IS_GM45(dev))
5781                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5782                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
5783         } else if (IS_I965GM(dev)) {
5784                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5785                 I915_WRITE(RENCLK_GATE_D2, 0);
5786                 I915_WRITE(DSPCLK_GATE_D, 0);
5787                 I915_WRITE(RAMCLK_GATE_D, 0);
5788                 I915_WRITE16(DEUC, 0);
5789         } else if (IS_I965G(dev)) {
5790                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5791                        I965_RCC_CLOCK_GATE_DISABLE |
5792                        I965_RCPB_CLOCK_GATE_DISABLE |
5793                        I965_ISC_CLOCK_GATE_DISABLE |
5794                        I965_FBC_CLOCK_GATE_DISABLE);
5795                 I915_WRITE(RENCLK_GATE_D2, 0);
5796         } else if (IS_I9XX(dev)) {
5797                 u32 dstate = I915_READ(D_STATE);
5798
5799                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5800                         DSTATE_DOT_CLOCK_GATING;
5801                 I915_WRITE(D_STATE, dstate);
5802         } else if (IS_I85X(dev) || IS_I865G(dev)) {
5803                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5804         } else if (IS_I830(dev)) {
5805                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5806         }
5807
5808         /*
5809          * GPU can automatically power down the render unit if given a page
5810          * to save state.
5811          */
5812         if (IS_IRONLAKE_M(dev)) {
5813                 if (dev_priv->renderctx == NULL)
5814                         dev_priv->renderctx = intel_alloc_context_page(dev);
5815                 if (dev_priv->renderctx) {
5816                         struct drm_i915_gem_object *obj_priv;
5817                         obj_priv = to_intel_bo(dev_priv->renderctx);
5818                         if (obj_priv) {
5819                                 BEGIN_LP_RING(4);
5820                                 OUT_RING(MI_SET_CONTEXT);
5821                                 OUT_RING(obj_priv->gtt_offset |
5822                                                 MI_MM_SPACE_GTT |
5823                                                 MI_SAVE_EXT_STATE_EN |
5824                                                 MI_RESTORE_EXT_STATE_EN |
5825                                                 MI_RESTORE_INHIBIT);
5826                                 OUT_RING(MI_NOOP);
5827                                 OUT_RING(MI_FLUSH);
5828                                 ADVANCE_LP_RING();
5829                         }
5830                 } else
5831                         DRM_DEBUG_KMS("Failed to allocate render context."
5832                                        "Disable RC6\n");
5833         }
5834
5835         if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
5836                 struct drm_i915_gem_object *obj_priv = NULL;
5837
5838                 if (dev_priv->pwrctx) {
5839                         obj_priv = to_intel_bo(dev_priv->pwrctx);
5840                 } else {
5841                         struct drm_gem_object *pwrctx;
5842
5843                         pwrctx = intel_alloc_context_page(dev);
5844                         if (pwrctx) {
5845                                 dev_priv->pwrctx = pwrctx;
5846                                 obj_priv = to_intel_bo(pwrctx);
5847                         }
5848                 }
5849
5850                 if (obj_priv) {
5851                         I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
5852                         I915_WRITE(MCHBAR_RENDER_STANDBY,
5853                                    I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
5854                 }
5855         }
5856 }
5857
5858 /* Set up chip specific display functions */
5859 static void intel_init_display(struct drm_device *dev)
5860 {
5861         struct drm_i915_private *dev_priv = dev->dev_private;
5862
5863         /* We always want a DPMS function */
5864         if (HAS_PCH_SPLIT(dev))
5865                 dev_priv->display.dpms = ironlake_crtc_dpms;
5866         else
5867                 dev_priv->display.dpms = i9xx_crtc_dpms;
5868
5869         if (I915_HAS_FBC(dev)) {
5870                 if (IS_IRONLAKE_M(dev)) {
5871                         dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
5872                         dev_priv->display.enable_fbc = ironlake_enable_fbc;
5873                         dev_priv->display.disable_fbc = ironlake_disable_fbc;
5874                 } else if (IS_GM45(dev)) {
5875                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5876                         dev_priv->display.enable_fbc = g4x_enable_fbc;
5877                         dev_priv->display.disable_fbc = g4x_disable_fbc;
5878                 } else if (IS_I965GM(dev)) {
5879                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5880                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
5881                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
5882                 }
5883                 /* 855GM needs testing */
5884         }
5885
5886         /* Returns the core display clock speed */
5887         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
5888                 dev_priv->display.get_display_clock_speed =
5889                         i945_get_display_clock_speed;
5890         else if (IS_I915G(dev))
5891                 dev_priv->display.get_display_clock_speed =
5892                         i915_get_display_clock_speed;
5893         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
5894                 dev_priv->display.get_display_clock_speed =
5895                         i9xx_misc_get_display_clock_speed;
5896         else if (IS_I915GM(dev))
5897                 dev_priv->display.get_display_clock_speed =
5898                         i915gm_get_display_clock_speed;
5899         else if (IS_I865G(dev))
5900                 dev_priv->display.get_display_clock_speed =
5901                         i865_get_display_clock_speed;
5902         else if (IS_I85X(dev))
5903                 dev_priv->display.get_display_clock_speed =
5904                         i855_get_display_clock_speed;
5905         else /* 852, 830 */
5906                 dev_priv->display.get_display_clock_speed =
5907                         i830_get_display_clock_speed;
5908
5909         /* For FIFO watermark updates */
5910         if (HAS_PCH_SPLIT(dev)) {
5911                 if (IS_IRONLAKE(dev)) {
5912                         if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5913                                 dev_priv->display.update_wm = ironlake_update_wm;
5914                         else {
5915                                 DRM_DEBUG_KMS("Failed to get proper latency. "
5916                                               "Disable CxSR\n");
5917                                 dev_priv->display.update_wm = NULL;
5918                         }
5919                 } else
5920                         dev_priv->display.update_wm = NULL;
5921         } else if (IS_PINEVIEW(dev)) {
5922                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5923                                             dev_priv->is_ddr3,
5924                                             dev_priv->fsb_freq,
5925                                             dev_priv->mem_freq)) {
5926                         DRM_INFO("failed to find known CxSR latency "
5927                                  "(found ddr%s fsb freq %d, mem freq %d), "
5928                                  "disabling CxSR\n",
5929                                  (dev_priv->is_ddr3 == 1) ? "3": "2",
5930                                  dev_priv->fsb_freq, dev_priv->mem_freq);
5931                         /* Disable CxSR and never update its watermark again */
5932                         pineview_disable_cxsr(dev);
5933                         dev_priv->display.update_wm = NULL;
5934                 } else
5935                         dev_priv->display.update_wm = pineview_update_wm;
5936         } else if (IS_G4X(dev))
5937                 dev_priv->display.update_wm = g4x_update_wm;
5938         else if (IS_I965G(dev))
5939                 dev_priv->display.update_wm = i965_update_wm;
5940         else if (IS_I9XX(dev)) {
5941                 dev_priv->display.update_wm = i9xx_update_wm;
5942                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5943         } else if (IS_I85X(dev)) {
5944                 dev_priv->display.update_wm = i9xx_update_wm;
5945                 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5946         } else {
5947                 dev_priv->display.update_wm = i830_update_wm;
5948                 if (IS_845G(dev))
5949                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
5950                 else
5951                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
5952         }
5953 }
5954
5955 /*
5956  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
5957  * resume, or other times.  This quirk makes sure that's the case for
5958  * affected systems.
5959  */
5960 static void quirk_pipea_force (struct drm_device *dev)
5961 {
5962         struct drm_i915_private *dev_priv = dev->dev_private;
5963
5964         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
5965         DRM_DEBUG_DRIVER("applying pipe a force quirk\n");
5966 }
5967
5968 struct intel_quirk {
5969         int device;
5970         int subsystem_vendor;
5971         int subsystem_device;
5972         void (*hook)(struct drm_device *dev);
5973 };
5974
5975 struct intel_quirk intel_quirks[] = {
5976         /* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
5977         { 0x2a42, 0x103c, 0x30eb, quirk_pipea_force },
5978         /* HP Mini needs pipe A force quirk (LP: #322104) */
5979         { 0x27ae,0x103c, 0x361a, quirk_pipea_force },
5980
5981         /* Thinkpad R31 needs pipe A force quirk */
5982         { 0x3577, 0x1014, 0x0505, quirk_pipea_force },
5983         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
5984         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
5985
5986         /* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
5987         { 0x3577,  0x1014, 0x0513, quirk_pipea_force },
5988         /* ThinkPad X40 needs pipe A force quirk */
5989
5990         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
5991         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
5992
5993         /* 855 & before need to leave pipe A & dpll A up */
5994         { 0x3582, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5995         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
5996 };
5997
5998 static void intel_init_quirks(struct drm_device *dev)
5999 {
6000         struct pci_dev *d = dev->pdev;
6001         int i;
6002
6003         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
6004                 struct intel_quirk *q = &intel_quirks[i];
6005
6006                 if (d->device == q->device &&
6007                     (d->subsystem_vendor == q->subsystem_vendor ||
6008                      q->subsystem_vendor == PCI_ANY_ID) &&
6009                     (d->subsystem_device == q->subsystem_device ||
6010                      q->subsystem_device == PCI_ANY_ID))
6011                         q->hook(dev);
6012         }
6013 }
6014
6015 /* Disable the VGA plane that we never use */
6016 static void i915_disable_vga(struct drm_device *dev)
6017 {
6018         struct drm_i915_private *dev_priv = dev->dev_private;
6019         u8 sr1;
6020         u32 vga_reg;
6021
6022         if (HAS_PCH_SPLIT(dev))
6023                 vga_reg = CPU_VGACNTRL;
6024         else
6025                 vga_reg = VGACNTRL;
6026
6027         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
6028         outb(1, VGA_SR_INDEX);
6029         sr1 = inb(VGA_SR_DATA);
6030         outb(sr1 | 1<<5, VGA_SR_DATA);
6031         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
6032         udelay(300);
6033
6034         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
6035         POSTING_READ(vga_reg);
6036 }
6037
6038 void intel_modeset_init(struct drm_device *dev)
6039 {
6040         struct drm_i915_private *dev_priv = dev->dev_private;
6041         int i;
6042
6043         drm_mode_config_init(dev);
6044
6045         dev->mode_config.min_width = 0;
6046         dev->mode_config.min_height = 0;
6047
6048         dev->mode_config.funcs = (void *)&intel_mode_funcs;
6049
6050         intel_init_quirks(dev);
6051
6052         intel_init_display(dev);
6053
6054         if (IS_I965G(dev)) {
6055                 dev->mode_config.max_width = 8192;
6056                 dev->mode_config.max_height = 8192;
6057         } else if (IS_I9XX(dev)) {
6058                 dev->mode_config.max_width = 4096;
6059                 dev->mode_config.max_height = 4096;
6060         } else {
6061                 dev->mode_config.max_width = 2048;
6062                 dev->mode_config.max_height = 2048;
6063         }
6064
6065         /* set memory base */
6066         if (IS_I9XX(dev))
6067                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
6068         else
6069                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
6070
6071         if (IS_MOBILE(dev) || IS_I9XX(dev))
6072                 dev_priv->num_pipe = 2;
6073         else
6074                 dev_priv->num_pipe = 1;
6075         DRM_DEBUG_KMS("%d display pipe%s available.\n",
6076                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
6077
6078         for (i = 0; i < dev_priv->num_pipe; i++) {
6079                 intel_crtc_init(dev, i);
6080         }
6081
6082         intel_setup_outputs(dev);
6083
6084         intel_init_clock_gating(dev);
6085
6086         /* Just disable it once at startup */
6087         i915_disable_vga(dev);
6088
6089         if (IS_IRONLAKE_M(dev)) {
6090                 ironlake_enable_drps(dev);
6091                 intel_init_emon(dev);
6092         }
6093
6094         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
6095         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
6096                     (unsigned long)dev);
6097
6098         intel_setup_overlay(dev);
6099 }
6100
6101 void intel_modeset_cleanup(struct drm_device *dev)
6102 {
6103         struct drm_i915_private *dev_priv = dev->dev_private;
6104         struct drm_crtc *crtc;
6105         struct intel_crtc *intel_crtc;
6106
6107         mutex_lock(&dev->struct_mutex);
6108
6109         drm_kms_helper_poll_fini(dev);
6110         intel_fbdev_fini(dev);
6111
6112         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6113                 /* Skip inactive CRTCs */
6114                 if (!crtc->fb)
6115                         continue;
6116
6117                 intel_crtc = to_intel_crtc(crtc);
6118                 intel_increase_pllclock(crtc);
6119         }
6120
6121         if (dev_priv->display.disable_fbc)
6122                 dev_priv->display.disable_fbc(dev);
6123
6124         if (dev_priv->renderctx) {
6125                 struct drm_i915_gem_object *obj_priv;
6126
6127                 obj_priv = to_intel_bo(dev_priv->renderctx);
6128                 I915_WRITE(CCID, obj_priv->gtt_offset &~ CCID_EN);
6129                 I915_READ(CCID);
6130                 i915_gem_object_unpin(dev_priv->renderctx);
6131                 drm_gem_object_unreference(dev_priv->renderctx);
6132         }
6133
6134         if (dev_priv->pwrctx) {
6135                 struct drm_i915_gem_object *obj_priv;
6136
6137                 obj_priv = to_intel_bo(dev_priv->pwrctx);
6138                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
6139                 I915_READ(PWRCTXA);
6140                 i915_gem_object_unpin(dev_priv->pwrctx);
6141                 drm_gem_object_unreference(dev_priv->pwrctx);
6142         }
6143
6144         if (IS_IRONLAKE_M(dev))
6145                 ironlake_disable_drps(dev);
6146
6147         mutex_unlock(&dev->struct_mutex);
6148
6149         /* Disable the irq before mode object teardown, for the irq might
6150          * enqueue unpin/hotplug work. */
6151         drm_irq_uninstall(dev);
6152         cancel_work_sync(&dev_priv->hotplug_work);
6153
6154         /* Shut off idle work before the crtcs get freed. */
6155         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6156                 intel_crtc = to_intel_crtc(crtc);
6157                 del_timer_sync(&intel_crtc->idle_timer);
6158         }
6159         del_timer_sync(&dev_priv->idle_timer);
6160         cancel_work_sync(&dev_priv->idle_work);
6161
6162         drm_mode_config_cleanup(dev);
6163 }
6164
6165 /*
6166  * Return which encoder is currently attached for connector.
6167  */
6168 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
6169 {
6170         return &intel_attached_encoder(connector)->base;
6171 }
6172
6173 void intel_connector_attach_encoder(struct intel_connector *connector,
6174                                     struct intel_encoder *encoder)
6175 {
6176         connector->encoder = encoder;
6177         drm_mode_connector_attach_encoder(&connector->base,
6178                                           &encoder->base);
6179 }
6180
6181 /*
6182  * set vga decode state - true == enable VGA decode
6183  */
6184 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
6185 {
6186         struct drm_i915_private *dev_priv = dev->dev_private;
6187         u16 gmch_ctrl;
6188
6189         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
6190         if (state)
6191                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
6192         else
6193                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
6194         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
6195         return 0;
6196 }